* [PATCH] can: fix Xilinx ZynqMP CAN RX FIFO logic
@ 2022-08-12 17:25 Anton Kochkov
2022-08-17 9:50 ` Francisco Iglesias
0 siblings, 1 reply; 2+ messages in thread
From: Anton Kochkov @ 2022-08-12 17:25 UTC (permalink / raw)
To: qemu-devel
Cc: Anton Kochkov, Pavel Pisa, Vikram Garhwal, Francisco Iglesias,
Jason Wang
Function "update_rx_fifo()" should operate on the RX FIFO
registers, not the TX FIFO ones.
Signed-off-by: Anton Kochkov <anton.kochkov@proton.me>
Resolves: https://gitlab.com/qemu-projects/qemu/-/issues/1123
---
hw/net/can/xlnx-zynqmp-can.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
index 82ac48cee2..e93e6c5e19 100644
--- a/hw/net/can/xlnx-zynqmp-can.c
+++ b/hw/net/can/xlnx-zynqmp-can.c
@@ -696,30 +696,30 @@ static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame)
timestamp));
/* First 32 bit of the data. */
- fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT,
- R_TXFIFO_DATA1_DB3_LENGTH,
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA1_DB3_SHIFT,
+ R_RXFIFO_DATA1_DB3_LENGTH,
frame->data[0]) |
- deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT,
- R_TXFIFO_DATA1_DB2_LENGTH,
+ deposit32(0, R_RXFIFO_DATA1_DB2_SHIFT,
+ R_RXFIFO_DATA1_DB2_LENGTH,
frame->data[1]) |
- deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT,
- R_TXFIFO_DATA1_DB1_LENGTH,
+ deposit32(0, R_RXFIFO_DATA1_DB1_SHIFT,
+ R_RXFIFO_DATA1_DB1_LENGTH,
frame->data[2]) |
- deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT,
- R_TXFIFO_DATA1_DB0_LENGTH,
+ deposit32(0, R_RXFIFO_DATA1_DB0_SHIFT,
+ R_RXFIFO_DATA1_DB0_LENGTH,
frame->data[3]));
/* Last 32 bit of the data. */
- fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT,
- R_TXFIFO_DATA2_DB7_LENGTH,
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA2_DB7_SHIFT,
+ R_RXFIFO_DATA2_DB7_LENGTH,
frame->data[4]) |
- deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT,
- R_TXFIFO_DATA2_DB6_LENGTH,
+ deposit32(0, R_RXFIFO_DATA2_DB6_SHIFT,
+ R_RXFIFO_DATA2_DB6_LENGTH,
frame->data[5]) |
- deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT,
- R_TXFIFO_DATA2_DB5_LENGTH,
+ deposit32(0, R_RXFIFO_DATA2_DB5_SHIFT,
+ R_RXFIFO_DATA2_DB5_LENGTH,
frame->data[6]) |
- deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT,
- R_TXFIFO_DATA2_DB4_LENGTH,
+ deposit32(0, R_RXFIFO_DATA2_DB4_SHIFT,
+ R_RXFIFO_DATA2_DB4_LENGTH,
frame->data[7]));
ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
--
2.37.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] can: fix Xilinx ZynqMP CAN RX FIFO logic
2022-08-12 17:25 [PATCH] can: fix Xilinx ZynqMP CAN RX FIFO logic Anton Kochkov
@ 2022-08-17 9:50 ` Francisco Iglesias
0 siblings, 0 replies; 2+ messages in thread
From: Francisco Iglesias @ 2022-08-17 9:50 UTC (permalink / raw)
To: Anton Kochkov
Cc: qemu-devel, Pavel Pisa, Vikram Garhwal, Francisco Iglesias, Jason Wang
On [2022 Aug 12] Fri 17:25:28, Anton Kochkov wrote:
> Function "update_rx_fifo()" should operate on the RX FIFO
> registers, not the TX FIFO ones.
Hi Anton,
Should we update the git commit message to say this is done for readability /
keeping it consistent? (the defines have the same values)
Otherwise:
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Best regards,
Francisco Iglesias
>
> Signed-off-by: Anton Kochkov <anton.kochkov@proton.me>
> Resolves: https://gitlab.com/qemu-projects/qemu/-/issues/1123
> ---
> hw/net/can/xlnx-zynqmp-can.c | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
> index 82ac48cee2..e93e6c5e19 100644
> --- a/hw/net/can/xlnx-zynqmp-can.c
> +++ b/hw/net/can/xlnx-zynqmp-can.c
> @@ -696,30 +696,30 @@ static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame)
> timestamp));
>
> /* First 32 bit of the data. */
> - fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT,
> - R_TXFIFO_DATA1_DB3_LENGTH,
> + fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA1_DB3_SHIFT,
> + R_RXFIFO_DATA1_DB3_LENGTH,
> frame->data[0]) |
> - deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT,
> - R_TXFIFO_DATA1_DB2_LENGTH,
> + deposit32(0, R_RXFIFO_DATA1_DB2_SHIFT,
> + R_RXFIFO_DATA1_DB2_LENGTH,
> frame->data[1]) |
> - deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT,
> - R_TXFIFO_DATA1_DB1_LENGTH,
> + deposit32(0, R_RXFIFO_DATA1_DB1_SHIFT,
> + R_RXFIFO_DATA1_DB1_LENGTH,
> frame->data[2]) |
> - deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT,
> - R_TXFIFO_DATA1_DB0_LENGTH,
> + deposit32(0, R_RXFIFO_DATA1_DB0_SHIFT,
> + R_RXFIFO_DATA1_DB0_LENGTH,
> frame->data[3]));
> /* Last 32 bit of the data. */
> - fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT,
> - R_TXFIFO_DATA2_DB7_LENGTH,
> + fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA2_DB7_SHIFT,
> + R_RXFIFO_DATA2_DB7_LENGTH,
> frame->data[4]) |
> - deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT,
> - R_TXFIFO_DATA2_DB6_LENGTH,
> + deposit32(0, R_RXFIFO_DATA2_DB6_SHIFT,
> + R_RXFIFO_DATA2_DB6_LENGTH,
> frame->data[5]) |
> - deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT,
> - R_TXFIFO_DATA2_DB5_LENGTH,
> + deposit32(0, R_RXFIFO_DATA2_DB5_SHIFT,
> + R_RXFIFO_DATA2_DB5_LENGTH,
> frame->data[6]) |
> - deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT,
> - R_TXFIFO_DATA2_DB4_LENGTH,
> + deposit32(0, R_RXFIFO_DATA2_DB4_SHIFT,
> + R_RXFIFO_DATA2_DB4_LENGTH,
> frame->data[7]));
>
> ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
> --
> 2.37.1
>
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2022-08-17 9:56 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-08-12 17:25 [PATCH] can: fix Xilinx ZynqMP CAN RX FIFO logic Anton Kochkov
2022-08-17 9:50 ` Francisco Iglesias
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.