* [Intel-gfx] [PATCH 0/3] Enable Pipewriteback
@ 2022-08-18 10:36 Suraj Kandpal
2022-08-18 10:36 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define WD trancoder for i915 Suraj Kandpal
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Suraj Kandpal @ 2022-08-18 10:36 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, jani.nikula
A patch series was floated in the drm mailing list which aimed to change
the drm_connector and drm_encoder fields to pointer in the
drm_connector_writeback structure, this received a huge pushback from
the community but since i915 expects each connector present in the
drm_device list to be a intel_connector but drm_writeback framework
makes us have a connector which cannot be embedded in an intel_connector
structure.
[1] https://patchwork.kernel.org/project/dri-devel/patch/20220202081702.22119-1-suraj.kandpal@intel.com/
[2] https://patchwork.kernel.org/project/dri-devel/patch/20220202085429.22261-6-suraj.kandpal@intel.com/
Since no one had an issue with encoder field being changed into a
pointer it was decided to break the connector and encoder pointer
changes into two different series.The encoder field changes is
currently being worked upon by Abhinav Kumar and the changes have been
merged.
[3]https://patchwork.kernel.org/project/dri-devel/list/?series=633565
Going forward we use a drm_connector which is not embedded in
intel_connector.
We also create a intel_encoder to avoid changes to many
iterators but no intel_connector. We also changed all iterators that
go through connectors and add a check to only cast connectors which are
not writeback connectors.
I had also floated a previous series to Enable writeback but floating a
new one as i created an extra patch in this series as suggested by
Jani, Nikula for intel_connector iterator changes.
Please go check the below link if interested.
[4]https://patchwork.freedesktop.org/series/106902/
Suraj Kandpal (3):
drm/i915: Define WD trancoder for i915
drm/i915 : Changing intel_connector iterators
drm/i915: Enabling WD Transcoder
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 6 +
.../drm/i915/display/intel_crtc_state_dump.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +
drivers/gpu/drm/i915/display/intel_display.c | 63 +-
drivers/gpu/drm/i915/display/intel_display.h | 18 +-
.../drm/i915/display/intel_display_debugfs.c | 13 +-
.../drm/i915/display/intel_display_types.h | 33 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 6 +
.../drm/i915/display/intel_modeset_setup.c | 114 ++-
.../drm/i915/display/intel_modeset_verify.c | 17 +-
drivers/gpu/drm/i915/display/intel_opregion.c | 3 +
.../gpu/drm/i915/display/intel_wb_connector.h | 20 +
drivers/gpu/drm/i915/display/intel_wd.c | 704 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_wd.h | 48 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 8 +-
drivers/gpu/drm/i915/i915_pci.c | 7 +-
drivers/gpu/drm/i915/i915_reg.h | 139 ++++
20 files changed, 1154 insertions(+), 55 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_wb_connector.h
create mode 100644 drivers/gpu/drm/i915/display/intel_wd.c
create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h
--
2.37.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [Intel-gfx] [PATCH 1/3] drm/i915: Define WD trancoder for i915 2022-08-18 10:36 [Intel-gfx] [PATCH 0/3] Enable Pipewriteback Suraj Kandpal @ 2022-08-18 10:36 ` Suraj Kandpal 2022-08-18 10:36 ` [Intel-gfx] [PATCH 2/3] drm/i915 : Changing intel_connector iterators Suraj Kandpal ` (4 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Suraj Kandpal @ 2022-08-18 10:36 UTC (permalink / raw) To: intel-gfx; +Cc: ville.syrjala, jani.nikula Adding WD Types, WD transcoder to enum list and WD Transcoder offsets. Adding i915 register definitions related to WD transcoder Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_display.h | 6 + .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 139 ++++++++++++++++++ 3 files changed, 146 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index fa5371036239..4e9f22954a41 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -120,6 +120,8 @@ enum transcoder { TRANSCODER_DSI_1, TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ + TRANSCODER_WD_0, + TRANSCODER_WD_1, I915_MAX_TRANSCODERS }; @@ -141,6 +143,10 @@ static inline const char *transcoder_name(enum transcoder transcoder) return "DSI A"; case TRANSCODER_DSI_C: return "DSI C"; + case TRANSCODER_WD_0: + return "WD 0"; + case TRANSCODER_WD_1: + return "WD 1"; default: return "<invalid>"; } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 0da9b208d56e..0e94bd430bcb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -79,6 +79,7 @@ enum intel_output_type { INTEL_OUTPUT_DSI = 9, INTEL_OUTPUT_DDI = 10, INTEL_OUTPUT_DP_MST = 11, + INTEL_OUTPUT_WD = 12, }; enum hdmi_force_audio { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bf5c39d9f953..e3fced4b9980 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2059,6 +2059,8 @@ #define TRANSCODER_EDP_OFFSET 0x6f000 #define TRANSCODER_DSI0_OFFSET 0x6b000 #define TRANSCODER_DSI1_OFFSET 0x6b800 +#define TRANSCODER_WD0_OFFSET 0x6e000 +#define TRANSCODER_WD1_OFFSET 0x6e800 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) @@ -3831,6 +3833,11 @@ #define PIPE_DSI0_OFFSET 0x7b000 #define PIPE_DSI1_OFFSET 0x7b800 +/* WD 0 and 1 */ +#define PIPE_WD0_OFFSET 0x7e000 +#define PIPE_WD1_OFFSET 0x7d000 + + #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) @@ -4495,6 +4502,10 @@ #define _PIPEDSI0CONF 0x7b008 #define _PIPEDSI1CONF 0x7b808 +/* WD 0 and 1 */ +#define _PIPEWD0CONF 0x7e008 +#define _PIPEWD1CONF 0x7d008 + /* Sprite A control */ #define _DVSACNTR 0x72180 #define DVS_ENABLE REG_BIT(31) @@ -5720,6 +5731,7 @@ #define GEN8_DE_MISC_IER _MMIO(0x4446c) #define GEN8_DE_MISC_GSE (1 << 27) #define GEN8_DE_EDP_PSR (1 << 19) +#define GEN8_DE_MISC_WD0 (1 << 23) #define GEN8_PCU_ISR _MMIO(0x444e0) #define GEN8_PCU_IMR _MMIO(0x444e4) @@ -8714,6 +8726,133 @@ enum skl_power_gate { #define DSB_ENABLE (1 << 31) #define DSB_STATUS (1 << 0) +#define TGL_ROOT_DEVICE_ID 0x9A00 +#define TGL_ROOT_DEVICE_MASK 0xFF00 +#define TGL_ROOT_DEVICE_SKU_MASK 0xF +#define TGL_ROOT_DEVICE_SKU_ULX 0x2 +#define TGL_ROOT_DEVICE_SKU_ULT 0x4 + +/* Gen12 WD */ +#define _MMIO_WD(tc, wd0, wd1) _MMIO_TRANS((tc) - TRANSCODER_WD_0, \ + wd0, wd1) + +#define WD_TRANS_ENABLE (1 << 31) +#define WD_TRANS_DISABLE 0 +#define WD_TRANS_ACTIVE (1 << 30) + +/* WD transcoder control */ +#define _WD_TRANS_FUNC_CTL_0 0x6e400 +#define _WD_TRANS_FUNC_CTL_1 0x6ec00 +#define WD_TRANS_FUNC_CTL(tc) _MMIO_WD(tc,\ + _WD_TRANS_FUNC_CTL_0,\ + _WD_TRANS_FUNC_CTL_1) + +#define TRANS_WD_FUNC_ENABLE (1 << 31) +#define WD_TRIGGERED_CAP_MODE_ENABLE (1 << 30) +#define START_TRIGGER_FRAME (1 << 29) +#define STOP_TRIGGER_FRAME (1 << 28) +#define WD_CTL_POINTER_ETEH (0 << 18) +#define WD_CTL_POINTER_ETDH (1 << 18) +#define WD_CTL_POINTER_DTDH (2 << 18) +#define WD_INPUT_SELECT_MASK (7 << 12) +#define WD_INPUT_PIPE_A (0 << 12) +#define WD_INPUT_PIPE_B (5 << 12) +#define WD_INPUT_PIPE_C (6 << 12) +#define WD_INPUT_PIPE_D (7 << 12) + +#define WD_PIX_FMT_MASK (0x3 << 20) +#define WD_PIX_FMT_YUYV (0x1 << 20) +#define WD_PIX_FMT_XYUV8888 (0x2 << 20) +#define WD_PIX_FMT_XBGR8888 (0x3 << 20) +#define WD_PIX_FMT_Y410 (0x4 << 20) +#define WD_PIX_FMT_YUV422 (0x5 << 20) +#define WD_PIX_FMT_XBGR2101010 (0x6 << 20) +#define WD_PIX_FMT_RGB565 (0x7 << 20) + +#define WD_FRAME_NUMBER_MASK 15 + +#define _WD_STRIDE_0 0x6e510 +#define _WD_STRIDE_1 0x6ed10 +#define WD_STRIDE(tc) _MMIO_WD(tc,\ + _WD_STRIDE_0,\ + _WD_STRIDE_1) +#define WD_STRIDE_SHIFT 6 +#define WD_STRIDE_MASK (0x3ff << WD_STRIDE_SHIFT) + +#define _WD_STREAMCAP_CTL0 0x6e590 +#define _WD_STREAMCAP_CTL1 0x6ed90 +#define WD_STREAMCAP_CTL(tc) _MMIO_WD(tc,\ + _WD_STREAMCAP_CTL0,\ + _WD_STREAMCAP_CTL1) + +#define WD_STREAM_CAP_MODE_EN (1 << 31) +#define WD_STRAT_MASK (3 << 24) +#define WD_SLICING_STRAT_1_1 (0 << 24) +#define WD_SLICING_STRAT_2_1 (1 << 24) +#define WD_SLICING_STRAT_4_1 (2 << 24) +#define WD_SLICING_STRAT_8_1 (3 << 24) +#define WD_STREAM_OVERRUN_STATUS 1 + +#define _WD_SURF_0 0x6e514 +#define _WD_SURF_1 0x6ed14 +#define WD_SURF(tc) _MMIO_WD(tc,\ + _WD_SURF_0,\ + _WD_SURF_1) + +#define _WD_IMR_0 0x6e560 +#define _WD_IMR_1 0x6ed60 +#define WD_IMR(tc) _MMIO_WD(tc,\ + _WD_IMR_0,\ + _WD_IMR_1) +#define WD_FRAME_COMPLETE_INT (1 << 7) +#define WD_GTT_FAULT_INT (1 << 6) +#define WD_VBLANK_INT (1 << 5) +#define WD_OVERRUN_INT (1 << 4) +#define WD_CAPTURING_INT (1 << 3) +#define WD_WRITE_COMPLETE_INT (1 << 2) + +#define _WD_IIR_0 0x6e564 +#define _WD_IIR_1 0x6ed64 +#define WD_IIR(tc) _MMIO_WD(tc,\ + _WD_IIR_0,\ + _WD_IIR_1) + +#define _WD_FRAME_STATUS_0 0x6e56b +#define _WD_FRAME_STATUS_1 0x6ed6b +#define WD_FRAME_STATUS(tc) _MMIO_WD(tc,\ + _WD_FRAME_STATUS_0,\ + _WD_FRAME_STATUS_1) + +#define WD_FRAME_COMPLETE (1 << 31) +#define WD_STATE_IDLE (0 << 24) +#define WD_STATE_CAPSTART (1 << 24) +#define WD_STATE_FRAME_START (2 << 24) +#define WD_STATE_CAPACITIVE (3 << 24) +#define WD_STATE_TG_DONE (4 << 24) +#define WD_STATE_WDX_DONE (5 << 24) +#define WD_STATE_QUICK_CAP (6 << 24) + +#define _WD_27_M_0 0x6e524 +#define _WD_27_M_1 0x6ed24 +#define WD_27_M(tc) _MMIO_WD(tc,\ + _WD_27_M_0,\ + _WD_27_M_1) + +#define _WD_27_N_0 0x6e528 + +//Address looks wrong in bspec: +#define _WD_27_N_1 0x6ec28 +#define WD_27_N(tc) _MMIO_WD(tc,\ + _WD_27_N_0,\ + _WD_27_N_1) + +#define _WD_TAIL_CFG_0 0x6e520 +#define _WD_TAIL_CFG_1 0x6ed20 + +#define WD_TAIL_CFG(tc) _MMIO_WD(tc,\ + _WD_TAIL_CFG_0,\ + _WD_TAIL_CFG_1) + #define CLKREQ_POLICY _MMIO(0x101038) #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) -- 2.37.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915 : Changing intel_connector iterators 2022-08-18 10:36 [Intel-gfx] [PATCH 0/3] Enable Pipewriteback Suraj Kandpal 2022-08-18 10:36 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define WD trancoder for i915 Suraj Kandpal @ 2022-08-18 10:36 ` Suraj Kandpal 2022-08-18 10:36 ` [Intel-gfx] [PATCH 3/3] drm/i915: Enabling WD Transcoder Suraj Kandpal ` (3 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Suraj Kandpal @ 2022-08-18 10:36 UTC (permalink / raw) To: intel-gfx; +Cc: ville.syrjala, jani.nikula Changing intel_connector iterators as with writeback introduction not all drm_connector will be embedded within intel_connector. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_display.h | 7 ++--- .../drm/i915/display/intel_display_types.h | 26 ++++++++++++++++++- .../drm/i915/display/intel_modeset_setup.c | 11 +++++--- 3 files changed, 35 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 4e9f22954a41..3b9987b5f304 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -52,6 +52,7 @@ struct intel_crtc_state; struct intel_digital_port; struct intel_dp; struct intel_encoder; +struct intel_connector; struct intel_initial_plane_config; struct intel_load_detect_pipe; struct intel_plane; @@ -469,16 +470,12 @@ enum hpd_pin { for_each_if(intel_encoder_can_psr(intel_encoder)) #define for_each_intel_connector_iter(intel_connector, iter) \ - while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) + while ((intel_connector = intel_connector_list_iter_next(iter))) #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ for_each_if((intel_encoder)->base.crtc == (__crtc)) -#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ - list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ - for_each_if((intel_connector)->base.encoder == (__encoder)) - #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ for ((__i) = 0; \ (__i) < (__state)->base.dev->mode_config.num_total_plane && \ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 0e94bd430bcb..7a82b7acbaf2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1497,12 +1497,14 @@ struct cxsr_latency { #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi) -#define to_intel_connector(x) container_of(x, struct intel_connector, base) +#define to_intel_wb_connector(x) container_of(x, struct intel_wb_connector, base) #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) #define to_intel_plane(x) container_of(x, struct intel_plane, base) #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi) #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) +#define to_intel_connector(x) (((x->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)) ? \ + NULL : container_of(x, struct intel_connector, base)) struct intel_hdmi { i915_reg_t hdmi_reg; @@ -2068,4 +2070,26 @@ to_intel_frontbuffer(struct drm_framebuffer *fb) return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; } +static inline struct intel_connector * +intel_connector_list_iter_next(struct drm_connector_list_iter *iter) +{ + struct drm_connector *connector; + bool flag = true; + /* + * Skipping connector that are Writeback connector as they will + * not be embedded in intel connector + */ + while (flag) { + connector = drm_connector_list_iter_next(iter); + if (connector && !to_intel_connector(connector)) + continue; + + flag = false; + + if (connector) + return to_intel_connector(connector); + + } + return NULL; +} #endif /* __INTEL_DISPLAY_TYPES_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index f0e04d3904c6..20a5a9e33eca 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -204,11 +204,16 @@ static bool intel_crtc_has_encoders(struct intel_crtc *crtc) static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) { - struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_connector *connector; + struct drm_connector_list_iter conn_iter; - for_each_connector_on_encoder(dev, &encoder->base, connector) - return connector; + drm_connector_list_iter_begin(&i915->drm, &conn_iter); + for_each_intel_connector_iter(connector, &conn_iter) { + if (&encoder->base == connector->base.encoder) + return connector; + } + drm_connector_list_iter_end(&conn_iter); return NULL; } -- 2.37.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915: Enabling WD Transcoder 2022-08-18 10:36 [Intel-gfx] [PATCH 0/3] Enable Pipewriteback Suraj Kandpal 2022-08-18 10:36 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define WD trancoder for i915 Suraj Kandpal 2022-08-18 10:36 ` [Intel-gfx] [PATCH 2/3] drm/i915 : Changing intel_connector iterators Suraj Kandpal @ 2022-08-18 10:36 ` Suraj Kandpal 2022-08-18 13:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Pipewriteback Patchwork ` (2 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Suraj Kandpal @ 2022-08-18 10:36 UTC (permalink / raw) To: intel-gfx; +Cc: ville.syrjala, jani.nikula Adding support for writeback transcoder to start capturing frames using interrupt mechanism Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_acpi.c | 1 + drivers/gpu/drm/i915/display/intel_crtc.c | 6 + .../drm/i915/display/intel_crtc_state_dump.c | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 6 + drivers/gpu/drm/i915/display/intel_display.c | 63 +- drivers/gpu/drm/i915/display/intel_display.h | 5 + .../drm/i915/display/intel_display_debugfs.c | 13 +- .../drm/i915/display/intel_display_types.h | 6 + drivers/gpu/drm/i915/display/intel_dpll.c | 6 + .../drm/i915/display/intel_modeset_setup.c | 103 ++- .../drm/i915/display/intel_modeset_verify.c | 17 +- drivers/gpu/drm/i915/display/intel_opregion.c | 3 + .../gpu/drm/i915/display/intel_wb_connector.h | 20 + drivers/gpu/drm/i915/display/intel_wd.c | 704 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_wd.h | 48 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 8 +- drivers/gpu/drm/i915/i915_pci.c | 7 +- 19 files changed, 973 insertions(+), 46 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_wb_connector.h create mode 100644 drivers/gpu/drm/i915/display/intel_wd.c create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 522ef9b4aff3..ec63ed16c250 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -302,6 +302,7 @@ i915-y += \ display/intel_tv.o \ display/intel_vdsc.o \ display/intel_vrr.o \ + display/intel_wd.o \ display/vlv_dsi.o \ display/vlv_dsi_pll.o diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c b/drivers/gpu/drm/i915/display/intel_acpi.c index e78430001f07..ae08db164f73 100644 --- a/drivers/gpu/drm/i915/display/intel_acpi.c +++ b/drivers/gpu/drm/i915/display/intel_acpi.c @@ -247,6 +247,7 @@ static u32 acpi_display_type(struct intel_connector *connector) case DRM_MODE_CONNECTOR_LVDS: case DRM_MODE_CONNECTOR_eDP: case DRM_MODE_CONNECTOR_DSI: + case DRM_MODE_CONNECTOR_WRITEBACK: display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL; break; case DRM_MODE_CONNECTOR_Unknown: diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 6792a9056f46..66d552758720 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -491,6 +491,9 @@ void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state) if (new_crtc_state->do_async_flip) return; + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD)) + return; + if (intel_crtc_needs_vblank_work(new_crtc_state)) intel_crtc_vblank_work_init(new_crtc_state); @@ -638,6 +641,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) if (new_crtc_state->do_async_flip) return; + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD)) + return; + trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end); /* diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index e9212f69c360..8435065f3b7d 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -71,6 +71,7 @@ static const char * const output_type_str[] = { OUTPUT_TYPE(DSI), OUTPUT_TYPE(DDI), OUTPUT_TYPE(DP_MST), + OUTPUT_TYPE(WD), }; #undef OUTPUT_TYPE diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a4c8493f3ce7..1360406ca531 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1974,6 +1974,12 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) */ if (encoder->type == INTEL_OUTPUT_DP_MST) return; + /* + * WD transcoder is a virtual encoder hence sanization + * is not required for it + */ + if (encoder->type == INTEL_OUTPUT_WD) + return; if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { u8 pipe_mask; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f143adefdf38..7d31a0a64b2c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -115,6 +115,7 @@ #include "intel_sprite.h" #include "intel_tc.h" #include "intel_vga.h" +#include "intel_wd.h" #include "i9xx_plane.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -1510,6 +1511,9 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state) continue; intel_connector = to_intel_connector(connector); + if (!intel_connector) + continue; + encoder = intel_connector_primary_encoder(intel_connector); if (!encoder->update_prepare) continue; @@ -1539,6 +1543,9 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state) continue; intel_connector = to_intel_connector(connector); + if (!intel_connector) + continue; + encoder = intel_connector_primary_encoder(intel_connector); if (!encoder->update_complete) continue; @@ -1549,6 +1556,39 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state) } } +static void intel_queue_writeback_job(struct intel_atomic_state *state, + struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) +{ + struct drm_connector_state *new_conn_state; + struct drm_connector *connector; + struct drm_writeback_connector *wb_conn; + int i; + + for_each_new_connector_in_state(&state->base, connector, new_conn_state, + i) { + if (!new_conn_state->writeback_job) + continue; + + wb_conn = drm_connector_to_writeback(connector); + drm_writeback_queue_job(wb_conn, new_conn_state); + } +} + +static void intel_enable_writeback_capture(struct intel_atomic_state *state, + struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) +{ + struct drm_connector_state *new_conn_state; + struct drm_connector *connector; + int i; + + for_each_new_connector_in_state(&state->base, connector, new_conn_state, + i) { + if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) + continue; + intel_wd_enable_capture(crtc_state, new_conn_state); + } +} + static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -1649,8 +1689,12 @@ static void intel_encoders_post_disable(struct intel_atomic_state *state, int i; for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { - struct intel_encoder *encoder = - to_intel_encoder(old_conn_state->best_encoder); + struct intel_encoder *encoder; + + if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) + continue; + + encoder = to_intel_encoder(old_conn_state->best_encoder); if (old_conn_state->crtc != &crtc->base) continue; @@ -1927,7 +1971,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, bdw_set_pipemisc(new_crtc_state); if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && - !transcoder_is_dsi(cpu_transcoder)) + !transcoder_is_dsi(cpu_transcoder) && + !transcoder_is_wd(cpu_transcoder)) hsw_configure_cpu_transcoder(new_crtc_state); crtc->active = true; @@ -7575,6 +7620,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) } } + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + intel_wd_set_vblank_event(state, crtc, new_crtc_state); + } + intel_encoders_update_prepare(state); intel_dbuf_pre_plane_update(state); @@ -7585,6 +7634,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_crtc_enable_flip_done(state, crtc); } + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (!(new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))) + continue; + intel_queue_writeback_job(state, crtc, new_crtc_state); + intel_enable_writeback_capture(state, crtc, new_crtc_state); + } + /* Now enable the clocks, plane, pipe, and connectors that we set up. */ dev_priv->display->commit_modeset_enables(state); @@ -7965,6 +8021,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) intel_ddi_init(dev_priv, PORT_TC1); intel_ddi_init(dev_priv, PORT_TC2); } else if (DISPLAY_VER(dev_priv) >= 12) { + intel_wd_init(dev_priv, TRANSCODER_WD_0); intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); intel_ddi_init(dev_priv, PORT_TC1); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 3b9987b5f304..4879ca2e96f7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -158,6 +158,11 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder) return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; } +static inline bool transcoder_is_wd(enum transcoder transcoder) +{ + return transcoder == TRANSCODER_WD_0 || transcoder == TRANSCODER_WD_1; +} + /* * Global legacy plane identifier. Valid only for primary/sprite * planes on pre-g4x, and only for primary planes on g4x-bdw. diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 225b6bfc783c..0dad54058762 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -547,7 +547,7 @@ static void intel_hdmi_info(struct seq_file *m, static void intel_connector_info(struct seq_file *m, struct drm_connector *connector) { - struct intel_connector *intel_connector = to_intel_connector(connector); + struct intel_connector *intel_connector; const struct drm_connector_state *conn_state = connector->state; struct intel_encoder *encoder = to_intel_encoder(conn_state->best_encoder); @@ -570,6 +570,8 @@ static void intel_connector_info(struct seq_file *m, if (!encoder) return; + intel_connector = to_intel_connector(connector); + switch (connector->connector_type) { case DRM_MODE_CONNECTOR_DisplayPort: case DRM_MODE_CONNECTOR_eDP: @@ -587,12 +589,15 @@ static void intel_connector_info(struct seq_file *m, break; } - seq_puts(m, "\tHDCP version: "); - intel_hdcp_info(m, intel_connector); + if (intel_connector) { + seq_puts(m, "\tHDCP version: "); + intel_hdcp_info(m, intel_connector); + } seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc); - intel_panel_info(m, intel_connector); + if (intel_connector) + intel_panel_info(m, intel_connector); seq_printf(m, "\tmodes:\n"); list_for_each_entry(mode, &connector->modes, head) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 7a82b7acbaf2..7b550c532dfb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -44,6 +44,7 @@ #include <drm/drm_vblank.h> #include <drm/drm_vblank_work.h> #include <drm/i915_mei_hdcp_interface.h> +#include <drm/drm_writeback.h> #include <media/cec-notifier.h> #include "i915_vma.h" @@ -1370,6 +1371,11 @@ struct intel_crtc { bool cpu_fifo_underrun_disabled; bool pch_fifo_underrun_disabled; + struct { + struct drm_pending_vblank_event *e; + atomic_t work_busy; + wait_queue_head_t wd_wait; + } wd; /* per-pipe watermark state */ struct { /* watermarks currently being used */ diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 5262f16b45ac..82bb8e170197 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -939,6 +939,9 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, struct intel_encoder *encoder = intel_get_crtc_new_encoder(state, crtc_state); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD)) + return 0; + if (DISPLAY_VER(dev_priv) < 11 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; @@ -955,6 +958,9 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, struct intel_encoder *encoder = intel_get_crtc_new_encoder(state, crtc_state); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD)) + return 0; + if (DISPLAY_VER(dev_priv) < 11 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 20a5a9e33eca..c7465516dec3 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -23,6 +23,7 @@ #include "intel_modeset_setup.h" #include "intel_pch_display.h" #include "intel_pm.h" +#include "intel_wd.h" static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, struct drm_modeset_acquire_ctx *ctx) @@ -110,17 +111,17 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915) { - struct intel_connector *connector; + struct drm_connector *connector; struct drm_connector_list_iter conn_iter; drm_connector_list_iter_begin(&i915->drm, &conn_iter); - for_each_intel_connector_iter(connector, &conn_iter) { - struct drm_connector_state *conn_state = connector->base.state; + drm_for_each_connector_iter(connector, &conn_iter) { + struct drm_connector_state *conn_state = connector->state; struct intel_encoder *encoder = - to_intel_encoder(connector->base.encoder); + to_intel_encoder(connector->encoder); if (conn_state->crtc) - drm_connector_put(&connector->base); + drm_connector_put(connector); if (encoder) { struct intel_crtc *crtc = @@ -132,7 +133,7 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private conn_state->crtc = &crtc->base; conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; - drm_connector_get(&connector->base); + drm_connector_get(connector); } else { conn_state->best_encoder = NULL; conn_state->crtc = NULL; @@ -427,6 +428,8 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) struct intel_crtc *crtc; struct intel_encoder *encoder; struct intel_connector *connector; + struct drm_connector *_connector; + struct drm_encoder *_encoder; struct drm_connector_list_iter conn_iter; u8 active_pipes = 0; @@ -503,38 +506,70 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) intel_dpll_readout_hw_state(i915); drm_connector_list_iter_begin(&i915->drm, &conn_iter); - for_each_intel_connector_iter(connector, &conn_iter) { - if (connector->get_hw_state(connector)) { - struct intel_crtc_state *crtc_state; - struct intel_crtc *crtc; - - connector->base.dpms = DRM_MODE_DPMS_ON; - - encoder = intel_attached_encoder(connector); - connector->base.encoder = &encoder->base; - - crtc = to_intel_crtc(encoder->base.crtc); - crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; - - if (crtc_state && crtc_state->hw.active) { - /* - * This has to be done during hardware readout - * because anything calling .crtc_disable may - * rely on the connector_mask being accurate. - */ - crtc_state->uapi.connector_mask |= - drm_connector_mask(&connector->base); - crtc_state->uapi.encoder_mask |= - drm_encoder_mask(&encoder->base); + drm_for_each_connector_iter(_connector, &conn_iter) { + struct intel_crtc_state *crtc_state; + struct intel_crtc *crtc; + struct drm_writeback_connector *wb_conn; + struct intel_wd *intel_wd; + + connector = to_intel_connector(_connector); + if (!connector) { + wb_conn = drm_connector_to_writeback(_connector); + intel_wd = wb_conn_to_intel_wd(wb_conn); + _encoder = &intel_wd->base.base; + _connector->encoder = _encoder; + encoder = to_intel_encoder(_encoder); + pipe = 0; + if (encoder->get_hw_state(encoder, &pipe)) { + _connector->dpms = DRM_MODE_DPMS_ON; + crtc = to_intel_crtc(_encoder->crtc); + crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; + + if (crtc_state && crtc_state->hw.active) { + /* + * This has to be done during hardware readout + * because anything calling .crtc_disable may + * rely on the connector_mask being accurate. + */ + crtc_state->uapi.connector_mask |= + drm_connector_mask(&connector->base); + crtc_state->uapi.encoder_mask |= + drm_encoder_mask(&encoder->base); + } + } else { + _connector->dpms = DRM_MODE_DPMS_OFF; + _connector->encoder = NULL; } } else { - connector->base.dpms = DRM_MODE_DPMS_OFF; - connector->base.encoder = NULL; + if (connector->get_hw_state(connector)) { + connector->base.dpms = DRM_MODE_DPMS_OFF; + encoder = intel_attached_encoder(connector); + connector->base.encoder = &encoder->base; + + crtc = to_intel_crtc(encoder->base.crtc); + crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; + + if (crtc_state && crtc_state->hw.active) { + /* + * This has to be done during hardware readout + * because anything calling .crtc_disable may + * rely on the connector_mask being accurate. + */ + crtc_state->uapi.connector_mask |= + drm_connector_mask(&connector->base); + crtc_state->uapi.encoder_mask |= + drm_encoder_mask(&encoder->base); + } + } else { + connector->base.dpms = DRM_MODE_DPMS_OFF; + connector->base.encoder = NULL; + } } drm_dbg_kms(&i915->drm, - "[CONNECTOR:%d:%s] hw state readout: %s\n", - connector->base.base.id, connector->base.name, - str_enabled_disabled(connector->base.encoder)); + "[CONNECTOR:%d:%s] hw state readout: %s\n", + _connector->base.id, _connector->name, + str_enabled_disabled(_connector->encoder)); + } drm_connector_list_iter_end(&conn_iter); diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index a91586d77cb6..0e06daac74c1 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -25,11 +25,16 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct drm_connector *_connector = conn_state->connector; + struct intel_connector *connector; + struct drm_i915_private *i915 = to_i915(_connector->dev); drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", - connector->base.base.id, connector->base.name); + _connector->base.id, _connector->name); + + connector = to_intel_connector(_connector); + if (!connector) + return; if (connector->get_hw_state(connector)) { struct intel_encoder *encoder = intel_attached_encoder(connector); @@ -119,6 +124,9 @@ verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_stat encoder->base.base.id, encoder->base.name); + if (encoder->type == INTEL_OUTPUT_WD) + continue; + for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, new_conn_state, i) { if (old_conn_state->best_encoder == &encoder->base) @@ -177,6 +185,9 @@ verify_crtc_state(struct intel_crtc *crtc, intel_crtc_get_pipe_config(pipe_config); + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD)) + return; + /* we keep both pipes enabled on 830 */ if (IS_I830(dev_priv) && pipe_config->hw.active) pipe_config->hw.active = new_crtc_state->hw.active; diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index 1c0c745c142d..73a5a12e2c48 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -374,6 +374,9 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, if (ret) return ret; + if (intel_encoder->type == INTEL_OUTPUT_WD) + return 0; + if (intel_encoder->type == INTEL_OUTPUT_DSI) port = 0; else diff --git a/drivers/gpu/drm/i915/display/intel_wb_connector.h b/drivers/gpu/drm/i915/display/intel_wb_connector.h new file mode 100644 index 000000000000..39dceddc7b4d --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_wb_connector.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT*/ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_WB_CONNECTOR_H__ +#define __INTEL_WB_CONNECTOR_H__ + +#include "intel_display.h" + +struct intel_wb_connector *intel_wb_connector_alloc(void); +void intel_wb_connector_free(struct intel_wb_connector *connector); +void intel_wb_connector_destroy(struct drm_connector *connector); +bool intel_wb_connector_get_hw_state(struct intel_wb_connector *connector); +enum pipe intel_wb_connector_get_pipe(struct intel_wb_connector *connector); +void intel_wb_connector_attach_encoder(struct intel_wb_connector *connector, + struct intel_encoder *encoder); + +#endif /* __INTEL_WB_CONNECTOR_H__ */ + diff --git a/drivers/gpu/drm/i915/display/intel_wd.c b/drivers/gpu/drm/i915/display/intel_wd.c new file mode 100644 index 000000000000..5ae5316f06b4 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_wd.c @@ -0,0 +1,704 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2022 Intel Corporation + */ + +#include <drm/drm_atomic_helper.h> +#include <drm/drm_fourcc.h> + +#include "intel_atomic.h" +#include "intel_connector.h" +#include "intel_wd.h" +#include "intel_fb_pin.h" +#include "intel_de.h" + +enum { + WD_CAPTURE_4_PIX, + WD_CAPTURE_2_PIX, +} wd_capture_format; + +struct drm_writeback_job +*intel_get_writeback_job_from_queue(struct intel_wd *intel_wd) +{ + struct drm_writeback_job *job; + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev); + struct drm_writeback_connector *wb_conn = + &intel_wd->wb_conn; + unsigned long flags; + + spin_lock_irqsave(&wb_conn->job_lock, flags); + job = list_first_entry_or_null(&wb_conn->job_queue, + struct drm_writeback_job, + list_entry); + spin_unlock_irqrestore(&wb_conn->job_lock, flags); + if (job == NULL) { + drm_dbg_kms(&i915->drm, "job queue is empty\n"); + return NULL; + } + + return job; +} + +/*Check with Spec*/ +static const u32 wb_fmts[] = { + DRM_FORMAT_YUV444, + DRM_FORMAT_XYUV8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_Y410, + DRM_FORMAT_YUV422, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_RGB565, +}; + +static int intel_wd_get_format(int pixel_format) +{ + int wd_format = -EINVAL; + + switch (pixel_format) { + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_XYUV8888: + case DRM_FORMAT_YUV444: + wd_format = WD_CAPTURE_4_PIX; + break; + case DRM_FORMAT_YUV422: + case DRM_FORMAT_RGB565: + wd_format = WD_CAPTURE_2_PIX; + break; + default: + DRM_ERROR("unsupported pixel format %x!\n", + pixel_format); + } + + return wd_format; +} + +static int intel_wd_verify_pix_format(int format) +{ + const struct drm_format_info *info = drm_format_info(format); + int pix_format = info->format; + int i = 0; + + for (i = 0; i < ARRAY_SIZE(wb_fmts); i++) + if (pix_format == wb_fmts[i]) + return 0; + + return 1; +} + +static u32 intel_wd_get_stride(const struct intel_crtc_state *crtc_state, + int format) +{ + const struct drm_format_info *info = drm_format_info(format); + int wd_format; + int hactive, pixel_size; + + wd_format = intel_wd_get_format(info->format); + + switch (wd_format) { + case WD_CAPTURE_4_PIX: + pixel_size = 4; + break; + case WD_CAPTURE_2_PIX: + pixel_size = 2; + break; + default: + pixel_size = 1; + break; + } + + hactive = crtc_state->hw.adjusted_mode.crtc_hdisplay; + + return DIV_ROUND_UP(hactive * pixel_size, 64); +} + +static int intel_wd_pin_fb(struct intel_wd *intel_wd, + struct drm_framebuffer *fb) +{ + const struct i915_ggtt_view view = { + .type = I915_GGTT_VIEW_NORMAL, + }; + struct i915_vma *vma; + + vma = intel_pin_and_fence_fb_obj(fb, false, &view, false, + &intel_wd->flags); + + if (IS_ERR(vma)) + return PTR_ERR(vma); + + intel_wd->vma = vma; + return 0; +} + +static void intel_configure_slicing_strategy(struct drm_i915_private *dev_priv, + struct intel_wd *intel_wd, u32 *tmp) +{ + *tmp &= ~WD_STRAT_MASK; + if (intel_wd->slicing_strategy == 1) + *tmp |= WD_SLICING_STRAT_1_1; + else if (intel_wd->slicing_strategy == 2) + *tmp |= WD_SLICING_STRAT_2_1; + else if (intel_wd->slicing_strategy == 3) + *tmp |= WD_SLICING_STRAT_4_1; + else if (intel_wd->slicing_strategy == 4) + *tmp |= WD_SLICING_STRAT_8_1; + + intel_de_write(dev_priv, WD_STREAMCAP_CTL(intel_wd->trans), + *tmp); + +} + +static enum drm_mode_status +intel_wd_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + drm_dbg_kms(connector->dev, ":"); + return MODE_OK; +} + +static int intel_wd_get_modes(struct drm_connector *connector) +{ + return 0; +} + +static void intel_wd_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + struct intel_crtc *intel_crtc = + to_intel_crtc(pipe_config->uapi.crtc); + + if (intel_crtc) { + memcpy(pipe_config, intel_crtc->config, + sizeof(*pipe_config)); + pipe_config->output_types |= BIT(INTEL_OUTPUT_WD); + } + +} + +static int intel_wd_compute_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state) +{ + struct intel_wd *intel_wd = enc_to_intel_wd(encoder); + struct drm_writeback_job *job; + + job = intel_get_writeback_job_from_queue(intel_wd); + if (job || conn_state->writeback_job) { + intel_wd->wd_crtc = to_intel_crtc(pipe_config->uapi.crtc); + return 0; + } + + return 0; +} + +static void intel_wd_get_power_domains(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_wd *intel_wd = enc_to_intel_wd(encoder); + intel_wakeref_t wakeref; + + wakeref = intel_display_power_get(i915, + encoder->power_domain); + + intel_wd->io_wakeref[0] = wakeref; +} + +static bool intel_wd_get_hw_state(struct intel_encoder *encoder, + enum pipe *pipe) +{ + bool ret = false; + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_wd *intel_wd = enc_to_intel_wd(encoder); + struct intel_crtc *wd_crtc = intel_wd->wd_crtc; + intel_wakeref_t wakeref; + u32 tmp; + + if (wd_crtc) + return false; + + wakeref = intel_display_power_get_if_enabled(dev_priv, + encoder->power_domain); + + if (!wakeref) + goto out; + + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + ret = tmp & WD_TRANS_ACTIVE; + if (ret) { + *pipe = wd_crtc->pipe; + return true; + } + +out: + intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + return false; + +} + +static int intel_wd_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_st, + struct drm_connector_state *conn_st) +{ + /* Check for the format and buffers and property validity */ + struct drm_framebuffer *fb; + struct drm_writeback_job *job = conn_st->writeback_job; + struct drm_i915_private *i915 = to_i915(encoder->dev); + const struct drm_display_mode *mode = &crtc_st->mode; + int ret; + + if (!job) { + drm_dbg_kms(&i915->drm, "No writeback job created returning\n"); + return -EINVAL; + } + + fb = job->fb; + if (!fb) { + drm_dbg_kms(&i915->drm, "Invalid framebuffer\n"); + return -EINVAL; + } + + if (fb->width != mode->hdisplay || fb->height != mode->vdisplay) { + drm_dbg_kms(&i915->drm, "Invalid framebuffer size %ux%u\n", + fb->width, fb->height); + return -EINVAL; + } + + ret = intel_wd_verify_pix_format(fb->format->format); + if (ret) { + drm_dbg_kms(&i915->drm, "Unsupported framebuffer format %08x\n", + fb->format->format); + return -EINVAL; + } + + return 0; +} + + +static const struct drm_encoder_helper_funcs wd_encoder_helper_funcs = { + .atomic_check = intel_wd_encoder_atomic_check, +}; + +static void intel_wd_connector_destroy(struct drm_connector *connector) +{ + drm_connector_cleanup(connector); + kfree(connector); +} + +static enum drm_connector_status +intel_wb_connector_detect(struct drm_connector *connector, bool force) +{ + return connector_status_connected; +} + +static const struct drm_connector_funcs wd_connector_funcs = { + .detect = intel_wb_connector_detect, + .reset = drm_atomic_helper_connector_reset, + .destroy = intel_wd_connector_destroy, + .fill_modes = drm_helper_probe_single_connector_modes, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, +}; + +static const struct drm_connector_helper_funcs wd_connector_helper_funcs = { + .get_modes = intel_wd_get_modes, + .mode_valid = intel_wd_mode_valid, +}; + +static const struct drm_encoder_funcs drm_writeback_encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +static bool intel_fastset_dis(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + return false; +} + +static void intel_wd_connector_init(struct intel_wd *intel_wd) +{ + drm_atomic_helper_connector_reset(&intel_wd->wb_conn.base); +} + +static void intel_wd_disable_capture(struct intel_wd *intel_wd) +{ + struct drm_i915_private *dev_priv = to_i915(intel_wd->base.base.dev); + u32 tmp; + + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), 0xFF); + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + tmp &= WD_TRANS_DISABLE; + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp); + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans)); + tmp |= ~TRANS_WD_FUNC_ENABLE; +} + +void intel_wd_init(struct drm_i915_private *i915, enum transcoder trans) +{ + struct intel_wd *intel_wd; + struct intel_encoder *encoder; + struct drm_writeback_connector *wb_conn; + int n_formats = ARRAY_SIZE(wb_fmts); + struct drm_encoder *drm_enc; + int err, ret; + + intel_wd = kzalloc(sizeof(*intel_wd), GFP_KERNEL); + + if (!intel_wd) + return; + + intel_wd_connector_init(intel_wd); + encoder = &intel_wd->base; + drm_enc = &encoder->base; + wb_conn = &intel_wd->wb_conn; + intel_wd->trans = trans; + intel_wd->triggered_cap_mode = 1; + intel_wd->frame_num = 1; + intel_wd->slicing_strategy = 1; + encoder->get_config = intel_wd_get_config; + encoder->compute_config = intel_wd_compute_config; + encoder->get_hw_state = intel_wd_get_hw_state; + encoder->type = INTEL_OUTPUT_WD; + encoder->cloneable = 0; + encoder->pipe_mask = ~0; + encoder->power_domain = POWER_DOMAIN_TRANSCODER_B; + encoder->get_power_domains = intel_wd_get_power_domains; + encoder->initial_fastset_check = intel_fastset_dis; + + drm_encoder_helper_add(drm_enc, + &wd_encoder_helper_funcs); + + drm_enc->possible_crtcs = ~0; + ret = drm_encoder_init(&i915->drm, drm_enc, + &drm_writeback_encoder_funcs, + DRM_MODE_ENCODER_VIRTUAL, NULL); + + if (ret) { + drm_dbg_kms(&i915->drm, + "Writeback drm_encoder init Failed: %d\n", + ret); + goto cleanup; + } + + err = drm_writeback_connector_init_with_encoder(&i915->drm, + wb_conn, drm_enc, &wd_connector_funcs, + wb_fmts, n_formats); + + if (err != 0) { + drm_dbg_kms(&i915->drm, + "drm_writeback_connector_init: Failed: %d\n", + err); + goto cleanup; + } + + wb_conn->base.encoder = drm_enc; + drm_connector_helper_add(&wb_conn->base, &wd_connector_helper_funcs); + wb_conn->base.status = connector_status_connected; + return; + +cleanup: + kfree(intel_wd); + return; +} + +static void intel_wd_writeback_complete(struct intel_wd *intel_wd, + struct drm_writeback_job *job, int status) +{ + struct drm_writeback_connector *wb_conn = + &intel_wd->wb_conn; + drm_writeback_signal_completion(wb_conn, status); +} + +static int intel_wd_setup_transcoder(struct intel_wd *intel_wd, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct drm_writeback_job *job) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); + enum pipe pipe = intel_crtc->pipe; + struct drm_framebuffer *fb; + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + struct drm_gem_object *wd_fb_obj; + int ret; + u32 stride, tmp; + u16 hactive, vactive; + + fb = job->fb; + wd_fb_obj = fb->obj[0]; + if (!wd_fb_obj) { + drm_dbg_kms(&dev_priv->drm, "No framebuffer gem object created\n"); + return -1; + } + + ret = intel_wd_pin_fb(intel_wd, fb); + drm_WARN_ON(&dev_priv->drm, ret != 0); + /*Write stride and surface registers in that particular order*/ + stride = intel_wd_get_stride(pipe_config, fb->format->format); + + tmp = intel_de_read(dev_priv, WD_STRIDE(intel_wd->trans)); + tmp &= ~WD_STRIDE_MASK; + tmp |= (stride << WD_STRIDE_SHIFT); + + intel_de_write(dev_priv, WD_STRIDE(intel_wd->trans), tmp); + + tmp = intel_de_read(dev_priv, WD_SURF(intel_wd->trans)); + + intel_de_write(dev_priv, WD_SURF(intel_wd->trans), + i915_ggtt_offset(intel_wd->vma)); + + tmp = intel_de_read_fw(dev_priv, WD_IIR(intel_wd->trans)); + intel_de_write_fw(dev_priv, WD_IIR(intel_wd->trans), tmp); + + tmp = ~(WD_GTT_FAULT_INT|WD_WRITE_COMPLETE_INT|WD_FRAME_COMPLETE_INT| + WD_VBLANK_INT|WD_OVERRUN_INT|WD_CAPTURING_INT); + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), tmp); + + if (intel_wd->stream_cap) { + tmp = intel_de_read(dev_priv, + WD_STREAMCAP_CTL(intel_wd->trans)); + tmp |= WD_STREAM_CAP_MODE_EN; + intel_configure_slicing_strategy(dev_priv, intel_wd, &tmp); + } + + hactive = pipe_config->uapi.mode.hdisplay; + vactive = pipe_config->uapi.mode.vdisplay; + tmp = intel_de_read(dev_priv, HTOTAL(intel_wd->trans)); + tmp = intel_de_read(dev_priv, VTOTAL(intel_wd->trans)); + + /* minimum hactive as per bspec: 64 pixels*/ + if (hactive < 64) + drm_err(&dev_priv->drm, "hactive is less then 64 pixels\n"); + + intel_de_write(dev_priv, HTOTAL(intel_wd->trans), hactive - 1); + intel_de_write(dev_priv, VTOTAL(intel_wd->trans), vactive - 1); + + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans)); + /* select pixel format */ + tmp &= ~WD_PIX_FMT_MASK; + + switch (fb->format->format) { + default: + fallthrough; + case DRM_FORMAT_YUYV: + tmp |= WD_PIX_FMT_YUYV; + break; + case DRM_FORMAT_XYUV8888: + tmp |= WD_PIX_FMT_XYUV8888; + break; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB8888: + tmp |= WD_PIX_FMT_XBGR8888; + break; + case DRM_FORMAT_Y410: + tmp |= WD_PIX_FMT_Y410; + break; + case DRM_FORMAT_YUV422: + tmp |= WD_PIX_FMT_YUV422; + break; + case DRM_FORMAT_XBGR2101010: + tmp |= WD_PIX_FMT_XBGR2101010; + break; + case DRM_FORMAT_RGB565: + tmp |= WD_PIX_FMT_RGB565; + break; + } + + if (intel_wd->triggered_cap_mode) + tmp |= WD_TRIGGERED_CAP_MODE_ENABLE; + + if (intel_wd->stream_cap) + tmp |= WD_CTL_POINTER_DTDH; + + /*select input pipe*/ + tmp &= ~WD_INPUT_SELECT_MASK; + switch (pipe) { + default: + fallthrough; + case PIPE_A: + tmp |= WD_INPUT_PIPE_A; + break; + case PIPE_B: + tmp |= WD_INPUT_PIPE_B; + break; + case PIPE_C: + tmp |= WD_INPUT_PIPE_C; + break; + case PIPE_D: + tmp |= WD_INPUT_PIPE_D; + break; + } + + /* enable DDI buffer */ + if (!(tmp & TRANS_WD_FUNC_ENABLE)) + tmp |= TRANS_WD_FUNC_ENABLE; + + intel_de_write(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans), tmp); + + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + ret = tmp & WD_TRANS_ACTIVE; + if (!ret) { + /*enable the transcoder */ + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + tmp |= WD_TRANS_ENABLE; + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp); + + /* wait for transcoder to be enabled */ + if (intel_de_wait_for_set(dev_priv, PIPECONF(intel_wd->trans), + WD_TRANS_ACTIVE, 10)) + drm_err(&dev_priv->drm, "WD transcoder could not be enabled\n"); + } + + return 0; +} + +static int intel_wd_capture(struct intel_wd *intel_wd, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct drm_writeback_job *job) +{ + u32 tmp; + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev); + int ret = 0, status = 0; + struct intel_crtc *wd_crtc = intel_wd->wd_crtc; + unsigned long flags; + + if (!job->out_fence) + drm_dbg_kms(&i915->drm, "Not able to get out_fence for job\n"); + + ret = intel_wd_setup_transcoder(intel_wd, pipe_config, + conn_state, job); + + if (ret < 0) { + drm_dbg_kms(&i915->drm, + "WD transcoder setup not completed aborting capture\n"); + return -1; + } + + if (wd_crtc == NULL) { + drm_err(&i915->drm, "CRTC not attached\n"); + return -1; + } + + tmp = intel_de_read_fw(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans)); + tmp |= START_TRIGGER_FRAME; + tmp &= ~WD_FRAME_NUMBER_MASK; + tmp |= intel_wd->frame_num; + intel_de_write_fw(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans), tmp); + + if (!intel_de_wait_for_set(i915, WD_IIR(intel_wd->trans), + WD_FRAME_COMPLETE_INT, 100)){ + drm_dbg_kms(&i915->drm, "frame captured\n"); + status = 0; + } else { + drm_dbg_kms(&i915->drm, "frame not captured triggering stop frame\n"); + tmp = intel_de_read(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans)); + tmp |= STOP_TRIGGER_FRAME; + intel_de_write(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans), tmp); + status = -1; + } + + intel_wd_writeback_complete(intel_wd, job, status); + if (wd_crtc->wd.e) { + spin_lock_irqsave(&i915->drm.event_lock, flags); + drm_dbg_kms(&i915->drm, "send %p\n", wd_crtc->wd.e); + drm_crtc_send_vblank_event(&wd_crtc->base, + wd_crtc->wd.e); + spin_unlock_irqrestore(&i915->drm.event_lock, flags); + wd_crtc->wd.e = NULL; + } else { + drm_err(&i915->drm, "Event NULL! %p, %p\n", &i915->drm, + wd_crtc); + } + if (intel_get_writeback_job_from_queue(intel_wd) == NULL) + intel_wd_disable_capture(intel_wd); + return 0; + +} + +void intel_wd_enable_capture(struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state) +{ + struct drm_i915_private *i915 = + to_i915(conn_state->connector->dev); + struct drm_writeback_connector *wb_conn = + drm_connector_to_writeback(conn_state->connector); + struct intel_wd *intel_wd = wb_conn_to_intel_wd(wb_conn); + struct drm_writeback_job *job; + + job = intel_get_writeback_job_from_queue(intel_wd); + if (job == NULL) { + drm_dbg_kms(&i915->drm, + "job queue is empty not capturing any frame\n"); + return; + } + + intel_wd_capture(intel_wd, pipe_config, + conn_state, job); + intel_wd->frame_num += 1; + +} + +void intel_wd_set_vblank_event(struct intel_atomic_state *state, struct intel_crtc *intel_crtc, + struct intel_crtc_state *intel_crtc_state) +{ + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + struct drm_crtc_state *crtc_state = &intel_crtc_state->uapi; + struct intel_encoder *encoder; + struct intel_wd *intel_wd; + struct drm_connector_state *conn_state; + struct drm_connector *connector; + int i; + + for_each_intel_encoder(&i915->drm, encoder) { + + if (encoder->type != INTEL_OUTPUT_WD) + continue; + + intel_wd = enc_to_intel_wd(encoder); + if (!intel_wd->wd_crtc) + return; + } + + if (intel_crtc == intel_wd->wd_crtc) { + for_each_new_connector_in_state(&state->base, connector, conn_state, + i) { + if (!conn_state->writeback_job) + continue; + + intel_crtc->wd.e = crtc_state->event; + crtc_state->event = NULL; + } + } +} +void intel_wd_handle_isr(struct drm_i915_private *i915) +{ + u32 iir_value = 0; + struct intel_encoder *encoder; + struct intel_wd *intel_wd; + + iir_value = intel_de_read(i915, WD_IIR(TRANSCODER_WD_0)); + + for_each_intel_encoder(&i915->drm, encoder) { + + if (encoder->type != INTEL_OUTPUT_WD) + continue; + + intel_wd = enc_to_intel_wd(encoder); + if (!intel_wd->wd_crtc) { + drm_err(&i915->drm, "NO CRTC attached with WD\n"); + goto clear_iir; + } + } + + if (iir_value & WD_FRAME_COMPLETE_INT) + return; + +clear_iir: + intel_de_write(i915, WD_IIR(TRANSCODER_WD_0), iir_value); +} diff --git a/drivers/gpu/drm/i915/display/intel_wd.h b/drivers/gpu/drm/i915/display/intel_wd.h new file mode 100644 index 000000000000..0fcd1a746593 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_wd.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT*/ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef _INTEL_WD_H +#define _INTEL_WD_H + +#include <drm/drm_crtc.h> + +#include "intel_display_types.h" + +#define I915_MAX_WD_TANSCODERS 2 + +struct intel_wd { + struct intel_encoder base; + struct drm_writeback_connector wb_conn; + struct intel_crtc *wd_crtc; + intel_wakeref_t io_wakeref[I915_MAX_WD_TANSCODERS]; + enum transcoder trans; + struct i915_vma *vma; + unsigned long flags; + struct drm_writeback_job *job; + int triggered_cap_mode; + int frame_num; + bool stream_cap; + bool start_capture; + int slicing_strategy; +}; + +static inline struct intel_wd *enc_to_intel_wd(struct intel_encoder *encoder) +{ + return container_of(&encoder->base, struct intel_wd, base.base); +} + +static inline struct intel_wd *wb_conn_to_intel_wd(struct drm_writeback_connector *wb_conn) +{ + return container_of(wb_conn, struct intel_wd, wb_conn); +} + +void intel_wd_init(struct drm_i915_private *dev_priv, enum transcoder trans); +void intel_wd_enable_capture(struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state); +void intel_wd_handle_isr(struct drm_i915_private *dev_priv); +void intel_wd_set_vblank_event(struct intel_atomic_state *state, struct intel_crtc *crtc, + struct intel_crtc_state *crtc_state); +struct drm_writeback_job *intel_get_writeback_job_from_queue(struct intel_wd *intel_wd); +#endif/* _INTEL_WD_H */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 086bbe8945d6..73ef94757fc8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -35,6 +35,7 @@ #include <linux/pm_qos.h> #include <drm/drm_connector.h> +#include <drm/drm_writeback.h> #include <drm/ttm/ttm_device.h> #include "display/intel_cdclk.h" diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 0389f532d926..6504ef528d90 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -42,6 +42,7 @@ #include "display/intel_hotplug.h" #include "display/intel_lpe_audio.h" #include "display/intel_psr.h" +#include "display/intel_wd.h" #include "gt/intel_breadcrumbs.h" #include "gt/intel_gt.h" @@ -2342,6 +2343,11 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) found = true; } + if (iir & GEN8_DE_MISC_WD0) { + intel_wd_handle_isr(dev_priv); + found = true; + } + if (iir & GEN8_DE_EDP_PSR) { struct intel_encoder *encoder; u32 psr_iir; @@ -3767,7 +3773,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) u32 de_pipe_enables; u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); u32 de_port_enables; - u32 de_misc_masked = GEN8_DE_EDP_PSR; + u32 de_misc_masked = GEN8_DE_EDP_PSR | GEN8_DE_MISC_WD0; u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D); enum pipe pipe; diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index aacc10f2e73f..bf4f1a7968c5 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -864,7 +864,8 @@ static const struct intel_device_info jsl_info = { .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1)| \ + BIT(TRANSCODER_WD_0), \ .display.pipe_offsets = { \ [TRANSCODER_A] = PIPE_A_OFFSET, \ [TRANSCODER_B] = PIPE_B_OFFSET, \ @@ -872,6 +873,8 @@ static const struct intel_device_info jsl_info = { [TRANSCODER_D] = PIPE_D_OFFSET, \ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ + [TRANSCODER_WD_0] = PIPE_WD0_OFFSET, \ + [TRANSCODER_WD_1] = PIPE_WD1_OFFSET, \ }, \ .display.trans_offsets = { \ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ @@ -880,6 +883,8 @@ static const struct intel_device_info jsl_info = { [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ + [TRANSCODER_WD_0] = TRANSCODER_WD0_OFFSET, \ + [TRANSCODER_WD_1] = TRANSCODER_WD1_OFFSET, \ }, \ TGL_CURSOR_OFFSETS, \ .has_global_mocs = 1, \ -- 2.37.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Pipewriteback 2022-08-18 10:36 [Intel-gfx] [PATCH 0/3] Enable Pipewriteback Suraj Kandpal ` (2 preceding siblings ...) 2022-08-18 10:36 ` [Intel-gfx] [PATCH 3/3] drm/i915: Enabling WD Transcoder Suraj Kandpal @ 2022-08-18 13:23 ` Patchwork 2022-08-18 13:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-08-18 13:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2022-08-18 13:23 UTC (permalink / raw) To: Suraj Kandpal; +Cc: intel-gfx == Series Details == Series: Enable Pipewriteback URL : https://patchwork.freedesktop.org/series/107440/ State : warning == Summary == Error: dim checkpatch failed c89414f4d5ea drm/i915: Define WD trancoder for i915 -:68: CHECK:LINE_SPACING: Please don't use multiple blank lines #68: FILE: drivers/gpu/drm/i915/i915_reg.h:3728: + + total: 0 errors, 0 warnings, 1 checks, 194 lines checked cbd7b9684e83 drm/i915 : Changing intel_connector iterators -:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #56: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1506: +#define to_intel_connector(x) (((x->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)) ? \ + NULL : container_of(x, struct intel_connector, base)) -:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #56: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1506: +#define to_intel_connector(x) (((x->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)) ? \ + NULL : container_of(x, struct intel_connector, base)) -:84: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #84: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:2092: + + } total: 0 errors, 0 warnings, 3 checks, 84 lines checked 658200363d65 drm/i915: Enabling WD Transcoder Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in <module> import git ModuleNotFoundError: No module named 'git' Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in <module> import git ModuleNotFoundError: No module named 'git' Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in <module> import git ModuleNotFoundError: No module named 'git' -:125: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #125: FILE: drivers/gpu/drm/i915/display/intel_display.c:1559: +static void intel_queue_writeback_job(struct intel_atomic_state *state, + struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) -:143: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #143: FILE: drivers/gpu/drm/i915/display/intel_display.c:1577: +static void intel_enable_writeback_capture(struct intel_atomic_state *state, + struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) -:534: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #534: new file mode 100644 -:555: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #555: FILE: drivers/gpu/drm/i915/display/intel_wb_connector.h:17: +void intel_wb_connector_attach_encoder(struct intel_wb_connector *connector, + struct intel_encoder *encoder); -:595: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #595: FILE: drivers/gpu/drm/i915/display/intel_wd.c:31: + job = list_first_entry_or_null(&wb_conn->job_queue, + struct drm_writeback_job, -:598: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!job" #598: FILE: drivers/gpu/drm/i915/display/intel_wd.c:34: + if (job == NULL) { -:636: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #636: FILE: drivers/gpu/drm/i915/display/intel_wd.c:72: + DRM_ERROR("unsupported pixel format %x!\n", + pixel_format); -:656: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #656: FILE: drivers/gpu/drm/i915/display/intel_wd.c:92: +static u32 intel_wd_get_stride(const struct intel_crtc_state *crtc_state, + int format) -:682: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #682: FILE: drivers/gpu/drm/i915/display/intel_wd.c:118: +static int intel_wd_pin_fb(struct intel_wd *intel_wd, + struct drm_framebuffer *fb) -:690: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #690: FILE: drivers/gpu/drm/i915/display/intel_wd.c:126: + vma = intel_pin_and_fence_fb_obj(fb, false, &view, false, + &intel_wd->flags); -:700: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #700: FILE: drivers/gpu/drm/i915/display/intel_wd.c:136: +static void intel_configure_slicing_strategy(struct drm_i915_private *dev_priv, + struct intel_wd *intel_wd, u32 *tmp) -:713: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #713: FILE: drivers/gpu/drm/i915/display/intel_wd.c:149: + intel_de_write(dev_priv, WD_STREAMCAP_CTL(intel_wd->trans), + *tmp); -:715: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #715: FILE: drivers/gpu/drm/i915/display/intel_wd.c:151: + +} -:719: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #719: FILE: drivers/gpu/drm/i915/display/intel_wd.c:155: +intel_wd_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) -:731: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #731: FILE: drivers/gpu/drm/i915/display/intel_wd.c:167: +static void intel_wd_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) -:738: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #738: FILE: drivers/gpu/drm/i915/display/intel_wd.c:174: + memcpy(pipe_config, intel_crtc->config, + sizeof(*pipe_config)); -:742: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #742: FILE: drivers/gpu/drm/i915/display/intel_wd.c:178: + +} -:745: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #745: FILE: drivers/gpu/drm/i915/display/intel_wd.c:181: +static int intel_wd_compute_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config, -:761: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #761: FILE: drivers/gpu/drm/i915/display/intel_wd.c:197: +static void intel_wd_get_power_domains(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) -:768: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #768: FILE: drivers/gpu/drm/i915/display/intel_wd.c:204: + wakeref = intel_display_power_get(i915, + encoder->power_domain); -:774: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #774: FILE: drivers/gpu/drm/i915/display/intel_wd.c:210: +static bool intel_wd_get_hw_state(struct intel_encoder *encoder, + enum pipe *pipe) -:787: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #787: FILE: drivers/gpu/drm/i915/display/intel_wd.c:223: + wakeref = intel_display_power_get_if_enabled(dev_priv, + encoder->power_domain); -:803: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #803: FILE: drivers/gpu/drm/i915/display/intel_wd.c:239: + +} -:806: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #806: FILE: drivers/gpu/drm/i915/display/intel_wd.c:242: +static int intel_wd_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_st, -:829: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #829: FILE: drivers/gpu/drm/i915/display/intel_wd.c:265: + drm_dbg_kms(&i915->drm, "Invalid framebuffer size %ux%u\n", + fb->width, fb->height); -:836: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #836: FILE: drivers/gpu/drm/i915/display/intel_wd.c:272: + drm_dbg_kms(&i915->drm, "Unsupported framebuffer format %08x\n", + fb->format->format); -:843: CHECK:LINE_SPACING: Please don't use multiple blank lines #843: FILE: drivers/gpu/drm/i915/display/intel_wd.c:279: + + -:879: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #879: FILE: drivers/gpu/drm/i915/display/intel_wd.c:315: +static bool intel_fastset_dis(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) -:935: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #935: FILE: drivers/gpu/drm/i915/display/intel_wd.c:371: + drm_encoder_helper_add(drm_enc, + &wd_encoder_helper_funcs); -:944: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #944: FILE: drivers/gpu/drm/i915/display/intel_wd.c:380: + drm_dbg_kms(&i915->drm, + "Writeback drm_encoder init Failed: %d\n", -:950: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #950: FILE: drivers/gpu/drm/i915/display/intel_wd.c:386: + err = drm_writeback_connector_init_with_encoder(&i915->drm, + wb_conn, drm_enc, &wd_connector_funcs, -:955: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #955: FILE: drivers/gpu/drm/i915/display/intel_wd.c:391: + drm_dbg_kms(&i915->drm, + "drm_writeback_connector_init: Failed: %d\n", -:968: WARNING:RETURN_VOID: void function return statements are not generally useful #968: FILE: drivers/gpu/drm/i915/display/intel_wd.c:404: + return; +} -:971: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #971: FILE: drivers/gpu/drm/i915/display/intel_wd.c:407: +static void intel_wd_writeback_complete(struct intel_wd *intel_wd, + struct drm_writeback_job *job, int status) -:979: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #979: FILE: drivers/gpu/drm/i915/display/intel_wd.c:415: +static int intel_wd_setup_transcoder(struct intel_wd *intel_wd, + struct intel_crtc_state *pipe_config, -:1013: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1013: FILE: drivers/gpu/drm/i915/display/intel_wd.c:449: + intel_de_write(dev_priv, WD_SURF(intel_wd->trans), + i915_ggtt_offset(intel_wd->vma)); -:1018: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV) #1018: FILE: drivers/gpu/drm/i915/display/intel_wd.c:454: + tmp = ~(WD_GTT_FAULT_INT|WD_WRITE_COMPLETE_INT|WD_FRAME_COMPLETE_INT| ^ -:1018: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV) #1018: FILE: drivers/gpu/drm/i915/display/intel_wd.c:454: + tmp = ~(WD_GTT_FAULT_INT|WD_WRITE_COMPLETE_INT|WD_FRAME_COMPLETE_INT| ^ -:1018: CHECK:SPACING: space preferred before that '|' (ctx:VxE) #1018: FILE: drivers/gpu/drm/i915/display/intel_wd.c:454: + tmp = ~(WD_GTT_FAULT_INT|WD_WRITE_COMPLETE_INT|WD_FRAME_COMPLETE_INT| ^ -:1019: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV) #1019: FILE: drivers/gpu/drm/i915/display/intel_wd.c:455: + WD_VBLANK_INT|WD_OVERRUN_INT|WD_CAPTURING_INT); ^ -:1019: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV) #1019: FILE: drivers/gpu/drm/i915/display/intel_wd.c:455: + WD_VBLANK_INT|WD_OVERRUN_INT|WD_CAPTURING_INT); ^ -:1024: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1024: FILE: drivers/gpu/drm/i915/display/intel_wd.c:460: + tmp = intel_de_read(dev_priv, + WD_STREAMCAP_CTL(intel_wd->trans)); -:1113: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1113: FILE: drivers/gpu/drm/i915/display/intel_wd.c:549: + if (intel_de_wait_for_set(dev_priv, PIPECONF(intel_wd->trans), + WD_TRANS_ACTIVE, 10)) -:1121: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1121: FILE: drivers/gpu/drm/i915/display/intel_wd.c:557: +static int intel_wd_capture(struct intel_wd *intel_wd, + struct intel_crtc_state *pipe_config, -:1135: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1135: FILE: drivers/gpu/drm/i915/display/intel_wd.c:571: + ret = intel_wd_setup_transcoder(intel_wd, pipe_config, + conn_state, job); -:1139: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1139: FILE: drivers/gpu/drm/i915/display/intel_wd.c:575: + drm_dbg_kms(&i915->drm, + "WD transcoder setup not completed aborting capture\n"); -:1143: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!wd_crtc" #1143: FILE: drivers/gpu/drm/i915/display/intel_wd.c:579: + if (wd_crtc == NULL) { -:1149: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1149: FILE: drivers/gpu/drm/i915/display/intel_wd.c:585: + tmp = intel_de_read_fw(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans)); -:1154: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1154: FILE: drivers/gpu/drm/i915/display/intel_wd.c:590: + intel_de_write_fw(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans), tmp); -:1157: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1157: FILE: drivers/gpu/drm/i915/display/intel_wd.c:593: + if (!intel_de_wait_for_set(i915, WD_IIR(intel_wd->trans), + WD_FRAME_COMPLETE_INT, 100)){ -:1163: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1163: FILE: drivers/gpu/drm/i915/display/intel_wd.c:599: + tmp = intel_de_read(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans)); -:1166: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1166: FILE: drivers/gpu/drm/i915/display/intel_wd.c:602: + intel_de_write(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans), tmp); -:1175: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1175: FILE: drivers/gpu/drm/i915/display/intel_wd.c:611: + drm_crtc_send_vblank_event(&wd_crtc->base, + wd_crtc->wd.e); -:1182: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!intel_get_writeback_job_from_queue" #1182: FILE: drivers/gpu/drm/i915/display/intel_wd.c:618: + if (intel_get_writeback_job_from_queue(intel_wd) == NULL) -:1186: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #1186: FILE: drivers/gpu/drm/i915/display/intel_wd.c:622: + +} -:1189: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1189: FILE: drivers/gpu/drm/i915/display/intel_wd.c:625: +void intel_wd_enable_capture(struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state) -:1199: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!job" #1199: FILE: drivers/gpu/drm/i915/display/intel_wd.c:635: + if (job == NULL) { -:1201: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1201: FILE: drivers/gpu/drm/i915/display/intel_wd.c:637: + drm_dbg_kms(&i915->drm, + "job queue is empty not capturing any frame\n"); -:1206: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1206: FILE: drivers/gpu/drm/i915/display/intel_wd.c:642: + intel_wd_capture(intel_wd, pipe_config, + conn_state, job); -:1209: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #1209: FILE: drivers/gpu/drm/i915/display/intel_wd.c:645: + +} -:1212: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1212: FILE: drivers/gpu/drm/i915/display/intel_wd.c:648: +void intel_wd_set_vblank_event(struct intel_atomic_state *state, struct intel_crtc *intel_crtc, + struct intel_crtc_state *intel_crtc_state) -:1223: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' #1223: FILE: drivers/gpu/drm/i915/display/intel_wd.c:659: + for_each_intel_encoder(&i915->drm, encoder) { + -:1243: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #1243: FILE: drivers/gpu/drm/i915/display/intel_wd.c:679: +} +void intel_wd_handle_isr(struct drm_i915_private *i915) -:1252: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' #1252: FILE: drivers/gpu/drm/i915/display/intel_wd.c:688: + for_each_intel_encoder(&i915->drm, encoder) { + -:1317: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1317: FILE: drivers/gpu/drm/i915/display/intel_wd.h:43: +void intel_wd_enable_capture(struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state); -:1320: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1320: FILE: drivers/gpu/drm/i915/display/intel_wd.h:46: +void intel_wd_set_vblank_event(struct intel_atomic_state *state, struct intel_crtc *crtc, + struct intel_crtc_state *crtc_state); -:1377: CHECK:SPACING: spaces preferred around that '|' (ctx:VxE) #1377: FILE: drivers/gpu/drm/i915/i915_pci.c:868: + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1)| \ ^ total: 0 errors, 2 warnings, 65 checks, 1268 lines checked ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable Pipewriteback 2022-08-18 10:36 [Intel-gfx] [PATCH 0/3] Enable Pipewriteback Suraj Kandpal ` (3 preceding siblings ...) 2022-08-18 13:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Pipewriteback Patchwork @ 2022-08-18 13:23 ` Patchwork 2022-08-18 13:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2022-08-18 13:23 UTC (permalink / raw) To: Suraj Kandpal; +Cc: intel-gfx == Series Details == Series: Enable Pipewriteback URL : https://patchwork.freedesktop.org/series/107440/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Enable Pipewriteback 2022-08-18 10:36 [Intel-gfx] [PATCH 0/3] Enable Pipewriteback Suraj Kandpal ` (4 preceding siblings ...) 2022-08-18 13:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2022-08-18 13:33 ` Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2022-08-18 13:33 UTC (permalink / raw) To: Suraj Kandpal; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 13413 bytes --] == Series Details == Series: Enable Pipewriteback URL : https://patchwork.freedesktop.org/series/107440/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11997 -> Patchwork_107440v1 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_107440v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107440v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/index.html Participating hosts (33 -> 29) ------------------------------ Additional (1): fi-kbl-soraka Missing (5): bat-dg1-6 bat-dg1-5 fi-icl-u2 bat-rplp-1 bat-rpls-2 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_107440v1: ### IGT changes ### #### Possible regressions #### * igt@i915_module_load@load: - fi-ilk-650: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-ilk-650/igt@i915_module_load@load.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-ilk-650/igt@i915_module_load@load.html - fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-blb-e6850/igt@i915_module_load@load.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-blb-e6850/igt@i915_module_load@load.html - fi-skl-6600u: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-skl-6600u/igt@i915_module_load@load.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-skl-6600u/igt@i915_module_load@load.html - fi-bdw-gvtdvm: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-bdw-gvtdvm/igt@i915_module_load@load.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-bdw-gvtdvm/igt@i915_module_load@load.html - fi-pnv-d510: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-pnv-d510/igt@i915_module_load@load.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-pnv-d510/igt@i915_module_load@load.html - fi-snb-2520m: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-snb-2520m/igt@i915_module_load@load.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-snb-2520m/igt@i915_module_load@load.html - fi-skl-6700k2: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-skl-6700k2/igt@i915_module_load@load.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-skl-6700k2/igt@i915_module_load@load.html - fi-kbl-7567u: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-kbl-7567u/igt@i915_module_load@load.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-kbl-7567u/igt@i915_module_load@load.html - fi-cfl-8700k: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-cfl-8700k/igt@i915_module_load@load.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-cfl-8700k/igt@i915_module_load@load.html - fi-elk-e7500: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-elk-e7500/igt@i915_module_load@load.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-elk-e7500/igt@i915_module_load@load.html - fi-bsw-nick: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-bsw-nick/igt@i915_module_load@load.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-bsw-nick/igt@i915_module_load@load.html - fi-hsw-g3258: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-hsw-g3258/igt@i915_module_load@load.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-hsw-g3258/igt@i915_module_load@load.html - fi-bsw-kefka: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-bsw-kefka/igt@i915_module_load@load.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-bsw-kefka/igt@i915_module_load@load.html - fi-cfl-guc: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-cfl-guc/igt@i915_module_load@load.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-cfl-guc/igt@i915_module_load@load.html - fi-bdw-5557u: [PASS][29] -> [INCOMPLETE][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-bdw-5557u/igt@i915_module_load@load.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-bdw-5557u/igt@i915_module_load@load.html - fi-hsw-4770: [PASS][31] -> [INCOMPLETE][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-hsw-4770/igt@i915_module_load@load.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-hsw-4770/igt@i915_module_load@load.html - fi-ivb-3770: [PASS][33] -> [INCOMPLETE][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-ivb-3770/igt@i915_module_load@load.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-ivb-3770/igt@i915_module_load@load.html #### Warnings #### * igt@i915_module_load@load: - fi-rkl-11600: [DMESG-WARN][35] ([i915#6599]) -> [INCOMPLETE][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-rkl-11600/igt@i915_module_load@load.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-rkl-11600/igt@i915_module_load@load.html - fi-glk-j4005: [DMESG-WARN][37] ([i915#6599]) -> [INCOMPLETE][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-glk-j4005/igt@i915_module_load@load.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-glk-j4005/igt@i915_module_load@load.html - fi-rkl-guc: [DMESG-WARN][39] ([i915#6599]) -> [INCOMPLETE][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-rkl-guc/igt@i915_module_load@load.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-rkl-guc/igt@i915_module_load@load.html - fi-adl-ddr5: [DMESG-WARN][41] ([i915#6599]) -> [INCOMPLETE][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-adl-ddr5/igt@i915_module_load@load.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-adl-ddr5/igt@i915_module_load@load.html - fi-cfl-8109u: [DMESG-WARN][43] ([i915#6599]) -> [INCOMPLETE][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-cfl-8109u/igt@i915_module_load@load.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-cfl-8109u/igt@i915_module_load@load.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_module_load@load: - {fi-jsl-1}: [DMESG-WARN][45] ([i915#6599]) -> [INCOMPLETE][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-jsl-1/igt@i915_module_load@load.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-jsl-1/igt@i915_module_load@load.html - {fi-ehl-2}: [DMESG-WARN][47] ([i915#6599]) -> [INCOMPLETE][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-ehl-2/igt@i915_module_load@load.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-ehl-2/igt@i915_module_load@load.html - {fi-tgl-dsi}: [PASS][49] -> [DMESG-WARN][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-tgl-dsi/igt@i915_module_load@load.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-tgl-dsi/igt@i915_module_load@load.html Known issues ------------ Here are the changes found in Patchwork_107440v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@runner@aborted: - fi-hsw-4770: NOTRUN -> [FAIL][51] ([i915#4312] / [i915#5594] / [i915#6246]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-hsw-4770/igt@runner@aborted.html - fi-skl-6700k2: NOTRUN -> [FAIL][52] ([i915#4312] / [i915#6599]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-skl-6700k2/igt@runner@aborted.html - fi-ivb-3770: NOTRUN -> [FAIL][53] ([i915#4312] / [i915#6219]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-ivb-3770/igt@runner@aborted.html - fi-elk-e7500: NOTRUN -> [FAIL][54] ([i915#4312]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-elk-e7500/igt@runner@aborted.html - fi-ilk-650: NOTRUN -> [FAIL][55] ([i915#4312] / [i915#4991]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-ilk-650/igt@runner@aborted.html - fi-skl-6600u: NOTRUN -> [FAIL][56] ([i915#4312] / [i915#6599]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-skl-6600u/igt@runner@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][57] ([i915#4312]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-bdw-5557u/igt@runner@aborted.html - fi-snb-2520m: NOTRUN -> [FAIL][58] ([i915#4312]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-snb-2520m/igt@runner@aborted.html - fi-kbl-soraka: NOTRUN -> [FAIL][59] ([i915#6219]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-kbl-soraka/igt@runner@aborted.html - fi-kbl-7567u: NOTRUN -> [FAIL][60] ([i915#4312] / [i915#6219]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-kbl-7567u/igt@runner@aborted.html - fi-cfl-8700k: NOTRUN -> [FAIL][61] ([i915#4312] / [i915#6599]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-cfl-8700k/igt@runner@aborted.html - fi-bsw-nick: NOTRUN -> [FAIL][62] ([i915#4312]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-bsw-nick/igt@runner@aborted.html - fi-hsw-g3258: NOTRUN -> [FAIL][63] ([i915#4312] / [i915#6246]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-hsw-g3258/igt@runner@aborted.html - fi-bdw-gvtdvm: NOTRUN -> [FAIL][64] ([i915#4312]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-bdw-gvtdvm/igt@runner@aborted.html - fi-bsw-kefka: NOTRUN -> [FAIL][65] ([i915#4312]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-bsw-kefka/igt@runner@aborted.html - fi-cfl-guc: NOTRUN -> [FAIL][66] ([i915#4312] / [i915#6599]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-cfl-guc/igt@runner@aborted.html #### Warnings #### * igt@runner@aborted: - fi-blb-e6850: [FAIL][67] ([fdo#109271] / [i915#2403] / [i915#4312]) -> [FAIL][68] ([i915#2403] / [i915#4312]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-blb-e6850/igt@runner@aborted.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-blb-e6850/igt@runner@aborted.html - fi-pnv-d510: [FAIL][69] ([fdo#109271] / [i915#2403] / [i915#4312]) -> [FAIL][70] ([i915#2403] / [i915#4312]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11997/fi-pnv-d510/igt@runner@aborted.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/fi-pnv-d510/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594 [i915#6219]: https://gitlab.freedesktop.org/drm/intel/issues/6219 [i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246 [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599 Build changes ------------- * Linux: CI_DRM_11997 -> Patchwork_107440v1 CI-20190529: 20190529 CI_DRM_11997: ce38effc5cd7cb2af612fd8946149275e3c1f919 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6630: b5e2222c9a988015bdf237e6ebb9f5b6d87ac7e1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_107440v1: ce38effc5cd7cb2af612fd8946149275e3c1f919 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 4d41c988c5f9 drm/i915: Enabling WD Transcoder 6d45603d6e79 drm/i915 : Changing intel_connector iterators 75d4ba983cb6 drm/i915: Define WD trancoder for i915 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v1/index.html [-- Attachment #2: Type: text/html, Size: 17024 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 0/3] Enable Pipewriteback Framework @ 2022-08-22 19:24 Kandpal, Suraj 2022-08-22 19:24 ` [Intel-gfx] [PATCH 3/3] drm/i915: Enabling WD Transcoder Kandpal, Suraj 0 siblings, 1 reply; 9+ messages in thread From: Kandpal, Suraj @ 2022-08-22 19:24 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula A patch series was floated in the drm mailing list which aimed to change the drm_connector and drm_encoder fields to pointer in the drm_connector_writeback structure, this received a huge pushback from the community but since i915 expects each connector present in the drm_device list to be a intel_connector but drm_writeback framework makes us have a connector which cannot be embedded in an intel_connector structure. [1] https://patchwork.kernel.org/project/dri-devel/patch/20220202081702.22119-1-suraj.kandpal@intel.com/ [2] https://patchwork.kernel.org/project/dri-devel/patch/20220202085429.22261-6-suraj.kandpal@intel.com/ Since no one had an issue with encoder field being changed into a pointer it was decided to break the connector and encoder pointer changes into two different series.The encoder field changes is currently being worked upon by Abhinav Kumar and the changes have been merged. [3]https://patchwork.kernel.org/project/dri-devel/list/?series=633565 Going forward we use a drm_connector which is not embedded in intel_connector. We also create a intel_encoder to avoid changes to many iterators but no intel_connector. We also changed all iterators that go through connectors and add a check to only cast connectors which are not writeback connectors. I had also floated a previous series to Enable writeback but floating a new one as i created an extra patch in this series as suggested by Jani, Nikula for intel_connector iterator changes. Please go check the below link if interested. [4]https://patchwork.freedesktop.org/series/106902/ Suraj Kandpal (3): drm/i915: Define WD trancoder for i915 drm/i915 : Changing intel_connector iterators drm/i915: Enabling WD Transcoder drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_acpi.c | 1 + drivers/gpu/drm/i915/display/intel_crtc.c | 6 + .../drm/i915/display/intel_crtc_state_dump.c | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 6 + drivers/gpu/drm/i915/display/intel_display.c | 65 +- drivers/gpu/drm/i915/display/intel_display.h | 18 +- .../drm/i915/display/intel_display_debugfs.c | 13 +- .../drm/i915/display/intel_display_types.h | 33 +- drivers/gpu/drm/i915/display/intel_dpll.c | 6 + .../drm/i915/display/intel_modeset_setup.c | 119 ++- .../drm/i915/display/intel_modeset_verify.c | 17 +- drivers/gpu/drm/i915/display/intel_opregion.c | 3 + .../gpu/drm/i915/display/intel_wb_connector.h | 20 + drivers/gpu/drm/i915/display/intel_wd.c | 699 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_wd.h | 48 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 8 +- drivers/gpu/drm/i915/i915_pci.c | 7 +- drivers/gpu/drm/i915/i915_reg.h | 139 ++++ 20 files changed, 1156 insertions(+), 55 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_wb_connector.h create mode 100644 drivers/gpu/drm/i915/display/intel_wd.c create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h -- 2.25.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915: Enabling WD Transcoder 2022-08-22 19:24 [Intel-gfx] [PATCH 0/3] Enable Pipewriteback Framework Kandpal, Suraj @ 2022-08-22 19:24 ` Kandpal, Suraj 0 siblings, 0 replies; 9+ messages in thread From: Kandpal, Suraj @ 2022-08-22 19:24 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula From: Suraj Kandpal <suraj.kandpal@intel.com> Adding support for writeback transcoder to start capturing frames using interrupt mechanism Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_acpi.c | 1 + drivers/gpu/drm/i915/display/intel_crtc.c | 6 + .../drm/i915/display/intel_crtc_state_dump.c | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 6 + drivers/gpu/drm/i915/display/intel_display.c | 65 +- drivers/gpu/drm/i915/display/intel_display.h | 5 + .../drm/i915/display/intel_display_debugfs.c | 13 +- .../drm/i915/display/intel_display_types.h | 6 + drivers/gpu/drm/i915/display/intel_dpll.c | 6 + .../drm/i915/display/intel_modeset_setup.c | 103 ++- .../drm/i915/display/intel_modeset_verify.c | 17 +- drivers/gpu/drm/i915/display/intel_opregion.c | 3 + .../gpu/drm/i915/display/intel_wb_connector.h | 20 + drivers/gpu/drm/i915/display/intel_wd.c | 699 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_wd.h | 48 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 8 +- drivers/gpu/drm/i915/i915_pci.c | 7 +- 19 files changed, 970 insertions(+), 46 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_wb_connector.h create mode 100644 drivers/gpu/drm/i915/display/intel_wd.c create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 522ef9b4aff3..ec63ed16c250 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -302,6 +302,7 @@ i915-y += \ display/intel_tv.o \ display/intel_vdsc.o \ display/intel_vrr.o \ + display/intel_wd.o \ display/vlv_dsi.o \ display/vlv_dsi_pll.o diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c b/drivers/gpu/drm/i915/display/intel_acpi.c index e78430001f07..ae08db164f73 100644 --- a/drivers/gpu/drm/i915/display/intel_acpi.c +++ b/drivers/gpu/drm/i915/display/intel_acpi.c @@ -247,6 +247,7 @@ static u32 acpi_display_type(struct intel_connector *connector) case DRM_MODE_CONNECTOR_LVDS: case DRM_MODE_CONNECTOR_eDP: case DRM_MODE_CONNECTOR_DSI: + case DRM_MODE_CONNECTOR_WRITEBACK: display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL; break; case DRM_MODE_CONNECTOR_Unknown: diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 6792a9056f46..66d552758720 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -491,6 +491,9 @@ void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state) if (new_crtc_state->do_async_flip) return; + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD)) + return; + if (intel_crtc_needs_vblank_work(new_crtc_state)) intel_crtc_vblank_work_init(new_crtc_state); @@ -638,6 +641,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) if (new_crtc_state->do_async_flip) return; + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD)) + return; + trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end); /* diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index e9212f69c360..8435065f3b7d 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -71,6 +71,7 @@ static const char * const output_type_str[] = { OUTPUT_TYPE(DSI), OUTPUT_TYPE(DDI), OUTPUT_TYPE(DP_MST), + OUTPUT_TYPE(WD), }; #undef OUTPUT_TYPE diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a4c8493f3ce7..1360406ca531 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1974,6 +1974,12 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) */ if (encoder->type == INTEL_OUTPUT_DP_MST) return; + /* + * WD transcoder is a virtual encoder hence sanization + * is not required for it + */ + if (encoder->type == INTEL_OUTPUT_WD) + return; if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { u8 pipe_mask; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f143adefdf38..52fb23846856 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -115,6 +115,7 @@ #include "intel_sprite.h" #include "intel_tc.h" #include "intel_vga.h" +#include "intel_wd.h" #include "i9xx_plane.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -1510,6 +1511,9 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state) continue; intel_connector = to_intel_connector(connector); + if (!intel_connector) + continue; + encoder = intel_connector_primary_encoder(intel_connector); if (!encoder->update_prepare) continue; @@ -1539,6 +1543,9 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state) continue; intel_connector = to_intel_connector(connector); + if (!intel_connector) + continue; + encoder = intel_connector_primary_encoder(intel_connector); if (!encoder->update_complete) continue; @@ -1549,6 +1556,39 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state) } } +static void intel_queue_writeback_job(struct intel_atomic_state *state, + struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) +{ + struct drm_connector_state *new_conn_state; + struct drm_connector *connector; + struct drm_writeback_connector *wb_conn; + int i; + + for_each_new_connector_in_state(&state->base, connector, new_conn_state, + i) { + if (!new_conn_state->writeback_job) + continue; + + wb_conn = drm_connector_to_writeback(connector); + drm_writeback_queue_job(wb_conn, new_conn_state); + } +} + +static void intel_enable_writeback_capture(struct intel_atomic_state *state, + struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) +{ + struct drm_connector_state *new_conn_state; + struct drm_connector *connector; + int i; + + for_each_new_connector_in_state(&state->base, connector, new_conn_state, + i) { + if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) + continue; + intel_wd_enable_capture(crtc_state, new_conn_state); + } +} + static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -1649,8 +1689,12 @@ static void intel_encoders_post_disable(struct intel_atomic_state *state, int i; for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { - struct intel_encoder *encoder = - to_intel_encoder(old_conn_state->best_encoder); + struct intel_encoder *encoder; + + if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) + continue; + + encoder = to_intel_encoder(old_conn_state->best_encoder); if (old_conn_state->crtc != &crtc->base) continue; @@ -1927,7 +1971,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, bdw_set_pipemisc(new_crtc_state); if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && - !transcoder_is_dsi(cpu_transcoder)) + !transcoder_is_dsi(cpu_transcoder) && + !transcoder_is_wd(cpu_transcoder)) hsw_configure_cpu_transcoder(new_crtc_state); crtc->active = true; @@ -7575,6 +7620,12 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) } } + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (!(new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))) + continue; + intel_wd_set_vblank_event(state, crtc, new_crtc_state); + } + intel_encoders_update_prepare(state); intel_dbuf_pre_plane_update(state); @@ -7585,6 +7636,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_crtc_enable_flip_done(state, crtc); } + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (!(new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))) + continue; + intel_queue_writeback_job(state, crtc, new_crtc_state); + intel_enable_writeback_capture(state, crtc, new_crtc_state); + } + /* Now enable the clocks, plane, pipe, and connectors that we set up. */ dev_priv->display->commit_modeset_enables(state); @@ -7965,6 +8023,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) intel_ddi_init(dev_priv, PORT_TC1); intel_ddi_init(dev_priv, PORT_TC2); } else if (DISPLAY_VER(dev_priv) >= 12) { + intel_wd_init(dev_priv, TRANSCODER_WD_0); intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); intel_ddi_init(dev_priv, PORT_TC1); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 3b9987b5f304..4879ca2e96f7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -158,6 +158,11 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder) return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; } +static inline bool transcoder_is_wd(enum transcoder transcoder) +{ + return transcoder == TRANSCODER_WD_0 || transcoder == TRANSCODER_WD_1; +} + /* * Global legacy plane identifier. Valid only for primary/sprite * planes on pre-g4x, and only for primary planes on g4x-bdw. diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 225b6bfc783c..0dad54058762 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -547,7 +547,7 @@ static void intel_hdmi_info(struct seq_file *m, static void intel_connector_info(struct seq_file *m, struct drm_connector *connector) { - struct intel_connector *intel_connector = to_intel_connector(connector); + struct intel_connector *intel_connector; const struct drm_connector_state *conn_state = connector->state; struct intel_encoder *encoder = to_intel_encoder(conn_state->best_encoder); @@ -570,6 +570,8 @@ static void intel_connector_info(struct seq_file *m, if (!encoder) return; + intel_connector = to_intel_connector(connector); + switch (connector->connector_type) { case DRM_MODE_CONNECTOR_DisplayPort: case DRM_MODE_CONNECTOR_eDP: @@ -587,12 +589,15 @@ static void intel_connector_info(struct seq_file *m, break; } - seq_puts(m, "\tHDCP version: "); - intel_hdcp_info(m, intel_connector); + if (intel_connector) { + seq_puts(m, "\tHDCP version: "); + intel_hdcp_info(m, intel_connector); + } seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc); - intel_panel_info(m, intel_connector); + if (intel_connector) + intel_panel_info(m, intel_connector); seq_printf(m, "\tmodes:\n"); list_for_each_entry(mode, &connector->modes, head) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 7a82b7acbaf2..7b550c532dfb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -44,6 +44,7 @@ #include <drm/drm_vblank.h> #include <drm/drm_vblank_work.h> #include <drm/i915_mei_hdcp_interface.h> +#include <drm/drm_writeback.h> #include <media/cec-notifier.h> #include "i915_vma.h" @@ -1370,6 +1371,11 @@ struct intel_crtc { bool cpu_fifo_underrun_disabled; bool pch_fifo_underrun_disabled; + struct { + struct drm_pending_vblank_event *e; + atomic_t work_busy; + wait_queue_head_t wd_wait; + } wd; /* per-pipe watermark state */ struct { /* watermarks currently being used */ diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 5262f16b45ac..82bb8e170197 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -939,6 +939,9 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, struct intel_encoder *encoder = intel_get_crtc_new_encoder(state, crtc_state); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD)) + return 0; + if (DISPLAY_VER(dev_priv) < 11 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; @@ -955,6 +958,9 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, struct intel_encoder *encoder = intel_get_crtc_new_encoder(state, crtc_state); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD)) + return 0; + if (DISPLAY_VER(dev_priv) < 11 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 985dfa5f7aa1..0e48c1a31024 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -23,6 +23,7 @@ #include "intel_modeset_setup.h" #include "intel_pch_display.h" #include "intel_pm.h" +#include "intel_wd.h" static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, struct drm_modeset_acquire_ctx *ctx) @@ -110,17 +111,17 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915) { - struct intel_connector *connector; + struct drm_connector *connector; struct drm_connector_list_iter conn_iter; drm_connector_list_iter_begin(&i915->drm, &conn_iter); - for_each_intel_connector_iter(connector, &conn_iter) { - struct drm_connector_state *conn_state = connector->base.state; + drm_for_each_connector_iter(connector, &conn_iter) { + struct drm_connector_state *conn_state = connector->state; struct intel_encoder *encoder = - to_intel_encoder(connector->base.encoder); + to_intel_encoder(connector->encoder); if (conn_state->crtc) - drm_connector_put(&connector->base); + drm_connector_put(connector); if (encoder) { struct intel_crtc *crtc = @@ -132,7 +133,7 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private conn_state->crtc = &crtc->base; conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; - drm_connector_get(&connector->base); + drm_connector_get(connector); } else { conn_state->best_encoder = NULL; conn_state->crtc = NULL; @@ -432,6 +433,8 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) struct intel_crtc *crtc; struct intel_encoder *encoder; struct intel_connector *connector; + struct drm_connector *_connector; + struct drm_encoder *_encoder; struct drm_connector_list_iter conn_iter; u8 active_pipes = 0; @@ -508,38 +511,70 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) intel_dpll_readout_hw_state(i915); drm_connector_list_iter_begin(&i915->drm, &conn_iter); - for_each_intel_connector_iter(connector, &conn_iter) { - if (connector->get_hw_state(connector)) { - struct intel_crtc_state *crtc_state; - struct intel_crtc *crtc; - - connector->base.dpms = DRM_MODE_DPMS_ON; - - encoder = intel_attached_encoder(connector); - connector->base.encoder = &encoder->base; - - crtc = to_intel_crtc(encoder->base.crtc); - crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; - - if (crtc_state && crtc_state->hw.active) { - /* - * This has to be done during hardware readout - * because anything calling .crtc_disable may - * rely on the connector_mask being accurate. - */ - crtc_state->uapi.connector_mask |= - drm_connector_mask(&connector->base); - crtc_state->uapi.encoder_mask |= - drm_encoder_mask(&encoder->base); + drm_for_each_connector_iter(_connector, &conn_iter) { + struct intel_crtc_state *crtc_state; + struct intel_crtc *crtc; + struct drm_writeback_connector *wb_conn; + struct intel_wd *intel_wd; + + connector = to_intel_connector(_connector); + if (!connector) { + wb_conn = drm_connector_to_writeback(_connector); + intel_wd = wb_conn_to_intel_wd(wb_conn); + _encoder = &intel_wd->base.base; + _connector->encoder = _encoder; + encoder = to_intel_encoder(_encoder); + pipe = 0; + if (encoder->get_hw_state(encoder, &pipe)) { + _connector->dpms = DRM_MODE_DPMS_ON; + crtc = to_intel_crtc(_encoder->crtc); + crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; + + if (crtc_state && crtc_state->hw.active) { + /* + * This has to be done during hardware readout + * because anything calling .crtc_disable may + * rely on the connector_mask being accurate. + */ + crtc_state->uapi.connector_mask |= + drm_connector_mask(&connector->base); + crtc_state->uapi.encoder_mask |= + drm_encoder_mask(&encoder->base); + } + } else { + _connector->dpms = DRM_MODE_DPMS_OFF; + _connector->encoder = NULL; } } else { - connector->base.dpms = DRM_MODE_DPMS_OFF; - connector->base.encoder = NULL; + if (connector->get_hw_state(connector)) { + connector->base.dpms = DRM_MODE_DPMS_OFF; + encoder = intel_attached_encoder(connector); + connector->base.encoder = &encoder->base; + + crtc = to_intel_crtc(encoder->base.crtc); + crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; + + if (crtc_state && crtc_state->hw.active) { + /* + * This has to be done during hardware readout + * because anything calling .crtc_disable may + * rely on the connector_mask being accurate. + */ + crtc_state->uapi.connector_mask |= + drm_connector_mask(&connector->base); + crtc_state->uapi.encoder_mask |= + drm_encoder_mask(&encoder->base); + } + } else { + connector->base.dpms = DRM_MODE_DPMS_OFF; + connector->base.encoder = NULL; + } } drm_dbg_kms(&i915->drm, - "[CONNECTOR:%d:%s] hw state readout: %s\n", - connector->base.base.id, connector->base.name, - str_enabled_disabled(connector->base.encoder)); + "[CONNECTOR:%d:%s] hw state readout: %s\n", + _connector->base.id, _connector->name, + str_enabled_disabled(_connector->encoder)); + } drm_connector_list_iter_end(&conn_iter); diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index a91586d77cb6..0e06daac74c1 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -25,11 +25,16 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct drm_connector *_connector = conn_state->connector; + struct intel_connector *connector; + struct drm_i915_private *i915 = to_i915(_connector->dev); drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", - connector->base.base.id, connector->base.name); + _connector->base.id, _connector->name); + + connector = to_intel_connector(_connector); + if (!connector) + return; if (connector->get_hw_state(connector)) { struct intel_encoder *encoder = intel_attached_encoder(connector); @@ -119,6 +124,9 @@ verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_stat encoder->base.base.id, encoder->base.name); + if (encoder->type == INTEL_OUTPUT_WD) + continue; + for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, new_conn_state, i) { if (old_conn_state->best_encoder == &encoder->base) @@ -177,6 +185,9 @@ verify_crtc_state(struct intel_crtc *crtc, intel_crtc_get_pipe_config(pipe_config); + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD)) + return; + /* we keep both pipes enabled on 830 */ if (IS_I830(dev_priv) && pipe_config->hw.active) pipe_config->hw.active = new_crtc_state->hw.active; diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index 1c0c745c142d..73a5a12e2c48 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -374,6 +374,9 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, if (ret) return ret; + if (intel_encoder->type == INTEL_OUTPUT_WD) + return 0; + if (intel_encoder->type == INTEL_OUTPUT_DSI) port = 0; else diff --git a/drivers/gpu/drm/i915/display/intel_wb_connector.h b/drivers/gpu/drm/i915/display/intel_wb_connector.h new file mode 100644 index 000000000000..39dceddc7b4d --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_wb_connector.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT*/ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_WB_CONNECTOR_H__ +#define __INTEL_WB_CONNECTOR_H__ + +#include "intel_display.h" + +struct intel_wb_connector *intel_wb_connector_alloc(void); +void intel_wb_connector_free(struct intel_wb_connector *connector); +void intel_wb_connector_destroy(struct drm_connector *connector); +bool intel_wb_connector_get_hw_state(struct intel_wb_connector *connector); +enum pipe intel_wb_connector_get_pipe(struct intel_wb_connector *connector); +void intel_wb_connector_attach_encoder(struct intel_wb_connector *connector, + struct intel_encoder *encoder); + +#endif /* __INTEL_WB_CONNECTOR_H__ */ + diff --git a/drivers/gpu/drm/i915/display/intel_wd.c b/drivers/gpu/drm/i915/display/intel_wd.c new file mode 100644 index 000000000000..a30cf1055db4 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_wd.c @@ -0,0 +1,699 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2022 Intel Corporation + */ + +#include <drm/drm_atomic_helper.h> +#include <drm/drm_fourcc.h> + +#include "intel_atomic.h" +#include "intel_connector.h" +#include "intel_wd.h" +#include "intel_fb_pin.h" +#include "intel_de.h" + +enum { + WD_CAPTURE_4_PIX, + WD_CAPTURE_2_PIX, +} wd_capture_format; + +struct drm_writeback_job +*intel_get_writeback_job_from_queue(struct intel_wd *intel_wd) +{ + struct drm_writeback_job *job; + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev); + struct drm_writeback_connector *wb_conn = + &intel_wd->wb_conn; + unsigned long flags; + + spin_lock_irqsave(&wb_conn->job_lock, flags); + job = list_first_entry_or_null(&wb_conn->job_queue, + struct drm_writeback_job, + list_entry); + spin_unlock_irqrestore(&wb_conn->job_lock, flags); + if (job == NULL) { + drm_dbg_kms(&i915->drm, "job queue is empty\n"); + return NULL; + } + + return job; +} + +/*Check with Spec*/ +static const u32 wb_fmts[] = { + DRM_FORMAT_YUV444, + DRM_FORMAT_XYUV8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_Y410, + DRM_FORMAT_YUV422, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_RGB565, +}; + +static int intel_wd_get_format(int pixel_format) +{ + int wd_format = -EINVAL; + + switch (pixel_format) { + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_XYUV8888: + case DRM_FORMAT_YUV444: + wd_format = WD_CAPTURE_4_PIX; + break; + case DRM_FORMAT_YUV422: + case DRM_FORMAT_RGB565: + wd_format = WD_CAPTURE_2_PIX; + break; + default: + DRM_ERROR("unsupported pixel format %x!\n", + pixel_format); + } + + return wd_format; +} + +static int intel_wd_verify_pix_format(int format) +{ + const struct drm_format_info *info = drm_format_info(format); + int pix_format = info->format; + int i = 0; + + for (i = 0; i < ARRAY_SIZE(wb_fmts); i++) + if (pix_format == wb_fmts[i]) + return 0; + + return 1; +} + +static u32 intel_wd_get_stride(const struct intel_crtc_state *crtc_state, + int format) +{ + const struct drm_format_info *info = drm_format_info(format); + int wd_format; + int hactive, pixel_size; + + wd_format = intel_wd_get_format(info->format); + + switch (wd_format) { + case WD_CAPTURE_4_PIX: + pixel_size = 4; + break; + case WD_CAPTURE_2_PIX: + pixel_size = 2; + break; + default: + pixel_size = 1; + break; + } + + hactive = crtc_state->hw.adjusted_mode.crtc_hdisplay; + + return DIV_ROUND_UP(hactive * pixel_size, 64); +} + +static int intel_wd_pin_fb(struct intel_wd *intel_wd, + struct drm_framebuffer *fb) +{ + const struct i915_ggtt_view view = { + .type = I915_GGTT_VIEW_NORMAL, + }; + struct i915_vma *vma; + + vma = intel_pin_and_fence_fb_obj(fb, false, &view, false, + &intel_wd->flags); + + if (IS_ERR(vma)) + return PTR_ERR(vma); + + intel_wd->vma = vma; + return 0; +} + +static void intel_configure_slicing_strategy(struct drm_i915_private *dev_priv, + struct intel_wd *intel_wd, u32 *tmp) +{ + *tmp &= ~WD_STRAT_MASK; + if (intel_wd->slicing_strategy == 1) + *tmp |= WD_SLICING_STRAT_1_1; + else if (intel_wd->slicing_strategy == 2) + *tmp |= WD_SLICING_STRAT_2_1; + else if (intel_wd->slicing_strategy == 3) + *tmp |= WD_SLICING_STRAT_4_1; + else if (intel_wd->slicing_strategy == 4) + *tmp |= WD_SLICING_STRAT_8_1; + + intel_de_write(dev_priv, WD_STREAMCAP_CTL(intel_wd->trans), + *tmp); +} + +static enum drm_mode_status +intel_wd_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + drm_dbg_kms(connector->dev, ":"); + return MODE_OK; +} + +static int intel_wd_get_modes(struct drm_connector *connector) +{ + return 0; +} + +static void intel_wd_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + struct intel_crtc *intel_crtc = + to_intel_crtc(pipe_config->uapi.crtc); + + if (intel_crtc) { + memcpy(pipe_config, intel_crtc->config, + sizeof(*pipe_config)); + pipe_config->output_types |= BIT(INTEL_OUTPUT_WD); + } +} + +static int intel_wd_compute_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state) +{ + struct intel_wd *intel_wd = enc_to_intel_wd(encoder); + struct drm_writeback_job *job; + + job = intel_get_writeback_job_from_queue(intel_wd); + if (job || conn_state->writeback_job) { + intel_wd->wd_crtc = to_intel_crtc(pipe_config->uapi.crtc); + return 0; + } + + return 0; +} + +static void intel_wd_get_power_domains(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_wd *intel_wd = enc_to_intel_wd(encoder); + intel_wakeref_t wakeref; + + wakeref = intel_display_power_get(i915, + encoder->power_domain); + + intel_wd->io_wakeref[0] = wakeref; +} + +static bool intel_wd_get_hw_state(struct intel_encoder *encoder, + enum pipe *pipe) +{ + bool ret = false; + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_wd *intel_wd = enc_to_intel_wd(encoder); + struct intel_crtc *wd_crtc = intel_wd->wd_crtc; + intel_wakeref_t wakeref; + u32 tmp; + + if (wd_crtc) + return false; + + wakeref = intel_display_power_get_if_enabled(dev_priv, + encoder->power_domain); + + if (!wakeref) + goto out; + + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + ret = tmp & WD_TRANS_ACTIVE; + if (ret) { + *pipe = wd_crtc->pipe; + return true; + } + +out: + intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + return false; +} + +static int intel_wd_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_st, + struct drm_connector_state *conn_st) +{ + /* Check for the format and buffers and property validity */ + struct drm_framebuffer *fb; + struct drm_writeback_job *job = conn_st->writeback_job; + struct drm_i915_private *i915 = to_i915(encoder->dev); + const struct drm_display_mode *mode = &crtc_st->mode; + int ret; + + if (!job) { + drm_dbg_kms(&i915->drm, "No writeback job created returning\n"); + return -EINVAL; + } + + fb = job->fb; + if (!fb) { + drm_dbg_kms(&i915->drm, "Invalid framebuffer\n"); + return -EINVAL; + } + + if (fb->width != mode->hdisplay || fb->height != mode->vdisplay) { + drm_dbg_kms(&i915->drm, "Invalid framebuffer size %ux%u\n", + fb->width, fb->height); + return -EINVAL; + } + + ret = intel_wd_verify_pix_format(fb->format->format); + if (ret) { + drm_dbg_kms(&i915->drm, "Unsupported framebuffer format %08x\n", + fb->format->format); + return -EINVAL; + } + + return 0; +} + + +static const struct drm_encoder_helper_funcs wd_encoder_helper_funcs = { + .atomic_check = intel_wd_encoder_atomic_check, +}; + +static void intel_wd_connector_destroy(struct drm_connector *connector) +{ + drm_connector_cleanup(connector); + kfree(connector); +} + +static enum drm_connector_status +intel_wb_connector_detect(struct drm_connector *connector, bool force) +{ + return connector_status_connected; +} + +static const struct drm_connector_funcs wd_connector_funcs = { + .detect = intel_wb_connector_detect, + .reset = drm_atomic_helper_connector_reset, + .destroy = intel_wd_connector_destroy, + .fill_modes = drm_helper_probe_single_connector_modes, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, +}; + +static const struct drm_connector_helper_funcs wd_connector_helper_funcs = { + .get_modes = intel_wd_get_modes, + .mode_valid = intel_wd_mode_valid, +}; + +static const struct drm_encoder_funcs drm_writeback_encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +static bool intel_fastset_dis(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + return false; +} + +static void intel_wd_connector_init(struct intel_wd *intel_wd) +{ + drm_atomic_helper_connector_reset(&intel_wd->wb_conn.base); +} + +static void intel_wd_disable_capture(struct intel_wd *intel_wd) +{ + struct drm_i915_private *dev_priv = to_i915(intel_wd->base.base.dev); + u32 tmp; + + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), 0xFF); + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + tmp &= WD_TRANS_DISABLE; + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp); + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans)); + tmp |= ~TRANS_WD_FUNC_ENABLE; +} + +void intel_wd_init(struct drm_i915_private *i915, enum transcoder trans) +{ + struct intel_wd *intel_wd; + struct intel_encoder *encoder; + struct drm_writeback_connector *wb_conn; + int n_formats = ARRAY_SIZE(wb_fmts); + struct drm_encoder *drm_enc; + int err, ret; + + intel_wd = kzalloc(sizeof(*intel_wd), GFP_KERNEL); + + if (!intel_wd) + return; + + intel_wd_connector_init(intel_wd); + encoder = &intel_wd->base; + drm_enc = &encoder->base; + wb_conn = &intel_wd->wb_conn; + intel_wd->trans = trans; + intel_wd->triggered_cap_mode = 1; + intel_wd->frame_num = 1; + intel_wd->slicing_strategy = 1; + encoder->get_config = intel_wd_get_config; + encoder->compute_config = intel_wd_compute_config; + encoder->get_hw_state = intel_wd_get_hw_state; + encoder->type = INTEL_OUTPUT_WD; + encoder->cloneable = 0; + encoder->pipe_mask = ~0; + encoder->power_domain = POWER_DOMAIN_TRANSCODER_B; + encoder->get_power_domains = intel_wd_get_power_domains; + encoder->initial_fastset_check = intel_fastset_dis; + + drm_encoder_helper_add(drm_enc, + &wd_encoder_helper_funcs); + + drm_enc->possible_crtcs = ~0; + ret = drm_encoder_init(&i915->drm, drm_enc, + &drm_writeback_encoder_funcs, + DRM_MODE_ENCODER_VIRTUAL, NULL); + + if (ret) { + drm_dbg_kms(&i915->drm, + "Writeback drm_encoder init Failed: %d\n", + ret); + goto cleanup; + } + + err = drm_writeback_connector_init_with_encoder(&i915->drm, + wb_conn, drm_enc, &wd_connector_funcs, + wb_fmts, n_formats); + + if (err != 0) { + drm_dbg_kms(&i915->drm, + "drm_writeback_connector_init: Failed: %d\n", + err); + goto cleanup; + } + + wb_conn->base.encoder = drm_enc; + drm_connector_helper_add(&wb_conn->base, &wd_connector_helper_funcs); + wb_conn->base.status = connector_status_connected; + return; + +cleanup: + kfree(intel_wd); + return; +} + +static void intel_wd_writeback_complete(struct intel_wd *intel_wd, + struct drm_writeback_job *job, int status) +{ + struct drm_writeback_connector *wb_conn = + &intel_wd->wb_conn; + drm_writeback_signal_completion(wb_conn, status); +} + +static int intel_wd_setup_transcoder(struct intel_wd *intel_wd, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct drm_writeback_job *job) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); + enum pipe pipe = intel_crtc->pipe; + struct drm_framebuffer *fb; + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + struct drm_gem_object *wd_fb_obj; + int ret; + u32 stride, tmp; + u16 hactive, vactive; + + fb = job->fb; + wd_fb_obj = fb->obj[0]; + if (!wd_fb_obj) { + drm_dbg_kms(&dev_priv->drm, "No framebuffer gem object created\n"); + return -1; + } + + ret = intel_wd_pin_fb(intel_wd, fb); + drm_WARN_ON(&dev_priv->drm, ret != 0); + /*Write stride and surface registers in that particular order*/ + stride = intel_wd_get_stride(pipe_config, fb->format->format); + + tmp = intel_de_read(dev_priv, WD_STRIDE(intel_wd->trans)); + tmp &= ~WD_STRIDE_MASK; + tmp |= (stride << WD_STRIDE_SHIFT); + + intel_de_write(dev_priv, WD_STRIDE(intel_wd->trans), tmp); + + tmp = intel_de_read(dev_priv, WD_SURF(intel_wd->trans)); + + intel_de_write(dev_priv, WD_SURF(intel_wd->trans), + i915_ggtt_offset(intel_wd->vma)); + + tmp = intel_de_read_fw(dev_priv, WD_IIR(intel_wd->trans)); + intel_de_write_fw(dev_priv, WD_IIR(intel_wd->trans), tmp); + + tmp = ~(WD_GTT_FAULT_INT | WD_WRITE_COMPLETE_INT | WD_FRAME_COMPLETE_INT | + WD_VBLANK_INT | WD_OVERRUN_INT | WD_CAPTURING_INT); + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), tmp); + + if (intel_wd->stream_cap) { + tmp = intel_de_read(dev_priv, + WD_STREAMCAP_CTL(intel_wd->trans)); + tmp |= WD_STREAM_CAP_MODE_EN; + intel_configure_slicing_strategy(dev_priv, intel_wd, &tmp); + } + + hactive = pipe_config->uapi.mode.hdisplay; + vactive = pipe_config->uapi.mode.vdisplay; + tmp = intel_de_read(dev_priv, HTOTAL(intel_wd->trans)); + tmp = intel_de_read(dev_priv, VTOTAL(intel_wd->trans)); + + /* minimum hactive as per bspec: 64 pixels*/ + if (hactive < 64) + drm_err(&dev_priv->drm, "hactive is less then 64 pixels\n"); + + intel_de_write(dev_priv, HTOTAL(intel_wd->trans), hactive - 1); + intel_de_write(dev_priv, VTOTAL(intel_wd->trans), vactive - 1); + + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans)); + /* select pixel format */ + tmp &= ~WD_PIX_FMT_MASK; + + switch (fb->format->format) { + default: + fallthrough; + case DRM_FORMAT_YUYV: + tmp |= WD_PIX_FMT_YUYV; + break; + case DRM_FORMAT_XYUV8888: + tmp |= WD_PIX_FMT_XYUV8888; + break; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB8888: + tmp |= WD_PIX_FMT_XBGR8888; + break; + case DRM_FORMAT_Y410: + tmp |= WD_PIX_FMT_Y410; + break; + case DRM_FORMAT_YUV422: + tmp |= WD_PIX_FMT_YUV422; + break; + case DRM_FORMAT_XBGR2101010: + tmp |= WD_PIX_FMT_XBGR2101010; + break; + case DRM_FORMAT_RGB565: + tmp |= WD_PIX_FMT_RGB565; + break; + } + + if (intel_wd->triggered_cap_mode) + tmp |= WD_TRIGGERED_CAP_MODE_ENABLE; + + if (intel_wd->stream_cap) + tmp |= WD_CTL_POINTER_DTDH; + + /*select input pipe*/ + tmp &= ~WD_INPUT_SELECT_MASK; + switch (pipe) { + default: + fallthrough; + case PIPE_A: + tmp |= WD_INPUT_PIPE_A; + break; + case PIPE_B: + tmp |= WD_INPUT_PIPE_B; + break; + case PIPE_C: + tmp |= WD_INPUT_PIPE_C; + break; + case PIPE_D: + tmp |= WD_INPUT_PIPE_D; + break; + } + + /* enable DDI buffer */ + if (!(tmp & TRANS_WD_FUNC_ENABLE)) + tmp |= TRANS_WD_FUNC_ENABLE; + + intel_de_write(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans), tmp); + + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + ret = tmp & WD_TRANS_ACTIVE; + if (!ret) { + /*enable the transcoder */ + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + tmp |= WD_TRANS_ENABLE; + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp); + + /* wait for transcoder to be enabled */ + if (intel_de_wait_for_set(dev_priv, PIPECONF(intel_wd->trans), + WD_TRANS_ACTIVE, 10)) + drm_err(&dev_priv->drm, "WD transcoder could not be enabled\n"); + } + + return 0; +} + +static int intel_wd_capture(struct intel_wd *intel_wd, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct drm_writeback_job *job) +{ + u32 tmp; + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev); + int ret = 0, status = 0; + struct intel_crtc *wd_crtc = intel_wd->wd_crtc; + unsigned long flags; + + if (!job->out_fence) + drm_dbg_kms(&i915->drm, "Not able to get out_fence for job\n"); + + ret = intel_wd_setup_transcoder(intel_wd, pipe_config, + conn_state, job); + + if (ret < 0) { + drm_dbg_kms(&i915->drm, + "WD transcoder setup not completed aborting capture\n"); + return -1; + } + + if (!wd_crtc) { + drm_err(&i915->drm, "CRTC not attached\n"); + return -1; + } + + tmp = intel_de_read_fw(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans)); + tmp |= START_TRIGGER_FRAME; + tmp &= ~WD_FRAME_NUMBER_MASK; + tmp |= intel_wd->frame_num; + intel_de_write_fw(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans), tmp); + + if (!intel_de_wait_for_set(i915, WD_IIR(intel_wd->trans), + WD_FRAME_COMPLETE_INT, 100)){ + drm_dbg_kms(&i915->drm, "frame captured\n"); + status = 0; + } else { + drm_dbg_kms(&i915->drm, "frame not captured triggering stop frame\n"); + tmp = intel_de_read(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans)); + tmp |= STOP_TRIGGER_FRAME; + intel_de_write(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans), tmp); + status = -1; + } + + intel_wd_writeback_complete(intel_wd, job, status); + if (wd_crtc->wd.e) { + spin_lock_irqsave(&i915->drm.event_lock, flags); + drm_dbg_kms(&i915->drm, "send %p\n", wd_crtc->wd.e); + drm_crtc_send_vblank_event(&wd_crtc->base, + wd_crtc->wd.e); + spin_unlock_irqrestore(&i915->drm.event_lock, flags); + wd_crtc->wd.e = NULL; + } else { + drm_err(&i915->drm, "Event NULL! %p, %p\n", &i915->drm, + wd_crtc); + } + if (!intel_get_writeback_job_from_queue(intel_wd)) + intel_wd_disable_capture(intel_wd); + return 0; +} + +void intel_wd_enable_capture(struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state) +{ + struct drm_i915_private *i915 = + to_i915(conn_state->connector->dev); + struct drm_writeback_connector *wb_conn = + drm_connector_to_writeback(conn_state->connector); + struct intel_wd *intel_wd = wb_conn_to_intel_wd(wb_conn); + struct drm_writeback_job *job; + + job = intel_get_writeback_job_from_queue(intel_wd); + if (!job) { + drm_dbg_kms(&i915->drm, + "job queue is empty not capturing any frame\n"); + return; + } + + intel_wd_capture(intel_wd, pipe_config, + conn_state, job); + intel_wd->frame_num += 1; +} + +void intel_wd_set_vblank_event(struct intel_atomic_state *state, struct intel_crtc *intel_crtc, + struct intel_crtc_state *intel_crtc_state) +{ + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + struct drm_crtc_state *crtc_state = &intel_crtc_state->uapi; + struct intel_encoder *encoder; + struct intel_wd *intel_wd; + struct drm_connector_state *conn_state; + struct drm_connector *connector; + int i; + + for_each_intel_encoder(&i915->drm, encoder) { + if (encoder->type != INTEL_OUTPUT_WD) + continue; + + intel_wd = enc_to_intel_wd(encoder); + if (!intel_wd->wd_crtc) + return; + } + + if (intel_wd && intel_crtc == intel_wd->wd_crtc) { + for_each_new_connector_in_state(&state->base, connector, conn_state, + i) { + if (!conn_state->writeback_job) + continue; + + intel_crtc->wd.e = crtc_state->event; + crtc_state->event = NULL; + } + } +} + +void intel_wd_handle_isr(struct drm_i915_private *i915) +{ + u32 iir_value = 0; + struct intel_encoder *encoder; + struct intel_wd *intel_wd; + + iir_value = intel_de_read(i915, WD_IIR(TRANSCODER_WD_0)); + + for_each_intel_encoder(&i915->drm, encoder) { + + if (encoder->type != INTEL_OUTPUT_WD) + continue; + + intel_wd = enc_to_intel_wd(encoder); + if (!intel_wd->wd_crtc) { + drm_err(&i915->drm, "NO CRTC attached with WD\n"); + goto clear_iir; + } + } + + if (iir_value & WD_FRAME_COMPLETE_INT) + return; + +clear_iir: + intel_de_write(i915, WD_IIR(TRANSCODER_WD_0), iir_value); +} diff --git a/drivers/gpu/drm/i915/display/intel_wd.h b/drivers/gpu/drm/i915/display/intel_wd.h new file mode 100644 index 000000000000..0fcd1a746593 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_wd.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT*/ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef _INTEL_WD_H +#define _INTEL_WD_H + +#include <drm/drm_crtc.h> + +#include "intel_display_types.h" + +#define I915_MAX_WD_TANSCODERS 2 + +struct intel_wd { + struct intel_encoder base; + struct drm_writeback_connector wb_conn; + struct intel_crtc *wd_crtc; + intel_wakeref_t io_wakeref[I915_MAX_WD_TANSCODERS]; + enum transcoder trans; + struct i915_vma *vma; + unsigned long flags; + struct drm_writeback_job *job; + int triggered_cap_mode; + int frame_num; + bool stream_cap; + bool start_capture; + int slicing_strategy; +}; + +static inline struct intel_wd *enc_to_intel_wd(struct intel_encoder *encoder) +{ + return container_of(&encoder->base, struct intel_wd, base.base); +} + +static inline struct intel_wd *wb_conn_to_intel_wd(struct drm_writeback_connector *wb_conn) +{ + return container_of(wb_conn, struct intel_wd, wb_conn); +} + +void intel_wd_init(struct drm_i915_private *dev_priv, enum transcoder trans); +void intel_wd_enable_capture(struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state); +void intel_wd_handle_isr(struct drm_i915_private *dev_priv); +void intel_wd_set_vblank_event(struct intel_atomic_state *state, struct intel_crtc *crtc, + struct intel_crtc_state *crtc_state); +struct drm_writeback_job *intel_get_writeback_job_from_queue(struct intel_wd *intel_wd); +#endif/* _INTEL_WD_H */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 086bbe8945d6..73ef94757fc8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -35,6 +35,7 @@ #include <linux/pm_qos.h> #include <drm/drm_connector.h> +#include <drm/drm_writeback.h> #include <drm/ttm/ttm_device.h> #include "display/intel_cdclk.h" diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 0389f532d926..6504ef528d90 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -42,6 +42,7 @@ #include "display/intel_hotplug.h" #include "display/intel_lpe_audio.h" #include "display/intel_psr.h" +#include "display/intel_wd.h" #include "gt/intel_breadcrumbs.h" #include "gt/intel_gt.h" @@ -2342,6 +2343,11 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) found = true; } + if (iir & GEN8_DE_MISC_WD0) { + intel_wd_handle_isr(dev_priv); + found = true; + } + if (iir & GEN8_DE_EDP_PSR) { struct intel_encoder *encoder; u32 psr_iir; @@ -3767,7 +3773,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) u32 de_pipe_enables; u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); u32 de_port_enables; - u32 de_misc_masked = GEN8_DE_EDP_PSR; + u32 de_misc_masked = GEN8_DE_EDP_PSR | GEN8_DE_MISC_WD0; u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D); enum pipe pipe; diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index aacc10f2e73f..636ce7819021 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -864,7 +864,8 @@ static const struct intel_device_info jsl_info = { .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1) | \ + BIT(TRANSCODER_WD_0), \ .display.pipe_offsets = { \ [TRANSCODER_A] = PIPE_A_OFFSET, \ [TRANSCODER_B] = PIPE_B_OFFSET, \ @@ -872,6 +873,8 @@ static const struct intel_device_info jsl_info = { [TRANSCODER_D] = PIPE_D_OFFSET, \ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ + [TRANSCODER_WD_0] = PIPE_WD0_OFFSET, \ + [TRANSCODER_WD_1] = PIPE_WD1_OFFSET, \ }, \ .display.trans_offsets = { \ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ @@ -880,6 +883,8 @@ static const struct intel_device_info jsl_info = { [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ + [TRANSCODER_WD_0] = TRANSCODER_WD0_OFFSET, \ + [TRANSCODER_WD_1] = TRANSCODER_WD1_OFFSET, \ }, \ TGL_CURSOR_OFFSETS, \ .has_global_mocs = 1, \ -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 0/3] i915 private writeback framework
@ 2022-05-02 5:42 Suraj Kandpal
2022-05-02 5:42 ` [Intel-gfx] [PATCH 3/3] drm/i915: Enabling WD Transcoder Suraj Kandpal
0 siblings, 1 reply; 9+ messages in thread
From: Suraj Kandpal @ 2022-05-02 5:42 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, Suraj Kandpal, uma.shankar, arun.r.murthy
A patch series was floated in the drm mailing list which aimed to change
the drm_connector and drm_encoder fields to pointer in the
drm_connector_writeback structure, this received a huge pushback from
the community but since i915 expects each connector present in the
drm_device list to be a intel_connector but drm_writeback framework.
[1] https://patchwork.kernel.org/project/dri-devel/patch/20220202081702.22119-1-suraj.kandpal@intel.com/
[2] https://patchwork.kernel.org/project/dri-devel/patch/20220202085429.22261-6-suraj.kandpal@intel.com/
This forces us to use a drm_connector which is not embedded in
intel_connector the current drm_writeback framework becomes very
unfeasible to us as it would mean a lot of checks at a lot of places
to take into account the above issue.Since no one had an issue with
encoder field being changed into a pointer it was decided to break the
connector and encoder pointer changes into two different series.The
encoder field changes is currently being worked upon by Abhinav Kumar
[3]https://patchwork.kernel.org/project/dri-devel/list/?series=633565
In the meantime for i915 to start using the writeback functionality we
came up with a interim solution to own writeback pipeline bypassing one
provided by drm which is what these patches do.
Note: these are temp patches till we figure out how we can either change
drm core writeback to work with our intel_connector structure or find a
different solution which allows us to work with the current
Suraj Kandpal (3):
drm/i915: Creating writeback pipeline to bypass drm_writeback
framework
drm/i915: Define WD trancoder for i915
drm/i915: Enabling WD Transcoder
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 89 +-
drivers/gpu/drm/i915/display/intel_display.h | 15 +
.../drm/i915/display/intel_display_types.h | 18 +
drivers/gpu/drm/i915/display/intel_dpll.c | 3 +
drivers/gpu/drm/i915/display/intel_opregion.c | 3 +
.../gpu/drm/i915/display/intel_wb_connector.c | 296 ++++++
.../gpu/drm/i915/display/intel_wb_connector.h | 99 ++
drivers/gpu/drm/i915/display/intel_wd.c | 978 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_wd.h | 82 ++
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_irq.c | 8 +-
drivers/gpu/drm/i915/i915_pci.c | 7 +-
drivers/gpu/drm/i915/i915_reg.h | 139 +++
15 files changed, 1742 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_wb_connector.c
create mode 100644 drivers/gpu/drm/i915/display/intel_wb_connector.h
create mode 100644 drivers/gpu/drm/i915/display/intel_wd.c
create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h
--
2.35.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [Intel-gfx] [PATCH 3/3] drm/i915: Enabling WD Transcoder 2022-05-02 5:42 [PATCH 0/3] i915 private writeback framework Suraj Kandpal @ 2022-05-02 5:42 ` Suraj Kandpal 0 siblings, 0 replies; 9+ messages in thread From: Suraj Kandpal @ 2022-05-02 5:42 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: jani.nikula Adding support for writeback transcoder to start capturing frames using interrupt mechanism Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_acpi.c | 1 + drivers/gpu/drm/i915/display/intel_display.c | 89 +- drivers/gpu/drm/i915/display/intel_display.h | 9 + .../drm/i915/display/intel_display_types.h | 13 + drivers/gpu/drm/i915/display/intel_dpll.c | 3 + drivers/gpu/drm/i915/display/intel_opregion.c | 3 + drivers/gpu/drm/i915/display/intel_wd.c | 978 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_wd.h | 82 ++ drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_irq.c | 8 +- drivers/gpu/drm/i915/i915_pci.c | 7 +- drivers/gpu/drm/i915/i915_reg.h | 137 +++ 13 files changed, 1330 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_wd.c create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 8bd1dd01dc81..7a665d95e2b2 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -299,6 +299,7 @@ i915-y += \ display/intel_vdsc.o \ display/intel_vrr.o \ display/intel_wb_connector.o\ + display/intel_wd.o\ display/vlv_dsi.o \ display/vlv_dsi_pll.o diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c b/drivers/gpu/drm/i915/display/intel_acpi.c index e78430001f07..ae08db164f73 100644 --- a/drivers/gpu/drm/i915/display/intel_acpi.c +++ b/drivers/gpu/drm/i915/display/intel_acpi.c @@ -247,6 +247,7 @@ static u32 acpi_display_type(struct intel_connector *connector) case DRM_MODE_CONNECTOR_LVDS: case DRM_MODE_CONNECTOR_eDP: case DRM_MODE_CONNECTOR_DSI: + case DRM_MODE_CONNECTOR_WRITEBACK: display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL; break; case DRM_MODE_CONNECTOR_Unknown: diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0decf3d24237..451dbc02c69b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -113,6 +113,7 @@ #include "intel_sprite.h" #include "intel_tc.h" #include "intel_vga.h" +#include "intel_wd.h" #include "i9xx_plane.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -1551,6 +1552,72 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state) } } +static void intel_queue_writeback_job(struct intel_atomic_state *state, + struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) +{ + struct drm_connector_state *new_conn_state; + struct drm_connector *connector; + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + struct intel_wd *intel_wd; + struct intel_connector *intel_connector; + struct intel_digital_connector_state *intel_conn_state; + struct intel_encoder *encoder; + int i; + + for_each_intel_encoder_with_wd(&i915->drm, encoder) { + intel_wd = enc_to_intel_wd(encoder); + + if (intel_wd->wd_crtc != intel_crtc) + return; + + } + + for_each_new_connector_in_state(&state->base, connector, new_conn_state, + i) { + intel_conn_state = to_intel_digital_connector_state(new_conn_state); + if (!intel_conn_state->job) + continue; + intel_connector = to_intel_connector(connector); + intel_writeback_queue_job(&intel_connector->wb_conn, new_conn_state); + drm_dbg_kms(&i915->drm, "queueing writeback job\n"); + } +} + +static void intel_find_writeback_connector(struct intel_atomic_state *state, + struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) +{ + struct drm_connector_state *new_conn_state; + struct drm_connector *connector; + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + struct intel_wd *intel_wd; + struct intel_encoder *encoder; + int i; + + for_each_intel_encoder_with_wd(&i915->drm, encoder) { + intel_wd = enc_to_intel_wd(encoder); + + if (intel_wd->wd_crtc != intel_crtc) + return; + + } + + for_each_new_connector_in_state(&state->base, connector, new_conn_state, + i) { + struct intel_connector *intel_connector; + + intel_connector = to_intel_connector(connector); + drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]: status: %s\n", + connector->base.id, connector->name, + drm_get_connector_status_name(connector->status)); + encoder = intel_connector_primary_encoder(intel_connector); + if (encoder->type == INTEL_OUTPUT_WD) { + drm_dbg_kms(&i915->drm, "encoder intel_output_wd found\n"); + intel_wd_enable_capture(encoder, crtc_state, new_conn_state); + } + } + +} + static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -1929,7 +1996,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, bdw_set_pipemisc(new_crtc_state); if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && - !transcoder_is_dsi(cpu_transcoder)) + !transcoder_is_dsi(cpu_transcoder) && + !transcoder_is_wd(cpu_transcoder)) hsw_configure_cpu_transcoder(new_crtc_state); crtc->active = true; @@ -2542,6 +2610,9 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, if (connector->get_hw_state(connector)) { struct intel_encoder *encoder = intel_attached_encoder(connector); + if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) + return; + I915_STATE_WARN(!crtc_state, "connector enabled without attached crtc\n"); @@ -5152,6 +5223,7 @@ static const char * const output_type_str[] = { OUTPUT_TYPE(DSI), OUTPUT_TYPE(DDI), OUTPUT_TYPE(DP_MST), + OUTPUT_TYPE(WD), }; #undef OUTPUT_TYPE @@ -8486,6 +8558,12 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) } } + if (DISPLAY_VER(dev_priv) >= 12) { + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + intel_wd_set_vblank_event(crtc, new_crtc_state); + } + } + intel_encoders_update_prepare(state); intel_dbuf_pre_plane_update(state); @@ -8572,6 +8650,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_sagv_post_plane_update(state); + if (DISPLAY_VER(dev_priv) >= 12) { + intel_wd_prepare_out_fence(dev, &state->base); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + intel_queue_writeback_job(state, crtc, new_crtc_state); + intel_find_writeback_connector(state, crtc, new_crtc_state); + } + } + drm_atomic_helper_commit_hw_done(&state->base); if (state->modeset) { @@ -8876,6 +8962,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) intel_ddi_init(dev_priv, PORT_TC1); intel_ddi_init(dev_priv, PORT_TC2); } else if (DISPLAY_VER(dev_priv) >= 12) { + intel_wd_init(dev_priv, TRANSCODER_WD_0); intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); intel_ddi_init(dev_priv, PORT_TC1); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 62dc26b3bf76..e63483ec7838 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -156,6 +156,11 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder) return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; } +static inline bool transcoder_is_wd(enum transcoder transcoder) +{ + return transcoder == TRANSCODER_WD_0 || transcoder == TRANSCODER_WD_1; +} + /* * Global legacy plane identifier. Valid only for primary/sprite * planes on pre-g4x, and only for primary planes on g4x-bdw. @@ -467,6 +472,10 @@ enum hpd_pin { for_each_intel_encoder((dev), (intel_encoder)) \ for_each_if(intel_encoder_can_psr(intel_encoder)) +#define for_each_intel_encoder_with_wd(dev, intel_encoder) \ + for_each_intel_encoder(dev, intel_encoder) \ + for_each_if(intel_encoder_is_wd(intel_encoder)) + #define for_each_intel_connector_iter(intel_connector, iter) \ while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index be47f7ba592c..252d7db46eb0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1301,6 +1301,11 @@ struct intel_crtc { bool cpu_fifo_underrun_disabled; bool pch_fifo_underrun_disabled; + struct { + struct drm_pending_vblank_event *e; + atomic_t work_busy; + wait_queue_head_t wd_wait; + } wd; /* per-pipe watermark state */ struct { /* watermarks currently being used */ @@ -1429,6 +1434,7 @@ struct cxsr_latency { #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi) #define to_intel_connector(x) container_of(x, struct intel_connector, base) +#define to_intel_wb_connector(x) container_of(x, struct intel_wb_connector, base) #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) #define to_intel_plane(x) container_of(x, struct intel_plane, base) @@ -1861,6 +1867,13 @@ static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) } } +static inline bool intel_encoder_is_wd(struct intel_encoder *encoder) +{ + if (encoder->type == INTEL_OUTPUT_WD) + return true; + return false; +} + static inline struct intel_lspcon * enc_to_intel_lspcon(struct intel_encoder *encoder) { diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 6eef0b8a91eb..0ba10aa37491 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -946,6 +946,9 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, intel_get_crtc_new_encoder(state, crtc_state); int ret; + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD)) + return 0; + if (DISPLAY_VER(dev_priv) < 11 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index f31e8c3f8ce0..b7a0ac9bad05 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -370,6 +370,9 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, if (ret) return ret; + if (intel_encoder->type == INTEL_OUTPUT_WD) + return 0; + if (intel_encoder->type == INTEL_OUTPUT_DSI) port = 0; else diff --git a/drivers/gpu/drm/i915/display/intel_wd.c b/drivers/gpu/drm/i915/display/intel_wd.c new file mode 100644 index 000000000000..f8130362e754 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_wd.c @@ -0,0 +1,978 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright © 2021 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Suraj Kandpal <suraj.kandpal@intel.com> + * Arun Murthy <arun.r.murthy@intel.com> + * + */ + +#include <drm/drm_atomic_helper.h> +#include <drm/drm_fourcc.h> + +#include "intel_atomic.h" +#include "intel_connector.h" +#include "intel_wd.h" +#include "intel_fb_pin.h" +#include "intel_de.h" +#include "intel_wb_connector.h" + +enum { + WD_CAPTURE_4_PIX, + WD_CAPTURE_2_PIX, +} wd_capture_format; + +static struct intel_writeback_job +*intel_get_writeback_job_from_queue(struct intel_wd *intel_wd) +{ + struct intel_writeback_job *job; + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev); + struct intel_writeback_connector *wb_conn = + &intel_wd->attached_connector->wb_conn; + unsigned long flags; + + spin_lock_irqsave(&wb_conn->job_lock, flags); + job = list_first_entry_or_null(&wb_conn->job_queue, + struct intel_writeback_job, + list_entry); + spin_unlock_irqrestore(&wb_conn->job_lock, flags); + if (job == NULL) { + drm_dbg_kms(&i915->drm, "job queue is empty\n"); + return NULL; + } + + return job; +} + +/*Check with Spec*/ +static const u32 wb_fmts[] = { + DRM_FORMAT_YUV444, + DRM_FORMAT_XYUV8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_Y410, + DRM_FORMAT_YUV422, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_RGB565, + +}; + +static int intel_wd_get_format(int pixel_format) +{ + int wd_format = -EINVAL; + + switch (pixel_format) { + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_XYUV8888: + case DRM_FORMAT_YUV444: + wd_format = WD_CAPTURE_4_PIX; + break; + case DRM_FORMAT_YUV422: + case DRM_FORMAT_RGB565: + wd_format = WD_CAPTURE_2_PIX; + break; + default: + DRM_ERROR("unsupported pixel format %x!\n", + pixel_format); + } + + return wd_format; +} + +static int intel_wd_verify_pix_format(int format) +{ + const struct drm_format_info *info = drm_format_info(format); + int pix_format = info->format; + int i = 0; + + for (i = 0; i < ARRAY_SIZE(wb_fmts); i++) + if (pix_format == wb_fmts[i]) + return 0; + + return 1; +} + +static u32 intel_wd_get_stride(const struct intel_crtc_state *crtc_state, + int format) +{ + const struct drm_format_info *info = drm_format_info(format); + int wd_format; + int hactive, pixel_size; + + wd_format = intel_wd_get_format(info->format); + + switch (wd_format) { + case WD_CAPTURE_4_PIX: + pixel_size = 4; + break; + case WD_CAPTURE_2_PIX: + pixel_size = 2; + break; + default: + pixel_size = 1; + break; + } + + hactive = crtc_state->hw.adjusted_mode.crtc_hdisplay; + + return DIV_ROUND_UP(hactive * pixel_size, 64); +} + +static int intel_wd_pin_fb(struct intel_wd *intel_wd, + struct drm_framebuffer *fb) +{ + const struct i915_ggtt_view view = { + .type = I915_GGTT_VIEW_NORMAL, + }; + struct i915_vma *vma; + + vma = intel_pin_and_fence_fb_obj(fb, false, &view, false, + &intel_wd->flags); + + if (IS_ERR(vma)) + return PTR_ERR(vma); + + intel_wd->vma = vma; + return 0; +} + +static void intel_configure_slicing_strategy(struct drm_i915_private *i915, + struct intel_wd *intel_wd, u32 *tmp) +{ + *tmp &= ~WD_STRAT_MASK; + if (intel_wd->slicing_strategy == 1) + *tmp |= WD_SLICING_STRAT_1_1; + else if (intel_wd->slicing_strategy == 2) + *tmp |= WD_SLICING_STRAT_2_1; + else if (intel_wd->slicing_strategy == 3) + *tmp |= WD_SLICING_STRAT_4_1; + else if (intel_wd->slicing_strategy == 4) + *tmp |= WD_SLICING_STRAT_8_1; + + intel_de_write(i915, WD_STREAMCAP_CTL(intel_wd->trans), + *tmp); + +} + +static enum drm_mode_status +intel_wd_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + return MODE_OK; +} + +static int intel_wd_get_modes(struct drm_connector *connector) +{ + return 0; +} + +static void intel_wd_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_crtc *intel_crtc = + to_intel_crtc(pipe_config->uapi.crtc); + + drm_dbg_kms(&i915->drm, "\n"); + if (intel_crtc) { + memcpy(pipe_config, intel_crtc->config, + sizeof(*pipe_config)); + pipe_config->output_types |= BIT(INTEL_OUTPUT_WD); + drm_dbg_kms(&i915->drm, "crtc found\n"); + } + +} + +static int intel_wd_compute_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state) +{ + struct intel_wd *intel_wd = enc_to_intel_wd(encoder); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_digital_connector_state *intel_conn_state = + to_intel_digital_connector_state(conn_state); + struct intel_writeback_job *job; + + drm_dbg_kms(&i915->drm, "\n"); + job = intel_get_writeback_job_from_queue(intel_wd); + if (job || intel_conn_state->job) { + intel_wd->wd_crtc = to_intel_crtc(pipe_config->uapi.crtc); + return 0; + } + drm_dbg_kms(&i915->drm, "No writebackjob in queue\n"); + + return 0; +} + +static void intel_wd_get_power_domains(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_wd *intel_wd = enc_to_intel_wd(encoder); + intel_wakeref_t wakeref; + + wakeref = intel_display_power_get(i915, + encoder->power_domain); + + intel_wd->io_wakeref[0] = wakeref; + drm_dbg_kms(&i915->drm, "\n"); +} + +static bool intel_wd_get_hw_state(struct intel_encoder *encoder, + enum pipe *pipe) +{ + bool ret = false; + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_wd *intel_wd = enc_to_intel_wd(encoder); + struct intel_crtc *wd_crtc = intel_wd->wd_crtc; + intel_wakeref_t wakeref; + u32 tmp; + + if (wd_crtc) + return false; + + wakeref = intel_display_power_get_if_enabled(dev_priv, + encoder->power_domain); + drm_dbg_kms(encoder->base.dev, "power enabled : %s\n", + !wakeref ? "false":"true"); + + if (!wakeref) + return false; + + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + ret = tmp & WD_TRANS_ACTIVE; + drm_dbg_kms(encoder->base.dev, "trancoder enabled: %s\n", + ret ? "true":"false"); + if (ret) { + *pipe = wd_crtc->pipe; + drm_dbg_kms(encoder->base.dev, "pipe selected is %d\n", + wd_crtc->pipe); + } + return true; +} + +static int intel_wd_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_st, + struct drm_connector_state *conn_st) +{ + /* Check for the format and buffers and property validity */ + struct drm_framebuffer *fb; + struct intel_digital_connector_state *intel_conn_state = + to_intel_digital_connector_state(conn_st); + struct intel_writeback_job *job = intel_conn_state->job; + struct drm_i915_private *i915 = to_i915(encoder->dev); + const struct drm_display_mode *mode = &crtc_st->mode; + int ret; + + drm_dbg_kms(&i915->drm, "\n"); + + if (!job) { + drm_dbg_kms(&i915->drm, "No writeback job created returning\n"); + return -EINVAL; + } + + fb = job->fb; + + if (!fb) { + drm_dbg_kms(&i915->drm, "Invalid framebuffer\n"); + return -EINVAL; + } + + if (fb->width != mode->hdisplay || fb->height != mode->vdisplay) { + drm_dbg_kms(&i915->drm, "Invalid framebuffer size %ux%u\n", + fb->width, fb->height); + return -EINVAL; + } + + ret = intel_wd_verify_pix_format(fb->format->format); + + if (ret) { + drm_dbg_kms(&i915->drm, "Unsupported framebuffer format %08x\n", + fb->format->format); + return -EINVAL; + } + + return 0; +} + + +static const struct drm_encoder_helper_funcs wd_encoder_helper_funcs = { + .atomic_check = intel_wd_encoder_atomic_check, +}; + +static void intel_wd_connector_destroy(struct drm_connector *connector) +{ + drm_dbg_kms(connector->dev, "\n"); + drm_connector_cleanup(connector); + kfree(connector); +} + +static enum drm_connector_status +intel_wb_connector_detect(struct drm_connector *connector, bool force) +{ + drm_dbg_kms(connector->dev, "Writeback connector connected\n"); + return connector_status_connected; +} + +static int intel_atomic_set_writeback_fb_for_connector( + struct drm_connector_state *conn_state, + struct drm_framebuffer *fb) +{ + int ret; + struct drm_connector *conn = conn_state->connector; + + ret = intel_writeback_set_fb(conn_state, fb); + if (ret < 0) + return ret; + + if (fb) + drm_dbg_atomic(conn->dev, + "Set [FB:%d] for connector state %p\n", + fb->base.id, conn_state); + else + drm_dbg_atomic(conn->dev, + "Set [NOFB] for connector state %p\n", + conn_state); + + return 0; +} + +static int set_out_fence_for_connector(struct drm_atomic_state *state, + struct drm_connector *connector, + s32 __user *fence_ptr) +{ + unsigned int index = drm_connector_index(connector); + + if (!fence_ptr) + return 0; + + if (put_user(-1, fence_ptr)) + return -EFAULT; + + state->connectors[index].out_fence_ptr = fence_ptr; + + return 0; +} + +static struct drm_mode_object *__intel_object_find(struct drm_device *dev, + uint32_t id, uint32_t type) +{ + struct drm_mode_object *obj = NULL; + + mutex_lock(&dev->mode_config.idr_mutex); + obj = idr_find(&dev->mode_config.object_idr, id); + if (obj && type != DRM_MODE_OBJECT_ANY && obj->type != type) + obj = NULL; + if (obj && obj->id != id) + obj = NULL; + if (obj && obj->free_cb) { + if (!kref_get_unless_zero(&obj->refcount)) + obj = NULL; + } + mutex_unlock(&dev->mode_config.idr_mutex); + + return obj; +} + +static struct drm_framebuffer *intel_wb_framebuffer_lookup(struct drm_device *dev, + uint32_t id) +{ + struct drm_mode_object *obj; + struct drm_framebuffer *fb = NULL; + + obj = __intel_object_find(dev, id, DRM_MODE_OBJECT_FB); + if (obj) + fb = obj_to_fb(obj); + return fb; +} + +static s32 __user *intel_get_out_fence_for_connector(struct drm_atomic_state *state, + struct drm_connector *connector) +{ + unsigned int index = drm_connector_index(connector); + s32 __user *fence_ptr; + + fence_ptr = state->connectors[index].out_fence_ptr; + state->connectors[index].out_fence_ptr = NULL; + + return fence_ptr; +} + +static int intel_setup_out_fence(struct intel_out_fence_state *fence_state, + struct dma_fence *fence) +{ + + fence_state->fd = get_unused_fd_flags(O_CLOEXEC); + if (fence_state->fd < 0) + return fence_state->fd; + + if (put_user(fence_state->fd, fence_state->out_fence_ptr)) + return -EFAULT; + + fence_state->sync_file = sync_file_create(fence); + if (!fence_state->sync_file) + return -ENOMEM; + + return 0; +} + +int intel_wd_prepare_out_fence(struct drm_device *dev, + struct drm_atomic_state *state) +{ + struct drm_connector *conn; + struct drm_connector_state *conn_state; + int i, ret; + + drm_dbg_kms(dev, "\n"); + + for_each_new_connector_in_state(state, conn, conn_state, i) { + struct intel_writeback_connector *wb_conn; + struct intel_connector *intel_conn = + to_intel_connector(conn); + struct dma_fence *fence; + struct intel_wd *intel_wd; + struct intel_digital_connector_state *intel_conn_state = + to_intel_digital_connector_state(conn_state); + s32 __user *fence_ptr; + + if (conn->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) + continue; + + if (!intel_conn_state->job) + continue; + + intel_wd = enc_to_intel_wd(intel_conn->encoder); + fence_ptr = intel_get_out_fence_for_connector(state, conn); + if (!fence_ptr) + continue; + + intel_wd->fence_state->out_fence_ptr = fence_ptr; + + wb_conn = &intel_conn->wb_conn; + fence = intel_writeback_get_out_fence(wb_conn); + if (!fence) + return -ENOMEM; + + ret = intel_setup_out_fence(intel_wd->fence_state, fence); + if (ret) { + dma_fence_put(fence); + return ret; + } + + intel_conn_state->job->out_fence = fence; + } + + return 0; +} + +void intel_wd_complete_signaling(struct intel_wd *intel_wd) +{ + struct intel_out_fence_state *fence_state; + + fence_state = intel_wd->fence_state; + fd_install(fence_state->fd, + fence_state->sync_file->file); + +} + +static int intel_set_writeback_property(struct drm_connector *connector, + struct drm_connector_state *state, struct drm_property *property, + uint64_t val) +{ + struct drm_device *dev = connector->dev; + struct drm_i915_private *i915 = to_i915(dev); + + if (property == i915->wb_fb_id_property) { + struct drm_framebuffer *fb; + int ret; + + fb = intel_wb_framebuffer_lookup(dev, val); + ret = intel_atomic_set_writeback_fb_for_connector(state, fb); + if (fb) + drm_framebuffer_put(fb); + return ret; + } else if (property == i915->wb_out_fence_ptr_property) { + s32 __user *fence_ptr = u64_to_user_ptr(val); + + return set_out_fence_for_connector(state->state, connector, + fence_ptr); + } else { + drm_dbg_atomic(connector->dev, + "[CONNECTOR:%d:%s] unknown property [PROP:%d:%s]]\n", + connector->base.id, connector->name, + property->base.id, property->name); + return -EINVAL; + } + + return 0; + +} + +static int intel_get_writeback_property(struct drm_connector *connector, + const struct drm_connector_state *state, struct drm_property *property, + uint64_t *val) +{ + struct drm_device *dev = connector->dev; + struct drm_i915_private *i915 = to_i915(dev); + + if (property == i915->wb_fb_id_property) + *val = 0; + else if (property == i915->wb_out_fence_ptr_property) + *val = 0; + else { + drm_dbg_atomic(&i915->drm, + "Unknown property [PROP:%d:%s]\n", + property->base.id, property->name); + return -EINVAL; + } + + return 0; +} + +static const struct drm_connector_funcs wd_connector_funcs = { + .detect = intel_wb_connector_detect, + .reset = drm_atomic_helper_connector_reset, + .destroy = intel_wd_connector_destroy, + .fill_modes = drm_helper_probe_single_connector_modes, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + .atomic_set_property = intel_set_writeback_property, + .atomic_get_property = intel_get_writeback_property, + .atomic_duplicate_state = intel_digital_connector_duplicate_state, +}; + +static const struct drm_connector_helper_funcs wd_connector_helper_funcs = { + .get_modes = intel_wd_get_modes, + .mode_valid = intel_wd_mode_valid, +}; + +static bool intel_fastset_dis(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + pipe_config->uapi.mode_changed = true; + drm_dbg_kms(encoder->base.dev, "\n"); + return false; +} + +void intel_wd_init(struct drm_i915_private *i915, enum transcoder trans) +{ + struct intel_wd *intel_wd; + struct intel_encoder *encoder; + struct intel_out_fence_state *fence_state; + struct intel_connector *intel_connector; + struct intel_writeback_connector *wb_conn; + int n_formats = ARRAY_SIZE(wb_fmts); + int err; + + drm_dbg_kms(&i915->drm, "\n"); + intel_wd = kzalloc(sizeof(*intel_wd), GFP_KERNEL); + if (!intel_wd) + return; + + intel_connector = intel_connector_alloc(); + if (!intel_connector) { + kfree(intel_wd); + return; + } + + fence_state = kzalloc(sizeof(*fence_state), GFP_KERNEL); + if (!intel_wd) { + kfree(intel_wd); + kfree(intel_connector); + return; + } + + wb_conn = &intel_connector->wb_conn; + wb_conn->base = &intel_connector->base; + wb_conn->encoder = &intel_wd->base.base; + + encoder = &intel_wd->base; + intel_wd->attached_connector = intel_connector; + intel_wd->fence_state = fence_state; + intel_wd->trans = trans; + intel_wd->triggered_cap_mode = 1; + intel_wd->frame_num = 1; + intel_wd->slicing_strategy = 1; + encoder->get_config = intel_wd_get_config; + encoder->compute_config = intel_wd_compute_config; + encoder->get_hw_state = intel_wd_get_hw_state; + encoder->type = INTEL_OUTPUT_WD; + encoder->cloneable = 0; + encoder->pipe_mask = ~0; + encoder->power_domain = POWER_DOMAIN_TRANSCODER_B; + encoder->get_power_domains = intel_wd_get_power_domains; + encoder->initial_fastset_check = intel_fastset_dis; + intel_connector->get_hw_state = + intel_connector_get_hw_state; + + drm_dbg_kms(&i915->drm, "\n"); + err = intel_writeback_connector_init(&i915->drm, wb_conn, + &wd_connector_funcs, + &wd_encoder_helper_funcs, + wb_fmts, n_formats); + + if (err != 0) { + drm_dbg_kms(&i915->drm, + "intel_writeback_connector_init: Failed: %d\n", + err); + goto cleanup; + } + + drm_connector_helper_add(wb_conn->base, &wd_connector_helper_funcs); + intel_connector_attach_encoder(intel_connector, encoder); + wb_conn->base->status = connector_status_connected; + return; + +cleanup: + kfree(intel_wd); + intel_connector_free(intel_connector); +} + +static void intel_wd_writeback_complete(struct intel_wd *intel_wd, + struct intel_writeback_job *job, int status) +{ + struct intel_writeback_connector *wb_conn = + &intel_wd->attached_connector->wb_conn; + intel_writeback_signal_completion(wb_conn, status); + intel_wd_complete_signaling(intel_wd); +} + +static int intel_wd_setup_transcoder(struct intel_wd *intel_wd, + struct intel_crtc_state *pipe_config, + struct intel_writeback_job *job) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); + enum pipe pipe = intel_crtc->pipe; + struct drm_framebuffer *fb; + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + struct drm_gem_object *wd_fb_obj; + int ret; + u32 stride, tmp; + u16 hactive, vactive; + + fb = job->fb; + wd_fb_obj = fb->obj[0]; + if (!wd_fb_obj) { + drm_dbg_kms(&dev_priv->drm, "No framebuffer gem object created\n"); + return -1; + } + ret = intel_wd_pin_fb(intel_wd, fb); + drm_WARN_ON(&dev_priv->drm, ret != 0); + + /*Write stride and surface registers in that particular order*/ + stride = intel_wd_get_stride(pipe_config, fb->format->format); + + tmp = intel_de_read(dev_priv, WD_STRIDE(intel_wd->trans)); + tmp &= ~WD_STRIDE_MASK; + tmp |= (stride << WD_STRIDE_SHIFT); + + intel_de_write(dev_priv, WD_STRIDE(intel_wd->trans), tmp); + + tmp = intel_de_read(dev_priv, WD_SURF(intel_wd->trans)); + drm_dbg_kms(&dev_priv->drm, "%d is the surface address\n", tmp); + + intel_de_write(dev_priv, WD_SURF(intel_wd->trans), + i915_ggtt_offset(intel_wd->vma)); + + tmp = intel_de_read_fw(dev_priv, WD_IIR(intel_wd->trans)); + intel_de_write_fw(dev_priv, WD_IIR(intel_wd->trans), tmp); + + tmp = ~(WD_GTT_FAULT_INT|WD_WRITE_COMPLETE_INT|WD_FRAME_COMPLETE_INT| + WD_VBLANK_INT|WD_OVERRUN_INT|WD_CAPTURING_INT); + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), tmp); + + if (intel_wd->stream_cap) { + tmp = intel_de_read(dev_priv, + WD_STREAMCAP_CTL(intel_wd->trans)); + tmp |= WD_STREAM_CAP_MODE_EN; + intel_configure_slicing_strategy(dev_priv, intel_wd, &tmp); + } + + hactive = pipe_config->uapi.mode.hdisplay; + vactive = pipe_config->uapi.mode.vdisplay; + + drm_dbg_kms(&dev_priv->drm, "hactive : %d, vactive: %d\n", hactive, vactive); + + tmp = intel_de_read(dev_priv, HTOTAL(intel_wd->trans)); + drm_dbg_kms(&dev_priv->drm, "hactive_reg : %d\n", tmp); + tmp = intel_de_read(dev_priv, VTOTAL(intel_wd->trans)); + drm_dbg_kms(&dev_priv->drm, "vactive_reg : %d\n", tmp); + /* minimum hactive as per bspec: 64 pixels*/ + if (hactive < 64) + drm_err(&dev_priv->drm, "hactive is less then 64 pixels\n"); + + intel_de_write(dev_priv, HTOTAL(intel_wd->trans), hactive - 1); + intel_de_write(dev_priv, VTOTAL(intel_wd->trans), vactive - 1); + + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans)); + /* select pixel format */ + tmp &= ~WD_PIX_FMT_MASK; + + switch (fb->format->format) { + default: + fallthrough; + case DRM_FORMAT_YUYV: + tmp |= WD_PIX_FMT_YUYV; + break; + case DRM_FORMAT_XYUV8888: + tmp |= WD_PIX_FMT_XYUV8888; + break; + case DRM_FORMAT_XBGR8888: + tmp |= WD_PIX_FMT_XBGR8888; + break; + case DRM_FORMAT_Y410: + tmp |= WD_PIX_FMT_Y410; + break; + case DRM_FORMAT_YUV422: + tmp |= WD_PIX_FMT_YUV422; + break; + case DRM_FORMAT_XBGR2101010: + tmp |= WD_PIX_FMT_XBGR2101010; + break; + case DRM_FORMAT_RGB565: + tmp |= WD_PIX_FMT_RGB565; + break; + } + + if (intel_wd->triggered_cap_mode) + tmp |= WD_TRIGGERED_CAP_MODE_ENABLE; + + if (intel_wd->stream_cap) + tmp |= WD_CTL_POINTER_DTDH; + + /*select input pipe*/ + tmp &= ~WD_INPUT_SELECT_MASK; + drm_dbg_kms(&dev_priv->drm, "Selected pipe is %d\n", pipe); + switch (pipe) { + default: + fallthrough; + case PIPE_A: + tmp |= WD_INPUT_PIPE_A; + break; + case PIPE_B: + tmp |= WD_INPUT_PIPE_B; + break; + case PIPE_C: + tmp |= WD_INPUT_PIPE_C; + break; + case PIPE_D: + tmp |= WD_INPUT_PIPE_D; + break; + } + + /* enable DDI buffer */ + if (!(tmp & TRANS_WD_FUNC_ENABLE)) + tmp |= TRANS_WD_FUNC_ENABLE; + + intel_de_write(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans), tmp); + + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + ret = tmp & WD_TRANS_ACTIVE; + drm_dbg_kms(&dev_priv->drm, "Trancoder enabled: %s\n", ret ? "true":"false"); + + if (!ret) { + /*enable the transcoder */ + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + tmp |= WD_TRANS_ENABLE; + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp); + + /* wait for transcoder to be enabled */ + if (intel_de_wait_for_set(dev_priv, PIPECONF(intel_wd->trans), + WD_TRANS_ACTIVE, 10)) + drm_err(&dev_priv->drm, "WD transcoder not enabled\n"); + } + + return 0; +} + +static void intel_wd_disable_capture(struct intel_wd *intel_wd) +{ + struct drm_i915_private *dev_priv = to_i915(intel_wd->base.base.dev); + u32 tmp; + + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), 0xFF); + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans)); + tmp &= WD_TRANS_DISABLE; + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp); + + drm_dbg_kms(&dev_priv->drm, "WD Trans_Conf value after disable = 0x%08x\n", + intel_de_read(dev_priv, PIPECONF(intel_wd->trans))); + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans)); + tmp |= ~TRANS_WD_FUNC_ENABLE; +} + +static int intel_wd_capture(struct intel_wd *intel_wd, + struct intel_crtc_state *pipe_config, + struct intel_writeback_job *job) +{ + u32 tmp; + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev); + int ret = 0, status = 0; + struct intel_crtc *wd_crtc = intel_wd->wd_crtc; + unsigned long flags; + + drm_dbg_kms(&i915->drm, "\n"); + + if (!job->out_fence) + drm_dbg_kms(&i915->drm, "Not able to get out_fence for job\n"); + + ret = intel_wd_setup_transcoder(intel_wd, pipe_config, job); + + if (ret < 0) { + drm_dbg_kms(&i915->drm, + "wd transcoder setup not completed aborting capture\n"); + return -1; + } + + if (wd_crtc == NULL) { + DRM_ERROR("CRTC not attached\n"); + return -1; + } + + tmp = intel_de_read_fw(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans)); + tmp |= START_TRIGGER_FRAME; + tmp &= ~WD_FRAME_NUMBER_MASK; + tmp |= intel_wd->frame_num; + intel_de_write_fw(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans), tmp); + + if (!intel_de_wait_for_set(i915, WD_IIR(intel_wd->trans), + WD_FRAME_COMPLETE_INT, 100)){ + drm_dbg_kms(&i915->drm, "frame captured\n"); + tmp = intel_de_read(i915, WD_IIR(intel_wd->trans)); + drm_dbg_kms(&i915->drm, "iir value : %d\n", tmp); + status = 0; + } else { + drm_dbg_kms(&i915->drm, "frame not captured triggering stop frame\n"); + tmp = intel_de_read(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans)); + tmp |= STOP_TRIGGER_FRAME; + intel_de_write(i915, + WD_TRANS_FUNC_CTL(intel_wd->trans), tmp); + status = -1; + } + + intel_de_write(i915, WD_IIR(intel_wd->trans), tmp); + intel_wd_writeback_complete(intel_wd, job, status); + if (intel_get_writeback_job_from_queue(intel_wd) == NULL) + intel_wd_disable_capture(intel_wd); + if (wd_crtc->wd.e) { + spin_lock_irqsave(&i915->drm.event_lock, flags); + drm_dbg_kms(&i915->drm, "send %p\n", wd_crtc->wd.e); + drm_crtc_send_vblank_event(&wd_crtc->base, + wd_crtc->wd.e); + spin_unlock_irqrestore(&i915->drm.event_lock, flags); + wd_crtc->wd.e = NULL; + } else { + DRM_ERROR("Event NULL! %p, %p\n", &i915->drm, + wd_crtc); + } + return 0; + +} + +void intel_wd_enable_capture(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_wd *intel_wd = enc_to_intel_wd(encoder); + struct intel_writeback_job *job; + + drm_dbg_kms(&i915->drm, "\n"); + + job = intel_get_writeback_job_from_queue(intel_wd); + if (job == NULL) { + drm_dbg_kms(&i915->drm, + "job queue is empty not capturing any frame\n"); + return; + } + + intel_wd_capture(intel_wd, pipe_config, job); + intel_wd->frame_num += 1; + +} + +void intel_wd_set_vblank_event(struct intel_crtc *intel_crtc, + struct intel_crtc_state *intel_crtc_state) +{ + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + struct drm_crtc_state *state = &intel_crtc_state->uapi; + struct intel_encoder *encoder; + struct intel_wd *intel_wd; + + for_each_intel_encoder_with_wd(&i915->drm, encoder) { + intel_wd = enc_to_intel_wd(encoder); + + if (!intel_wd->wd_crtc) { + drm_dbg_kms(&i915->drm, "wd crtc not found\n"); + return; + } + } + + if (intel_crtc == intel_wd->wd_crtc) { + intel_crtc->wd.e = state->event; + state->event = NULL; + if (intel_crtc->wd.e) + drm_dbg_kms(&i915->drm, "WD event:%p\n", + intel_crtc->wd.e); + else + drm_dbg_kms(&i915->drm, "WD no event\n"); + } +} + +void intel_wd_handle_isr(struct drm_i915_private *i915) +{ + u32 iir_value = 0; + struct intel_encoder *encoder; + struct intel_wd *intel_wd; + + iir_value = intel_de_read(i915, WD_IIR(TRANSCODER_WD_0)); + drm_dbg_kms(&i915->drm, "\n"); + + for_each_intel_encoder_with_wd(&i915->drm, encoder) { + intel_wd = enc_to_intel_wd(encoder); + + if (!intel_wd->wd_crtc) { + DRM_ERROR("NO CRTC attached with WD\n"); + goto clear_iir; + } + } + + if (iir_value & WD_VBLANK_INT) + drm_dbg_kms(&i915->drm, "vblank interrupt for wd transcoder\n"); + if (iir_value & WD_WRITE_COMPLETE_INT) + drm_dbg_kms(&i915->drm, + "wd write complete interrupt encountered\n"); + else + DRM_INFO("iir: %x\n", iir_value); + if (iir_value & WD_FRAME_COMPLETE_INT) { + drm_dbg_kms(&i915->drm, + "frame complete interrupt for wd transcoder\n"); + return; + } +clear_iir: + intel_de_write(i915, WD_IIR(TRANSCODER_WD_0), iir_value); +} diff --git a/drivers/gpu/drm/i915/display/intel_wd.h b/drivers/gpu/drm/i915/display/intel_wd.h new file mode 100644 index 000000000000..2309afa23bb8 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_wd.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * Copyright © 2021 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author : + * Suraj Kandpal<suraj.kandpal@intel.com> + * Arun Murthy<arun.r.murthy@intel.com> + */ + +#ifndef _INTEL_WD_H +#define _INTEL_WD_H + +#include <drm/drm_crtc.h> +#include <linux/sync_file.h> + +#include "intel_display_types.h" + +#define I915_MAX_WD_TANSCODERS 2 + +struct intel_out_fence_state { + s32 __user *out_fence_ptr; + struct sync_file *sync_file; + int fd; +}; + +struct intel_wd { + struct intel_encoder base; + struct intel_crtc *wd_crtc; + struct intel_out_fence_state *fence_state; + intel_wakeref_t io_wakeref[I915_MAX_WD_TANSCODERS]; + struct intel_connector *attached_connector; + enum transcoder trans; + struct i915_vma *vma; + unsigned long flags; + struct intel_writeback_job *job; + int triggered_cap_mode; + int frame_num; + bool stream_cap; + bool start_capture; + int slicing_strategy; +}; + +struct intel_wd_clk_vals { + u32 cdclk; + u16 link_m; + u16 link_n; +}; + +extern struct sync_file *sync_file_create(struct dma_fence *fence); +static inline struct intel_wd *enc_to_intel_wd(struct intel_encoder *encoder) +{ + return container_of(&encoder->base, struct intel_wd, base.base); +} +void intel_wd_init(struct drm_i915_private *dev_priv, enum transcoder trans); +void intel_wd_enable_capture(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state); +void intel_wd_handle_isr(struct drm_i915_private *dev_priv); +void intel_wd_set_vblank_event(struct intel_crtc *crtc, + struct intel_crtc_state *state); +int intel_wd_prepare_out_fence(struct drm_device *dev, + struct drm_atomic_state *state); +void intel_wd_complete_signaling(struct intel_wd *intel_wd); +#endif/* _INTEL_WD_H */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3c8ac44d9fa3..e6a4407a499b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -35,6 +35,8 @@ #include <linux/pm_qos.h> #include <drm/drm_connector.h> +#include <drm/drm_writeback.h> +#include <drm/i915_mei_hdcp_interface.h> #include <drm/ttm/ttm_device.h> #include "display/intel_bios.h" diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 73cebc6aa650..95a6a8f7a911 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -42,6 +42,7 @@ #include "display/intel_hotplug.h" #include "display/intel_lpe_audio.h" #include "display/intel_psr.h" +#include "display/intel_wd.h" #include "gt/intel_breadcrumbs.h" #include "gt/intel_gt.h" @@ -2342,6 +2343,11 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) found = true; } + if (iir & GEN8_DE_MISC_WD0) { + intel_wd_handle_isr(dev_priv); + found = true; + } + if (iir & GEN8_DE_EDP_PSR) { struct intel_encoder *encoder; u32 psr_iir; @@ -3767,7 +3773,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) u32 de_pipe_enables; u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); u32 de_port_enables; - u32 de_misc_masked = GEN8_DE_EDP_PSR; + u32 de_misc_masked = GEN8_DE_EDP_PSR | GEN8_DE_MISC_WD0; u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D); enum pipe pipe; diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 7739d6c33481..7c2b69c3a68a 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -853,7 +853,8 @@ static const struct intel_device_info jsl_info = { .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1)| \ + BIT(TRANSCODER_WD_0), \ .pipe_offsets = { \ [TRANSCODER_A] = PIPE_A_OFFSET, \ [TRANSCODER_B] = PIPE_B_OFFSET, \ @@ -861,6 +862,8 @@ static const struct intel_device_info jsl_info = { [TRANSCODER_D] = PIPE_D_OFFSET, \ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ + [TRANSCODER_WD_0] = PIPE_WD0_OFFSET, \ + [TRANSCODER_WD_1] = PIPE_WD1_OFFSET, \ }, \ .trans_offsets = { \ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ @@ -869,6 +872,8 @@ static const struct intel_device_info jsl_info = { [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ + [TRANSCODER_WD_0] = TRANSCODER_WD0_OFFSET, \ + [TRANSCODER_WD_1] = TRANSCODER_WD1_OFFSET, \ }, \ TGL_CURSOR_OFFSETS, \ .has_global_mocs = 1, \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e9f6301a6394..24d7d5076572 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3818,6 +3818,11 @@ #define PIPE_DSI0_OFFSET 0x7b000 #define PIPE_DSI1_OFFSET 0x7b800 +/* WD 0 and 1 */ +#define PIPE_WD0_OFFSET 0x7e000 +#define PIPE_WD1_OFFSET 0x7d000 + + #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) @@ -4482,6 +4487,10 @@ #define _PIPEDSI0CONF 0x7b008 #define _PIPEDSI1CONF 0x7b808 +/* WD 0 and 1 */ +#define _PIPEWD0CONF 0x7e008 +#define _PIPEWD1CONF 0x7d008 + /* Sprite A control */ #define _DVSACNTR 0x72180 #define DVS_ENABLE REG_BIT(31) @@ -5707,6 +5716,7 @@ #define GEN8_DE_MISC_IER _MMIO(0x4446c) #define GEN8_DE_MISC_GSE (1 << 27) #define GEN8_DE_EDP_PSR (1 << 19) +#define GEN8_DE_MISC_WD0 (1 << 23) #define GEN8_PCU_ISR _MMIO(0x444e0) #define GEN8_PCU_IMR _MMIO(0x444e4) @@ -8858,6 +8868,133 @@ enum skl_power_gate { #define DSB_ENABLE (1 << 31) #define DSB_STATUS (1 << 0) +#define TGL_ROOT_DEVICE_ID 0x9A00 +#define TGL_ROOT_DEVICE_MASK 0xFF00 +#define TGL_ROOT_DEVICE_SKU_MASK 0xF +#define TGL_ROOT_DEVICE_SKU_ULX 0x2 +#define TGL_ROOT_DEVICE_SKU_ULT 0x4 + +/* Gen12 WD */ +#define _MMIO_WD(tc, wd0, wd1) _MMIO_TRANS((tc) - TRANSCODER_WD_0, \ + wd0, wd1) + +#define WD_TRANS_ENABLE (1 << 31) +#define WD_TRANS_DISABLE 0 +#define WD_TRANS_ACTIVE (1 << 30) + +/* WD transcoder control */ +#define _WD_TRANS_FUNC_CTL_0 0x6e400 +#define _WD_TRANS_FUNC_CTL_1 0x6ec00 +#define WD_TRANS_FUNC_CTL(tc) _MMIO_WD(tc,\ + _WD_TRANS_FUNC_CTL_0,\ + _WD_TRANS_FUNC_CTL_1) + +#define TRANS_WD_FUNC_ENABLE (1 << 31) +#define WD_TRIGGERED_CAP_MODE_ENABLE (1 << 30) +#define START_TRIGGER_FRAME (1 << 29) +#define STOP_TRIGGER_FRAME (1 << 28) +#define WD_CTL_POINTER_ETEH (0 << 18) +#define WD_CTL_POINTER_ETDH (1 << 18) +#define WD_CTL_POINTER_DTDH (2 << 18) +#define WD_INPUT_SELECT_MASK (7 << 12) +#define WD_INPUT_PIPE_A (0 << 12) +#define WD_INPUT_PIPE_B (5 << 12) +#define WD_INPUT_PIPE_C (6 << 12) +#define WD_INPUT_PIPE_D (7 << 12) + +#define WD_PIX_FMT_MASK (0x3 << 20) +#define WD_PIX_FMT_YUYV (0x1 << 20) +#define WD_PIX_FMT_XYUV8888 (0x2 << 20) +#define WD_PIX_FMT_XBGR8888 (0x3 << 20) +#define WD_PIX_FMT_Y410 (0x4 << 20) +#define WD_PIX_FMT_YUV422 (0x5 << 20) +#define WD_PIX_FMT_XBGR2101010 (0x6 << 20) +#define WD_PIX_FMT_RGB565 (0x7 << 20) + +#define WD_FRAME_NUMBER_MASK 15 + +#define _WD_STRIDE_0 0x6e510 +#define _WD_STRIDE_1 0x6ed10 +#define WD_STRIDE(tc) _MMIO_WD(tc,\ + _WD_STRIDE_0,\ + _WD_STRIDE_1) +#define WD_STRIDE_SHIFT 6 +#define WD_STRIDE_MASK (0x3ff << WD_STRIDE_SHIFT) + +#define _WD_STREAMCAP_CTL0 0x6e590 +#define _WD_STREAMCAP_CTL1 0x6ed90 +#define WD_STREAMCAP_CTL(tc) _MMIO_WD(tc,\ + _WD_STREAMCAP_CTL0,\ + _WD_STREAMCAP_CTL1) + +#define WD_STREAM_CAP_MODE_EN (1 << 31) +#define WD_STRAT_MASK (3 << 24) +#define WD_SLICING_STRAT_1_1 (0 << 24) +#define WD_SLICING_STRAT_2_1 (1 << 24) +#define WD_SLICING_STRAT_4_1 (2 << 24) +#define WD_SLICING_STRAT_8_1 (3 << 24) +#define WD_STREAM_OVERRUN_STATUS 1 + +#define _WD_SURF_0 0x6e514 +#define _WD_SURF_1 0x6ed14 +#define WD_SURF(tc) _MMIO_WD(tc,\ + _WD_SURF_0,\ + _WD_SURF_1) + +#define _WD_IMR_0 0x6e560 +#define _WD_IMR_1 0x6ed60 +#define WD_IMR(tc) _MMIO_WD(tc,\ + _WD_IMR_0,\ + _WD_IMR_1) +#define WD_FRAME_COMPLETE_INT (1 << 7) +#define WD_GTT_FAULT_INT (1 << 6) +#define WD_VBLANK_INT (1 << 5) +#define WD_OVERRUN_INT (1 << 4) +#define WD_CAPTURING_INT (1 << 3) +#define WD_WRITE_COMPLETE_INT (1 << 2) + +#define _WD_IIR_0 0x6e564 +#define _WD_IIR_1 0x6ed64 +#define WD_IIR(tc) _MMIO_WD(tc,\ + _WD_IIR_0,\ + _WD_IIR_1) + +#define _WD_FRAME_STATUS_0 0x6e56b +#define _WD_FRAME_STATUS_1 0x6ed6b +#define WD_FRAME_STATUS(tc) _MMIO_WD(tc,\ + _WD_FRAME_STATUS_0,\ + _WD_FRAME_STATUS_1) + +#define WD_FRAME_COMPLETE (1 << 31) +#define WD_STATE_IDLE (0 << 24) +#define WD_STATE_CAPSTART (1 << 24) +#define WD_STATE_FRAME_START (2 << 24) +#define WD_STATE_CAPACITIVE (3 << 24) +#define WD_STATE_TG_DONE (4 << 24) +#define WD_STATE_WDX_DONE (5 << 24) +#define WD_STATE_QUICK_CAP (6 << 24) + +#define _WD_27_M_0 0x6e524 +#define _WD_27_M_1 0x6ed24 +#define WD_27_M(tc) _MMIO_WD(tc,\ + _WD_27_M_0,\ + _WD_27_M_1) + +#define _WD_27_N_0 0x6e528 + +//Address looks wrong in bspec: +#define _WD_27_N_1 0x6ec28 +#define WD_27_N(tc) _MMIO_WD(tc,\ + _WD_27_N_0,\ + _WD_27_N_1) + +#define _WD_TAIL_CFG_0 0x6e520 +#define _WD_TAIL_CFG_1 0x6ed20 + +#define WD_TAIL_CFG(tc) _MMIO_WD(tc,\ + _WD_TAIL_CFG_0,\ + _WD_TAIL_CFG_1) + #define CLKREQ_POLICY _MMIO(0x101038) #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) -- 2.35.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-08-22 19:26 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-08-18 10:36 [Intel-gfx] [PATCH 0/3] Enable Pipewriteback Suraj Kandpal 2022-08-18 10:36 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define WD trancoder for i915 Suraj Kandpal 2022-08-18 10:36 ` [Intel-gfx] [PATCH 2/3] drm/i915 : Changing intel_connector iterators Suraj Kandpal 2022-08-18 10:36 ` [Intel-gfx] [PATCH 3/3] drm/i915: Enabling WD Transcoder Suraj Kandpal 2022-08-18 13:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Pipewriteback Patchwork 2022-08-18 13:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-08-18 13:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2022-08-22 19:24 [Intel-gfx] [PATCH 0/3] Enable Pipewriteback Framework Kandpal, Suraj 2022-08-22 19:24 ` [Intel-gfx] [PATCH 3/3] drm/i915: Enabling WD Transcoder Kandpal, Suraj 2022-05-02 5:42 [PATCH 0/3] i915 private writeback framework Suraj Kandpal 2022-05-02 5:42 ` [Intel-gfx] [PATCH 3/3] drm/i915: Enabling WD Transcoder Suraj Kandpal
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