From: Maxime Chevallier <maxime.chevallier@bootlin.com> To: davem@davemloft.net, Rob Herring <robh+dt@kernel.org> Cc: Maxime Chevallier <maxime.chevallier@bootlin.com>, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn <andrew@lunn.ch>, Jakub Kicinski <kuba@kernel.org>, Eric Dumazet <edumazet@google.com>, Paolo Abeni <pabeni@redhat.com>, Florian Fainelli <f.fainelli@gmail.com>, Heiner Kallweit <hkallweit1@gmail.com>, Russell King <linux@armlinux.org.uk>, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, devicetree@vger.kernel.org Subject: [PATCH net-next v3 5/5] dt-bindings: net: altera: tse: add an optional pcs register range Date: Thu, 1 Sep 2022 16:35:43 +0200 [thread overview] Message-ID: <20220901143543.416977-6-maxime.chevallier@bootlin.com> (raw) In-Reply-To: <20220901143543.416977-1-maxime.chevallier@bootlin.com> Some implementations of the TSE have their PCS as an external bloc, exposed at its own register range. Document this, and add a new example showing a case using the pcs and the new phylink conversion to connect an sfp port to a TSE mac. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> --- V2->V3 : - Fixed construct of reg/reg-names - Fixed example to use an all-zero mac-addr V1->V2 : - Fixed example .../devicetree/bindings/net/altr,tse.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/net/altr,tse.yaml b/Documentation/devicetree/bindings/net/altr,tse.yaml index 78c7a2047910..8d1d94494349 100644 --- a/Documentation/devicetree/bindings/net/altr,tse.yaml +++ b/Documentation/devicetree/bindings/net/altr,tse.yaml @@ -95,7 +95,9 @@ allOf: properties: reg: minItems: 6 + maxItems: 7 reg-names: + minItems: 6 items: - const: control_port - const: rx_csr @@ -103,10 +105,35 @@ allOf: - const: rx_resp - const: tx_csr - const: tx_desc + - const: pcs unevaluatedProperties: false examples: + - | + tse_sub_0: ethernet@c0100000 { + compatible = "altr,tse-msgdma-1.0"; + reg = <0xc0100000 0x00000400>, + <0xc0101000 0x00000020>, + <0xc0102000 0x00000020>, + <0xc0103000 0x00000008>, + <0xc0104000 0x00000020>, + <0xc0105000 0x00000020>, + <0xc0106000 0x00000100>; + reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc", "pcs"; + interrupt-parent = <&intc>; + interrupts = <0 44 4>,<0 45 4>; + interrupt-names = "rx_irq","tx_irq"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + max-frame-size = <1500>; + local-mac-address = [ 00 00 00 00 00 00 ]; + altr,has-supplementary-unicast; + altr,has-hash-multicast-filter; + sfp = <&sfp0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; - | tse_sub_1_eth_tse_0: ethernet@1,00001000 { compatible = "altr,tse-msgdma-1.0"; -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Maxime Chevallier <maxime.chevallier@bootlin.com> To: davem@davemloft.net, Rob Herring <robh+dt@kernel.org> Cc: Maxime Chevallier <maxime.chevallier@bootlin.com>, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn <andrew@lunn.ch>, Jakub Kicinski <kuba@kernel.org>, Eric Dumazet <edumazet@google.com>, Paolo Abeni <pabeni@redhat.com>, Florian Fainelli <f.fainelli@gmail.com>, Heiner Kallweit <hkallweit1@gmail.com>, Russell King <linux@armlinux.org.uk>, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, devicetree@vger.kernel.org Subject: [PATCH net-next v3 5/5] dt-bindings: net: altera: tse: add an optional pcs register range Date: Thu, 1 Sep 2022 16:35:43 +0200 [thread overview] Message-ID: <20220901143543.416977-6-maxime.chevallier@bootlin.com> (raw) In-Reply-To: <20220901143543.416977-1-maxime.chevallier@bootlin.com> Some implementations of the TSE have their PCS as an external bloc, exposed at its own register range. Document this, and add a new example showing a case using the pcs and the new phylink conversion to connect an sfp port to a TSE mac. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> --- V2->V3 : - Fixed construct of reg/reg-names - Fixed example to use an all-zero mac-addr V1->V2 : - Fixed example .../devicetree/bindings/net/altr,tse.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/net/altr,tse.yaml b/Documentation/devicetree/bindings/net/altr,tse.yaml index 78c7a2047910..8d1d94494349 100644 --- a/Documentation/devicetree/bindings/net/altr,tse.yaml +++ b/Documentation/devicetree/bindings/net/altr,tse.yaml @@ -95,7 +95,9 @@ allOf: properties: reg: minItems: 6 + maxItems: 7 reg-names: + minItems: 6 items: - const: control_port - const: rx_csr @@ -103,10 +105,35 @@ allOf: - const: rx_resp - const: tx_csr - const: tx_desc + - const: pcs unevaluatedProperties: false examples: + - | + tse_sub_0: ethernet@c0100000 { + compatible = "altr,tse-msgdma-1.0"; + reg = <0xc0100000 0x00000400>, + <0xc0101000 0x00000020>, + <0xc0102000 0x00000020>, + <0xc0103000 0x00000008>, + <0xc0104000 0x00000020>, + <0xc0105000 0x00000020>, + <0xc0106000 0x00000100>; + reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc", "pcs"; + interrupt-parent = <&intc>; + interrupts = <0 44 4>,<0 45 4>; + interrupt-names = "rx_irq","tx_irq"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + max-frame-size = <1500>; + local-mac-address = [ 00 00 00 00 00 00 ]; + altr,has-supplementary-unicast; + altr,has-hash-multicast-filter; + sfp = <&sfp0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; - | tse_sub_1_eth_tse_0: ethernet@1,00001000 { compatible = "altr,tse-msgdma-1.0"; -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-09-01 14:36 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-01 14:35 [PATCH net-next v3 0/5] net: altera: tse: phylink conversion Maxime Chevallier 2022-09-01 14:35 ` Maxime Chevallier 2022-09-01 14:35 ` [PATCH net-next v3 1/5] dt-bindings: net: Convert Altera TSE bindings to yaml Maxime Chevallier 2022-09-01 14:35 ` Maxime Chevallier 2022-09-01 14:35 ` [PATCH net-next v3 2/5] net: altera: tse: cosmetic change to use reverse xmas tree ordering Maxime Chevallier 2022-09-01 14:35 ` Maxime Chevallier 2022-09-01 14:35 ` [PATCH net-next v3 3/5] net: pcs: add new PCS driver for altera TSE PCS Maxime Chevallier 2022-09-01 14:35 ` Maxime Chevallier 2022-10-09 5:38 ` Sean Anderson 2022-10-09 5:38 ` Sean Anderson 2022-10-26 9:37 ` Maxime Chevallier 2022-10-26 9:37 ` Maxime Chevallier 2022-10-26 12:05 ` Andrew Lunn 2022-10-26 12:05 ` Andrew Lunn 2022-10-26 12:47 ` Russell King (Oracle) 2022-10-26 12:47 ` Russell King (Oracle) 2022-09-01 14:35 ` [PATCH net-next v3 4/5] net: altera: tse: convert to phylink Maxime Chevallier 2022-09-01 14:35 ` Maxime Chevallier 2022-09-02 4:10 ` Jakub Kicinski 2022-09-02 4:10 ` Jakub Kicinski 2022-09-02 7:57 ` Maxime Chevallier 2022-09-02 7:57 ` Maxime Chevallier 2022-09-01 14:35 ` Maxime Chevallier [this message] 2022-09-01 14:35 ` [PATCH net-next v3 5/5] dt-bindings: net: altera: tse: add an optional pcs register range Maxime Chevallier
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