[PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Heiko Stuebner]

This can also do without the ifdef and use IS_ENABLED instead and
for better readability, getting rid of that switch also seems
waranted.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/kernel/cpufeature.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 553d755483ed..764ea220161f 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
 #ifdef CONFIG_RISCV_ALTERNATIVE
 static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
 {
-#ifdef CONFIG_RISCV_ISA_SVPBMT
-	switch (stage) {
-	case RISCV_ALTERNATIVES_EARLY_BOOT:
+	if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
 		return false;
-	default:
-		return riscv_isa_extension_available(NULL, SVPBMT);
-	}
-#endif
 
-	return false;
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		return false;
+
+	return riscv_isa_extension_available(NULL, SVPBMT);
 }
 
 static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
-- 
2.35.1

[PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Heiko Stuebner]

This can also do without the ifdef and use IS_ENABLED instead and
for better readability, getting rid of that switch also seems
waranted.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/kernel/cpufeature.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 553d755483ed..764ea220161f 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
 #ifdef CONFIG_RISCV_ALTERNATIVE
 static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
 {
-#ifdef CONFIG_RISCV_ISA_SVPBMT
-	switch (stage) {
-	case RISCV_ALTERNATIVES_EARLY_BOOT:
+	if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
 		return false;
-	default:
-		return riscv_isa_extension_available(NULL, SVPBMT);
-	}
-#endif
 
-	return false;
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		return false;
+
+	return riscv_isa_extension_available(NULL, SVPBMT);
 }
 
 static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
-- 
2.35.1


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[PATCH 2/4] riscv: drop some idefs from CMO initialization

[Heiko Stuebner]

Wrapping things in #ifdefs makes the code harder to read
while we also have IS_ENABLED() macros to do this in regular code
and the extension detection is not _that_ runtime critical.

So define a stub for riscv_noncoherent_supported() in the
non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
us IS_ENABLED.

Suggested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/errata/thead/errata.c    |  7 +++----
 arch/riscv/include/asm/cacheflush.h |  2 ++
 arch/riscv/kernel/cpufeature.c      | 22 +++++++++-------------
 3 files changed, 14 insertions(+), 17 deletions(-)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index 202c83f677b2..bffa711aaf64 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage,
 static bool errata_probe_cmo(unsigned int stage,
 			     unsigned long arch_id, unsigned long impid)
 {
-#ifdef CONFIG_ERRATA_THEAD_CMO
+	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
+		return false;
+
 	if (arch_id != 0 || impid != 0)
 		return false;
 
@@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage,
 
 	riscv_noncoherent_supported();
 	return true;
-#else
-	return false;
-#endif
 }
 
 static u32 thead_errata_probe(unsigned int stage,
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
index a60acaecfeda..4363d0beb38a 100644
--- a/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { }
 
 #ifdef CONFIG_RISCV_DMA_NONCOHERENT
 void riscv_noncoherent_supported(void);
+#else
+static inline void riscv_noncoherent_supported(void) {}
 #endif
 
 /*
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 764ea220161f..729f7a218093 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
 
 static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
 {
-#ifdef CONFIG_RISCV_ISA_ZICBOM
-	switch (stage) {
-	case RISCV_ALTERNATIVES_EARLY_BOOT:
+	if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
+		return false;
+
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		return false;
+
+	if (!riscv_isa_extension_available(NULL, ZICBOM))
 		return false;
-	default:
-		if (riscv_isa_extension_available(NULL, ZICBOM)) {
-			riscv_noncoherent_supported();
-			return true;
-		} else {
-			return false;
-		}
-	}
-#endif
 
-	return false;
+	riscv_noncoherent_supported();
+	return true;
 }
 
 /*
-- 
2.35.1

[PATCH 2/4] riscv: drop some idefs from CMO initialization

[Heiko Stuebner]

Wrapping things in #ifdefs makes the code harder to read
while we also have IS_ENABLED() macros to do this in regular code
and the extension detection is not _that_ runtime critical.

So define a stub for riscv_noncoherent_supported() in the
non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
us IS_ENABLED.

Suggested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/errata/thead/errata.c    |  7 +++----
 arch/riscv/include/asm/cacheflush.h |  2 ++
 arch/riscv/kernel/cpufeature.c      | 22 +++++++++-------------
 3 files changed, 14 insertions(+), 17 deletions(-)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index 202c83f677b2..bffa711aaf64 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage,
 static bool errata_probe_cmo(unsigned int stage,
 			     unsigned long arch_id, unsigned long impid)
 {
-#ifdef CONFIG_ERRATA_THEAD_CMO
+	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
+		return false;
+
 	if (arch_id != 0 || impid != 0)
 		return false;
 
@@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage,
 
 	riscv_noncoherent_supported();
 	return true;
-#else
-	return false;
-#endif
 }
 
 static u32 thead_errata_probe(unsigned int stage,
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
index a60acaecfeda..4363d0beb38a 100644
--- a/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { }
 
 #ifdef CONFIG_RISCV_DMA_NONCOHERENT
 void riscv_noncoherent_supported(void);
+#else
+static inline void riscv_noncoherent_supported(void) {}
 #endif
 
 /*
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 764ea220161f..729f7a218093 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
 
 static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
 {
-#ifdef CONFIG_RISCV_ISA_ZICBOM
-	switch (stage) {
-	case RISCV_ALTERNATIVES_EARLY_BOOT:
+	if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
+		return false;
+
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		return false;
+
+	if (!riscv_isa_extension_available(NULL, ZICBOM))
 		return false;
-	default:
-		if (riscv_isa_extension_available(NULL, ZICBOM)) {
-			riscv_noncoherent_supported();
-			return true;
-		} else {
-			return false;
-		}
-	}
-#endif
 
-	return false;
+	riscv_noncoherent_supported();
+	return true;
 }
 
 /*
-- 
2.35.1


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[PATCH 3/4] riscv: use BIT macros in t-head errata init

[Heiko Stuebner]

Using the appropriate BIT macro makes the code better readable.

Suggested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/errata/thead/errata.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index bffa711aaf64..a6f4bd8ccf3f 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -49,10 +49,10 @@ static u32 thead_errata_probe(unsigned int stage,
 	u32 cpu_req_errata = 0;
 
 	if (errata_probe_pbmt(stage, archid, impid))
-		cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);
+		cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
 
 	if (errata_probe_cmo(stage, archid, impid))
-		cpu_req_errata |= (1U << ERRATA_THEAD_CMO);
+		cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
 
 	return cpu_req_errata;
 }
-- 
2.35.1

[PATCH 3/4] riscv: use BIT macros in t-head errata init

[Heiko Stuebner]

Using the appropriate BIT macro makes the code better readable.

Suggested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/errata/thead/errata.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index bffa711aaf64..a6f4bd8ccf3f 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -49,10 +49,10 @@ static u32 thead_errata_probe(unsigned int stage,
 	u32 cpu_req_errata = 0;
 
 	if (errata_probe_pbmt(stage, archid, impid))
-		cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);
+		cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
 
 	if (errata_probe_cmo(stage, archid, impid))
-		cpu_req_errata |= (1U << ERRATA_THEAD_CMO);
+		cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
 
 	return cpu_req_errata;
 }
-- 
2.35.1


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[PATCH 4/4] riscv: check for kernel config option in t-head memory types errata

[Heiko Stuebner]

The t-head variant of page-based memory types should also check first
for the enabled kernel config option.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/errata/thead/errata.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index a6f4bd8ccf3f..902e12452821 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -17,6 +17,9 @@
 static bool errata_probe_pbmt(unsigned int stage,
 			      unsigned long arch_id, unsigned long impid)
 {
+	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
+		return false;
+
 	if (arch_id != 0 || impid != 0)
 		return false;
 
-- 
2.35.1

[PATCH 4/4] riscv: check for kernel config option in t-head memory types errata

[Heiko Stuebner]

The t-head variant of page-based memory types should also check first
for the enabled kernel config option.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/errata/thead/errata.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index a6f4bd8ccf3f..902e12452821 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -17,6 +17,9 @@
 static bool errata_probe_pbmt(unsigned int stage,
 			      unsigned long arch_id, unsigned long impid)
 {
+	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
+		return false;
+
 	if (arch_id != 0 || impid != 0)
 		return false;
 
-- 
2.35.1


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Re: [PATCH 2/4] riscv: drop some idefs from CMO initialization

[Guo Ren]

Reviewed-by: Guo Ren <guoren@kernel.org>

On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Wrapping things in #ifdefs makes the code harder to read
> while we also have IS_ENABLED() macros to do this in regular code
> and the extension detection is not _that_ runtime critical.
>
> So define a stub for riscv_noncoherent_supported() in the
> non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
> us IS_ENABLED.
>
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c    |  7 +++----
>  arch/riscv/include/asm/cacheflush.h |  2 ++
>  arch/riscv/kernel/cpufeature.c      | 22 +++++++++-------------
>  3 files changed, 14 insertions(+), 17 deletions(-)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index 202c83f677b2..bffa711aaf64 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage,
>  static bool errata_probe_cmo(unsigned int stage,
>                              unsigned long arch_id, unsigned long impid)
>  {
> -#ifdef CONFIG_ERRATA_THEAD_CMO
> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> +               return false;
> +
>         if (arch_id != 0 || impid != 0)
>                 return false;
>
> @@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage,
>
>         riscv_noncoherent_supported();
>         return true;
> -#else
> -       return false;
> -#endif
>  }
>
>  static u32 thead_errata_probe(unsigned int stage,
> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> index a60acaecfeda..4363d0beb38a 100644
> --- a/arch/riscv/include/asm/cacheflush.h
> +++ b/arch/riscv/include/asm/cacheflush.h
> @@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { }
>
>  #ifdef CONFIG_RISCV_DMA_NONCOHERENT
>  void riscv_noncoherent_supported(void);
> +#else
> +static inline void riscv_noncoherent_supported(void) {}
>  #endif
>
>  /*
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 764ea220161f..729f7a218093 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>
>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
>  {
> -#ifdef CONFIG_RISCV_ISA_ZICBOM
> -       switch (stage) {
> -       case RISCV_ALTERNATIVES_EARLY_BOOT:
> +       if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
> +               return false;
> +
> +       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +               return false;
> +
> +       if (!riscv_isa_extension_available(NULL, ZICBOM))
>                 return false;
> -       default:
> -               if (riscv_isa_extension_available(NULL, ZICBOM)) {
> -                       riscv_noncoherent_supported();
> -                       return true;
> -               } else {
> -                       return false;
> -               }
> -       }
> -#endif
>
> -       return false;
> +       riscv_noncoherent_supported();
> +       return true;
>  }
>
>  /*
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

Re: [PATCH 2/4] riscv: drop some idefs from CMO initialization

[Guo Ren]

Reviewed-by: Guo Ren <guoren@kernel.org>

On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Wrapping things in #ifdefs makes the code harder to read
> while we also have IS_ENABLED() macros to do this in regular code
> and the extension detection is not _that_ runtime critical.
>
> So define a stub for riscv_noncoherent_supported() in the
> non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
> us IS_ENABLED.
>
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c    |  7 +++----
>  arch/riscv/include/asm/cacheflush.h |  2 ++
>  arch/riscv/kernel/cpufeature.c      | 22 +++++++++-------------
>  3 files changed, 14 insertions(+), 17 deletions(-)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index 202c83f677b2..bffa711aaf64 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage,
>  static bool errata_probe_cmo(unsigned int stage,
>                              unsigned long arch_id, unsigned long impid)
>  {
> -#ifdef CONFIG_ERRATA_THEAD_CMO
> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> +               return false;
> +
>         if (arch_id != 0 || impid != 0)
>                 return false;
>
> @@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage,
>
>         riscv_noncoherent_supported();
>         return true;
> -#else
> -       return false;
> -#endif
>  }
>
>  static u32 thead_errata_probe(unsigned int stage,
> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> index a60acaecfeda..4363d0beb38a 100644
> --- a/arch/riscv/include/asm/cacheflush.h
> +++ b/arch/riscv/include/asm/cacheflush.h
> @@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { }
>
>  #ifdef CONFIG_RISCV_DMA_NONCOHERENT
>  void riscv_noncoherent_supported(void);
> +#else
> +static inline void riscv_noncoherent_supported(void) {}
>  #endif
>
>  /*
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 764ea220161f..729f7a218093 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>
>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
>  {
> -#ifdef CONFIG_RISCV_ISA_ZICBOM
> -       switch (stage) {
> -       case RISCV_ALTERNATIVES_EARLY_BOOT:
> +       if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
> +               return false;
> +
> +       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +               return false;
> +
> +       if (!riscv_isa_extension_available(NULL, ZICBOM))
>                 return false;
> -       default:
> -               if (riscv_isa_extension_available(NULL, ZICBOM)) {
> -                       riscv_noncoherent_supported();
> -                       return true;
> -               } else {
> -                       return false;
> -               }
> -       }
> -#endif
>
> -       return false;
> +       riscv_noncoherent_supported();
> +       return true;
>  }
>
>  /*
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

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Re: [PATCH 3/4] riscv: use BIT macros in t-head errata init

[Guo Ren]

Reviewed-by: Guo Ren <guoren@kernel.org>

On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Using the appropriate BIT macro makes the code better readable.
>
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index bffa711aaf64..a6f4bd8ccf3f 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -49,10 +49,10 @@ static u32 thead_errata_probe(unsigned int stage,
>         u32 cpu_req_errata = 0;
>
>         if (errata_probe_pbmt(stage, archid, impid))
> -               cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);
> +               cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
>
>         if (errata_probe_cmo(stage, archid, impid))
> -               cpu_req_errata |= (1U << ERRATA_THEAD_CMO);
> +               cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
>
>         return cpu_req_errata;
>  }
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

Re: [PATCH 3/4] riscv: use BIT macros in t-head errata init

[Guo Ren]

Reviewed-by: Guo Ren <guoren@kernel.org>

On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Using the appropriate BIT macro makes the code better readable.
>
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index bffa711aaf64..a6f4bd8ccf3f 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -49,10 +49,10 @@ static u32 thead_errata_probe(unsigned int stage,
>         u32 cpu_req_errata = 0;
>
>         if (errata_probe_pbmt(stage, archid, impid))
> -               cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);
> +               cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
>
>         if (errata_probe_cmo(stage, archid, impid))
> -               cpu_req_errata |= (1U << ERRATA_THEAD_CMO);
> +               cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
>
>         return cpu_req_errata;
>  }
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

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Re: [PATCH 4/4] riscv: check for kernel config option in t-head memory types errata

[Guo Ren]

Is it a Fixes?

On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> The t-head variant of page-based memory types should also check first
> for the enabled kernel config option.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index a6f4bd8ccf3f..902e12452821 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -17,6 +17,9 @@
>  static bool errata_probe_pbmt(unsigned int stage,
>                               unsigned long arch_id, unsigned long impid)
>  {
> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> +               return false;
> +
>         if (arch_id != 0 || impid != 0)
>                 return false;
>
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

Re: [PATCH 4/4] riscv: check for kernel config option in t-head memory types errata

[Guo Ren]

Is it a Fixes?

On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> The t-head variant of page-based memory types should also check first
> for the enabled kernel config option.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index a6f4bd8ccf3f..902e12452821 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -17,6 +17,9 @@
>  static bool errata_probe_pbmt(unsigned int stage,
>                               unsigned long arch_id, unsigned long impid)
>  {
> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> +               return false;
> +
>         if (arch_id != 0 || impid != 0)
>                 return false;
>
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

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Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Guo Ren]

Reviewed-by: Guo Ren <guoren@kernel.org>

On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> This can also do without the ifdef and use IS_ENABLED instead and
> for better readability, getting rid of that switch also seems
> waranted.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/kernel/cpufeature.c | 13 +++++--------
>  1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..764ea220161f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
>  #ifdef CONFIG_RISCV_ALTERNATIVE
>  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>  {
> -#ifdef CONFIG_RISCV_ISA_SVPBMT
> -       switch (stage) {
> -       case RISCV_ALTERNATIVES_EARLY_BOOT:
> +       if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
>                 return false;
> -       default:
> -               return riscv_isa_extension_available(NULL, SVPBMT);
> -       }
> -#endif
>
> -       return false;
> +       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +               return false;
> +
> +       return riscv_isa_extension_available(NULL, SVPBMT);
>  }
>
>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Guo Ren]

Reviewed-by: Guo Ren <guoren@kernel.org>

On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> This can also do without the ifdef and use IS_ENABLED instead and
> for better readability, getting rid of that switch also seems
> waranted.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/kernel/cpufeature.c | 13 +++++--------
>  1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..764ea220161f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
>  #ifdef CONFIG_RISCV_ALTERNATIVE
>  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>  {
> -#ifdef CONFIG_RISCV_ISA_SVPBMT
> -       switch (stage) {
> -       case RISCV_ALTERNATIVES_EARLY_BOOT:
> +       if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
>                 return false;
> -       default:
> -               return riscv_isa_extension_available(NULL, SVPBMT);
> -       }
> -#endif
>
> -       return false;
> +       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +               return false;
> +
> +       return riscv_isa_extension_available(NULL, SVPBMT);
>  }
>
>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

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Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Conor.Dooley]

On 01/09/2022 23:27, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> This can also do without the ifdef and use IS_ENABLED instead and
> for better readability, getting rid of that switch also seems
> waranted.

The change itself looks great to me, but the commit message here
does not stand by itself - the "also" stuff reads a bit oddly.
How about:
---8<---
For better readability (and compile time coverage) use IS_ENABLED
instead of ifdef and drop the new unneeded switch statement.
---8<---

Call me biased, but I much prefer how this looks now...

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>   arch/riscv/kernel/cpufeature.c | 13 +++++--------
>   1 file changed, 5 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..764ea220161f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
>   #ifdef CONFIG_RISCV_ALTERNATIVE
>   static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>   {
> -#ifdef CONFIG_RISCV_ISA_SVPBMT
> -       switch (stage) {
> -       case RISCV_ALTERNATIVES_EARLY_BOOT:
> +       if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
>                  return false;
> -       default:
> -               return riscv_isa_extension_available(NULL, SVPBMT);
> -       }
> -#endif
> 
> -       return false;
> +       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +               return false;
> +
> +       return riscv_isa_extension_available(NULL, SVPBMT);
>   }
> 
>   static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> --
> 2.35.1
> 

Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Conor.Dooley]

On 01/09/2022 23:27, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> This can also do without the ifdef and use IS_ENABLED instead and
> for better readability, getting rid of that switch also seems
> waranted.

The change itself looks great to me, but the commit message here
does not stand by itself - the "also" stuff reads a bit oddly.
How about:
---8<---
For better readability (and compile time coverage) use IS_ENABLED
instead of ifdef and drop the new unneeded switch statement.
---8<---

Call me biased, but I much prefer how this looks now...

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>   arch/riscv/kernel/cpufeature.c | 13 +++++--------
>   1 file changed, 5 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..764ea220161f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
>   #ifdef CONFIG_RISCV_ALTERNATIVE
>   static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>   {
> -#ifdef CONFIG_RISCV_ISA_SVPBMT
> -       switch (stage) {
> -       case RISCV_ALTERNATIVES_EARLY_BOOT:
> +       if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
>                  return false;
> -       default:
> -               return riscv_isa_extension_available(NULL, SVPBMT);
> -       }
> -#endif
> 
> -       return false;
> +       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +               return false;
> +
> +       return riscv_isa_extension_available(NULL, SVPBMT);
>   }
> 
>   static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> --
> 2.35.1
> 

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Re: [PATCH 4/4] riscv: check for kernel config option in t-head memory types errata

[Conor.Dooley]

On 02/09/2022 02:06, Guo Ren wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Is it a Fixes?

Looks like one to me, seems a fixes tag would be good to
have here... Either way:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> 
> On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
>>
>> The t-head variant of page-based memory types should also check first
>> for the enabled kernel config option.
>>
>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> ---
>>   arch/riscv/errata/thead/errata.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
>> index a6f4bd8ccf3f..902e12452821 100644
>> --- a/arch/riscv/errata/thead/errata.c
>> +++ b/arch/riscv/errata/thead/errata.c
>> @@ -17,6 +17,9 @@
>>   static bool errata_probe_pbmt(unsigned int stage,
>>                                unsigned long arch_id, unsigned long impid)
>>   {
>> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
>> +               return false;
>> +
>>          if (arch_id != 0 || impid != 0)
>>                  return false;
>>
>> --
>> 2.35.1
>>
> 
> 
> --
> Best Regards
>   Guo Ren

Re: [PATCH 4/4] riscv: check for kernel config option in t-head memory types errata

[Conor.Dooley]

On 02/09/2022 02:06, Guo Ren wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Is it a Fixes?

Looks like one to me, seems a fixes tag would be good to
have here... Either way:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> 
> On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
>>
>> The t-head variant of page-based memory types should also check first
>> for the enabled kernel config option.
>>
>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> ---
>>   arch/riscv/errata/thead/errata.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
>> index a6f4bd8ccf3f..902e12452821 100644
>> --- a/arch/riscv/errata/thead/errata.c
>> +++ b/arch/riscv/errata/thead/errata.c
>> @@ -17,6 +17,9 @@
>>   static bool errata_probe_pbmt(unsigned int stage,
>>                                unsigned long arch_id, unsigned long impid)
>>   {
>> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
>> +               return false;
>> +
>>          if (arch_id != 0 || impid != 0)
>>                  return false;
>>
>> --
>> 2.35.1
>>
> 
> 
> --
> Best Regards
>   Guo Ren

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Re: [PATCH 2/4] riscv: drop some idefs from CMO initialization

[Conor.Dooley]

On 01/09/2022 23:27, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Wrapping things in #ifdefs makes the code harder to read
> while we also have IS_ENABLED() macros to do this in regular code
> and the extension detection is not _that_ runtime critical.
> 
> So define a stub for riscv_noncoherent_supported() in the
> non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
> us IS_ENABLED.
> 
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>

To my "sensitive" eyes, this looks a lot nicer!

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>   arch/riscv/errata/thead/errata.c    |  7 +++----
>   arch/riscv/include/asm/cacheflush.h |  2 ++
>   arch/riscv/kernel/cpufeature.c      | 22 +++++++++-------------
>   3 files changed, 14 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index 202c83f677b2..bffa711aaf64 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage,
>   static bool errata_probe_cmo(unsigned int stage,
>                               unsigned long arch_id, unsigned long impid)
>   {
> -#ifdef CONFIG_ERRATA_THEAD_CMO
> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> +               return false;
> +
>          if (arch_id != 0 || impid != 0)
>                  return false;
> 
> @@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage,
> 
>          riscv_noncoherent_supported();
>          return true;
> -#else
> -       return false;
> -#endif
>   }
> 
>   static u32 thead_errata_probe(unsigned int stage,
> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> index a60acaecfeda..4363d0beb38a 100644
> --- a/arch/riscv/include/asm/cacheflush.h
> +++ b/arch/riscv/include/asm/cacheflush.h
> @@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { }
> 
>   #ifdef CONFIG_RISCV_DMA_NONCOHERENT
>   void riscv_noncoherent_supported(void);
> +#else
> +static inline void riscv_noncoherent_supported(void) {}
>   #endif
> 
>   /*
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 764ea220161f..729f7a218093 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
> 
>   static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
>   {
> -#ifdef CONFIG_RISCV_ISA_ZICBOM
> -       switch (stage) {
> -       case RISCV_ALTERNATIVES_EARLY_BOOT:
> +       if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
> +               return false;
> +
> +       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +               return false;
> +
> +       if (!riscv_isa_extension_available(NULL, ZICBOM))
>                  return false;
> -       default:
> -               if (riscv_isa_extension_available(NULL, ZICBOM)) {
> -                       riscv_noncoherent_supported();
> -                       return true;
> -               } else {
> -                       return false;
> -               }
> -       }
> -#endif
> 
> -       return false;
> +       riscv_noncoherent_supported();
> +       return true;
>   }
> 
>   /*
> --
> 2.35.1
> 

Re: [PATCH 2/4] riscv: drop some idefs from CMO initialization

[Conor.Dooley]

On 01/09/2022 23:27, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Wrapping things in #ifdefs makes the code harder to read
> while we also have IS_ENABLED() macros to do this in regular code
> and the extension detection is not _that_ runtime critical.
> 
> So define a stub for riscv_noncoherent_supported() in the
> non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
> us IS_ENABLED.
> 
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>

To my "sensitive" eyes, this looks a lot nicer!

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>   arch/riscv/errata/thead/errata.c    |  7 +++----
>   arch/riscv/include/asm/cacheflush.h |  2 ++
>   arch/riscv/kernel/cpufeature.c      | 22 +++++++++-------------
>   3 files changed, 14 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index 202c83f677b2..bffa711aaf64 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage,
>   static bool errata_probe_cmo(unsigned int stage,
>                               unsigned long arch_id, unsigned long impid)
>   {
> -#ifdef CONFIG_ERRATA_THEAD_CMO
> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> +               return false;
> +
>          if (arch_id != 0 || impid != 0)
>                  return false;
> 
> @@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage,
> 
>          riscv_noncoherent_supported();
>          return true;
> -#else
> -       return false;
> -#endif
>   }
> 
>   static u32 thead_errata_probe(unsigned int stage,
> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> index a60acaecfeda..4363d0beb38a 100644
> --- a/arch/riscv/include/asm/cacheflush.h
> +++ b/arch/riscv/include/asm/cacheflush.h
> @@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { }
> 
>   #ifdef CONFIG_RISCV_DMA_NONCOHERENT
>   void riscv_noncoherent_supported(void);
> +#else
> +static inline void riscv_noncoherent_supported(void) {}
>   #endif
> 
>   /*
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 764ea220161f..729f7a218093 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
> 
>   static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
>   {
> -#ifdef CONFIG_RISCV_ISA_ZICBOM
> -       switch (stage) {
> -       case RISCV_ALTERNATIVES_EARLY_BOOT:
> +       if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
> +               return false;
> +
> +       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +               return false;
> +
> +       if (!riscv_isa_extension_available(NULL, ZICBOM))
>                  return false;
> -       default:
> -               if (riscv_isa_extension_available(NULL, ZICBOM)) {
> -                       riscv_noncoherent_supported();
> -                       return true;
> -               } else {
> -                       return false;
> -               }
> -       }
> -#endif
> 
> -       return false;
> +       riscv_noncoherent_supported();
> +       return true;
>   }
> 
>   /*
> --
> 2.35.1
> 

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Re: [PATCH 3/4] riscv: use BIT macros in t-head errata init

[Conor.Dooley]

On 01/09/2022 23:27, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Using the appropriate BIT macro makes the code better readable.

As you might imagine, I agree!
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> 
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>   arch/riscv/errata/thead/errata.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index bffa711aaf64..a6f4bd8ccf3f 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -49,10 +49,10 @@ static u32 thead_errata_probe(unsigned int stage,
>          u32 cpu_req_errata = 0;
> 
>          if (errata_probe_pbmt(stage, archid, impid))
> -               cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);
> +               cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
> 
>          if (errata_probe_cmo(stage, archid, impid))
> -               cpu_req_errata |= (1U << ERRATA_THEAD_CMO);
> +               cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
> 
>          return cpu_req_errata;
>   }
> --
> 2.35.1
> 

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Re: [PATCH 3/4] riscv: use BIT macros in t-head errata init

[Conor.Dooley]

On 01/09/2022 23:27, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Using the appropriate BIT macro makes the code better readable.

As you might imagine, I agree!
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> 
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>   arch/riscv/errata/thead/errata.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index bffa711aaf64..a6f4bd8ccf3f 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -49,10 +49,10 @@ static u32 thead_errata_probe(unsigned int stage,
>          u32 cpu_req_errata = 0;
> 
>          if (errata_probe_pbmt(stage, archid, impid))
> -               cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);
> +               cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
> 
>          if (errata_probe_cmo(stage, archid, impid))
> -               cpu_req_errata |= (1U << ERRATA_THEAD_CMO);
> +               cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
> 
>          return cpu_req_errata;
>   }
> --
> 2.35.1
> 

Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Andrew Jones]

Hi Heiko,

Please use a cover-letter for a patch series. They allow the series to be
threaded better and people can reply to the cover-letter with series-wide
comments. For example, I'd like to reply to a cover-letter now with

For the series

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

but now it looks like I need to go back and reply to each patch
separately.

Thanks,
drew

On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote:
> This can also do without the ifdef and use IS_ENABLED instead and
> for better readability, getting rid of that switch also seems
> waranted.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/kernel/cpufeature.c | 13 +++++--------
>  1 file changed, 5 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..764ea220161f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
>  #ifdef CONFIG_RISCV_ALTERNATIVE
>  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>  {
> -#ifdef CONFIG_RISCV_ISA_SVPBMT
> -	switch (stage) {
> -	case RISCV_ALTERNATIVES_EARLY_BOOT:
> +	if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
>  		return false;
> -	default:
> -		return riscv_isa_extension_available(NULL, SVPBMT);
> -	}
> -#endif
>  
> -	return false;
> +	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +		return false;
> +
> +	return riscv_isa_extension_available(NULL, SVPBMT);
>  }
>  
>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> -- 
> 2.35.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Andrew Jones]

Hi Heiko,

Please use a cover-letter for a patch series. They allow the series to be
threaded better and people can reply to the cover-letter with series-wide
comments. For example, I'd like to reply to a cover-letter now with

For the series

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

but now it looks like I need to go back and reply to each patch
separately.

Thanks,
drew

On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote:
> This can also do without the ifdef and use IS_ENABLED instead and
> for better readability, getting rid of that switch also seems
> waranted.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/kernel/cpufeature.c | 13 +++++--------
>  1 file changed, 5 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..764ea220161f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
>  #ifdef CONFIG_RISCV_ALTERNATIVE
>  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>  {
> -#ifdef CONFIG_RISCV_ISA_SVPBMT
> -	switch (stage) {
> -	case RISCV_ALTERNATIVES_EARLY_BOOT:
> +	if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
>  		return false;
> -	default:
> -		return riscv_isa_extension_available(NULL, SVPBMT);
> -	}
> -#endif
>  
> -	return false;
> +	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +		return false;
> +
> +	return riscv_isa_extension_available(NULL, SVPBMT);
>  }
>  
>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> -- 
> 2.35.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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Re: [PATCH 2/4] riscv: drop some idefs from CMO initialization

[Andrew Jones]

On Fri, Sep 02, 2022 at 12:27:42AM +0200, Heiko Stuebner wrote:
> Wrapping things in #ifdefs makes the code harder to read
> while we also have IS_ENABLED() macros to do this in regular code
> and the extension detection is not _that_ runtime critical.
> 
> So define a stub for riscv_noncoherent_supported() in the
> non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
> us IS_ENABLED.
> 
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c    |  7 +++----
>  arch/riscv/include/asm/cacheflush.h |  2 ++
>  arch/riscv/kernel/cpufeature.c      | 22 +++++++++-------------
>  3 files changed, 14 insertions(+), 17 deletions(-)
>


Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [PATCH 2/4] riscv: drop some idefs from CMO initialization

[Andrew Jones]

On Fri, Sep 02, 2022 at 12:27:42AM +0200, Heiko Stuebner wrote:
> Wrapping things in #ifdefs makes the code harder to read
> while we also have IS_ENABLED() macros to do this in regular code
> and the extension detection is not _that_ runtime critical.
> 
> So define a stub for riscv_noncoherent_supported() in the
> non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
> us IS_ENABLED.
> 
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c    |  7 +++----
>  arch/riscv/include/asm/cacheflush.h |  2 ++
>  arch/riscv/kernel/cpufeature.c      | 22 +++++++++-------------
>  3 files changed, 14 insertions(+), 17 deletions(-)
>


Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

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Re: [PATCH 3/4] riscv: use BIT macros in t-head errata init

[Andrew Jones]

On Fri, Sep 02, 2022 at 12:27:43AM +0200, Heiko Stuebner wrote:
> Using the appropriate BIT macro makes the code better readable.
> 
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index bffa711aaf64..a6f4bd8ccf3f 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -49,10 +49,10 @@ static u32 thead_errata_probe(unsigned int stage,
>  	u32 cpu_req_errata = 0;
>  
>  	if (errata_probe_pbmt(stage, archid, impid))
> -		cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);
> +		cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
>  
>  	if (errata_probe_cmo(stage, archid, impid))
> -		cpu_req_errata |= (1U << ERRATA_THEAD_CMO);
> +		cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
>  
>  	return cpu_req_errata;
>  }
> -- 
> 2.35.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [PATCH 3/4] riscv: use BIT macros in t-head errata init

[Andrew Jones]

On Fri, Sep 02, 2022 at 12:27:43AM +0200, Heiko Stuebner wrote:
> Using the appropriate BIT macro makes the code better readable.
> 
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index bffa711aaf64..a6f4bd8ccf3f 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -49,10 +49,10 @@ static u32 thead_errata_probe(unsigned int stage,
>  	u32 cpu_req_errata = 0;
>  
>  	if (errata_probe_pbmt(stage, archid, impid))
> -		cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);
> +		cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
>  
>  	if (errata_probe_cmo(stage, archid, impid))
> -		cpu_req_errata |= (1U << ERRATA_THEAD_CMO);
> +		cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
>  
>  	return cpu_req_errata;
>  }
> -- 
> 2.35.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

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Re: [PATCH 4/4] riscv: check for kernel config option in t-head memory types errata

[Andrew Jones]

On Fri, Sep 02, 2022 at 12:27:44AM +0200, Heiko Stuebner wrote:
> The t-head variant of page-based memory types should also check first
> for the enabled kernel config option.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index a6f4bd8ccf3f..902e12452821 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -17,6 +17,9 @@
>  static bool errata_probe_pbmt(unsigned int stage,
>  			      unsigned long arch_id, unsigned long impid)
>  {
> +	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> +		return false;
> +
>  	if (arch_id != 0 || impid != 0)
>  		return false;
>  
> -- 
> 2.35.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [PATCH 4/4] riscv: check for kernel config option in t-head memory types errata

[Andrew Jones]

On Fri, Sep 02, 2022 at 12:27:44AM +0200, Heiko Stuebner wrote:
> The t-head variant of page-based memory types should also check first
> for the enabled kernel config option.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/errata/thead/errata.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index a6f4bd8ccf3f..902e12452821 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -17,6 +17,9 @@
>  static bool errata_probe_pbmt(unsigned int stage,
>  			      unsigned long arch_id, unsigned long impid)
>  {
> +	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> +		return false;
> +
>  	if (arch_id != 0 || impid != 0)
>  		return false;
>  
> -- 
> 2.35.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

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Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Andrew Jones]

On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote:
> This can also do without the ifdef and use IS_ENABLED instead and
> for better readability, getting rid of that switch also seems
> waranted.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/kernel/cpufeature.c | 13 +++++--------
>  1 file changed, 5 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..764ea220161f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
>  #ifdef CONFIG_RISCV_ALTERNATIVE
>  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>  {
> -#ifdef CONFIG_RISCV_ISA_SVPBMT
> -	switch (stage) {
> -	case RISCV_ALTERNATIVES_EARLY_BOOT:
> +	if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
>  		return false;
> -	default:
> -		return riscv_isa_extension_available(NULL, SVPBMT);
> -	}
> -#endif
>  
> -	return false;
> +	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +		return false;
> +
> +	return riscv_isa_extension_available(NULL, SVPBMT);
>  }
>  
>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> -- 
> 2.35.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

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Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Andrew Jones]

On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote:
> This can also do without the ifdef and use IS_ENABLED instead and
> for better readability, getting rid of that switch also seems
> waranted.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/kernel/cpufeature.c | 13 +++++--------
>  1 file changed, 5 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..764ea220161f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
>  #ifdef CONFIG_RISCV_ALTERNATIVE
>  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>  {
> -#ifdef CONFIG_RISCV_ISA_SVPBMT
> -	switch (stage) {
> -	case RISCV_ALTERNATIVES_EARLY_BOOT:
> +	if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
>  		return false;
> -	default:
> -		return riscv_isa_extension_available(NULL, SVPBMT);
> -	}
> -#endif
>  
> -	return false;
> +	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +		return false;
> +
> +	return riscv_isa_extension_available(NULL, SVPBMT);
>  }
>  
>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> -- 
> 2.35.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Heiko Stübner]

Am Freitag, 2. September 2022, 11:49:39 CEST schrieb Andrew Jones:
> Hi Heiko,
> 
> Please use a cover-letter for a patch series. They allow the series to be
> threaded better and people can reply to the cover-letter with series-wide
> comments. For example, I'd like to reply to a cover-letter now with
> 
> For the series
> 
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> 
> but now it looks like I need to go back and reply to each patch
> separately.

I'm not sure if tooling like b4 can handle Reviewed-by's in cover-letters.
At least some time back it couldn't, so am not sure if that was added
meanwhile. So tags added to cover-letters might even get lost.

But I'll add a cover-letter nevertheless - need a place for the v2 changelog
anyway :-)

Heiko


> 
> Thanks,
> drew
> 
> On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote:
> > This can also do without the ifdef and use IS_ENABLED instead and
> > for better readability, getting rid of that switch also seems
> > waranted.
> > 
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> >  arch/riscv/kernel/cpufeature.c | 13 +++++--------
> >  1 file changed, 5 insertions(+), 8 deletions(-)
> > 
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 553d755483ed..764ea220161f 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
> >  #ifdef CONFIG_RISCV_ALTERNATIVE
> >  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
> >  {
> > -#ifdef CONFIG_RISCV_ISA_SVPBMT
> > -	switch (stage) {
> > -	case RISCV_ALTERNATIVES_EARLY_BOOT:
> > +	if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
> >  		return false;
> > -	default:
> > -		return riscv_isa_extension_available(NULL, SVPBMT);
> > -	}
> > -#endif
> >  
> > -	return false;
> > +	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > +		return false;
> > +
> > +	return riscv_isa_extension_available(NULL, SVPBMT);
> >  }
> >  
> >  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> 





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Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Heiko Stübner]

Am Freitag, 2. September 2022, 11:49:39 CEST schrieb Andrew Jones:
> Hi Heiko,
> 
> Please use a cover-letter for a patch series. They allow the series to be
> threaded better and people can reply to the cover-letter with series-wide
> comments. For example, I'd like to reply to a cover-letter now with
> 
> For the series
> 
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> 
> but now it looks like I need to go back and reply to each patch
> separately.

I'm not sure if tooling like b4 can handle Reviewed-by's in cover-letters.
At least some time back it couldn't, so am not sure if that was added
meanwhile. So tags added to cover-letters might even get lost.

But I'll add a cover-letter nevertheless - need a place for the v2 changelog
anyway :-)

Heiko


> 
> Thanks,
> drew
> 
> On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote:
> > This can also do without the ifdef and use IS_ENABLED instead and
> > for better readability, getting rid of that switch also seems
> > waranted.
> > 
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> >  arch/riscv/kernel/cpufeature.c | 13 +++++--------
> >  1 file changed, 5 insertions(+), 8 deletions(-)
> > 
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 553d755483ed..764ea220161f 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
> >  #ifdef CONFIG_RISCV_ALTERNATIVE
> >  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
> >  {
> > -#ifdef CONFIG_RISCV_ISA_SVPBMT
> > -	switch (stage) {
> > -	case RISCV_ALTERNATIVES_EARLY_BOOT:
> > +	if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
> >  		return false;
> > -	default:
> > -		return riscv_isa_extension_available(NULL, SVPBMT);
> > -	}
> > -#endif
> >  
> > -	return false;
> > +	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > +		return false;
> > +
> > +	return riscv_isa_extension_available(NULL, SVPBMT);
> >  }
> >  
> >  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> 

Re: [PATCH 4/4] riscv: check for kernel config option in t-head memory types errata

[Heiko Stübner]

Am Freitag, 2. September 2022, 11:33:27 CEST schrieb Conor.Dooley@microchip.com:
> On 02/09/2022 02:06, Guo Ren wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > Is it a Fixes?
> 
> Looks like one to me, seems a fixes tag would be good to
> have here... Either way:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

The alternative itself also is protected by the kconfig-option,
so even if probe says "yes", nothing will be patched when
CONFIG_ERRATA_THEAD_PBMT is not enabled.

So for the memory-types it's more a change to keep it consistent
with the other extensions. But I guess we can add the fixes-tag
anyway, as it makes sure that doesn't get copy-pasted somewhere
else :-)


Heiko



> > 
> > On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
> >>
> >> The t-head variant of page-based memory types should also check first
> >> for the enabled kernel config option.
> >>
> >> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> >> ---
> >>   arch/riscv/errata/thead/errata.c | 3 +++
> >>   1 file changed, 3 insertions(+)
> >>
> >> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> >> index a6f4bd8ccf3f..902e12452821 100644
> >> --- a/arch/riscv/errata/thead/errata.c
> >> +++ b/arch/riscv/errata/thead/errata.c
> >> @@ -17,6 +17,9 @@
> >>   static bool errata_probe_pbmt(unsigned int stage,
> >>                                unsigned long arch_id, unsigned long impid)
> >>   {
> >> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> >> +               return false;
> >> +
> >>          if (arch_id != 0 || impid != 0)
> >>                  return false;
> >>
> >> --
> >> 2.35.1
> >>
> > 
> > 
> > --
> > Best Regards
> >   Guo Ren
> 
> 





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Re: [PATCH 4/4] riscv: check for kernel config option in t-head memory types errata

[Heiko Stübner]

Am Freitag, 2. September 2022, 11:33:27 CEST schrieb Conor.Dooley@microchip.com:
> On 02/09/2022 02:06, Guo Ren wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > Is it a Fixes?
> 
> Looks like one to me, seems a fixes tag would be good to
> have here... Either way:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

The alternative itself also is protected by the kconfig-option,
so even if probe says "yes", nothing will be patched when
CONFIG_ERRATA_THEAD_PBMT is not enabled.

So for the memory-types it's more a change to keep it consistent
with the other extensions. But I guess we can add the fixes-tag
anyway, as it makes sure that doesn't get copy-pasted somewhere
else :-)


Heiko



> > 
> > On Fri, Sep 2, 2022 at 6:28 AM Heiko Stuebner <heiko@sntech.de> wrote:
> >>
> >> The t-head variant of page-based memory types should also check first
> >> for the enabled kernel config option.
> >>
> >> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> >> ---
> >>   arch/riscv/errata/thead/errata.c | 3 +++
> >>   1 file changed, 3 insertions(+)
> >>
> >> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> >> index a6f4bd8ccf3f..902e12452821 100644
> >> --- a/arch/riscv/errata/thead/errata.c
> >> +++ b/arch/riscv/errata/thead/errata.c
> >> @@ -17,6 +17,9 @@
> >>   static bool errata_probe_pbmt(unsigned int stage,
> >>                                unsigned long arch_id, unsigned long impid)
> >>   {
> >> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> >> +               return false;
> >> +
> >>          if (arch_id != 0 || impid != 0)
> >>                  return false;
> >>
> >> --
> >> 2.35.1
> >>
> > 
> > 
> > --
> > Best Regards
> >   Guo Ren
> 
> 

Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Conor.Dooley]

On 02/09/2022 16:12, Heiko Stübner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Am Freitag, 2. September 2022, 11:49:39 CEST schrieb Andrew Jones:
>> Hi Heiko,
>>
>> Please use a cover-letter for a patch series. They allow the series to be
>> threaded better and people can reply to the cover-letter with series-wide
>> comments. For example, I'd like to reply to a cover-letter now with
>>
>> For the series
>>
>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>>
>> but now it looks like I need to go back and reply to each patch
>> separately.
> 
> I'm not sure if tooling like b4 can handle Reviewed-by's in cover-letters.

Yup, it can! At least `b4 {am,shazam} -t` will.
I am not sure if the new `b4 trailers` does.

> At least some time back it couldn't, so am not sure if that was added
> meanwhile. So tags added to cover-letters might even get lost.
> 
> But I'll add a cover-letter nevertheless - need a place for the v2 changelog
> anyway :-)
> 
> Heiko
> 
> 
>>
>> Thanks,
>> drew
>>
>> On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote:
>>> This can also do without the ifdef and use IS_ENABLED instead and
>>> for better readability, getting rid of that switch also seems
>>> waranted.
>>>
>>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>>> ---
>>>  arch/riscv/kernel/cpufeature.c | 13 +++++--------
>>>  1 file changed, 5 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>>> index 553d755483ed..764ea220161f 100644
>>> --- a/arch/riscv/kernel/cpufeature.c
>>> +++ b/arch/riscv/kernel/cpufeature.c
>>> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
>>>  #ifdef CONFIG_RISCV_ALTERNATIVE
>>>  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>>>  {
>>> -#ifdef CONFIG_RISCV_ISA_SVPBMT
>>> -   switch (stage) {
>>> -   case RISCV_ALTERNATIVES_EARLY_BOOT:
>>> +   if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
>>>             return false;
>>> -   default:
>>> -           return riscv_isa_extension_available(NULL, SVPBMT);
>>> -   }
>>> -#endif
>>>
>>> -   return false;
>>> +   if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
>>> +           return false;
>>> +
>>> +   return riscv_isa_extension_available(NULL, SVPBMT);
>>>  }
>>>
>>>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
>>
> 
> 
> 
> 

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Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Conor.Dooley]

On 02/09/2022 16:12, Heiko Stübner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Am Freitag, 2. September 2022, 11:49:39 CEST schrieb Andrew Jones:
>> Hi Heiko,
>>
>> Please use a cover-letter for a patch series. They allow the series to be
>> threaded better and people can reply to the cover-letter with series-wide
>> comments. For example, I'd like to reply to a cover-letter now with
>>
>> For the series
>>
>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>>
>> but now it looks like I need to go back and reply to each patch
>> separately.
> 
> I'm not sure if tooling like b4 can handle Reviewed-by's in cover-letters.

Yup, it can! At least `b4 {am,shazam} -t` will.
I am not sure if the new `b4 trailers` does.

> At least some time back it couldn't, so am not sure if that was added
> meanwhile. So tags added to cover-letters might even get lost.
> 
> But I'll add a cover-letter nevertheless - need a place for the v2 changelog
> anyway :-)
> 
> Heiko
> 
> 
>>
>> Thanks,
>> drew
>>
>> On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote:
>>> This can also do without the ifdef and use IS_ENABLED instead and
>>> for better readability, getting rid of that switch also seems
>>> waranted.
>>>
>>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>>> ---
>>>  arch/riscv/kernel/cpufeature.c | 13 +++++--------
>>>  1 file changed, 5 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>>> index 553d755483ed..764ea220161f 100644
>>> --- a/arch/riscv/kernel/cpufeature.c
>>> +++ b/arch/riscv/kernel/cpufeature.c
>>> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
>>>  #ifdef CONFIG_RISCV_ALTERNATIVE
>>>  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
>>>  {
>>> -#ifdef CONFIG_RISCV_ISA_SVPBMT
>>> -   switch (stage) {
>>> -   case RISCV_ALTERNATIVES_EARLY_BOOT:
>>> +   if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
>>>             return false;
>>> -   default:
>>> -           return riscv_isa_extension_available(NULL, SVPBMT);
>>> -   }
>>> -#endif
>>>
>>> -   return false;
>>> +   if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
>>> +           return false;
>>> +
>>> +   return riscv_isa_extension_available(NULL, SVPBMT);
>>>  }
>>>
>>>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
>>
> 
> 
> 
> 

Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Heiko Stübner]

Am Freitag, 2. September 2022, 17:26:21 CEST schrieb Conor.Dooley@microchip.com:
> On 02/09/2022 16:12, Heiko Stübner wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > Am Freitag, 2. September 2022, 11:49:39 CEST schrieb Andrew Jones:
> >> Hi Heiko,
> >>
> >> Please use a cover-letter for a patch series. They allow the series to be
> >> threaded better and people can reply to the cover-letter with series-wide
> >> comments. For example, I'd like to reply to a cover-letter now with
> >>
> >> For the series
> >>
> >> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> >>
> >> but now it looks like I need to go back and reply to each patch
> >> separately.
> > 
> > I'm not sure if tooling like b4 can handle Reviewed-by's in cover-letters.
> 
> Yup, it can! At least `b4 {am,shazam} -t` will.
> I am not sure if the new `b4 trailers` does.

That is great to know ... gotta love b4 :-)


> 
> > At least some time back it couldn't, so am not sure if that was added
> > meanwhile. So tags added to cover-letters might even get lost.
> > 
> > But I'll add a cover-letter nevertheless - need a place for the v2 changelog
> > anyway :-)
> > 
> > Heiko
> > 
> > 
> >>
> >> Thanks,
> >> drew
> >>
> >> On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote:
> >>> This can also do without the ifdef and use IS_ENABLED instead and
> >>> for better readability, getting rid of that switch also seems
> >>> waranted.
> >>>
> >>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> >>> ---
> >>>  arch/riscv/kernel/cpufeature.c | 13 +++++--------
> >>>  1 file changed, 5 insertions(+), 8 deletions(-)
> >>>
> >>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> >>> index 553d755483ed..764ea220161f 100644
> >>> --- a/arch/riscv/kernel/cpufeature.c
> >>> +++ b/arch/riscv/kernel/cpufeature.c
> >>> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
> >>>  #ifdef CONFIG_RISCV_ALTERNATIVE
> >>>  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
> >>>  {
> >>> -#ifdef CONFIG_RISCV_ISA_SVPBMT
> >>> -   switch (stage) {
> >>> -   case RISCV_ALTERNATIVES_EARLY_BOOT:
> >>> +   if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
> >>>             return false;
> >>> -   default:
> >>> -           return riscv_isa_extension_available(NULL, SVPBMT);
> >>> -   }
> >>> -#endif
> >>>
> >>> -   return false;
> >>> +   if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> >>> +           return false;
> >>> +
> >>> +   return riscv_isa_extension_available(NULL, SVPBMT);
> >>>  }
> >>>
> >>>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> >>
> > 
> > 
> > 
> > 
> 
> 





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Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Heiko Stübner]

Am Freitag, 2. September 2022, 17:26:21 CEST schrieb Conor.Dooley@microchip.com:
> On 02/09/2022 16:12, Heiko Stübner wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > Am Freitag, 2. September 2022, 11:49:39 CEST schrieb Andrew Jones:
> >> Hi Heiko,
> >>
> >> Please use a cover-letter for a patch series. They allow the series to be
> >> threaded better and people can reply to the cover-letter with series-wide
> >> comments. For example, I'd like to reply to a cover-letter now with
> >>
> >> For the series
> >>
> >> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> >>
> >> but now it looks like I need to go back and reply to each patch
> >> separately.
> > 
> > I'm not sure if tooling like b4 can handle Reviewed-by's in cover-letters.
> 
> Yup, it can! At least `b4 {am,shazam} -t` will.
> I am not sure if the new `b4 trailers` does.

That is great to know ... gotta love b4 :-)


> 
> > At least some time back it couldn't, so am not sure if that was added
> > meanwhile. So tags added to cover-letters might even get lost.
> > 
> > But I'll add a cover-letter nevertheless - need a place for the v2 changelog
> > anyway :-)
> > 
> > Heiko
> > 
> > 
> >>
> >> Thanks,
> >> drew
> >>
> >> On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote:
> >>> This can also do without the ifdef and use IS_ENABLED instead and
> >>> for better readability, getting rid of that switch also seems
> >>> waranted.
> >>>
> >>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> >>> ---
> >>>  arch/riscv/kernel/cpufeature.c | 13 +++++--------
> >>>  1 file changed, 5 insertions(+), 8 deletions(-)
> >>>
> >>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> >>> index 553d755483ed..764ea220161f 100644
> >>> --- a/arch/riscv/kernel/cpufeature.c
> >>> +++ b/arch/riscv/kernel/cpufeature.c
> >>> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
> >>>  #ifdef CONFIG_RISCV_ALTERNATIVE
> >>>  static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
> >>>  {
> >>> -#ifdef CONFIG_RISCV_ISA_SVPBMT
> >>> -   switch (stage) {
> >>> -   case RISCV_ALTERNATIVES_EARLY_BOOT:
> >>> +   if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
> >>>             return false;
> >>> -   default:
> >>> -           return riscv_isa_extension_available(NULL, SVPBMT);
> >>> -   }
> >>> -#endif
> >>>
> >>> -   return false;
> >>> +   if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> >>> +           return false;
> >>> +
> >>> +   return riscv_isa_extension_available(NULL, SVPBMT);
> >>>  }
> >>>
> >>>  static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> >>
> > 
> > 
> > 
> > 
> 
> 

Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Konstantin Ryabitsev]

On Fri, Sep 02, 2022 at 03:26:21PM +0000, Conor.Dooley@microchip.com wrote:
> >> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> >>
> >> but now it looks like I need to go back and reply to each patch
> >> separately.
> > 
> > I'm not sure if tooling like b4 can handle Reviewed-by's in cover-letters.
> 
> Yup, it can! At least `b4 {am,shazam} -t` will.
> I am not sure if the new `b4 trailers` does.

Yes, it's the default behaviour for "b4 trailers". It'll probably become the
default for "b4 am/shazam" at some point, too.

-K

Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing

[Konstantin Ryabitsev]

On Fri, Sep 02, 2022 at 03:26:21PM +0000, Conor.Dooley@microchip.com wrote:
> >> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> >>
> >> but now it looks like I need to go back and reply to each patch
> >> separately.
> > 
> > I'm not sure if tooling like b4 can handle Reviewed-by's in cover-letters.
> 
> Yup, it can! At least `b4 {am,shazam} -t` will.
> I am not sure if the new `b4 trailers` does.

Yes, it's the default behaviour for "b4 trailers". It'll probably become the
default for "b4 am/shazam" at some point, too.

-K

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