* [Intel-gfx] [PATCH 1/2] i915/pmu: Wire GuC backend to per-client busyness
@ 2022-09-01 23:54 Ashutosh Dixit
2022-09-01 23:54 ` [Intel-gfx] [RFC PATCH v2 2/2] Fix per client busyness locking Ashutosh Dixit
2022-09-02 0:12 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] i915/pmu: Wire GuC backend to per-client busyness Patchwork
0 siblings, 2 replies; 4+ messages in thread
From: Ashutosh Dixit @ 2022-09-01 23:54 UTC (permalink / raw)
To: intel-gfx
From: John Harrison <John.C.Harrison@Intel.com>
GuC provides engine_id and last_switch_in ticks for an active context in
the pphwsp. The context image provides a 32 bit total ticks which is the
accumulated by the context (a.k.a. context[CTX_TIMESTAMP]). This
information is used to calculate the context busyness as follows:
If the engine_id is valid, then busyness is the sum of accumulated total
ticks and active ticks. Active ticks is calculated with current gt time
as reference.
If engine_id is invalid, busyness is equal to accumulated total ticks.
Since KMD (CPU) retrieves busyness data from 2 sources - GPU and GuC, a
potential race was highlighted in an earlier review that can lead to
double accounting of busyness. While the solution to this is a wip,
busyness is still usable for platforms running GuC submission.
Remaining work: Enable and test context busyness for
virtual_parent_context_ops and virtual_child_context_ops.
v2: (Tvrtko)
- Use COPS_RUNTIME_ACTIVE_TOTAL
- Add code comment for the race
- Undo local variables initializations
v3:
- Add support for virtual engines based on
https://patchwork.freedesktop.org/series/105227/
v4:
- Update commit message with remaining work.
- Rebase
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_context.c | 12 +++-
drivers/gpu/drm/i915/gt/intel_context.h | 6 +-
drivers/gpu/drm/i915/gt/intel_context_types.h | 6 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 5 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 65 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_drm_client.c | 6 +-
6 files changed, 89 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index 654a092ed3d6..e2d70a9fdac0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -576,16 +576,24 @@ void intel_context_bind_parent_child(struct intel_context *parent,
child->parallel.parent = parent;
}
-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
+u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
{
u64 total, active;
+ if (ce->ops->update_stats)
+ ce->ops->update_stats(ce);
+
total = ce->stats.runtime.total;
if (ce->ops->flags & COPS_RUNTIME_CYCLES)
total *= ce->engine->gt->clock_period_ns;
active = READ_ONCE(ce->stats.active);
- if (active)
+ /*
+ * When COPS_RUNTIME_ACTIVE_TOTAL is set for ce->cops, the backend
+ * already provides the total active time of the context, so skip this
+ * calculation when this flag is set.
+ */
+ if (active && !(ce->ops->flags & COPS_RUNTIME_ACTIVE_TOTAL))
active = intel_context_clock() - active;
return total + active;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h
index 8e2d70630c49..3d1d7436c1a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -58,7 +58,7 @@ static inline bool intel_context_is_parent(struct intel_context *ce)
return !!ce->parallel.number_children;
}
-static inline bool intel_context_is_pinned(struct intel_context *ce);
+static inline bool intel_context_is_pinned(const struct intel_context *ce);
static inline struct intel_context *
intel_context_to_parent(struct intel_context *ce)
@@ -118,7 +118,7 @@ static inline int intel_context_lock_pinned(struct intel_context *ce)
* Returns: true if the context is currently pinned for use by the GPU.
*/
static inline bool
-intel_context_is_pinned(struct intel_context *ce)
+intel_context_is_pinned(const struct intel_context *ce)
{
return atomic_read(&ce->pin_count);
}
@@ -362,7 +362,7 @@ intel_context_clear_nopreempt(struct intel_context *ce)
clear_bit(CONTEXT_NOPREEMPT, &ce->flags);
}
-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce);
+u64 intel_context_get_total_runtime_ns(struct intel_context *ce);
u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);
static inline u64 intel_context_clock(void)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 04eacae1aca5..f7ff4c7d81c7 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -38,6 +38,9 @@ struct intel_context_ops {
#define COPS_RUNTIME_CYCLES_BIT 1
#define COPS_RUNTIME_CYCLES BIT(COPS_RUNTIME_CYCLES_BIT)
+#define COPS_RUNTIME_ACTIVE_TOTAL_BIT 2
+#define COPS_RUNTIME_ACTIVE_TOTAL BIT(COPS_RUNTIME_ACTIVE_TOTAL_BIT)
+
int (*alloc)(struct intel_context *ce);
void (*revoke)(struct intel_context *ce, struct i915_request *rq,
@@ -56,6 +59,8 @@ struct intel_context_ops {
void (*sched_disable)(struct intel_context *ce);
+ void (*update_stats)(struct intel_context *ce);
+
void (*reset)(struct intel_context *ce);
void (*destroy)(struct kref *kref);
@@ -148,6 +153,7 @@ struct intel_context {
struct ewma_runtime avg;
u64 total;
u32 last;
+ u64 start_gt_clk;
I915_SELFTEST_DECLARE(u32 num_underflow);
I915_SELFTEST_DECLARE(u32 max_underflow);
} runtime;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 323b055e5db9..c7b54f1631b9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -196,6 +196,11 @@ static inline u8 guc_class_to_engine_class(u8 guc_class)
return guc_class_engine_class_map[guc_class];
}
+/* Per context engine usage stats: */
+#define PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO (0x500 / sizeof(u32))
+#define PPHWSP_GUC_CONTEXT_USAGE_STAMP_HI (PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO + 1)
+#define PPHWSP_GUC_CONTEXT_USAGE_ENGINE_ID (PPHWSP_GUC_CONTEXT_USAGE_STAMP_HI + 1)
+
/* Work item for submitting workloads into work queue of GuC. */
struct guc_wq_item {
u32 header;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0d56b615bf78..bee8cf10f749 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -378,7 +378,7 @@ static inline void set_context_guc_id_invalid(struct intel_context *ce)
ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
}
-static inline struct intel_guc *ce_to_guc(struct intel_context *ce)
+static inline struct intel_guc *ce_to_guc(const struct intel_context *ce)
{
return &ce->engine->gt->uc.guc;
}
@@ -1376,13 +1376,16 @@ static void __update_guc_busyness_stats(struct intel_guc *guc)
spin_unlock_irqrestore(&guc->timestamp.lock, flags);
}
+static void __guc_context_update_clks(struct intel_context *ce);
static void guc_timestamp_ping(struct work_struct *wrk)
{
struct intel_guc *guc = container_of(wrk, typeof(*guc),
timestamp.work.work);
struct intel_uc *uc = container_of(guc, typeof(*uc), guc);
struct intel_gt *gt = guc_to_gt(guc);
+ struct intel_context *ce;
intel_wakeref_t wakeref;
+ unsigned long index;
int srcu, ret;
/*
@@ -1396,6 +1399,10 @@ static void guc_timestamp_ping(struct work_struct *wrk)
with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
__update_guc_busyness_stats(guc);
+ /* adjust context stats for overflow */
+ xa_for_each(&guc->context_lookup, index, ce)
+ __guc_context_update_clks(ce);
+
intel_gt_reset_unlock(gt, srcu);
mod_delayed_work(system_highpri_wq, &guc->timestamp.work,
@@ -1469,6 +1476,56 @@ void intel_guc_busyness_unpark(struct intel_gt *gt)
guc->timestamp.ping_delay);
}
+static void __guc_context_update_clks(struct intel_context *ce)
+{
+ struct intel_guc *guc = ce_to_guc(ce);
+ struct intel_gt *gt = ce->engine->gt;
+ u32 *pphwsp, last_switch, engine_id;
+ u64 start_gt_clk, active;
+ unsigned long flags;
+ ktime_t unused;
+
+ spin_lock_irqsave(&guc->timestamp.lock, flags);
+
+ /*
+ * GPU updates ce->lrc_reg_state[CTX_TIMESTAMP] when context is switched
+ * out, however GuC updates PPHWSP offsets below. Hence KMD (CPU)
+ * relies on GuC and GPU for busyness calculations. Due to this, A
+ * potential race was highlighted in an earlier review that can lead to
+ * double accounting of busyness. While the solution to this is a wip,
+ * busyness is still usable for platforms running GuC submission.
+ */
+ pphwsp = ((void *)ce->lrc_reg_state) - LRC_STATE_OFFSET;
+ last_switch = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO]);
+ engine_id = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_ENGINE_ID]);
+
+ guc_update_pm_timestamp(guc, &unused);
+
+ if (engine_id != 0xffffffff && last_switch) {
+ start_gt_clk = READ_ONCE(ce->stats.runtime.start_gt_clk);
+ __extend_last_switch(guc, &start_gt_clk, last_switch);
+ active = intel_gt_clock_interval_to_ns(gt, guc->timestamp.gt_stamp - start_gt_clk);
+ WRITE_ONCE(ce->stats.runtime.start_gt_clk, start_gt_clk);
+ WRITE_ONCE(ce->stats.active, active);
+ } else {
+ lrc_update_runtime(ce);
+ }
+
+ spin_unlock_irqrestore(&guc->timestamp.lock, flags);
+}
+
+static void guc_context_update_stats(struct intel_context *ce)
+{
+ if (!intel_context_pin_if_active(ce)) {
+ WRITE_ONCE(ce->stats.runtime.start_gt_clk, 0);
+ WRITE_ONCE(ce->stats.active, 0);
+ return;
+ }
+
+ __guc_context_update_clks(ce);
+ intel_context_unpin(ce);
+}
+
static inline bool
submission_disabled(struct intel_guc *guc)
{
@@ -2723,6 +2780,7 @@ static void guc_context_unpin(struct intel_context *ce)
{
struct intel_guc *guc = ce_to_guc(ce);
+ lrc_update_runtime(ce);
unpin_guc_id(guc, ce);
lrc_unpin(ce);
@@ -3344,6 +3402,7 @@ static void remove_from_context(struct i915_request *rq)
}
static const struct intel_context_ops guc_context_ops = {
+ .flags = COPS_RUNTIME_CYCLES | COPS_RUNTIME_ACTIVE_TOTAL,
.alloc = guc_context_alloc,
.pre_pin = guc_context_pre_pin,
@@ -3360,6 +3419,8 @@ static const struct intel_context_ops guc_context_ops = {
.sched_disable = guc_context_sched_disable,
+ .update_stats = guc_context_update_stats,
+
.reset = lrc_reset,
.destroy = guc_context_destroy,
@@ -3593,6 +3654,7 @@ static int guc_virtual_context_alloc(struct intel_context *ce)
}
static const struct intel_context_ops virtual_guc_context_ops = {
+ .flags = COPS_RUNTIME_CYCLES | COPS_RUNTIME_ACTIVE_TOTAL,
.alloc = guc_virtual_context_alloc,
.pre_pin = guc_virtual_context_pre_pin,
@@ -3608,6 +3670,7 @@ static const struct intel_context_ops virtual_guc_context_ops = {
.exit = guc_virtual_context_exit,
.sched_disable = guc_context_sched_disable,
+ .update_stats = guc_context_update_stats,
.destroy = guc_context_destroy,
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
index b09d1d386574..8d81119fff14 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -147,11 +147,7 @@ void i915_drm_client_fdinfo(struct seq_file *m, struct file *f)
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
seq_printf(m, "drm-client-id:\t%u\n", client->id);
- /*
- * Temporarily skip showing client engine information with GuC submission till
- * fetching engine busyness is implemented in the GuC submission backend
- */
- if (GRAPHICS_VER(i915) < 8 || intel_uc_uses_guc_submission(&i915->gt0.uc))
+ if (GRAPHICS_VER(i915) < 8)
return;
for (i = 0; i < ARRAY_SIZE(uabi_class_names); i++)
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] [RFC PATCH v2 2/2] Fix per client busyness locking
2022-09-01 23:54 [Intel-gfx] [PATCH 1/2] i915/pmu: Wire GuC backend to per-client busyness Ashutosh Dixit
@ 2022-09-01 23:54 ` Ashutosh Dixit
2022-09-02 2:39 ` kernel test robot
2022-09-02 0:12 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] i915/pmu: Wire GuC backend to per-client busyness Patchwork
1 sibling, 1 reply; 4+ messages in thread
From: Ashutosh Dixit @ 2022-09-01 23:54 UTC (permalink / raw)
To: intel-gfx
1. Do all ce->stats updates and reads under guc->timestamp.lock
2. Pin context image before reading
3. Merge __guc_context_update_clks and guc_context_update_stats into a
single function
4. Call lrc_update_runtime() unconditionally in guc_context_update_stats
5. Seems no need to update ce->stats.active with this approach
Some of the above steps may not be correct or complete but the idea is to
discuss/improve the original patch.
v2 (Address review comments from Umesh):
* Don't pin context when called from intel_context_get_total_runtime_ns
* Don't pin context in lrc_update_runtime_locked
* ce->stats.active is now used to cache previous active value
* Move lrc_update_runtime to else in __guc_context_update_stats
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/gt/intel_context.c | 9 +--
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 57 ++++++++++++-------
3 files changed, 40 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index e2d70a9fdac0..51dce98003ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -581,19 +581,14 @@ u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
u64 total, active;
if (ce->ops->update_stats)
- ce->ops->update_stats(ce);
+ return ce->ops->update_stats(ce, false);
total = ce->stats.runtime.total;
if (ce->ops->flags & COPS_RUNTIME_CYCLES)
total *= ce->engine->gt->clock_period_ns;
active = READ_ONCE(ce->stats.active);
- /*
- * When COPS_RUNTIME_ACTIVE_TOTAL is set for ce->cops, the backend
- * already provides the total active time of the context, so skip this
- * calculation when this flag is set.
- */
- if (active && !(ce->ops->flags & COPS_RUNTIME_ACTIVE_TOTAL))
+ if (active)
active = intel_context_clock() - active;
return total + active;
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index f7ff4c7d81c7..06dad9eeecdb 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -59,7 +59,7 @@ struct intel_context_ops {
void (*sched_disable)(struct intel_context *ce);
- void (*update_stats)(struct intel_context *ce);
+ u64 (*update_stats)(struct intel_context *ce, bool pin);
void (*reset)(struct intel_context *ce);
void (*destroy)(struct kref *kref);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index bee8cf10f749..b3c6f57f45cb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1376,7 +1376,6 @@ static void __update_guc_busyness_stats(struct intel_guc *guc)
spin_unlock_irqrestore(&guc->timestamp.lock, flags);
}
-static void __guc_context_update_clks(struct intel_context *ce);
static void guc_timestamp_ping(struct work_struct *wrk)
{
struct intel_guc *guc = container_of(wrk, typeof(*guc),
@@ -1401,7 +1400,8 @@ static void guc_timestamp_ping(struct work_struct *wrk)
/* adjust context stats for overflow */
xa_for_each(&guc->context_lookup, index, ce)
- __guc_context_update_clks(ce);
+ if (ce->ops->update_stats)
+ ce->ops->update_stats(ce, true);
intel_gt_reset_unlock(gt, srcu);
@@ -1476,17 +1476,13 @@ void intel_guc_busyness_unpark(struct intel_gt *gt)
guc->timestamp.ping_delay);
}
-static void __guc_context_update_clks(struct intel_context *ce)
+static u64 __guc_context_update_stats(struct intel_context *ce)
{
struct intel_guc *guc = ce_to_guc(ce);
struct intel_gt *gt = ce->engine->gt;
u32 *pphwsp, last_switch, engine_id;
- u64 start_gt_clk, active;
- unsigned long flags;
ktime_t unused;
- spin_lock_irqsave(&guc->timestamp.lock, flags);
-
/*
* GPU updates ce->lrc_reg_state[CTX_TIMESTAMP] when context is switched
* out, however GuC updates PPHWSP offsets below. Hence KMD (CPU)
@@ -1502,28 +1498,49 @@ static void __guc_context_update_clks(struct intel_context *ce)
guc_update_pm_timestamp(guc, &unused);
if (engine_id != 0xffffffff && last_switch) {
- start_gt_clk = READ_ONCE(ce->stats.runtime.start_gt_clk);
- __extend_last_switch(guc, &start_gt_clk, last_switch);
- active = intel_gt_clock_interval_to_ns(gt, guc->timestamp.gt_stamp - start_gt_clk);
- WRITE_ONCE(ce->stats.runtime.start_gt_clk, start_gt_clk);
- WRITE_ONCE(ce->stats.active, active);
+ __extend_last_switch(guc, &ce->stats.runtime.start_gt_clk, last_switch);
+ ce->stats.active = intel_gt_clock_interval_to_ns(gt,
+ guc->timestamp.gt_stamp - ce->stats.runtime.start_gt_clk);
} else {
lrc_update_runtime(ce);
+ ce->stats.active = 0;
}
- spin_unlock_irqrestore(&guc->timestamp.lock, flags);
+ return ce->stats.runtime.total + ce->stats.active;
}
-static void guc_context_update_stats(struct intel_context *ce)
+u64 guc_context_update_stats(struct intel_context *ce, bool pin)
{
- if (!intel_context_pin_if_active(ce)) {
- WRITE_ONCE(ce->stats.runtime.start_gt_clk, 0);
- WRITE_ONCE(ce->stats.active, 0);
- return;
+ struct intel_guc *guc = ce_to_guc(ce);
+ unsigned long flags;
+ u64 ret;
+
+ if (pin) {
+ intel_context_pin(ce);
+ } else {
+ /* Return previously computed value */
+ spin_lock_irqsave(&guc->timestamp.lock, flags);
+ ret = ce->stats.runtime.total + ce->stats.active;
+ spin_unlock_irqrestore(&guc->timestamp.lock, flags);
+ return ret;
}
- __guc_context_update_clks(ce);
+ spin_lock_irqsave(&guc->timestamp.lock, flags);
+ ret = __guc_context_update_stats(ce);
+ spin_unlock_irqrestore(&guc->timestamp.lock, flags);
+
intel_context_unpin(ce);
+ return ret;
+}
+
+static void lrc_update_runtime_locked(struct intel_context *ce)
+{
+ struct intel_guc *guc = ce_to_guc(ce);
+ unsigned long flags;
+
+ spin_lock_irqsave(&guc->timestamp.lock, flags);
+ lrc_update_runtime(ce);
+ spin_unlock_irqrestore(&guc->timestamp.lock, flags);
}
static inline bool
@@ -2780,7 +2797,7 @@ static void guc_context_unpin(struct intel_context *ce)
{
struct intel_guc *guc = ce_to_guc(ce);
- lrc_update_runtime(ce);
+ lrc_update_runtime_locked(ce);
unpin_guc_id(guc, ce);
lrc_unpin(ce);
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] i915/pmu: Wire GuC backend to per-client busyness
2022-09-01 23:54 [Intel-gfx] [PATCH 1/2] i915/pmu: Wire GuC backend to per-client busyness Ashutosh Dixit
2022-09-01 23:54 ` [Intel-gfx] [RFC PATCH v2 2/2] Fix per client busyness locking Ashutosh Dixit
@ 2022-09-02 0:12 ` Patchwork
1 sibling, 0 replies; 4+ messages in thread
From: Patchwork @ 2022-09-02 0:12 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] i915/pmu: Wire GuC backend to per-client busyness
URL : https://patchwork.freedesktop.org/series/108053/
State : failure
== Summary ==
Error: make failed
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1512:5: error: no previous prototype for ‘guc_context_update_stats’ [-Werror=missing-prototypes]
u64 guc_context_update_stats(struct intel_context *ce, bool pin)
^~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
scripts/Makefile.build:249: recipe for target 'drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o] Error 1
scripts/Makefile.build:465: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:465: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:465: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1853: recipe for target 'drivers' failed
make: *** [drivers] Error 2
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [RFC PATCH v2 2/2] Fix per client busyness locking
2022-09-01 23:54 ` [Intel-gfx] [RFC PATCH v2 2/2] Fix per client busyness locking Ashutosh Dixit
@ 2022-09-02 2:39 ` kernel test robot
0 siblings, 0 replies; 4+ messages in thread
From: kernel test robot @ 2022-09-02 2:39 UTC (permalink / raw)
To: Ashutosh Dixit; +Cc: llvm, kbuild-all
Hi Ashutosh,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Ashutosh-Dixit/i915-pmu-Wire-GuC-backend-to-per-client-busyness/20220902-075534
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-a004 (https://download.01.org/0day-ci/archive/20220902/202209021008.CdocRSC0-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/b1db15edb2416229fdde749425de6a6ae7a4b94a
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Ashutosh-Dixit/i915-pmu-Wire-GuC-backend-to-per-client-busyness/20220902-075534
git checkout b1db15edb2416229fdde749425de6a6ae7a4b94a
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1512:5: warning: no previous prototype for function 'guc_context_update_stats' [-Wmissing-prototypes]
u64 guc_context_update_stats(struct intel_context *ce, bool pin)
^
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1512:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
u64 guc_context_update_stats(struct intel_context *ce, bool pin)
^
static
1 warning generated.
vim +/guc_context_update_stats +1512 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
1511
> 1512 u64 guc_context_update_stats(struct intel_context *ce, bool pin)
1513 {
1514 struct intel_guc *guc = ce_to_guc(ce);
1515 unsigned long flags;
1516 u64 ret;
1517
1518 if (pin) {
1519 intel_context_pin(ce);
1520 } else {
1521 /* Return previously computed value */
1522 spin_lock_irqsave(&guc->timestamp.lock, flags);
1523 ret = ce->stats.runtime.total + ce->stats.active;
1524 spin_unlock_irqrestore(&guc->timestamp.lock, flags);
1525 return ret;
1526 }
1527
1528 spin_lock_irqsave(&guc->timestamp.lock, flags);
1529 ret = __guc_context_update_stats(ce);
1530 spin_unlock_irqrestore(&guc->timestamp.lock, flags);
1531
1532 intel_context_unpin(ce);
1533 return ret;
1534 }
1535
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-09-02 2:40 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-01 23:54 [Intel-gfx] [PATCH 1/2] i915/pmu: Wire GuC backend to per-client busyness Ashutosh Dixit
2022-09-01 23:54 ` [Intel-gfx] [RFC PATCH v2 2/2] Fix per client busyness locking Ashutosh Dixit
2022-09-02 2:39 ` kernel test robot
2022-09-02 0:12 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] i915/pmu: Wire GuC backend to per-client busyness Patchwork
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