From: "Pali Rohár" <pali@kernel.org> To: "Bjorn Helgaas" <bhelgaas@google.com>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Andrew Lunn" <andrew@lunn.ch>, "Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>, "Gregory Clement" <gregory.clement@bootlin.com>, "Russell King" <linux@armlinux.org.uk>, "Krzysztof Wilczyński" <kw@linux.com>, "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>, "Mauri Sandberg" <maukka@ext.kapsi.fi> Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/7] bus: mvebu-mbus: add configuration space aperture Date: Mon, 5 Sep 2022 21:23:05 +0200 [thread overview] Message-ID: <20220905192310.22786-3-pali@kernel.org> (raw) In-Reply-To: <20220905192310.22786-1-pali@kernel.org> From: Mauri Sandberg <maukka@ext.kapsi.fi> Adds a new resource for describing PCI configuration space and accessor for it. Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> Signed-off-by: Pali Rohár <pali@kernel.org> --- drivers/bus/mvebu-mbus.c | 26 +++++++++++++++++++++++--- include/linux/mbus.h | 1 + 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c index 5dc2669432ba..9702c6ddbbe6 100644 --- a/drivers/bus/mvebu-mbus.c +++ b/drivers/bus/mvebu-mbus.c @@ -139,6 +139,7 @@ struct mvebu_mbus_state { struct dentry *debugfs_devs; struct resource pcie_mem_aperture; struct resource pcie_io_aperture; + struct resource pcie_cfg_aperture; const struct mvebu_mbus_soc_data *soc; int hw_io_coherency; @@ -950,6 +951,14 @@ void mvebu_mbus_get_pcie_io_aperture(struct resource *res) } EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_io_aperture); +void mvebu_mbus_get_pcie_cfg_aperture(struct resource *res) +{ + if (!res) + return; + *res = mbus_state.pcie_cfg_aperture; +} +EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_cfg_aperture); + int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr) { const struct mbus_dram_target_info *dram; @@ -1277,7 +1286,8 @@ static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus, static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, struct resource *mem, - struct resource *io) + struct resource *io, + struct resource *cfg) { u32 reg[2]; int ret; @@ -1290,6 +1300,8 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, mem->end = -1; memset(io, 0, sizeof(struct resource)); io->end = -1; + memset(cfg, 0, sizeof(struct resource)); + cfg->end = -1; ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg)); if (!ret) { @@ -1304,6 +1316,13 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, io->end = io->start + reg[1] - 1; io->flags = IORESOURCE_IO; } + + ret = of_property_read_u32_array(np, "pcie-cfg-aperture", reg, ARRAY_SIZE(reg)); + if (!ret) { + cfg->start = reg[0]; + cfg->end = cfg->start + reg[1] - 1; + cfg->flags = IORESOURCE_MEM; + } } int __init mvebu_mbus_dt_init(bool is_coherent) @@ -1359,9 +1378,10 @@ int __init mvebu_mbus_dt_init(bool is_coherent) mbus_state.hw_io_coherency = is_coherent; - /* Get optional pcie-{mem,io}-aperture properties */ + /* Get optional pcie-{mem,io,cfg}-aperture properties */ mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture, - &mbus_state.pcie_io_aperture); + &mbus_state.pcie_io_aperture, + &mbus_state.pcie_cfg_aperture); ret = mvebu_mbus_common_init(&mbus_state, mbuswins_res.start, diff --git a/include/linux/mbus.h b/include/linux/mbus.h index 4773145246ed..525b56ddd0c2 100644 --- a/include/linux/mbus.h +++ b/include/linux/mbus.h @@ -86,6 +86,7 @@ static inline int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr); void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); void mvebu_mbus_get_pcie_io_aperture(struct resource *res); +void mvebu_mbus_get_pcie_cfg_aperture(struct resource *res); int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr); int mvebu_mbus_add_window_remap_by_id(unsigned int target, unsigned int attribute, -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: "Pali Rohár" <pali@kernel.org> To: "Bjorn Helgaas" <bhelgaas@google.com>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Andrew Lunn" <andrew@lunn.ch>, "Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>, "Gregory Clement" <gregory.clement@bootlin.com>, "Russell King" <linux@armlinux.org.uk>, "Krzysztof Wilczyński" <kw@linux.com>, "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>, "Mauri Sandberg" <maukka@ext.kapsi.fi> Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/7] bus: mvebu-mbus: add configuration space aperture Date: Mon, 5 Sep 2022 21:23:05 +0200 [thread overview] Message-ID: <20220905192310.22786-3-pali@kernel.org> (raw) In-Reply-To: <20220905192310.22786-1-pali@kernel.org> From: Mauri Sandberg <maukka@ext.kapsi.fi> Adds a new resource for describing PCI configuration space and accessor for it. Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> Signed-off-by: Pali Rohár <pali@kernel.org> --- drivers/bus/mvebu-mbus.c | 26 +++++++++++++++++++++++--- include/linux/mbus.h | 1 + 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c index 5dc2669432ba..9702c6ddbbe6 100644 --- a/drivers/bus/mvebu-mbus.c +++ b/drivers/bus/mvebu-mbus.c @@ -139,6 +139,7 @@ struct mvebu_mbus_state { struct dentry *debugfs_devs; struct resource pcie_mem_aperture; struct resource pcie_io_aperture; + struct resource pcie_cfg_aperture; const struct mvebu_mbus_soc_data *soc; int hw_io_coherency; @@ -950,6 +951,14 @@ void mvebu_mbus_get_pcie_io_aperture(struct resource *res) } EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_io_aperture); +void mvebu_mbus_get_pcie_cfg_aperture(struct resource *res) +{ + if (!res) + return; + *res = mbus_state.pcie_cfg_aperture; +} +EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_cfg_aperture); + int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr) { const struct mbus_dram_target_info *dram; @@ -1277,7 +1286,8 @@ static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus, static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, struct resource *mem, - struct resource *io) + struct resource *io, + struct resource *cfg) { u32 reg[2]; int ret; @@ -1290,6 +1300,8 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, mem->end = -1; memset(io, 0, sizeof(struct resource)); io->end = -1; + memset(cfg, 0, sizeof(struct resource)); + cfg->end = -1; ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg)); if (!ret) { @@ -1304,6 +1316,13 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, io->end = io->start + reg[1] - 1; io->flags = IORESOURCE_IO; } + + ret = of_property_read_u32_array(np, "pcie-cfg-aperture", reg, ARRAY_SIZE(reg)); + if (!ret) { + cfg->start = reg[0]; + cfg->end = cfg->start + reg[1] - 1; + cfg->flags = IORESOURCE_MEM; + } } int __init mvebu_mbus_dt_init(bool is_coherent) @@ -1359,9 +1378,10 @@ int __init mvebu_mbus_dt_init(bool is_coherent) mbus_state.hw_io_coherency = is_coherent; - /* Get optional pcie-{mem,io}-aperture properties */ + /* Get optional pcie-{mem,io,cfg}-aperture properties */ mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture, - &mbus_state.pcie_io_aperture); + &mbus_state.pcie_io_aperture, + &mbus_state.pcie_cfg_aperture); ret = mvebu_mbus_common_init(&mbus_state, mbuswins_res.start, diff --git a/include/linux/mbus.h b/include/linux/mbus.h index 4773145246ed..525b56ddd0c2 100644 --- a/include/linux/mbus.h +++ b/include/linux/mbus.h @@ -86,6 +86,7 @@ static inline int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr); void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); void mvebu_mbus_get_pcie_io_aperture(struct resource *res); +void mvebu_mbus_get_pcie_cfg_aperture(struct resource *res); int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr); int mvebu_mbus_add_window_remap_by_id(unsigned int target, unsigned int attribute, -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-09-05 19:25 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-07-18 20:28 [PATCH 0/2] PCI: mvebu: add support for orion soc Mauri Sandberg 2022-07-18 20:28 ` Mauri Sandberg 2022-07-18 20:28 ` [PATCH 1/2] dt-bindings: PCI: mvebu: Add orion5x compatible Mauri Sandberg 2022-07-18 20:28 ` Mauri Sandberg 2022-07-22 0:27 ` Rob Herring 2022-07-22 0:27 ` Rob Herring 2022-07-18 20:28 ` [PATCH 1/6] dt-bindings: PCI: mvebu: Add orion compatible Mauri Sandberg 2022-07-18 20:28 ` Mauri Sandberg 2022-07-18 20:33 ` Mauri Sandberg 2022-07-18 20:33 ` Mauri Sandberg 2022-07-18 20:28 ` [PATCH 2/2] PCI: mvebu: add support for orion5x Mauri Sandberg 2022-07-18 20:28 ` Mauri Sandberg 2022-07-19 8:05 ` Arnd Bergmann 2022-07-19 8:05 ` Arnd Bergmann 2022-07-19 9:46 ` Pali Rohár 2022-07-19 9:46 ` Pali Rohár 2022-07-19 10:16 ` Arnd Bergmann 2022-07-19 10:16 ` Arnd Bergmann 2022-07-20 16:13 ` Pali Rohár 2022-07-20 16:13 ` Pali Rohár 2022-07-20 16:43 ` Andrew Lunn 2022-07-20 16:43 ` Andrew Lunn 2022-07-20 17:11 ` Arnd Bergmann 2022-07-20 17:11 ` Arnd Bergmann 2022-07-20 17:40 ` Rob Herring 2022-07-20 17:40 ` Rob Herring 2022-07-20 17:53 ` Pali Rohár 2022-07-20 17:53 ` Pali Rohár 2022-07-20 11:36 ` [PATCH 0/2] PCI: mvebu: add support for orion soc Arnd Bergmann 2022-07-20 11:36 ` Arnd Bergmann 2022-07-29 17:22 ` Bjorn Helgaas 2022-07-29 17:22 ` Bjorn Helgaas 2022-07-30 13:21 ` Mauri Sandberg 2022-07-30 13:21 ` Mauri Sandberg 2022-08-02 17:34 ` [PATCH v2 " Mauri Sandberg 2022-08-02 17:34 ` Mauri Sandberg 2022-08-02 17:34 ` [PATCH v2 1/2] dt-bindings: PCI: mvebu: Add orion5x compatible Mauri Sandberg 2022-08-02 17:34 ` Mauri Sandberg 2022-08-02 17:34 ` [PATCH v2 2/2] PCI: mvebu: add support for orion5x Mauri Sandberg 2022-08-02 17:34 ` Mauri Sandberg 2022-08-25 15:15 ` Lorenzo Pieralisi 2022-08-25 15:15 ` Lorenzo Pieralisi 2022-08-25 16:00 ` Pali Rohár 2022-08-25 16:00 ` Pali Rohár 2022-08-26 8:42 ` Lorenzo Pieralisi 2022-08-26 8:42 ` Lorenzo Pieralisi 2022-08-02 17:49 ` [PATCH v2 0/2] PCI: mvebu: add support for orion soc Pali Rohár 2022-08-02 17:49 ` Pali Rohár 2022-09-05 19:23 ` [PATCH v3 0/7] " Pali Rohár 2022-09-05 19:23 ` Pali Rohár 2022-09-05 19:23 ` [PATCH v3 1/7] ARM: orion: Move PCIe mbus window mapping from orion5x_setup_wins() to pcie_setup() Pali Rohár 2022-09-05 19:23 ` Pali Rohár 2022-09-05 19:23 ` Pali Rohár [this message] 2022-09-05 19:23 ` [PATCH v3 2/7] bus: mvebu-mbus: add configuration space aperture Pali Rohár 2022-09-05 19:23 ` [PATCH v3 3/7] dt-bindings: PCI: mvebu: Add orion5x compatible Pali Rohár 2022-09-05 19:23 ` Pali Rohár 2022-09-06 16:20 ` Rob Herring 2022-09-06 16:20 ` Rob Herring 2022-09-05 19:23 ` [PATCH v3 4/7] PCI: mvebu: Remove unused busn member Pali Rohár 2022-09-05 19:23 ` Pali Rohár 2022-09-05 19:23 ` [PATCH v3 5/7] PCI: mvebu: Cleanup error handling in mvebu_pcie_probe() Pali Rohár 2022-09-05 19:23 ` Pali Rohár 2022-09-05 19:23 ` [PATCH v3 6/7] PCI: mvebu: Add support for Orion PCIe controller Pali Rohár 2022-09-05 19:23 ` Pali Rohár 2022-09-05 19:23 ` [PATCH v3 7/7] ARM: dts: orion5x: Add PCIe node Pali Rohár 2022-09-05 19:23 ` Pali Rohár 2022-09-16 12:25 ` [PATCH v3 0/7] PCI: mvebu: add support for orion soc Lorenzo Pieralisi 2022-09-16 12:25 ` Lorenzo Pieralisi 2022-10-27 14:10 ` Lorenzo Pieralisi 2022-10-27 14:10 ` Lorenzo Pieralisi 2022-11-06 23:28 ` Pali Rohár 2022-11-06 23:28 ` Pali Rohár 2022-11-11 12:49 ` Lorenzo Pieralisi 2022-11-11 12:49 ` Lorenzo Pieralisi 2022-11-11 16:54 ` Pali Rohár 2022-11-11 16:54 ` Pali Rohár
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220905192310.22786-3-pali@kernel.org \ --to=pali@kernel.org \ --cc=andrew@lunn.ch \ --cc=bhelgaas@google.com \ --cc=devicetree@vger.kernel.org \ --cc=gregory.clement@bootlin.com \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=kw@linux.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=linux@armlinux.org.uk \ --cc=lpieralisi@kernel.org \ --cc=maukka@ext.kapsi.fi \ --cc=robh+dt@kernel.org \ --cc=sebastian.hesselbarth@gmail.com \ --cc=thomas.petazzoni@bootlin.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.