* [PATCH] drm/i915: Invert if/else ladder for frequency read
@ 2022-09-07 20:30 ` Lucas De Marchi
0 siblings, 0 replies; 9+ messages in thread
From: Lucas De Marchi @ 2022-09-07 20:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.
With the new ranges it's easier to see what platform a branch started to
be taken. Besides the >= 11 change, the branch taken for GRAPHICS_VER == 10
is also different, but currently there is no such platform in i915.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/gt/intel_gt_clock_utils.c | 77 +++++++++----------
1 file changed, 37 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index d5d1b04dbcad..93608c9349fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -78,77 +78,74 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
u32 f19_2_mhz = 19200000;
u32 f24_mhz = 24000000;
- if (GRAPHICS_VER(uncore->i915) <= 4) {
- /*
- * PRMs say:
- *
- * "The value in this register increments once every 16
- * hclks." (through the “Clocking Configuration”
- * (“CLKCFG”) MCHBAR register)
- */
- return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
- } else if (GRAPHICS_VER(uncore->i915) <= 8) {
- /*
- * PRMs say:
- *
- * "The PCU TSC counts 10ns increments; this timestamp
- * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
- * rolling over every 1.5 hours).
- */
- return f12_5_mhz;
- } else if (GRAPHICS_VER(uncore->i915) <= 9) {
+ if (GRAPHICS_VER(uncore->i915) >= 11) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
+ /*
+ * First figure out the reference frequency. There are 2 ways
+ * we can compute the frequency, either through the
+ * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
+ * tells us which one we should use.
+ */
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(uncore);
} else {
- freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
+ u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
+
+ if (GRAPHICS_VER(uncore->i915) >= 11)
+ freq = gen11_get_crystal_clock_freq(uncore, c0);
+ else
+ freq = gen9_get_crystal_clock_freq(uncore, c0);
/*
* Now figure out how the command stream's timestamp
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
- CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
+ GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
}
return freq;
- } else if (GRAPHICS_VER(uncore->i915) <= 12) {
+ } else if (GRAPHICS_VER(uncore->i915) >= 9) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
- /*
- * First figure out the reference frequency. There are 2 ways
- * we can compute the frequency, either through the
- * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
- * tells us which one we should use.
- */
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(uncore);
} else {
- u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
-
- if (GRAPHICS_VER(uncore->i915) >= 11)
- freq = gen11_get_crystal_clock_freq(uncore, c0);
- else
- freq = gen9_get_crystal_clock_freq(uncore, c0);
+ freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
/*
* Now figure out how the command stream's timestamp
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
- GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
+ CTC_SHIFT_PARAMETER_SHIFT);
}
return freq;
+ } else if (GRAPHICS_VER(uncore->i915) >= 5) {
+ /*
+ * PRMs say:
+ *
+ * "The PCU TSC counts 10ns increments; this timestamp
+ * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
+ * rolling over every 1.5 hours).
+ */
+ return f12_5_mhz;
+ } else {
+ /*
+ * PRMs say:
+ *
+ * "The value in this register increments once every 16
+ * hclks." (through the “Clocking Configuration”
+ * (“CLKCFG”) MCHBAR register)
+ */
+ return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
}
-
- MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
- return 0;
}
void intel_gt_init_clock_frequency(struct intel_gt *gt)
--
2.37.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Invert if/else ladder for frequency read
@ 2022-09-07 20:30 ` Lucas De Marchi
0 siblings, 0 replies; 9+ messages in thread
From: Lucas De Marchi @ 2022-09-07 20:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.
With the new ranges it's easier to see what platform a branch started to
be taken. Besides the >= 11 change, the branch taken for GRAPHICS_VER == 10
is also different, but currently there is no such platform in i915.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/gt/intel_gt_clock_utils.c | 77 +++++++++----------
1 file changed, 37 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index d5d1b04dbcad..93608c9349fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -78,77 +78,74 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
u32 f19_2_mhz = 19200000;
u32 f24_mhz = 24000000;
- if (GRAPHICS_VER(uncore->i915) <= 4) {
- /*
- * PRMs say:
- *
- * "The value in this register increments once every 16
- * hclks." (through the “Clocking Configuration”
- * (“CLKCFG”) MCHBAR register)
- */
- return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
- } else if (GRAPHICS_VER(uncore->i915) <= 8) {
- /*
- * PRMs say:
- *
- * "The PCU TSC counts 10ns increments; this timestamp
- * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
- * rolling over every 1.5 hours).
- */
- return f12_5_mhz;
- } else if (GRAPHICS_VER(uncore->i915) <= 9) {
+ if (GRAPHICS_VER(uncore->i915) >= 11) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
+ /*
+ * First figure out the reference frequency. There are 2 ways
+ * we can compute the frequency, either through the
+ * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
+ * tells us which one we should use.
+ */
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(uncore);
} else {
- freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
+ u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
+
+ if (GRAPHICS_VER(uncore->i915) >= 11)
+ freq = gen11_get_crystal_clock_freq(uncore, c0);
+ else
+ freq = gen9_get_crystal_clock_freq(uncore, c0);
/*
* Now figure out how the command stream's timestamp
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
- CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
+ GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
}
return freq;
- } else if (GRAPHICS_VER(uncore->i915) <= 12) {
+ } else if (GRAPHICS_VER(uncore->i915) >= 9) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
- /*
- * First figure out the reference frequency. There are 2 ways
- * we can compute the frequency, either through the
- * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
- * tells us which one we should use.
- */
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(uncore);
} else {
- u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
-
- if (GRAPHICS_VER(uncore->i915) >= 11)
- freq = gen11_get_crystal_clock_freq(uncore, c0);
- else
- freq = gen9_get_crystal_clock_freq(uncore, c0);
+ freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
/*
* Now figure out how the command stream's timestamp
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
- GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
+ CTC_SHIFT_PARAMETER_SHIFT);
}
return freq;
+ } else if (GRAPHICS_VER(uncore->i915) >= 5) {
+ /*
+ * PRMs say:
+ *
+ * "The PCU TSC counts 10ns increments; this timestamp
+ * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
+ * rolling over every 1.5 hours).
+ */
+ return f12_5_mhz;
+ } else {
+ /*
+ * PRMs say:
+ *
+ * "The value in this register increments once every 16
+ * hclks." (through the “Clocking Configuration”
+ * (“CLKCFG”) MCHBAR register)
+ */
+ return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
}
-
- MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
- return 0;
}
void intel_gt_init_clock_frequency(struct intel_gt *gt)
--
2.37.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Invert if/else ladder for frequency read
2022-09-07 20:30 ` [Intel-gfx] " Lucas De Marchi
(?)
@ 2022-09-07 21:08 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-09-07 21:08 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Invert if/else ladder for frequency read
URL : https://patchwork.freedesktop.org/series/108268/
State : warning
== Summary ==
Error: dim checkpatch failed
39d3d3166a72 drm/i915: Invert if/else ladder for frequency read
-:120: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#120: FILE: drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c:139:
+ return f12_5_mhz;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 114 lines checked
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Invert if/else ladder for frequency read
2022-09-07 20:30 ` [Intel-gfx] " Lucas De Marchi
(?)
(?)
@ 2022-09-07 21:19 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-09-07 21:19 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4205 bytes --]
== Series Details ==
Series: drm/i915: Invert if/else ladder for frequency read
URL : https://patchwork.freedesktop.org/series/108268/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12090 -> Patchwork_108268v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/index.html
Participating hosts (43 -> 42)
------------------------------
Additional (1): fi-snb-2600
Missing (2): fi-rkl-11600 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_108268v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +20 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-snb-2600/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gem:
- fi-pnv-d510: NOTRUN -> [DMESG-FAIL][2] ([i915#4528])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-pnv-d510/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: NOTRUN -> [INCOMPLETE][3] ([i915#3921])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_addfb_basic@addfb25-yf-tiled-legacy:
- fi-icl-u2: [PASS][4] -> [DMESG-WARN][5] ([i915#4890])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-icl-u2/igt@kms_addfb_basic@addfb25-yf-tiled-legacy.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-icl-u2/igt@kms_addfb_basic@addfb25-yf-tiled-legacy.html
* igt@kms_chamelium@vga-hpd-fast:
- fi-snb-2600: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +7 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-snb-2600/igt@kms_chamelium@vga-hpd-fast.html
* igt@runner@aborted:
- fi-icl-u2: NOTRUN -> [FAIL][7] ([i915#4312] / [i915#6599])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-icl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [DMESG-FAIL][8] ([i915#4528]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-pnv-d510/igt@i915_selftest@live@requests.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- {bat-rpls-1}: [DMESG-FAIL][10] -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rpls-1/igt@i915_selftest@live@workarounds.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/bat-rpls-1/igt@i915_selftest@live@workarounds.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
Build changes
-------------
* Linux: CI_DRM_12090 -> Patchwork_108268v1
CI-20190529: 20190529
CI_DRM_12090: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108268v1: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
27d82f283738 drm/i915: Invert if/else ladder for frequency read
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/index.html
[-- Attachment #2: Type: text/html, Size: 5087 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Invert if/else ladder for frequency read
2022-09-07 20:30 ` [Intel-gfx] " Lucas De Marchi
@ 2022-09-07 23:22 ` Matt Roper
-1 siblings, 0 replies; 9+ messages in thread
From: Matt Roper @ 2022-09-07 23:22 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 01:30:41PM -0700, Lucas De Marchi wrote:
> Continue converting the driver to the convention of last version first,
> extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
> be handled by the first branch.
>
> With the new ranges it's easier to see what platform a branch started to
> be taken. Besides the >= 11 change, the branch taken for GRAPHICS_VER == 10
> is also different, but currently there is no such platform in i915.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 77 +++++++++----------
> 1 file changed, 37 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> index d5d1b04dbcad..93608c9349fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> @@ -78,77 +78,74 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> u32 f19_2_mhz = 19200000;
> u32 f24_mhz = 24000000;
>
> - if (GRAPHICS_VER(uncore->i915) <= 4) {
> - /*
> - * PRMs say:
> - *
> - * "The value in this register increments once every 16
> - * hclks." (through the “Clocking Configuration”
> - * (“CLKCFG”) MCHBAR register)
> - */
> - return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> - } else if (GRAPHICS_VER(uncore->i915) <= 8) {
> - /*
> - * PRMs say:
> - *
> - * "The PCU TSC counts 10ns increments; this timestamp
> - * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
> - * rolling over every 1.5 hours).
> - */
> - return f12_5_mhz;
> - } else if (GRAPHICS_VER(uncore->i915) <= 9) {
> + if (GRAPHICS_VER(uncore->i915) >= 11) {
> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> u32 freq = 0;
>
> + /*
> + * First figure out the reference frequency. There are 2 ways
> + * we can compute the frequency, either through the
> + * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
> + * tells us which one we should use.
> + */
> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> freq = read_reference_ts_freq(uncore);
> } else {
> - freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
> + u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> +
> + if (GRAPHICS_VER(uncore->i915) >= 11)
> + freq = gen11_get_crystal_clock_freq(uncore, c0);
> + else
> + freq = gen9_get_crystal_clock_freq(uncore, c0);
>
> /*
> * Now figure out how the command stream's timestamp
> * register increments from this frequency (it might
> * increment only every few clock cycle).
> */
> - freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
> - CTC_SHIFT_PARAMETER_SHIFT);
> + freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
> }
>
> return freq;
> - } else if (GRAPHICS_VER(uncore->i915) <= 12) {
> + } else if (GRAPHICS_VER(uncore->i915) >= 9) {
> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> u32 freq = 0;
>
> - /*
> - * First figure out the reference frequency. There are 2 ways
> - * we can compute the frequency, either through the
> - * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
> - * tells us which one we should use.
> - */
> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> freq = read_reference_ts_freq(uncore);
> } else {
> - u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> -
> - if (GRAPHICS_VER(uncore->i915) >= 11)
> - freq = gen11_get_crystal_clock_freq(uncore, c0);
> - else
> - freq = gen9_get_crystal_clock_freq(uncore, c0);
> + freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
>
> /*
> * Now figure out how the command stream's timestamp
> * register increments from this frequency (it might
> * increment only every few clock cycle).
> */
> - freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
> + freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
> + CTC_SHIFT_PARAMETER_SHIFT);
> }
>
> return freq;
> + } else if (GRAPHICS_VER(uncore->i915) >= 5) {
> + /*
> + * PRMs say:
> + *
> + * "The PCU TSC counts 10ns increments; this timestamp
> + * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
> + * rolling over every 1.5 hours).
> + */
> + return f12_5_mhz;
> + } else {
> + /*
> + * PRMs say:
> + *
> + * "The value in this register increments once every 16
> + * hclks." (through the “Clocking Configuration”
> + * (“CLKCFG”) MCHBAR register)
> + */
> + return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> }
> -
> - MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
> - return 0;
> }
>
> void intel_gt_init_clock_frequency(struct intel_gt *gt)
> --
> 2.37.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Invert if/else ladder for frequency read
@ 2022-09-07 23:22 ` Matt Roper
0 siblings, 0 replies; 9+ messages in thread
From: Matt Roper @ 2022-09-07 23:22 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 01:30:41PM -0700, Lucas De Marchi wrote:
> Continue converting the driver to the convention of last version first,
> extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
> be handled by the first branch.
>
> With the new ranges it's easier to see what platform a branch started to
> be taken. Besides the >= 11 change, the branch taken for GRAPHICS_VER == 10
> is also different, but currently there is no such platform in i915.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 77 +++++++++----------
> 1 file changed, 37 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> index d5d1b04dbcad..93608c9349fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> @@ -78,77 +78,74 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> u32 f19_2_mhz = 19200000;
> u32 f24_mhz = 24000000;
>
> - if (GRAPHICS_VER(uncore->i915) <= 4) {
> - /*
> - * PRMs say:
> - *
> - * "The value in this register increments once every 16
> - * hclks." (through the “Clocking Configuration”
> - * (“CLKCFG”) MCHBAR register)
> - */
> - return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> - } else if (GRAPHICS_VER(uncore->i915) <= 8) {
> - /*
> - * PRMs say:
> - *
> - * "The PCU TSC counts 10ns increments; this timestamp
> - * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
> - * rolling over every 1.5 hours).
> - */
> - return f12_5_mhz;
> - } else if (GRAPHICS_VER(uncore->i915) <= 9) {
> + if (GRAPHICS_VER(uncore->i915) >= 11) {
> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> u32 freq = 0;
>
> + /*
> + * First figure out the reference frequency. There are 2 ways
> + * we can compute the frequency, either through the
> + * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
> + * tells us which one we should use.
> + */
> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> freq = read_reference_ts_freq(uncore);
> } else {
> - freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
> + u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> +
> + if (GRAPHICS_VER(uncore->i915) >= 11)
> + freq = gen11_get_crystal_clock_freq(uncore, c0);
> + else
> + freq = gen9_get_crystal_clock_freq(uncore, c0);
>
> /*
> * Now figure out how the command stream's timestamp
> * register increments from this frequency (it might
> * increment only every few clock cycle).
> */
> - freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
> - CTC_SHIFT_PARAMETER_SHIFT);
> + freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
> }
>
> return freq;
> - } else if (GRAPHICS_VER(uncore->i915) <= 12) {
> + } else if (GRAPHICS_VER(uncore->i915) >= 9) {
> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> u32 freq = 0;
>
> - /*
> - * First figure out the reference frequency. There are 2 ways
> - * we can compute the frequency, either through the
> - * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
> - * tells us which one we should use.
> - */
> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> freq = read_reference_ts_freq(uncore);
> } else {
> - u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> -
> - if (GRAPHICS_VER(uncore->i915) >= 11)
> - freq = gen11_get_crystal_clock_freq(uncore, c0);
> - else
> - freq = gen9_get_crystal_clock_freq(uncore, c0);
> + freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
>
> /*
> * Now figure out how the command stream's timestamp
> * register increments from this frequency (it might
> * increment only every few clock cycle).
> */
> - freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
> + freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
> + CTC_SHIFT_PARAMETER_SHIFT);
> }
>
> return freq;
> + } else if (GRAPHICS_VER(uncore->i915) >= 5) {
> + /*
> + * PRMs say:
> + *
> + * "The PCU TSC counts 10ns increments; this timestamp
> + * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
> + * rolling over every 1.5 hours).
> + */
> + return f12_5_mhz;
> + } else {
> + /*
> + * PRMs say:
> + *
> + * "The value in this register increments once every 16
> + * hclks." (through the “Clocking Configuration”
> + * (“CLKCFG”) MCHBAR register)
> + */
> + return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> }
> -
> - MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
> - return 0;
> }
>
> void intel_gt_init_clock_frequency(struct intel_gt *gt)
> --
> 2.37.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Invert if/else ladder for frequency read
2022-09-07 20:30 ` [Intel-gfx] " Lucas De Marchi
` (3 preceding siblings ...)
(?)
@ 2022-09-08 3:29 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-09-08 3:29 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 25243 bytes --]
== Series Details ==
Series: drm/i915: Invert if/else ladder for frequency read
URL : https://patchwork.freedesktop.org/series/108268/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12090_full -> Patchwork_108268v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_108268v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108268v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108268v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-snb5/igt@i915_module_load@reload-with-fault-injection.html
Known issues
------------
Here are the changes found in Patchwork_108268v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-2x:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#1839])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@feature_discovery@display-2x.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb4/igt@gem_exec_balancer@parallel-contexts.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb7/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_capture@capture-recoverable:
- shard-iclb: NOTRUN -> [SKIP][6] ([i915#6344])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2846])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk2/igt@gem_exec_fair@basic-deadline.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-glk7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842]) +3 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-iclb: NOTRUN -> [SKIP][14] ([i915#4613])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_lmem_swapping@verify-random:
- shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl7/igt@gem_lmem_swapping@verify-random.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-snb: [PASS][16] -> [FAIL][17] ([i915#4998])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-snb2/igt@gem_ppgtt@blt-vs-render-ctxn.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-snb6/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][18] ([i915#2658])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl6/igt@gem_pread@exhaustion.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_userptr_blits@vma-merge:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#3318])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#5566] / [i915#716])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl4/igt@gen9_exec_parse@allowed-single.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl1/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][23] ([i915#2856])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@gen9_exec_parse@batch-without-end.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][24] ([i915#5286])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][25] ([fdo#110725] / [fdo#111614])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][26] ([fdo#110723])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_joiner@basic:
- shard-iclb: NOTRUN -> [SKIP][27] ([i915#2705])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
- shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271]) +122 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl6/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109278] / [i915#3886]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3886]) +3 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl7/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-random-ccs-data-4_tiled_dg2_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109278]) +4 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_ccs@pipe-d-random-ccs-data-4_tiled_dg2_mc_ccs.html
* igt@kms_chamelium@dp-crc-fast:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109284] / [fdo#111827])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-frame-dump:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl7/igt@kms_chamelium@dp-frame-dump.html
* igt@kms_content_protection@lic:
- shard-iclb: NOTRUN -> [SKIP][34] ([fdo#109300] / [fdo#111066])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_content_protection@lic.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: NOTRUN -> [FAIL][35] ([i915#4767])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109274])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1:
- shard-glk: [PASS][37] -> [FAIL][38] ([i915#2122])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk7/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-glk7/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][39] ([i915#2672]) +5 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#109280]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_lease@lease_invalid_plane:
- shard-snb: [PASS][41] -> [SKIP][42] ([fdo#109271]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-snb7/igt@kms_lease@lease_invalid_plane.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-snb7/igt@kms_lease@lease_invalid_plane.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][43] ([fdo#108145] / [i915#265])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-edp-1:
- shard-iclb: NOTRUN -> [SKIP][44] ([i915#5176]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-edp-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#658]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl3/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#111068] / [i915#658])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109441])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@kms_psr@psr2_primary_render.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][48] -> [SKIP][49] ([fdo#109441]) +2 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb4/igt@kms_psr@psr2_sprite_blt.html
* igt@prime_nv_api@i915_nv_import_vs_close:
- shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109291])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@prime_nv_api@i915_nv_import_vs_close.html
* igt@prime_vgem@fence-flip-hang:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109295])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@prime_vgem@fence-flip-hang.html
* igt@sysfs_clients@fair-3:
- shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#2994]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl6/igt@sysfs_clients@fair-3.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-close-race:
- shard-iclb: [INCOMPLETE][53] -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb1/igt@gem_ctx_exec@basic-close-race.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@gem_ctx_exec@basic-close-race.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [SKIP][55] ([i915#4525]) -> [PASS][56] +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb7/igt@gem_exec_balancer@parallel-bb-first.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][57] ([i915#2842]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][59] ([i915#2842]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl8/igt@gem_exec_fair@basic-none-solo@rcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][61] ([i915#2842]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][63] ([i915#2190]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-tglb3/igt@gem_huc_copy@huc-copy.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [DMESG-WARN][65] ([i915#5566] / [i915#716]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk6/igt@gen9_exec_parse@allowed-single.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-glk7/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][67] ([i915#454]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb6/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][69] ([i915#79]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-iclb: [DMESG-WARN][71] ([i915#2867]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb5/igt@kms_flip@flip-vs-suspend@c-edp1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb6/igt@kms_flip@flip-vs-suspend@c-edp1.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][73] ([fdo#109441]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglb: [SKIP][75] ([i915#5519]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-tglb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-tglb3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_sequence@get-forked@edp-1-pipe-a:
- shard-iclb: [DMESG-WARN][77] ([i915#4391]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb7/igt@kms_sequence@get-forked@edp-1-pipe-a.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb2/igt@kms_sequence@get-forked@edp-1-pipe-a.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][79] ([i915#180]) -> [PASS][80] +3 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Warnings ####
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][81] ([i915#2920]) -> [SKIP][82] ([i915#658]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb4/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-iclb: [SKIP][83] ([fdo#111068] / [i915#658]) -> [SKIP][84] ([i915#2920])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][85], [FAIL][86], [FAIL][87], [FAIL][88], [FAIL][89], [FAIL][90]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][91], [FAIL][92], [FAIL][93]) ([fdo#109271] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl3/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl3/igt@runner@aborted.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl6/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl8/igt@runner@aborted.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl8/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl2/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl8/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl1/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl1/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941
[i915#4998]: https://gitlab.freedesktop.org/drm/intel/issues/4998
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12090 -> Patchwork_108268v1
CI-20190529: 20190529
CI_DRM_12090: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108268v1: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/index.html
[-- Attachment #2: Type: text/html, Size: 28699 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Invert if/else ladder for frequency read
2022-09-07 20:30 ` [Intel-gfx] " Lucas De Marchi
` (4 preceding siblings ...)
(?)
@ 2022-09-08 11:08 ` Ville Syrjälä
2022-09-08 16:34 ` Lucas De Marchi
-1 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2022-09-08 11:08 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 01:30:41PM -0700, Lucas De Marchi wrote:
> Continue converting the driver to the convention of last version first,
> extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
> be handled by the first branch.
>
> With the new ranges it's easier to see what platform a branch started to
> be taken. Besides the >= 11 change, the branch taken for GRAPHICS_VER == 10
> is also different, but currently there is no such platform in i915.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 77 +++++++++----------
> 1 file changed, 37 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> index d5d1b04dbcad..93608c9349fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> @@ -78,77 +78,74 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> u32 f19_2_mhz = 19200000;
> u32 f24_mhz = 24000000;
>
> - if (GRAPHICS_VER(uncore->i915) <= 4) {
> - /*
> - * PRMs say:
> - *
> - * "The value in this register increments once every 16
> - * hclks." (through the “Clocking Configuration”
> - * (“CLKCFG”) MCHBAR register)
> - */
> - return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> - } else if (GRAPHICS_VER(uncore->i915) <= 8) {
> - /*
> - * PRMs say:
> - *
> - * "The PCU TSC counts 10ns increments; this timestamp
> - * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
> - * rolling over every 1.5 hours).
> - */
> - return f12_5_mhz;
> - } else if (GRAPHICS_VER(uncore->i915) <= 9) {
Is there a good reason each of these branches isn't just its own function?
> + if (GRAPHICS_VER(uncore->i915) >= 11) {
> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> u32 freq = 0;
>
> + /*
> + * First figure out the reference frequency. There are 2 ways
> + * we can compute the frequency, either through the
> + * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
> + * tells us which one we should use.
> + */
> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> freq = read_reference_ts_freq(uncore);
> } else {
> - freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
> + u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> +
> + if (GRAPHICS_VER(uncore->i915) >= 11)
> + freq = gen11_get_crystal_clock_freq(uncore, c0);
> + else
> + freq = gen9_get_crystal_clock_freq(uncore, c0);
>
> /*
> * Now figure out how the command stream's timestamp
> * register increments from this frequency (it might
> * increment only every few clock cycle).
> */
> - freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
> - CTC_SHIFT_PARAMETER_SHIFT);
> + freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
> }
>
> return freq;
> - } else if (GRAPHICS_VER(uncore->i915) <= 12) {
> + } else if (GRAPHICS_VER(uncore->i915) >= 9) {
> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> u32 freq = 0;
>
> - /*
> - * First figure out the reference frequency. There are 2 ways
> - * we can compute the frequency, either through the
> - * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
> - * tells us which one we should use.
> - */
> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> freq = read_reference_ts_freq(uncore);
> } else {
> - u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> -
> - if (GRAPHICS_VER(uncore->i915) >= 11)
> - freq = gen11_get_crystal_clock_freq(uncore, c0);
> - else
> - freq = gen9_get_crystal_clock_freq(uncore, c0);
> + freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
>
> /*
> * Now figure out how the command stream's timestamp
> * register increments from this frequency (it might
> * increment only every few clock cycle).
> */
> - freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
> + freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
> + CTC_SHIFT_PARAMETER_SHIFT);
> }
>
> return freq;
> + } else if (GRAPHICS_VER(uncore->i915) >= 5) {
> + /*
> + * PRMs say:
> + *
> + * "The PCU TSC counts 10ns increments; this timestamp
> + * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
> + * rolling over every 1.5 hours).
> + */
> + return f12_5_mhz;
> + } else {
> + /*
> + * PRMs say:
> + *
> + * "The value in this register increments once every 16
> + * hclks." (through the “Clocking Configuration”
> + * (“CLKCFG”) MCHBAR register)
> + */
> + return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> }
> -
> - MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
> - return 0;
> }
>
> void intel_gt_init_clock_frequency(struct intel_gt *gt)
> --
> 2.37.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Invert if/else ladder for frequency read
2022-09-08 11:08 ` [Intel-gfx] [PATCH] " Ville Syrjälä
@ 2022-09-08 16:34 ` Lucas De Marchi
0 siblings, 0 replies; 9+ messages in thread
From: Lucas De Marchi @ 2022-09-08 16:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Thu, Sep 08, 2022 at 02:08:55PM +0300, Ville Syrjälä wrote:
>On Wed, Sep 07, 2022 at 01:30:41PM -0700, Lucas De Marchi wrote:
>> Continue converting the driver to the convention of last version first,
>> extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
>> be handled by the first branch.
>>
>> With the new ranges it's easier to see what platform a branch started to
>> be taken. Besides the >= 11 change, the branch taken for GRAPHICS_VER == 10
>> is also different, but currently there is no such platform in i915.
>>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 77 +++++++++----------
>> 1 file changed, 37 insertions(+), 40 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> index d5d1b04dbcad..93608c9349fd 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> @@ -78,77 +78,74 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> u32 f19_2_mhz = 19200000;
>> u32 f24_mhz = 24000000;
>>
>> - if (GRAPHICS_VER(uncore->i915) <= 4) {
>> - /*
>> - * PRMs say:
>> - *
>> - * "The value in this register increments once every 16
>> - * hclks." (through the “Clocking Configuration”
>> - * (“CLKCFG”) MCHBAR register)
>> - */
>> - return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
>> - } else if (GRAPHICS_VER(uncore->i915) <= 8) {
>> - /*
>> - * PRMs say:
>> - *
>> - * "The PCU TSC counts 10ns increments; this timestamp
>> - * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
>> - * rolling over every 1.5 hours).
>> - */
>> - return f12_5_mhz;
>> - } else if (GRAPHICS_VER(uncore->i915) <= 9) {
>
>Is there a good reason each of these branches isn't just its own function?
Because they are a single line, hard to justify a separate function, but
yes, we could move each of those to a separate one since the others
start to span a little more.
Lucas De Marchi
>
>> + if (GRAPHICS_VER(uncore->i915) >= 11) {
>> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
>> u32 freq = 0;
>>
>> + /*
>> + * First figure out the reference frequency. There are 2 ways
>> + * we can compute the frequency, either through the
>> + * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
>> + * tells us which one we should use.
>> + */
>> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
>> freq = read_reference_ts_freq(uncore);
>> } else {
>> - freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
>> + u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
>> +
>> + if (GRAPHICS_VER(uncore->i915) >= 11)
>> + freq = gen11_get_crystal_clock_freq(uncore, c0);
>> + else
>> + freq = gen9_get_crystal_clock_freq(uncore, c0);
>>
>> /*
>> * Now figure out how the command stream's timestamp
>> * register increments from this frequency (it might
>> * increment only every few clock cycle).
>> */
>> - freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
>> - CTC_SHIFT_PARAMETER_SHIFT);
>> + freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
>> + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
>> }
>>
>> return freq;
>> - } else if (GRAPHICS_VER(uncore->i915) <= 12) {
>> + } else if (GRAPHICS_VER(uncore->i915) >= 9) {
>> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
>> u32 freq = 0;
>>
>> - /*
>> - * First figure out the reference frequency. There are 2 ways
>> - * we can compute the frequency, either through the
>> - * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
>> - * tells us which one we should use.
>> - */
>> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
>> freq = read_reference_ts_freq(uncore);
>> } else {
>> - u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
>> -
>> - if (GRAPHICS_VER(uncore->i915) >= 11)
>> - freq = gen11_get_crystal_clock_freq(uncore, c0);
>> - else
>> - freq = gen9_get_crystal_clock_freq(uncore, c0);
>> + freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
>>
>> /*
>> * Now figure out how the command stream's timestamp
>> * register increments from this frequency (it might
>> * increment only every few clock cycle).
>> */
>> - freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
>> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
>> + freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
>> + CTC_SHIFT_PARAMETER_SHIFT);
>> }
>>
>> return freq;
>> + } else if (GRAPHICS_VER(uncore->i915) >= 5) {
>> + /*
>> + * PRMs say:
>> + *
>> + * "The PCU TSC counts 10ns increments; this timestamp
>> + * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
>> + * rolling over every 1.5 hours).
>> + */
>> + return f12_5_mhz;
>> + } else {
>> + /*
>> + * PRMs say:
>> + *
>> + * "The value in this register increments once every 16
>> + * hclks." (through the “Clocking Configuration”
>> + * (“CLKCFG”) MCHBAR register)
>> + */
>> + return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
>> }
>> -
>> - MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
>> - return 0;
>> }
>>
>> void intel_gt_init_clock_frequency(struct intel_gt *gt)
>> --
>> 2.37.2
>
>--
>Ville Syrjälä
>Intel
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-09-08 16:34 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-07 20:30 [PATCH] drm/i915: Invert if/else ladder for frequency read Lucas De Marchi
2022-09-07 20:30 ` [Intel-gfx] " Lucas De Marchi
2022-09-07 21:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-09-07 21:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-07 23:22 ` [PATCH] " Matt Roper
2022-09-07 23:22 ` [Intel-gfx] " Matt Roper
2022-09-08 3:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
2022-09-08 11:08 ` [Intel-gfx] [PATCH] " Ville Syrjälä
2022-09-08 16:34 ` Lucas De Marchi
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