* [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
@ 2022-09-07 20:39 ` Lucas De Marchi
0 siblings, 0 replies; 12+ messages in thread
From: Lucas De Marchi @ 2022-09-07 20:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Check for media IP version instead of graphics since this is figuring
out the media engines' configuration. Currently the only platform with
non-matching graphics/media version is Meteor Lake: update the check in
gen11_vdbox_has_sfc() so it considers not only version 12, but also any
later version which then includes that platform.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..5cddee7c2f1d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
*/
if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
return false;
- else if (GRAPHICS_VER(i915) == 12)
+ else if (MEDIA_VER(i915) >= 12)
return (physical_vdbox % 2 == 0) ||
!(BIT(physical_vdbox - 1) & vdbox_mask);
- else if (GRAPHICS_VER(i915) == 11)
+ else if (MEDIA_VER(i915) == 11)
return logical_vdbox % 2 == 0;
- MISSING_CASE(GRAPHICS_VER(i915));
+ MISSING_CASE(MEDIA_VER(i915));
+
return false;
}
@@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
* and bits have disable semantices.
*/
media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
- if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
media_fuse = ~media_fuse;
vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
GEN11_GT_VEBOX_DISABLE_SHIFT;
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
} else {
--
2.37.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
@ 2022-09-07 20:39 ` Lucas De Marchi
0 siblings, 0 replies; 12+ messages in thread
From: Lucas De Marchi @ 2022-09-07 20:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Check for media IP version instead of graphics since this is figuring
out the media engines' configuration. Currently the only platform with
non-matching graphics/media version is Meteor Lake: update the check in
gen11_vdbox_has_sfc() so it considers not only version 12, but also any
later version which then includes that platform.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..5cddee7c2f1d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
*/
if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
return false;
- else if (GRAPHICS_VER(i915) == 12)
+ else if (MEDIA_VER(i915) >= 12)
return (physical_vdbox % 2 == 0) ||
!(BIT(physical_vdbox - 1) & vdbox_mask);
- else if (GRAPHICS_VER(i915) == 11)
+ else if (MEDIA_VER(i915) == 11)
return logical_vdbox % 2 == 0;
- MISSING_CASE(GRAPHICS_VER(i915));
+ MISSING_CASE(MEDIA_VER(i915));
+
return false;
}
@@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
* and bits have disable semantices.
*/
media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
- if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
media_fuse = ~media_fuse;
vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
GEN11_GT_VEBOX_DISABLE_SHIFT;
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
} else {
--
2.37.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] drm/i915/gt: Extract function to apply media fuses
2022-09-07 20:39 ` [Intel-gfx] " Lucas De Marchi
@ 2022-09-07 20:39 ` Lucas De Marchi
-1 siblings, 0 replies; 12+ messages in thread
From: Lucas De Marchi @ 2022-09-07 20:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Just like is done for compute and copy engines, extract a function to
handle media engines. While at it, be consistent on using or not the
uncore/gt/info variable aliases.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 136 ++++++++++++----------
1 file changed, 72 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 5cddee7c2f1d..5b9dfa0cd467 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -665,6 +665,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
return false;
}
+static void engine_mask_apply_media_fuses(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ unsigned int logical_vdbox = 0;
+ unsigned int i;
+ u32 media_fuse, fuse1;
+ u16 vdbox_mask;
+ u16 vebox_mask;
+
+ if (MEDIA_VER(gt->i915) < 11)
+ return;
+
+ /*
+ * On newer platforms the fusing register is called 'enable' and has
+ * enable semantics, while on older platforms it is called 'disable'
+ * and bits have disable semantices.
+ */
+ media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
+ media_fuse = ~media_fuse;
+
+ vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+ vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+ GEN11_GT_VEBOX_DISABLE_SHIFT;
+
+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
+ fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
+ gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
+ } else {
+ gt->info.sfc_mask = ~0;
+ }
+
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (!HAS_ENGINE(gt, _VCS(i))) {
+ vdbox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vdbox_mask)) {
+ gt->info.engine_mask &= ~BIT(_VCS(i));
+ drm_dbg(&i915->drm, "vcs%u fused off\n", i);
+ continue;
+ }
+
+ if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
+ gt->info.vdbox_sfc_access |= BIT(i);
+ logical_vdbox++;
+ }
+ drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
+ vdbox_mask, VDBOX_MASK(gt));
+ GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
+
+ for (i = 0; i < I915_MAX_VECS; i++) {
+ if (!HAS_ENGINE(gt, _VECS(i))) {
+ vebox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vebox_mask)) {
+ gt->info.engine_mask &= ~BIT(_VECS(i));
+ drm_dbg(&i915->drm, "vecs%u fused off\n", i);
+ }
+ }
+ drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
+ vebox_mask, VEBOX_MASK(gt));
+ GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
+}
+
static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -673,6 +741,9 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
unsigned long ccs_mask;
unsigned int i;
+ if (GRAPHICS_VER(i915) < 11)
+ return;
+
if (hweight32(CCS_MASK(gt)) <= 1)
return;
@@ -730,73 +801,10 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
struct intel_gt_info *info = >->info;
- struct intel_uncore *uncore = gt->uncore;
- unsigned int logical_vdbox = 0;
- unsigned int i;
- u32 media_fuse, fuse1;
- u16 vdbox_mask;
- u16 vebox_mask;
info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
- if (GRAPHICS_VER(i915) < 11)
- return info->engine_mask;
-
- /*
- * On newer platforms the fusing register is called 'enable' and has
- * enable semantics, while on older platforms it is called 'disable'
- * and bits have disable semantices.
- */
- media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
- if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
- media_fuse = ~media_fuse;
-
- vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
- vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
- GEN11_GT_VEBOX_DISABLE_SHIFT;
-
- if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
- fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
- gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
- } else {
- gt->info.sfc_mask = ~0;
- }
-
- for (i = 0; i < I915_MAX_VCS; i++) {
- if (!HAS_ENGINE(gt, _VCS(i))) {
- vdbox_mask &= ~BIT(i);
- continue;
- }
-
- if (!(BIT(i) & vdbox_mask)) {
- info->engine_mask &= ~BIT(_VCS(i));
- drm_dbg(&i915->drm, "vcs%u fused off\n", i);
- continue;
- }
-
- if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
- gt->info.vdbox_sfc_access |= BIT(i);
- logical_vdbox++;
- }
- drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
- vdbox_mask, VDBOX_MASK(gt));
- GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
-
- for (i = 0; i < I915_MAX_VECS; i++) {
- if (!HAS_ENGINE(gt, _VECS(i))) {
- vebox_mask &= ~BIT(i);
- continue;
- }
-
- if (!(BIT(i) & vebox_mask)) {
- info->engine_mask &= ~BIT(_VECS(i));
- drm_dbg(&i915->drm, "vecs%u fused off\n", i);
- }
- }
- drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
- vebox_mask, VEBOX_MASK(gt));
- GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
-
+ engine_mask_apply_media_fuses(gt);
engine_mask_apply_compute_fuses(gt);
engine_mask_apply_copy_fuses(gt);
--
2.37.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/gt: Extract function to apply media fuses
@ 2022-09-07 20:39 ` Lucas De Marchi
0 siblings, 0 replies; 12+ messages in thread
From: Lucas De Marchi @ 2022-09-07 20:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Just like is done for compute and copy engines, extract a function to
handle media engines. While at it, be consistent on using or not the
uncore/gt/info variable aliases.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 136 ++++++++++++----------
1 file changed, 72 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 5cddee7c2f1d..5b9dfa0cd467 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -665,6 +665,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
return false;
}
+static void engine_mask_apply_media_fuses(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ unsigned int logical_vdbox = 0;
+ unsigned int i;
+ u32 media_fuse, fuse1;
+ u16 vdbox_mask;
+ u16 vebox_mask;
+
+ if (MEDIA_VER(gt->i915) < 11)
+ return;
+
+ /*
+ * On newer platforms the fusing register is called 'enable' and has
+ * enable semantics, while on older platforms it is called 'disable'
+ * and bits have disable semantices.
+ */
+ media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
+ media_fuse = ~media_fuse;
+
+ vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+ vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+ GEN11_GT_VEBOX_DISABLE_SHIFT;
+
+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
+ fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
+ gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
+ } else {
+ gt->info.sfc_mask = ~0;
+ }
+
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (!HAS_ENGINE(gt, _VCS(i))) {
+ vdbox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vdbox_mask)) {
+ gt->info.engine_mask &= ~BIT(_VCS(i));
+ drm_dbg(&i915->drm, "vcs%u fused off\n", i);
+ continue;
+ }
+
+ if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
+ gt->info.vdbox_sfc_access |= BIT(i);
+ logical_vdbox++;
+ }
+ drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
+ vdbox_mask, VDBOX_MASK(gt));
+ GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
+
+ for (i = 0; i < I915_MAX_VECS; i++) {
+ if (!HAS_ENGINE(gt, _VECS(i))) {
+ vebox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vebox_mask)) {
+ gt->info.engine_mask &= ~BIT(_VECS(i));
+ drm_dbg(&i915->drm, "vecs%u fused off\n", i);
+ }
+ }
+ drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
+ vebox_mask, VEBOX_MASK(gt));
+ GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
+}
+
static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -673,6 +741,9 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
unsigned long ccs_mask;
unsigned int i;
+ if (GRAPHICS_VER(i915) < 11)
+ return;
+
if (hweight32(CCS_MASK(gt)) <= 1)
return;
@@ -730,73 +801,10 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
struct intel_gt_info *info = >->info;
- struct intel_uncore *uncore = gt->uncore;
- unsigned int logical_vdbox = 0;
- unsigned int i;
- u32 media_fuse, fuse1;
- u16 vdbox_mask;
- u16 vebox_mask;
info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
- if (GRAPHICS_VER(i915) < 11)
- return info->engine_mask;
-
- /*
- * On newer platforms the fusing register is called 'enable' and has
- * enable semantics, while on older platforms it is called 'disable'
- * and bits have disable semantices.
- */
- media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
- if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
- media_fuse = ~media_fuse;
-
- vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
- vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
- GEN11_GT_VEBOX_DISABLE_SHIFT;
-
- if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
- fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
- gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
- } else {
- gt->info.sfc_mask = ~0;
- }
-
- for (i = 0; i < I915_MAX_VCS; i++) {
- if (!HAS_ENGINE(gt, _VCS(i))) {
- vdbox_mask &= ~BIT(i);
- continue;
- }
-
- if (!(BIT(i) & vdbox_mask)) {
- info->engine_mask &= ~BIT(_VCS(i));
- drm_dbg(&i915->drm, "vcs%u fused off\n", i);
- continue;
- }
-
- if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
- gt->info.vdbox_sfc_access |= BIT(i);
- logical_vdbox++;
- }
- drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
- vdbox_mask, VDBOX_MASK(gt));
- GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
-
- for (i = 0; i < I915_MAX_VECS; i++) {
- if (!HAS_ENGINE(gt, _VECS(i))) {
- vebox_mask &= ~BIT(i);
- continue;
- }
-
- if (!(BIT(i) & vebox_mask)) {
- info->engine_mask &= ~BIT(_VECS(i));
- drm_dbg(&i915->drm, "vecs%u fused off\n", i);
- }
- }
- drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
- vebox_mask, VEBOX_MASK(gt));
- GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
-
+ engine_mask_apply_media_fuses(gt);
engine_mask_apply_compute_fuses(gt);
engine_mask_apply_copy_fuses(gt);
--
2.37.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
2022-09-07 20:39 ` [Intel-gfx] " Lucas De Marchi
(?)
(?)
@ 2022-09-07 21:43 ` Patchwork
-1 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-09-07 21:43 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2962 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
URL : https://patchwork.freedesktop.org/series/108269/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12090 -> Patchwork_108269v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/index.html
Participating hosts (43 -> 42)
------------------------------
Additional (1): fi-snb-2600
Missing (2): fi-icl-u2 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_108269v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +20 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/fi-snb-2600/igt@i915_pm_rpm@module-reload.html
* igt@kms_chamelium@vga-hpd-fast:
- fi-snb-2600: NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827]) +8 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/fi-snb-2600/igt@kms_chamelium@vga-hpd-fast.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}: [DMESG-WARN][3] ([i915#2867]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rplp-1/igt@gem_exec_suspend@basic-s3@smem.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/bat-rplp-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@workarounds:
- {bat-rpls-1}: [DMESG-FAIL][5] -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rpls-1/igt@i915_selftest@live@workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/bat-rpls-1/igt@i915_selftest@live@workarounds.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
Build changes
-------------
* Linux: CI_DRM_12090 -> Patchwork_108269v1
CI-20190529: 20190529
CI_DRM_12090: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108269v1: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
e0373a376ab4 drm/i915/gt: Extract function to apply media fuses
51a895dcc7ed drm/i915/gt: Use MEDIA_VER() when handling media fuses
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/index.html
[-- Attachment #2: Type: text/html, Size: 3744 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
2022-09-07 20:39 ` [Intel-gfx] " Lucas De Marchi
@ 2022-09-07 22:18 ` Matt Roper
-1 siblings, 0 replies; 12+ messages in thread
From: Matt Roper @ 2022-09-07 22:18 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 01:39:10PM -0700, Lucas De Marchi wrote:
> Check for media IP version instead of graphics since this is figuring
> out the media engines' configuration. Currently the only platform with
> non-matching graphics/media version is Meteor Lake: update the check in
> gen11_vdbox_has_sfc() so it considers not only version 12, but also any
> later version which then includes that platform.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 275ad72940c1..5cddee7c2f1d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
> */
> if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
> return false;
> - else if (GRAPHICS_VER(i915) == 12)
> + else if (MEDIA_VER(i915) >= 12)
> return (physical_vdbox % 2 == 0) ||
> !(BIT(physical_vdbox - 1) & vdbox_mask);
> - else if (GRAPHICS_VER(i915) == 11)
> + else if (MEDIA_VER(i915) == 11)
> return logical_vdbox % 2 == 0;
>
> - MISSING_CASE(GRAPHICS_VER(i915));
> + MISSING_CASE(MEDIA_VER(i915));
Do we even still need the MISSING_CASE given that we now have an
open-ended upper bound above and this is a "gen11" function that doesn't
get called at all on old platforms?
Personally I'd axe it, but up to you. Either way,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> +
> return false;
> }
>
> @@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> * and bits have disable semantices.
> */
> media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> media_fuse = ~media_fuse;
>
> vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> GEN11_GT_VEBOX_DISABLE_SHIFT;
>
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
> gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> } else {
> --
> 2.37.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
@ 2022-09-07 22:18 ` Matt Roper
0 siblings, 0 replies; 12+ messages in thread
From: Matt Roper @ 2022-09-07 22:18 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 01:39:10PM -0700, Lucas De Marchi wrote:
> Check for media IP version instead of graphics since this is figuring
> out the media engines' configuration. Currently the only platform with
> non-matching graphics/media version is Meteor Lake: update the check in
> gen11_vdbox_has_sfc() so it considers not only version 12, but also any
> later version which then includes that platform.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 275ad72940c1..5cddee7c2f1d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
> */
> if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
> return false;
> - else if (GRAPHICS_VER(i915) == 12)
> + else if (MEDIA_VER(i915) >= 12)
> return (physical_vdbox % 2 == 0) ||
> !(BIT(physical_vdbox - 1) & vdbox_mask);
> - else if (GRAPHICS_VER(i915) == 11)
> + else if (MEDIA_VER(i915) == 11)
> return logical_vdbox % 2 == 0;
>
> - MISSING_CASE(GRAPHICS_VER(i915));
> + MISSING_CASE(MEDIA_VER(i915));
Do we even still need the MISSING_CASE given that we now have an
open-ended upper bound above and this is a "gen11" function that doesn't
get called at all on old platforms?
Personally I'd axe it, but up to you. Either way,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> +
> return false;
> }
>
> @@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> * and bits have disable semantices.
> */
> media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> media_fuse = ~media_fuse;
>
> vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> GEN11_GT_VEBOX_DISABLE_SHIFT;
>
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
> gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> } else {
> --
> 2.37.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/gt: Extract function to apply media fuses
2022-09-07 20:39 ` [Intel-gfx] " Lucas De Marchi
@ 2022-09-07 22:20 ` Matt Roper
-1 siblings, 0 replies; 12+ messages in thread
From: Matt Roper @ 2022-09-07 22:20 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 01:39:11PM -0700, Lucas De Marchi wrote:
> Just like is done for compute and copy engines, extract a function to
> handle media engines. While at it, be consistent on using or not the
> uncore/gt/info variable aliases.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 136 ++++++++++++----------
> 1 file changed, 72 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 5cddee7c2f1d..5b9dfa0cd467 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -665,6 +665,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
> return false;
> }
>
> +static void engine_mask_apply_media_fuses(struct intel_gt *gt)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + unsigned int logical_vdbox = 0;
> + unsigned int i;
> + u32 media_fuse, fuse1;
> + u16 vdbox_mask;
> + u16 vebox_mask;
> +
> + if (MEDIA_VER(gt->i915) < 11)
> + return;
> +
> + /*
> + * On newer platforms the fusing register is called 'enable' and has
> + * enable semantics, while on older platforms it is called 'disable'
> + * and bits have disable semantices.
> + */
> + media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> + media_fuse = ~media_fuse;
> +
> + vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> + vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> + GEN11_GT_VEBOX_DISABLE_SHIFT;
> +
> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> + fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
> + gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> + } else {
> + gt->info.sfc_mask = ~0;
> + }
> +
> + for (i = 0; i < I915_MAX_VCS; i++) {
> + if (!HAS_ENGINE(gt, _VCS(i))) {
> + vdbox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vdbox_mask)) {
> + gt->info.engine_mask &= ~BIT(_VCS(i));
> + drm_dbg(&i915->drm, "vcs%u fused off\n", i);
> + continue;
> + }
> +
> + if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
> + gt->info.vdbox_sfc_access |= BIT(i);
> + logical_vdbox++;
> + }
> + drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> + vdbox_mask, VDBOX_MASK(gt));
> + GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
> +
> + for (i = 0; i < I915_MAX_VECS; i++) {
> + if (!HAS_ENGINE(gt, _VECS(i))) {
> + vebox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vebox_mask)) {
> + gt->info.engine_mask &= ~BIT(_VECS(i));
> + drm_dbg(&i915->drm, "vecs%u fused off\n", i);
> + }
> + }
> + drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
> + vebox_mask, VEBOX_MASK(gt));
> + GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> +}
> +
> static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -673,6 +741,9 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> unsigned long ccs_mask;
> unsigned int i;
>
> + if (GRAPHICS_VER(i915) < 11)
> + return;
> +
> if (hweight32(CCS_MASK(gt)) <= 1)
> return;
>
> @@ -730,73 +801,10 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> struct intel_gt_info *info = >->info;
> - struct intel_uncore *uncore = gt->uncore;
> - unsigned int logical_vdbox = 0;
> - unsigned int i;
> - u32 media_fuse, fuse1;
> - u16 vdbox_mask;
> - u16 vebox_mask;
>
> info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
>
> - if (GRAPHICS_VER(i915) < 11)
> - return info->engine_mask;
> -
> - /*
> - * On newer platforms the fusing register is called 'enable' and has
> - * enable semantics, while on older platforms it is called 'disable'
> - * and bits have disable semantices.
> - */
> - media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> - if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> - media_fuse = ~media_fuse;
> -
> - vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> - vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> - GEN11_GT_VEBOX_DISABLE_SHIFT;
> -
> - if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> - fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
> - gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> - } else {
> - gt->info.sfc_mask = ~0;
> - }
> -
> - for (i = 0; i < I915_MAX_VCS; i++) {
> - if (!HAS_ENGINE(gt, _VCS(i))) {
> - vdbox_mask &= ~BIT(i);
> - continue;
> - }
> -
> - if (!(BIT(i) & vdbox_mask)) {
> - info->engine_mask &= ~BIT(_VCS(i));
> - drm_dbg(&i915->drm, "vcs%u fused off\n", i);
> - continue;
> - }
> -
> - if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
> - gt->info.vdbox_sfc_access |= BIT(i);
> - logical_vdbox++;
> - }
> - drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> - vdbox_mask, VDBOX_MASK(gt));
> - GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
> -
> - for (i = 0; i < I915_MAX_VECS; i++) {
> - if (!HAS_ENGINE(gt, _VECS(i))) {
> - vebox_mask &= ~BIT(i);
> - continue;
> - }
> -
> - if (!(BIT(i) & vebox_mask)) {
> - info->engine_mask &= ~BIT(_VECS(i));
> - drm_dbg(&i915->drm, "vecs%u fused off\n", i);
> - }
> - }
> - drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
> - vebox_mask, VEBOX_MASK(gt));
> - GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> -
> + engine_mask_apply_media_fuses(gt);
> engine_mask_apply_compute_fuses(gt);
> engine_mask_apply_copy_fuses(gt);
>
> --
> 2.37.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Extract function to apply media fuses
@ 2022-09-07 22:20 ` Matt Roper
0 siblings, 0 replies; 12+ messages in thread
From: Matt Roper @ 2022-09-07 22:20 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 01:39:11PM -0700, Lucas De Marchi wrote:
> Just like is done for compute and copy engines, extract a function to
> handle media engines. While at it, be consistent on using or not the
> uncore/gt/info variable aliases.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 136 ++++++++++++----------
> 1 file changed, 72 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 5cddee7c2f1d..5b9dfa0cd467 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -665,6 +665,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
> return false;
> }
>
> +static void engine_mask_apply_media_fuses(struct intel_gt *gt)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + unsigned int logical_vdbox = 0;
> + unsigned int i;
> + u32 media_fuse, fuse1;
> + u16 vdbox_mask;
> + u16 vebox_mask;
> +
> + if (MEDIA_VER(gt->i915) < 11)
> + return;
> +
> + /*
> + * On newer platforms the fusing register is called 'enable' and has
> + * enable semantics, while on older platforms it is called 'disable'
> + * and bits have disable semantices.
> + */
> + media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> + media_fuse = ~media_fuse;
> +
> + vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> + vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> + GEN11_GT_VEBOX_DISABLE_SHIFT;
> +
> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> + fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
> + gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> + } else {
> + gt->info.sfc_mask = ~0;
> + }
> +
> + for (i = 0; i < I915_MAX_VCS; i++) {
> + if (!HAS_ENGINE(gt, _VCS(i))) {
> + vdbox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vdbox_mask)) {
> + gt->info.engine_mask &= ~BIT(_VCS(i));
> + drm_dbg(&i915->drm, "vcs%u fused off\n", i);
> + continue;
> + }
> +
> + if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
> + gt->info.vdbox_sfc_access |= BIT(i);
> + logical_vdbox++;
> + }
> + drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> + vdbox_mask, VDBOX_MASK(gt));
> + GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
> +
> + for (i = 0; i < I915_MAX_VECS; i++) {
> + if (!HAS_ENGINE(gt, _VECS(i))) {
> + vebox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vebox_mask)) {
> + gt->info.engine_mask &= ~BIT(_VECS(i));
> + drm_dbg(&i915->drm, "vecs%u fused off\n", i);
> + }
> + }
> + drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
> + vebox_mask, VEBOX_MASK(gt));
> + GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> +}
> +
> static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -673,6 +741,9 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> unsigned long ccs_mask;
> unsigned int i;
>
> + if (GRAPHICS_VER(i915) < 11)
> + return;
> +
> if (hweight32(CCS_MASK(gt)) <= 1)
> return;
>
> @@ -730,73 +801,10 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> struct intel_gt_info *info = >->info;
> - struct intel_uncore *uncore = gt->uncore;
> - unsigned int logical_vdbox = 0;
> - unsigned int i;
> - u32 media_fuse, fuse1;
> - u16 vdbox_mask;
> - u16 vebox_mask;
>
> info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
>
> - if (GRAPHICS_VER(i915) < 11)
> - return info->engine_mask;
> -
> - /*
> - * On newer platforms the fusing register is called 'enable' and has
> - * enable semantics, while on older platforms it is called 'disable'
> - * and bits have disable semantices.
> - */
> - media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> - if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> - media_fuse = ~media_fuse;
> -
> - vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> - vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> - GEN11_GT_VEBOX_DISABLE_SHIFT;
> -
> - if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> - fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
> - gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> - } else {
> - gt->info.sfc_mask = ~0;
> - }
> -
> - for (i = 0; i < I915_MAX_VCS; i++) {
> - if (!HAS_ENGINE(gt, _VCS(i))) {
> - vdbox_mask &= ~BIT(i);
> - continue;
> - }
> -
> - if (!(BIT(i) & vdbox_mask)) {
> - info->engine_mask &= ~BIT(_VCS(i));
> - drm_dbg(&i915->drm, "vcs%u fused off\n", i);
> - continue;
> - }
> -
> - if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
> - gt->info.vdbox_sfc_access |= BIT(i);
> - logical_vdbox++;
> - }
> - drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> - vdbox_mask, VDBOX_MASK(gt));
> - GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
> -
> - for (i = 0; i < I915_MAX_VECS; i++) {
> - if (!HAS_ENGINE(gt, _VECS(i))) {
> - vebox_mask &= ~BIT(i);
> - continue;
> - }
> -
> - if (!(BIT(i) & vebox_mask)) {
> - info->engine_mask &= ~BIT(_VECS(i));
> - drm_dbg(&i915->drm, "vecs%u fused off\n", i);
> - }
> - }
> - drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
> - vebox_mask, VEBOX_MASK(gt));
> - GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> -
> + engine_mask_apply_media_fuses(gt);
> engine_mask_apply_compute_fuses(gt);
> engine_mask_apply_copy_fuses(gt);
>
> --
> 2.37.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
2022-09-07 22:18 ` [Intel-gfx] " Matt Roper
@ 2022-09-07 22:22 ` Lucas De Marchi
-1 siblings, 0 replies; 12+ messages in thread
From: Lucas De Marchi @ 2022-09-07 22:22 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 03:18:00PM -0700, Matt Roper wrote:
>On Wed, Sep 07, 2022 at 01:39:10PM -0700, Lucas De Marchi wrote:
>> Check for media IP version instead of graphics since this is figuring
>> out the media engines' configuration. Currently the only platform with
>> non-matching graphics/media version is Meteor Lake: update the check in
>> gen11_vdbox_has_sfc() so it considers not only version 12, but also any
>> later version which then includes that platform.
>>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++++++-----
>> 1 file changed, 6 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 275ad72940c1..5cddee7c2f1d 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
>> */
>> if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
>> return false;
>> - else if (GRAPHICS_VER(i915) == 12)
>> + else if (MEDIA_VER(i915) >= 12)
>> return (physical_vdbox % 2 == 0) ||
>> !(BIT(physical_vdbox - 1) & vdbox_mask);
>> - else if (GRAPHICS_VER(i915) == 11)
>> + else if (MEDIA_VER(i915) == 11)
>> return logical_vdbox % 2 == 0;
>>
>> - MISSING_CASE(GRAPHICS_VER(i915));
>> + MISSING_CASE(MEDIA_VER(i915));
>
>Do we even still need the MISSING_CASE given that we now have an
>open-ended upper bound above and this is a "gen11" function that doesn't
>get called at all on old platforms?
>
>Personally I'd axe it, but up to you. Either way,
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
yeah, I will remove it
thanks
Lucas De Marchi
>
>> +
>> return false;
>> }
>>
>> @@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>> * and bits have disable semantices.
>> */
>> media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
>> - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
>> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
>> media_fuse = ~media_fuse;
>>
>> vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
>> vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
>> GEN11_GT_VEBOX_DISABLE_SHIFT;
>>
>> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
>> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
>> fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
>> gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
>> } else {
>> --
>> 2.37.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
@ 2022-09-07 22:22 ` Lucas De Marchi
0 siblings, 0 replies; 12+ messages in thread
From: Lucas De Marchi @ 2022-09-07 22:22 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 03:18:00PM -0700, Matt Roper wrote:
>On Wed, Sep 07, 2022 at 01:39:10PM -0700, Lucas De Marchi wrote:
>> Check for media IP version instead of graphics since this is figuring
>> out the media engines' configuration. Currently the only platform with
>> non-matching graphics/media version is Meteor Lake: update the check in
>> gen11_vdbox_has_sfc() so it considers not only version 12, but also any
>> later version which then includes that platform.
>>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++++++-----
>> 1 file changed, 6 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 275ad72940c1..5cddee7c2f1d 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
>> */
>> if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
>> return false;
>> - else if (GRAPHICS_VER(i915) == 12)
>> + else if (MEDIA_VER(i915) >= 12)
>> return (physical_vdbox % 2 == 0) ||
>> !(BIT(physical_vdbox - 1) & vdbox_mask);
>> - else if (GRAPHICS_VER(i915) == 11)
>> + else if (MEDIA_VER(i915) == 11)
>> return logical_vdbox % 2 == 0;
>>
>> - MISSING_CASE(GRAPHICS_VER(i915));
>> + MISSING_CASE(MEDIA_VER(i915));
>
>Do we even still need the MISSING_CASE given that we now have an
>open-ended upper bound above and this is a "gen11" function that doesn't
>get called at all on old platforms?
>
>Personally I'd axe it, but up to you. Either way,
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
yeah, I will remove it
thanks
Lucas De Marchi
>
>> +
>> return false;
>> }
>>
>> @@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>> * and bits have disable semantices.
>> */
>> media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
>> - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
>> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
>> media_fuse = ~media_fuse;
>>
>> vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
>> vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
>> GEN11_GT_VEBOX_DISABLE_SHIFT;
>>
>> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
>> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
>> fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
>> gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
>> } else {
>> --
>> 2.37.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
2022-09-07 20:39 ` [Intel-gfx] " Lucas De Marchi
` (3 preceding siblings ...)
(?)
@ 2022-09-08 4:22 ` Patchwork
-1 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-09-08 4:22 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 27172 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
URL : https://patchwork.freedesktop.org/series/108269/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12090_full -> Patchwork_108269v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_108269v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108269v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108269v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-tglb2/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-tglb3/igt@i915_module_load@reload-with-fault-injection.html
Known issues
------------
Here are the changes found in Patchwork_108269v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-2x:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#1839])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@feature_discovery@display-2x.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525]) +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb4/igt@gem_exec_balancer@parallel-out-fence.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb7/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_capture@capture-recoverable:
- shard-iclb: NOTRUN -> [SKIP][6] ([i915#6344])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2846])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk2/igt@gem_exec_fair@basic-deadline.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-glk7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_suspend@basic-s3@smem:
- shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl1/igt@gem_exec_suspend@basic-s3@smem.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl8/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_lmem_swapping@verify-random:
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl1/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][18] ([i915#2658])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl6/igt@gem_pread@exhaustion.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_userptr_blits@vma-merge:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#3318])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#2856])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@gen9_exec_parse@batch-without-end.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][22] -> [INCOMPLETE][23] ([i915#3921])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-snb2/igt@i915_selftest@live@hangcheck.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-snb5/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][24] ([i915#5286])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][25] ([fdo#110725] / [fdo#111614])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][26] ([fdo#110723])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_joiner@basic:
- shard-iclb: NOTRUN -> [SKIP][27] ([i915#2705])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
- shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271]) +122 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl6/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109278] / [i915#3886]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3886]) +3 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl1/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-random-ccs-data-4_tiled_dg2_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109278]) +4 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_ccs@pipe-d-random-ccs-data-4_tiled_dg2_mc_ccs.html
* igt@kms_chamelium@dp-crc-fast:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109284] / [fdo#111827])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-frame-dump:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl1/igt@kms_chamelium@dp-frame-dump.html
* igt@kms_content_protection@lic:
- shard-iclb: NOTRUN -> [SKIP][34] ([fdo#109300] / [fdo#111066])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_content_protection@lic.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [PASS][35] -> [FAIL][36] ([i915#2346]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109274])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][38] ([i915#2672]) +5 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][39] ([i915#3555])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][40] ([i915#2672] / [i915#3555])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][41] ([fdo#109280]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][42] ([fdo#108145] / [i915#265])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
- shard-iclb: [PASS][43] -> [SKIP][44] ([i915#5176]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb5/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-edp-1:
- shard-iclb: NOTRUN -> [SKIP][45] ([i915#5176]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-edp-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#658]) +2 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#111068] / [i915#658])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109441])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@kms_psr@psr2_primary_render.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][49] -> [SKIP][50] ([fdo#109441]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglb: [PASS][51] -> [SKIP][52] ([i915#5519])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-tglb3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-tglb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@prime_nv_api@i915_nv_import_vs_close:
- shard-iclb: NOTRUN -> [SKIP][53] ([fdo#109291])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@prime_nv_api@i915_nv_import_vs_close.html
* igt@prime_vgem@fence-flip-hang:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109295])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@prime_vgem@fence-flip-hang.html
* igt@sysfs_clients@fair-3:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2994]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl6/igt@sysfs_clients@fair-3.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-close-race:
- shard-iclb: [INCOMPLETE][56] -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb1/igt@gem_ctx_exec@basic-close-race.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@gem_ctx_exec@basic-close-race.html
* igt@gem_eio@kms:
- shard-tglb: [FAIL][58] ([i915#5784]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-tglb5/igt@gem_eio@kms.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-tglb7/igt@gem_eio@kms.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [SKIP][60] ([i915#4525]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb7/igt@gem_exec_balancer@parallel-bb-first.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [FAIL][62] ([i915#2842]) -> [PASS][63] +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-tglb6/igt@gem_exec_fair@basic-none-share@rcs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-tglb6/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][64] ([i915#2842]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl8/igt@gem_exec_fair@basic-none-solo@rcs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-tglu}: [FAIL][66] ([i915#2842]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-tglu-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][68] ([i915#2190]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-tglb5/igt@gem_huc_copy@huc-copy.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [DMESG-WARN][70] ([i915#5566] / [i915#716]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk6/igt@gen9_exec_parse@allowed-single.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-glk3/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][72] ([i915#454]) -> [PASS][73] +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb4/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][74] ([i915#79]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-iclb: [DMESG-WARN][76] ([i915#2867]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb5/igt@kms_flip@flip-vs-suspend@c-edp1.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb1/igt@kms_flip@flip-vs-suspend@c-edp1.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][78] ([fdo#109441]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_cpu.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglb: [SKIP][80] ([i915#5519]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-tglb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-tglb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_sequence@get-forked@edp-1-pipe-a:
- shard-iclb: [DMESG-WARN][82] ([i915#4391]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb7/igt@kms_sequence@get-forked@edp-1-pipe-a.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb2/igt@kms_sequence@get-forked@edp-1-pipe-a.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][84] ([i915#180]) -> [PASS][85] +3 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Warnings ####
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][86] ([i915#2920]) -> [SKIP][87] ([i915#658]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb5/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-iclb: [SKIP][88] ([i915#658]) -> [SKIP][89] ([i915#2920])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb5/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-iclb: [SKIP][90] ([fdo#111068] / [i915#658]) -> [SKIP][91] ([i915#2920])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12090 -> Patchwork_108269v1
CI-20190529: 20190529
CI_DRM_12090: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108269v1: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/index.html
[-- Attachment #2: Type: text/html, Size: 28689 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-09-08 4:22 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-07 20:39 [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses Lucas De Marchi
2022-09-07 20:39 ` [Intel-gfx] " Lucas De Marchi
2022-09-07 20:39 ` [PATCH 2/2] drm/i915/gt: Extract function to apply " Lucas De Marchi
2022-09-07 20:39 ` [Intel-gfx] " Lucas De Marchi
2022-09-07 22:20 ` Matt Roper
2022-09-07 22:20 ` [Intel-gfx] " Matt Roper
2022-09-07 21:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Use MEDIA_VER() when handling " Patchwork
2022-09-07 22:18 ` [PATCH 1/2] " Matt Roper
2022-09-07 22:18 ` [Intel-gfx] " Matt Roper
2022-09-07 22:22 ` Lucas De Marchi
2022-09-07 22:22 ` [Intel-gfx] " Lucas De Marchi
2022-09-08 4:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
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