* [igt-dev] [PATCH i-g-t v6 1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine
@ 2022-09-12 18:15 Adrian Larumbe
2022-09-12 18:15 ` [igt-dev] [PATCH i-g-t v6 2/2] i915/gem_ctx_isolation:: change semantics of ctx isolation uAPI Adrian Larumbe
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Adrian Larumbe @ 2022-09-12 18:15 UTC (permalink / raw)
To: petri.latvala, kamil.konieczny, igt-dev; +Cc: adrian.larumbe
Remove local compute engine definition as it was already synchronised into
include/drm-uapi/i915_drm.h from the kernel sources in a past commit.
Signed-off-by: Adrian Larumbe <adrian.larumbe@collabora.com>
---
lib/i915/i915_drm_local.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index ac35abf6af76..696e5aa05048 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -19,8 +19,6 @@ extern "C" {
* or local_ prefix and without any #ifndef's. Attempt should be made to
* clean these up when kernel uapi headers are sync'd.
*/
-#define I915_ENGINE_CLASS_COMPUTE 4
-
#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
/*
--
2.37.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] [PATCH i-g-t v6 2/2] i915/gem_ctx_isolation:: change semantics of ctx isolation uAPI
2022-09-12 18:15 [igt-dev] [PATCH i-g-t v6 1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine Adrian Larumbe
@ 2022-09-12 18:15 ` Adrian Larumbe
2022-09-14 19:54 ` Kamil Konieczny
2022-09-12 19:20 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,v6,1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine Patchwork
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Adrian Larumbe @ 2022-09-12 18:15 UTC (permalink / raw)
To: petri.latvala, kamil.konieczny, igt-dev; +Cc: adrian.larumbe
ioctl I915_PARAM_HAS_CONTEXT_ISOLATION param is meant to report whether all
the engines in the system support context isolation, but the way the return
value was being used did not respect the contract on the uAPI.
Skip all engine tests for which context isolation is not supported. Also
skip tests that involve an engine reset if both RCS and CCS engines are
present in the system. This is because they belong to the same reset
domain.
Signed-off-by: Adrian Larumbe <adrian.larumbe@collabora.com>
---
tests/i915/gem_ctx_isolation.c | 109 ++++++++++++++++++++++++---------
1 file changed, 80 insertions(+), 29 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 95d13969fa61..36afbaf74b64 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -45,6 +45,7 @@ enum {
VCS2 = ENGINE(I915_ENGINE_CLASS_VIDEO, 2),
VCS3 = ENGINE(I915_ENGINE_CLASS_VIDEO, 3),
VECS0 = ENGINE(I915_ENGINE_CLASS_VIDEO_ENHANCE, 0),
+ CCS0 = ENGINE(I915_ENGINE_CLASS_COMPUTE, 0),
};
#define ALL ~0u
@@ -164,6 +165,8 @@ static const struct named_register {
{ "xCS_GPR", GEN9, ALL, 0x600, 32, .relative = true },
+ /* TODO: add CCS0 registers */
+
{}
}, ignore_registers[] = {
{ "RCS timestamp", GEN6, ~0u, 0x2358 },
@@ -625,9 +628,40 @@ static void compare_regs(int fd, const struct intel_execution_engine2 *e,
num_errors, who);
}
+static bool
+engine_has_context_isolation(const struct intel_execution_engine2 *e,
+ int gen)
+{
+ if (gen > 8)
+ return true;
+
+ if (gen >= 6 && gen <= 8 && e->class == I915_ENGINE_CLASS_RENDER)
+ return true;
+
+ return false;
+}
+
+static bool
+has_engine_class(const intel_ctx_cfg_t *cfg, unsigned int class)
+{
+ const struct i915_engine_class_instance *eci;
+ unsigned int i;
+
+ igt_require(class <= I915_ENGINE_CLASS_COMPUTE);
+
+ for (i = 0; i < cfg->num_engines; i++) {
+ eci = &cfg->engines[i];
+ if (eci->engine_class == class)
+ return true;
+ }
+
+ return false;
+}
+
static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
const struct intel_execution_engine2 *e,
- unsigned int flags)
+ unsigned int flags,
+ int gen)
{
static const uint32_t values[] = {
0x0,
@@ -645,6 +679,7 @@ static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
/* Sigh -- hsw: we need cmdparser access to our own registers! */
igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
+ igt_require(engine_has_context_isolation(e, gen));
gem_quiescent_gpu(fd);
@@ -727,7 +762,8 @@ static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
static void isolation(int fd, const intel_ctx_cfg_t *cfg,
const struct intel_execution_engine2 *e,
- unsigned int flags)
+ unsigned int flags,
+ int gen)
{
static const uint32_t values[] = {
0x0,
@@ -741,6 +777,8 @@ static void isolation(int fd, const intel_ctx_cfg_t *cfg,
unsigned int num_values =
flags & (DIRTY1 | DIRTY2) ? ARRAY_SIZE(values) : 1;
+ igt_require(engine_has_context_isolation(e, gen));
+
gem_quiescent_gpu(fd);
for (int v = 0; v < num_values; v++) {
@@ -863,7 +901,8 @@ static void inject_reset_context(int fd, const intel_ctx_cfg_t *cfg,
static void preservation(int fd, const intel_ctx_cfg_t *cfg,
const struct intel_execution_engine2 *e,
- unsigned int flags)
+ unsigned int flags,
+ int gen)
{
static const uint32_t values[] = {
0x0,
@@ -880,6 +919,8 @@ static void preservation(int fd, const intel_ctx_cfg_t *cfg,
uint64_t ahnd[num_values + 1];
igt_spin_t *spin;
+ igt_require(engine_has_context_isolation(e, gen));
+
gem_quiescent_gpu(fd);
ctx[num_values] = intel_ctx_create(fd, cfg);
@@ -900,8 +941,19 @@ static void preservation(int fd, const intel_ctx_cfg_t *cfg,
gem_close(fd, read_regs(fd, ahnd[num_values], ctx[num_values], e, flags));
igt_spin_free(fd, spin);
- if (flags & RESET)
+ if (flags & RESET) {
+ /*
+ * TODO: handle this differently if CSS and RCS ever became
+ * part of different reset domains
+ */
+ igt_skip_on_f(has_engine_class(cfg, I915_ENGINE_CLASS_RENDER) &&
+ has_engine_class(cfg, I915_ENGINE_CLASS_COMPUTE),
+ "Both render and compute types of engines are present on the HW. \
+ Skipping test because architecturally we don't make cross engine \
+ isolation guarantees on those.\n");
+
inject_reset_context(fd, cfg, e);
+ }
switch (flags & SLEEP_MASK) {
case NOSLEEP:
@@ -960,7 +1012,7 @@ static unsigned int __has_context_isolation(int fd)
int value = 0;
memset(&gp, 0, sizeof(gp));
- gp.param = 50; /* I915_PARAM_HAS_CONTEXT_ISOLATION */
+ gp.param = I915_PARAM_HAS_CONTEXT_ISOLATION;
gp.value = &value;
igt_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
@@ -969,21 +1021,19 @@ static unsigned int __has_context_isolation(int fd)
return value;
}
-#define test_each_engine(e, i915, cfg, mask) \
+#define test_each_engine(e, i915, cfg) \
for_each_ctx_cfg_engine(i915, cfg, e) \
- for_each_if(mask & (1 << (e)->class)) \
- igt_dynamic_f("%s", (e)->name)
+ igt_dynamic_f("%s", (e)->name)
igt_main
{
- unsigned int has_context_isolation = 0;
+ bool has_context_isolation = 0;
const struct intel_execution_engine2 *e;
intel_ctx_cfg_t cfg;
int i915 = -1;
+ int gen;
igt_fixture {
- int gen;
-
i915 = drm_open_driver(DRIVER_INTEL);
igt_require_gem(i915);
igt_require(gem_has_contexts(i915));
@@ -993,6 +1043,7 @@ igt_main
igt_require(has_context_isolation);
gen = intel_gen(intel_get_drm_devid(i915));
+ igt_require(gen >= 2);
igt_warn_on_f(gen > LAST_KNOWN_GEN,
"GEN not recognized! Test needs to be updated to run.\n");
@@ -1004,43 +1055,43 @@ igt_main
}
igt_subtest_with_dynamic("nonpriv") {
- test_each_engine(e, i915, &cfg, has_context_isolation)
- nonpriv(i915, &cfg, e, 0);
+ test_each_engine(e, i915, &cfg)
+ nonpriv(i915, &cfg, e, 0, gen);
}
igt_subtest_with_dynamic("nonpriv-switch") {
- test_each_engine(e, i915, &cfg, has_context_isolation)
- nonpriv(i915, &cfg, e, DIRTY2);
+ test_each_engine(e, i915, &cfg)
+ nonpriv(i915, &cfg, e, DIRTY2, gen);
}
igt_subtest_with_dynamic("clean") {
- test_each_engine(e, i915, &cfg, has_context_isolation)
- isolation(i915, &cfg, e, 0);
+ test_each_engine(e, i915, &cfg)
+ isolation(i915, &cfg, e, 0, gen);
}
igt_subtest_with_dynamic("dirty-create") {
- test_each_engine(e, i915, &cfg, has_context_isolation)
- isolation(i915, &cfg, e, DIRTY1);
+ test_each_engine(e, i915, &cfg)
+ isolation(i915, &cfg, e, DIRTY1, gen);
}
igt_subtest_with_dynamic("dirty-switch") {
- test_each_engine(e, i915, &cfg, has_context_isolation)
- isolation(i915, &cfg, e, DIRTY2);
+ test_each_engine(e, i915, &cfg)
+ isolation(i915, &cfg, e, DIRTY2, gen);
}
igt_subtest_with_dynamic("preservation") {
- test_each_engine(e, i915, &cfg, has_context_isolation)
- preservation(i915, &cfg, e, 0);
+ test_each_engine(e, i915, &cfg)
+ preservation(i915, &cfg, e, 0, gen);
}
igt_subtest_with_dynamic("preservation-S3") {
- test_each_engine(e, i915, &cfg, has_context_isolation)
- preservation(i915, &cfg, e, S3);
+ test_each_engine(e, i915, &cfg)
+ preservation(i915, &cfg, e, S3, gen);
}
igt_subtest_with_dynamic("preservation-S4") {
- test_each_engine(e, i915, &cfg, has_context_isolation)
- preservation(i915, &cfg, e, S4);
+ test_each_engine(e, i915, &cfg)
+ preservation(i915, &cfg, e, S4, gen);
}
igt_fixture {
@@ -1050,8 +1101,8 @@ igt_main
igt_subtest_with_dynamic("preservation-reset") {
igt_hang_t hang = igt_allow_hang(i915, 0, 0);
- test_each_engine(e, i915, &cfg, has_context_isolation)
- preservation(i915, &cfg, e, RESET);
+ test_each_engine(e, i915, &cfg)
+ preservation(i915, &cfg, e, RESET, gen);
igt_disallow_hang(i915, hang);
}
--
2.37.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,v6,1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine
2022-09-12 18:15 [igt-dev] [PATCH i-g-t v6 1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine Adrian Larumbe
2022-09-12 18:15 ` [igt-dev] [PATCH i-g-t v6 2/2] i915/gem_ctx_isolation:: change semantics of ctx isolation uAPI Adrian Larumbe
@ 2022-09-12 19:20 ` Patchwork
2022-09-13 0:07 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-14 19:29 ` [igt-dev] [PATCH i-g-t v6 1/2] " Kamil Konieczny
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-09-12 19:20 UTC (permalink / raw)
To: Adrian Larumbe; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 3815 bytes --]
== Series Details ==
Series: series starting with [i-g-t,v6,1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine
URL : https://patchwork.freedesktop.org/series/108458/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12123 -> IGTPW_7771
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/index.html
Participating hosts (42 -> 39)
------------------------------
Missing (3): fi-ctg-p8600 bat-rpls-2 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_7771:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/bat-rpls-1/igt@i915_selftest@live@reset.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/bat-rpls-1/igt@i915_selftest@live@reset.html
Known issues
------------
Here are the changes found in IGTPW_7771 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][3] -> [INCOMPLETE][4] ([i915#4785])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][5] -> [DMESG-FAIL][6] ([i915#4528])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/fi-blb-e6850/igt@i915_selftest@live@requests.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#4312] / [i915#5594] / [i915#6246])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/fi-hsw-4770/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][8] ([i915#4494] / [i915#4957]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
[i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6650 -> IGTPW_7771
CI-20190529: 20190529
CI_DRM_12123: 5dd153b15e2e3198fca3d84db9e155f454645f91 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7771: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/index.html
IGT_6650: f7aff600ab16d6405f0704b1743d2b7909715752 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/index.html
[-- Attachment #2: Type: text/html, Size: 4453 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,v6,1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine
2022-09-12 18:15 [igt-dev] [PATCH i-g-t v6 1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine Adrian Larumbe
2022-09-12 18:15 ` [igt-dev] [PATCH i-g-t v6 2/2] i915/gem_ctx_isolation:: change semantics of ctx isolation uAPI Adrian Larumbe
2022-09-12 19:20 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,v6,1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine Patchwork
@ 2022-09-13 0:07 ` Patchwork
2022-09-14 19:29 ` [igt-dev] [PATCH i-g-t v6 1/2] " Kamil Konieczny
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-09-13 0:07 UTC (permalink / raw)
To: Adrian Larumbe; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 28276 bytes --]
== Series Details ==
Series: series starting with [i-g-t,v6,1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine
URL : https://patchwork.freedesktop.org/series/108458/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12123_full -> IGTPW_7771_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_7771_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_7771_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/index.html
Participating hosts (11 -> 7)
------------------------------
Missing (4): pig-skl-6260u pig-kbl-iris shard-rkl pig-glk-j5005
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_7771_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@basic-flip-before-cursor@atomic:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb7/igt@kms_cursor_legacy@basic-flip-before-cursor@atomic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb3/igt@kms_cursor_legacy@basic-flip-before-cursor@atomic.html
Known issues
------------
Here are the changes found in IGTPW_7771_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-reset@vcs0:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271]) +44 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-snb7/igt@gem_ctx_isolation@preservation-reset@vcs0.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-tglb5/igt@gem_eio@in-flight-contexts-10ms.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb2/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@kms:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#5784])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-tglb7/igt@gem_eio@kms.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb2/igt@gem_eio@kms.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb4/igt@gem_exec_balancer@parallel-keep-in-fence.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb7/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#2190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl4/igt@gem_huc_copy@huc-copy.html
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-glk8/igt@gem_huc_copy@huc-copy.html
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#2190])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- shard-tglb: NOTRUN -> [SKIP][16] ([i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb6/igt@gem_lmem_swapping@random-engines.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][17] ([i915#2658])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-snb5/igt@gem_pread@exhaustion.html
* igt@gem_pxp@fail-invalid-protected-context:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#4270])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb7/igt@gem_pxp@fail-invalid-protected-context.html
* igt@gen9_exec_parse@bb-large:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#2527] / [i915#2856])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb6/igt@gen9_exec_parse@bb-large.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#1769] / [i915#3555])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#1769] / [i915#3555])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-180:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#5286])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb5/igt@kms_big_fb@4-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-90:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271]) +38 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl1/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][24] ([i915#3689] / [i915#3886])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb2/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc:
- shard-tglb: NOTRUN -> [SKIP][25] ([i915#6095])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb1/igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html
- shard-iclb: NOTRUN -> [SKIP][26] ([fdo#109278])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb6/igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_rc_ccs_cc:
- shard-tglb: NOTRUN -> [SKIP][27] ([i915#3689] / [i915#6095])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb5/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][28] ([fdo#111615] / [i915#3689])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb1/igt@kms_ccs@pipe-c-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl2/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#3689]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb2/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html
* igt@kms_chamelium@hdmi-crc-single:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl3/igt@kms_chamelium@hdmi-crc-single.html
* igt@kms_content_protection@content_type_change:
- shard-tglb: NOTRUN -> [SKIP][32] ([i915#1063])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb1/igt@kms_content_protection@content_type_change.html
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109300] / [fdo#111066])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb6/igt@kms_content_protection@content_type_change.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-tglb: NOTRUN -> [SKIP][34] ([fdo#109274] / [fdo#111825])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][35] -> [FAIL][36] ([i915#4767])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109274]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-tglb: NOTRUN -> [SKIP][38] ([fdo#109274] / [fdo#111825] / [i915#3637]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-apl: [PASS][39] -> [DMESG-WARN][40] ([i915#180]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-apl3/igt@kms_flip@flip-vs-suspend@b-dp1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl3/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#3555]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][42] ([i915#2587] / [i915#2672]) +3 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][43] ([i915#2672]) +6 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#109280] / [fdo#111825]) +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#6497])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move:
- shard-glk: NOTRUN -> [SKIP][46] ([fdo#109271]) +6 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-glk9/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move.html
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109280]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move.html
* igt@kms_plane_lowres@tiling-4:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#112054] / [i915#5288])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb6/igt@kms_plane_lowres@tiling-4.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-d-edp-1:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#5176]) +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-d-edp-1.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][50] -> [SKIP][51] ([fdo#109441])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#2530])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb3/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html
* igt@perf@polling-parameterized:
- shard-tglb: [PASS][53] -> [FAIL][54] ([i915#5639])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-tglb5/igt@perf@polling-parameterized.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb2/igt@perf@polling-parameterized.html
* igt@prime_nv_pcopy@test3_1:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#109291])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb6/igt@prime_nv_pcopy@test3_1.html
- shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109291])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb4/igt@prime_nv_pcopy@test3_1.html
* igt@sysfs_clients@sema-25:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#2994])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl1/igt@sysfs_clients@sema-25.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-close-race:
- shard-iclb: [INCOMPLETE][58] -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb6/igt@gem_ctx_exec@basic-close-race.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb5/igt@gem_ctx_exec@basic-close-race.html
* igt@gem_exec_balancer@parallel:
- shard-iclb: [SKIP][60] ([i915#4525]) -> [PASS][61] +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb6/igt@gem_exec_balancer@parallel.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb2/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][62] ([i915#2842]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-apl8/igt@gem_exec_fair@basic-none-solo@rcs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][64] ([i915#2842]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [INCOMPLETE][66] ([i915#6775]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-tglb3/igt@i915_module_load@reload-with-fault-injection.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-tglb6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@live@sanitycheck:
- shard-snb: [SKIP][68] ([fdo#109271]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-snb6/igt@i915_selftest@live@sanitycheck.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-snb5/igt@i915_selftest@live@sanitycheck.html
* igt@kms_frontbuffer_tracking@psr-slowdraw:
- shard-iclb: [FAIL][70] ([i915#1888] / [i915#2546]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb1/igt@kms_frontbuffer_tracking@psr-slowdraw.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb2/igt@kms_frontbuffer_tracking@psr-slowdraw.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][72] ([fdo#109441]) -> [PASS][73] +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@perf@polling-parameterized:
- shard-glk: [FAIL][74] ([i915#5639]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk1/igt@perf@polling-parameterized.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-glk3/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][76] ([i915#4525]) -> [FAIL][77] ([i915#6117])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb7/igt@gem_exec_balancer@parallel-ordering.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][78] ([i915#588]) -> [SKIP][79] ([i915#658])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-glk: [SKIP][80] ([fdo#109271]) -> [SKIP][81] ([fdo#109271] / [i915#1888])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][82] ([i915#2920]) -> [SKIP][83] ([i915#658])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb3/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][84] ([i915#658]) -> [SKIP][85] ([i915#2920])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb5/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][86] ([i915#2920]) -> [SKIP][87] ([fdo#111068] / [i915#658])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][88] ([fdo#111068] / [i915#658]) -> [SKIP][89] ([i915#2920])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [FAIL][90] ([i915#5939]) -> [SKIP][91] ([fdo#109642] / [fdo#111068] / [i915#658])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-iclb4/igt@kms_psr2_su@page_flip-nv12.html
* igt@runner@aborted:
- shard-apl: ([FAIL][92], [FAIL][93], [FAIL][94]) ([fdo#109271] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-apl8/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-apl2/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12123/shard-apl7/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl7/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl3/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl7/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl3/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/shard-apl3/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#6775]: https://gitlab.freedesktop.org/drm/intel/issues/6775
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6650 -> IGTPW_7771
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12123: 5dd153b15e2e3198fca3d84db9e155f454645f91 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7771: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/index.html
IGT_6650: f7aff600ab16d6405f0704b1743d2b7909715752 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7771/index.html
[-- Attachment #2: Type: text/html, Size: 31995 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v6 1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine
2022-09-12 18:15 [igt-dev] [PATCH i-g-t v6 1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine Adrian Larumbe
` (2 preceding siblings ...)
2022-09-13 0:07 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-09-14 19:29 ` Kamil Konieczny
3 siblings, 0 replies; 8+ messages in thread
From: Kamil Konieczny @ 2022-09-14 19:29 UTC (permalink / raw)
To: igt-dev; +Cc: adrian.larumbe, petri.latvala
Hi,
On 2022-09-12 at 19:15:51 +0100, Adrian Larumbe wrote:
> Remove local compute engine definition as it was already synchronised into
> include/drm-uapi/i915_drm.h from the kernel sources in a past commit.
>
> Signed-off-by: Adrian Larumbe <adrian.larumbe@collabora.com>
imho you can still add r-b from Petri.
Regards,
Kamil
> ---
> lib/i915/i915_drm_local.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
> index ac35abf6af76..696e5aa05048 100644
> --- a/lib/i915/i915_drm_local.h
> +++ b/lib/i915/i915_drm_local.h
> @@ -19,8 +19,6 @@ extern "C" {
> * or local_ prefix and without any #ifndef's. Attempt should be made to
> * clean these up when kernel uapi headers are sync'd.
> */
> -#define I915_ENGINE_CLASS_COMPUTE 4
> -
> #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
>
> /*
> --
> 2.37.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v6 2/2] i915/gem_ctx_isolation:: change semantics of ctx isolation uAPI
2022-09-12 18:15 ` [igt-dev] [PATCH i-g-t v6 2/2] i915/gem_ctx_isolation:: change semantics of ctx isolation uAPI Adrian Larumbe
@ 2022-09-14 19:54 ` Kamil Konieczny
2022-09-19 7:18 ` Adrian Larumbe
2022-10-19 14:05 ` Adrian Larumbe
0 siblings, 2 replies; 8+ messages in thread
From: Kamil Konieczny @ 2022-09-14 19:54 UTC (permalink / raw)
To: igt-dev; +Cc: Adrian Larumbe, Petri Latvala
Hi Adrian,
On 2022-09-12 at 19:15:52 +0100, Adrian Larumbe wrote:
> ioctl I915_PARAM_HAS_CONTEXT_ISOLATION param is meant to report whether all
> the engines in the system support context isolation, but the way the return
> value was being used did not respect the contract on the uAPI.
May you point (maybe in cover letter ?) to discussion on this
topic ? From I t found, the uAPI description was long, started
with boolean meaning, but then added that this is a bitflag.
It is a little confusing, so the question is: is it really
all users take it as boolean ?
>
> Skip all engine tests for which context isolation is not supported. Also
> skip tests that involve an engine reset if both RCS and CCS engines are
> present in the system. This is because they belong to the same reset
> domain.
This should be another patch itself as it is only for DG2, or
am I missing something ?
>
> Signed-off-by: Adrian Larumbe <adrian.larumbe@collabora.com>
> ---
> tests/i915/gem_ctx_isolation.c | 109 ++++++++++++++++++++++++---------
> 1 file changed, 80 insertions(+), 29 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index 95d13969fa61..36afbaf74b64 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -45,6 +45,7 @@ enum {
> VCS2 = ENGINE(I915_ENGINE_CLASS_VIDEO, 2),
> VCS3 = ENGINE(I915_ENGINE_CLASS_VIDEO, 3),
> VECS0 = ENGINE(I915_ENGINE_CLASS_VIDEO_ENHANCE, 0),
> + CCS0 = ENGINE(I915_ENGINE_CLASS_COMPUTE, 0),
> };
>
> #define ALL ~0u
> @@ -164,6 +165,8 @@ static const struct named_register {
>
> { "xCS_GPR", GEN9, ALL, 0x600, 32, .relative = true },
>
> + /* TODO: add CCS0 registers */
> +
> {}
> }, ignore_registers[] = {
> { "RCS timestamp", GEN6, ~0u, 0x2358 },
> @@ -625,9 +628,40 @@ static void compare_regs(int fd, const struct intel_execution_engine2 *e,
> num_errors, who);
> }
>
> +static bool
> +engine_has_context_isolation(const struct intel_execution_engine2 *e,
> + int gen)
> +{
> + if (gen > 8)
> + return true;
> +
> + if (gen >= 6 && gen <= 8 && e->class == I915_ENGINE_CLASS_RENDER)
> + return true;
> +
> + return false;
> +}
> +
> +static bool
> +has_engine_class(const intel_ctx_cfg_t *cfg, unsigned int class)
> +{
> + const struct i915_engine_class_instance *eci;
> + unsigned int i;
> +
> + igt_require(class <= I915_ENGINE_CLASS_COMPUTE);
> +
> + for (i = 0; i < cfg->num_engines; i++) {
> + eci = &cfg->engines[i];
> + if (eci->engine_class == class)
> + return true;
> + }
> +
> + return false;
> +}
> +
> static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
> const struct intel_execution_engine2 *e,
> - unsigned int flags)
> + unsigned int flags,
> + int gen)
Please drop this change, use fd for obtaining gen.
> {
> static const uint32_t values[] = {
> 0x0,
> @@ -645,6 +679,7 @@ static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
>
> /* Sigh -- hsw: we need cmdparser access to our own registers! */
> igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
> + igt_require(engine_has_context_isolation(e, gen));
--------------------------------------------------- ^
Use fd here for getting gen.
>
> gem_quiescent_gpu(fd);
>
> @@ -727,7 +762,8 @@ static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
>
> static void isolation(int fd, const intel_ctx_cfg_t *cfg,
> const struct intel_execution_engine2 *e,
> - unsigned int flags)
> + unsigned int flags,
> + int gen)
> {
> static const uint32_t values[] = {
> 0x0,
> @@ -741,6 +777,8 @@ static void isolation(int fd, const intel_ctx_cfg_t *cfg,
> unsigned int num_values =
> flags & (DIRTY1 | DIRTY2) ? ARRAY_SIZE(values) : 1;
>
> + igt_require(engine_has_context_isolation(e, gen));
> +
> gem_quiescent_gpu(fd);
>
> for (int v = 0; v < num_values; v++) {
> @@ -863,7 +901,8 @@ static void inject_reset_context(int fd, const intel_ctx_cfg_t *cfg,
>
> static void preservation(int fd, const intel_ctx_cfg_t *cfg,
> const struct intel_execution_engine2 *e,
> - unsigned int flags)
> + unsigned int flags,
> + int gen)
> {
> static const uint32_t values[] = {
> 0x0,
> @@ -880,6 +919,8 @@ static void preservation(int fd, const intel_ctx_cfg_t *cfg,
> uint64_t ahnd[num_values + 1];
> igt_spin_t *spin;
>
> + igt_require(engine_has_context_isolation(e, gen));
> +
> gem_quiescent_gpu(fd);
>
> ctx[num_values] = intel_ctx_create(fd, cfg);
> @@ -900,8 +941,19 @@ static void preservation(int fd, const intel_ctx_cfg_t *cfg,
> gem_close(fd, read_regs(fd, ahnd[num_values], ctx[num_values], e, flags));
> igt_spin_free(fd, spin);
>
> - if (flags & RESET)
> + if (flags & RESET) {
> + /*
> + * TODO: handle this differently if CSS and RCS ever became
> + * part of different reset domains
> + */
> + igt_skip_on_f(has_engine_class(cfg, I915_ENGINE_CLASS_RENDER) &&
> + has_engine_class(cfg, I915_ENGINE_CLASS_COMPUTE),
> + "Both render and compute types of engines are present on the HW. \
> + Skipping test because architecturally we don't make cross engine \
> + isolation guarantees on those.\n");
> +
In comment you write about reset domain, yet in skip comment
you added that there is no ctx isolation between these engine
classes, so maybe we should skip this test also for non-reset ?
If you want to keep it for reset as is, change message
accordingly.
> inject_reset_context(fd, cfg, e);
> + }
>
> switch (flags & SLEEP_MASK) {
> case NOSLEEP:
> @@ -960,7 +1012,7 @@ static unsigned int __has_context_isolation(int fd)
> int value = 0;
>
> memset(&gp, 0, sizeof(gp));
> - gp.param = 50; /* I915_PARAM_HAS_CONTEXT_ISOLATION */
> + gp.param = I915_PARAM_HAS_CONTEXT_ISOLATION;
> gp.value = &value;
>
> igt_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
> @@ -969,21 +1021,19 @@ static unsigned int __has_context_isolation(int fd)
> return value;
> }
>
> -#define test_each_engine(e, i915, cfg, mask) \
> +#define test_each_engine(e, i915, cfg) \
> for_each_ctx_cfg_engine(i915, cfg, e) \
> - for_each_if(mask & (1 << (e)->class)) \
> - igt_dynamic_f("%s", (e)->name)
> + igt_dynamic_f("%s", (e)->name)
>
> igt_main
> {
> - unsigned int has_context_isolation = 0;
> + bool has_context_isolation = 0;
> const struct intel_execution_engine2 *e;
> intel_ctx_cfg_t cfg;
> int i915 = -1;
> + int gen;
------- ^
This should be unsigned.
Regards,
Kamil
>
> igt_fixture {
> - int gen;
> -
> i915 = drm_open_driver(DRIVER_INTEL);
> igt_require_gem(i915);
> igt_require(gem_has_contexts(i915));
> @@ -993,6 +1043,7 @@ igt_main
> igt_require(has_context_isolation);
>
> gen = intel_gen(intel_get_drm_devid(i915));
> + igt_require(gen >= 2);
>
> igt_warn_on_f(gen > LAST_KNOWN_GEN,
> "GEN not recognized! Test needs to be updated to run.\n");
> @@ -1004,43 +1055,43 @@ igt_main
> }
>
> igt_subtest_with_dynamic("nonpriv") {
> - test_each_engine(e, i915, &cfg, has_context_isolation)
> - nonpriv(i915, &cfg, e, 0);
> + test_each_engine(e, i915, &cfg)
> + nonpriv(i915, &cfg, e, 0, gen);
> }
>
> igt_subtest_with_dynamic("nonpriv-switch") {
> - test_each_engine(e, i915, &cfg, has_context_isolation)
> - nonpriv(i915, &cfg, e, DIRTY2);
> + test_each_engine(e, i915, &cfg)
> + nonpriv(i915, &cfg, e, DIRTY2, gen);
> }
>
> igt_subtest_with_dynamic("clean") {
> - test_each_engine(e, i915, &cfg, has_context_isolation)
> - isolation(i915, &cfg, e, 0);
> + test_each_engine(e, i915, &cfg)
> + isolation(i915, &cfg, e, 0, gen);
> }
>
> igt_subtest_with_dynamic("dirty-create") {
> - test_each_engine(e, i915, &cfg, has_context_isolation)
> - isolation(i915, &cfg, e, DIRTY1);
> + test_each_engine(e, i915, &cfg)
> + isolation(i915, &cfg, e, DIRTY1, gen);
> }
>
> igt_subtest_with_dynamic("dirty-switch") {
> - test_each_engine(e, i915, &cfg, has_context_isolation)
> - isolation(i915, &cfg, e, DIRTY2);
> + test_each_engine(e, i915, &cfg)
> + isolation(i915, &cfg, e, DIRTY2, gen);
> }
>
> igt_subtest_with_dynamic("preservation") {
> - test_each_engine(e, i915, &cfg, has_context_isolation)
> - preservation(i915, &cfg, e, 0);
> + test_each_engine(e, i915, &cfg)
> + preservation(i915, &cfg, e, 0, gen);
> }
>
> igt_subtest_with_dynamic("preservation-S3") {
> - test_each_engine(e, i915, &cfg, has_context_isolation)
> - preservation(i915, &cfg, e, S3);
> + test_each_engine(e, i915, &cfg)
> + preservation(i915, &cfg, e, S3, gen);
> }
>
> igt_subtest_with_dynamic("preservation-S4") {
> - test_each_engine(e, i915, &cfg, has_context_isolation)
> - preservation(i915, &cfg, e, S4);
> + test_each_engine(e, i915, &cfg)
> + preservation(i915, &cfg, e, S4, gen);
> }
>
> igt_fixture {
> @@ -1050,8 +1101,8 @@ igt_main
> igt_subtest_with_dynamic("preservation-reset") {
> igt_hang_t hang = igt_allow_hang(i915, 0, 0);
>
> - test_each_engine(e, i915, &cfg, has_context_isolation)
> - preservation(i915, &cfg, e, RESET);
> + test_each_engine(e, i915, &cfg)
> + preservation(i915, &cfg, e, RESET, gen);
>
> igt_disallow_hang(i915, hang);
> }
> --
> 2.37.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v6 2/2] i915/gem_ctx_isolation:: change semantics of ctx isolation uAPI
2022-09-14 19:54 ` Kamil Konieczny
@ 2022-09-19 7:18 ` Adrian Larumbe
2022-10-19 14:05 ` Adrian Larumbe
1 sibling, 0 replies; 8+ messages in thread
From: Adrian Larumbe @ 2022-09-19 7:18 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev, Petri Latvala
Hi Kamil,
On 14.09.2022 21:54, Kamil Konieczny wrote:
>Hi Adrian,
>
>On 2022-09-12 at 19:15:52 +0100, Adrian Larumbe wrote:
>> ioctl I915_PARAM_HAS_CONTEXT_ISOLATION param is meant to report whether all
>> the engines in the system support context isolation, but the way the return
>> value was being used did not respect the contract on the uAPI.
>
>May you point (maybe in cover letter ?) to discussion on this
>topic ? From I t found, the uAPI description was long, started
>with boolean meaning, but then added that this is a bitflag.
>It is a little confusing, so the question is: is it really
>all users take it as boolean ?
The issue was first described here:
https://gitlab.freedesktop.org/drm/intel/-/issues/4264
Now that you mention it, I should've probably included a link to the freedesktop
issue in a cover letter to provide context for the patch series.
The gitlab issue mentions Iris treating the parameter query's return value as a
boolean, which happens in Mesa at src/gallium/drivers/iris/iris_screen.c:776
That means IGT's behaviour needs to change to fit the expected uAPI because
the kernel does not provide additional uAPI for IGT tests, so the current
bitmask that represents engine context isolation has to be replaced by some
sort of userspace logic.
>> Skip all engine tests for which context isolation is not supported. Also
>> skip tests that involve an engine reset if both RCS and CCS engines are
>> present in the system. This is because they belong to the same reset
>> domain.
>
>This should be another patch itself as it is only for DG2, or
>am I missing something ?
This makes sense, I'll break the second patch into two: first one will change
the meaning of the parameter ioctl, and the second one will have the logic for
skipping tests for which context isolation is not guaranteed.
It seems like you pointed out this should only affect DG2, because it's the only
HW with both CCS and RCS engines, at least according to
drivers/gpu/drm/i915/i915_pci.c:1052.
>>
>> Signed-off-by: Adrian Larumbe <adrian.larumbe@collabora.com>
>> ---
>> tests/i915/gem_ctx_isolation.c | 109 ++++++++++++++++++++++++---------
>> 1 file changed, 80 insertions(+), 29 deletions(-)
>>
>> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
>> index 95d13969fa61..36afbaf74b64 100644
>> --- a/tests/i915/gem_ctx_isolation.c
>> +++ b/tests/i915/gem_ctx_isolation.c
>> @@ -45,6 +45,7 @@ enum {
>> VCS2 = ENGINE(I915_ENGINE_CLASS_VIDEO, 2),
>> VCS3 = ENGINE(I915_ENGINE_CLASS_VIDEO, 3),
>> VECS0 = ENGINE(I915_ENGINE_CLASS_VIDEO_ENHANCE, 0),
>> + CCS0 = ENGINE(I915_ENGINE_CLASS_COMPUTE, 0),
>> };
>>
>> #define ALL ~0u
>> @@ -164,6 +165,8 @@ static const struct named_register {
>>
>> { "xCS_GPR", GEN9, ALL, 0x600, 32, .relative = true },
>>
>> + /* TODO: add CCS0 registers */
>> +
>> {}
>> }, ignore_registers[] = {
>> { "RCS timestamp", GEN6, ~0u, 0x2358 },
>> @@ -625,9 +628,40 @@ static void compare_regs(int fd, const struct intel_execution_engine2 *e,
>> num_errors, who);
>> }
>>
>> +static bool
>> +engine_has_context_isolation(const struct intel_execution_engine2 *e,
>> + int gen)
>> +{
>> + if (gen > 8)
>> + return true;
>> +
>> + if (gen >= 6 && gen <= 8 && e->class == I915_ENGINE_CLASS_RENDER)
>> + return true;
>> +
>> + return false;
>> +}
>> +
>> +static bool
>> +has_engine_class(const intel_ctx_cfg_t *cfg, unsigned int class)
>> +{
>> + const struct i915_engine_class_instance *eci;
>> + unsigned int i;
>> +
>> + igt_require(class <= I915_ENGINE_CLASS_COMPUTE);
>> +
>> + for (i = 0; i < cfg->num_engines; i++) {
>> + eci = &cfg->engines[i];
>> + if (eci->engine_class == class)
>> + return true;
>> + }
>> +
>> + return false;
>> +}
>> +
>> static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
>> const struct intel_execution_engine2 *e,
>> - unsigned int flags)
>> + unsigned int flags,
>> + int gen)
>
>Please drop this change, use fd for obtaining gen.
>
>> {
>> static const uint32_t values[] = {
>> 0x0,
>> @@ -645,6 +679,7 @@ static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
>>
>> /* Sigh -- hsw: we need cmdparser access to our own registers! */
>> igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
>> + igt_require(engine_has_context_isolation(e, gen));
>--------------------------------------------------- ^
>Use fd here for getting gen.
>
>>
>> gem_quiescent_gpu(fd);
>>
>> @@ -727,7 +762,8 @@ static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
>>
>> static void isolation(int fd, const intel_ctx_cfg_t *cfg,
>> const struct intel_execution_engine2 *e,
>> - unsigned int flags)
>> + unsigned int flags,
>> + int gen)
>> {
>> static const uint32_t values[] = {
>> 0x0,
>> @@ -741,6 +777,8 @@ static void isolation(int fd, const intel_ctx_cfg_t *cfg,
>> unsigned int num_values =
>> flags & (DIRTY1 | DIRTY2) ? ARRAY_SIZE(values) : 1;
>>
>> + igt_require(engine_has_context_isolation(e, gen));
>> +
>> gem_quiescent_gpu(fd);
>>
>> for (int v = 0; v < num_values; v++) {
>> @@ -863,7 +901,8 @@ static void inject_reset_context(int fd, const intel_ctx_cfg_t *cfg,
>>
>> static void preservation(int fd, const intel_ctx_cfg_t *cfg,
>> const struct intel_execution_engine2 *e,
>> - unsigned int flags)
>> + unsigned int flags,
>> + int gen)
>> {
>> static const uint32_t values[] = {
>> 0x0,
>> @@ -880,6 +919,8 @@ static void preservation(int fd, const intel_ctx_cfg_t *cfg,
>> uint64_t ahnd[num_values + 1];
>> igt_spin_t *spin;
>>
>> + igt_require(engine_has_context_isolation(e, gen));
>> +
>> gem_quiescent_gpu(fd);
>>
>> ctx[num_values] = intel_ctx_create(fd, cfg);
>> @@ -900,8 +941,19 @@ static void preservation(int fd, const intel_ctx_cfg_t *cfg,
>> gem_close(fd, read_regs(fd, ahnd[num_values], ctx[num_values], e, flags));
>> igt_spin_free(fd, spin);
>>
>> - if (flags & RESET)
>> + if (flags & RESET) {
>> + /*
>> + * TODO: handle this differently if CSS and RCS ever became
>> + * part of different reset domains
>> + */
>> + igt_skip_on_f(has_engine_class(cfg, I915_ENGINE_CLASS_RENDER) &&
>> + has_engine_class(cfg, I915_ENGINE_CLASS_COMPUTE),
>> + "Both render and compute types of engines are present on the HW. \
>> + Skipping test because architecturally we don't make cross engine \
>> + isolation guarantees on those.\n");
>> +
>
>In comment you write about reset domain, yet in skip comment
>you added that there is no ctx isolation between these engine
>classes, so maybe we should skip this test also for non-reset ?
>If you want to keep it for reset as is, change message
>accordingly.
>
>> inject_reset_context(fd, cfg, e);
>> + }
>>
>> switch (flags & SLEEP_MASK) {
>> case NOSLEEP:
>> @@ -960,7 +1012,7 @@ static unsigned int __has_context_isolation(int fd)
>> int value = 0;
>>
>> memset(&gp, 0, sizeof(gp));
>> - gp.param = 50; /* I915_PARAM_HAS_CONTEXT_ISOLATION */
>> + gp.param = I915_PARAM_HAS_CONTEXT_ISOLATION;
>> gp.value = &value;
>>
>> igt_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
>> @@ -969,21 +1021,19 @@ static unsigned int __has_context_isolation(int fd)
>> return value;
>> }
>>
>> -#define test_each_engine(e, i915, cfg, mask) \
>> +#define test_each_engine(e, i915, cfg) \
>> for_each_ctx_cfg_engine(i915, cfg, e) \
>> - for_each_if(mask & (1 << (e)->class)) \
>> - igt_dynamic_f("%s", (e)->name)
>> + igt_dynamic_f("%s", (e)->name)
>>
>> igt_main
>> {
>> - unsigned int has_context_isolation = 0;
>> + bool has_context_isolation = 0;
>> const struct intel_execution_engine2 *e;
>> intel_ctx_cfg_t cfg;
>> int i915 = -1;
>> + int gen;
>------- ^
>This should be unsigned.
>
>Regards,
>Kamil
>
>>
>> igt_fixture {
>> - int gen;
>> -
>> i915 = drm_open_driver(DRIVER_INTEL);
>> igt_require_gem(i915);
>> igt_require(gem_has_contexts(i915));
>> @@ -993,6 +1043,7 @@ igt_main
>> igt_require(has_context_isolation);
>>
>> gen = intel_gen(intel_get_drm_devid(i915));
>> + igt_require(gen >= 2);
>>
>> igt_warn_on_f(gen > LAST_KNOWN_GEN,
>> "GEN not recognized! Test needs to be updated to run.\n");
>> @@ -1004,43 +1055,43 @@ igt_main
>> }
>>
>> igt_subtest_with_dynamic("nonpriv") {
>> - test_each_engine(e, i915, &cfg, has_context_isolation)
>> - nonpriv(i915, &cfg, e, 0);
>> + test_each_engine(e, i915, &cfg)
>> + nonpriv(i915, &cfg, e, 0, gen);
>> }
>>
>> igt_subtest_with_dynamic("nonpriv-switch") {
>> - test_each_engine(e, i915, &cfg, has_context_isolation)
>> - nonpriv(i915, &cfg, e, DIRTY2);
>> + test_each_engine(e, i915, &cfg)
>> + nonpriv(i915, &cfg, e, DIRTY2, gen);
>> }
>>
>> igt_subtest_with_dynamic("clean") {
>> - test_each_engine(e, i915, &cfg, has_context_isolation)
>> - isolation(i915, &cfg, e, 0);
>> + test_each_engine(e, i915, &cfg)
>> + isolation(i915, &cfg, e, 0, gen);
>> }
>>
>> igt_subtest_with_dynamic("dirty-create") {
>> - test_each_engine(e, i915, &cfg, has_context_isolation)
>> - isolation(i915, &cfg, e, DIRTY1);
>> + test_each_engine(e, i915, &cfg)
>> + isolation(i915, &cfg, e, DIRTY1, gen);
>> }
>>
>> igt_subtest_with_dynamic("dirty-switch") {
>> - test_each_engine(e, i915, &cfg, has_context_isolation)
>> - isolation(i915, &cfg, e, DIRTY2);
>> + test_each_engine(e, i915, &cfg)
>> + isolation(i915, &cfg, e, DIRTY2, gen);
>> }
>>
>> igt_subtest_with_dynamic("preservation") {
>> - test_each_engine(e, i915, &cfg, has_context_isolation)
>> - preservation(i915, &cfg, e, 0);
>> + test_each_engine(e, i915, &cfg)
>> + preservation(i915, &cfg, e, 0, gen);
>> }
>>
>> igt_subtest_with_dynamic("preservation-S3") {
>> - test_each_engine(e, i915, &cfg, has_context_isolation)
>> - preservation(i915, &cfg, e, S3);
>> + test_each_engine(e, i915, &cfg)
>> + preservation(i915, &cfg, e, S3, gen);
>> }
>>
>> igt_subtest_with_dynamic("preservation-S4") {
>> - test_each_engine(e, i915, &cfg, has_context_isolation)
>> - preservation(i915, &cfg, e, S4);
>> + test_each_engine(e, i915, &cfg)
>> + preservation(i915, &cfg, e, S4, gen);
>> }
>>
>> igt_fixture {
>> @@ -1050,8 +1101,8 @@ igt_main
>> igt_subtest_with_dynamic("preservation-reset") {
>> igt_hang_t hang = igt_allow_hang(i915, 0, 0);
>>
>> - test_each_engine(e, i915, &cfg, has_context_isolation)
>> - preservation(i915, &cfg, e, RESET);
>> + test_each_engine(e, i915, &cfg)
>> + preservation(i915, &cfg, e, RESET, gen);
>>
>> igt_disallow_hang(i915, hang);
>> }
>> --
>> 2.37.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v6 2/2] i915/gem_ctx_isolation:: change semantics of ctx isolation uAPI
2022-09-14 19:54 ` Kamil Konieczny
2022-09-19 7:18 ` Adrian Larumbe
@ 2022-10-19 14:05 ` Adrian Larumbe
1 sibling, 0 replies; 8+ messages in thread
From: Adrian Larumbe @ 2022-10-19 14:05 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev, Petri Latvala
Hi Kamil,
Sorry about the belated reply, but I was quite caught up with a plethora of other stuff.
I was about to put together v7 of the patch series when I realised I've another question.
On 14.09.2022 21:54, Kamil Konieczny wrote:
> Hi Adrian,
>
> On 2022-09-12 at 19:15:52 +0100, Adrian Larumbe wrote:
> > ioctl I915_PARAM_HAS_CONTEXT_ISOLATION param is meant to report whether all
> > the engines in the system support context isolation, but the way the return
> > value was being used did not respect the contract on the uAPI.
>
> May you point (maybe in cover letter ?) to discussion on this
> topic ? From I t found, the uAPI description was long, started
> with boolean meaning, but then added that this is a bitflag.
> It is a little confusing, so the question is: is it really
> all users take it as boolean ?
According to Dan Vetter, the only user the uAPI has to take into account is
Mesa, because no specific uAPI is provided for IGT tests. Because the Iris Mesa
backend deals with the return value of this param request as though it were a
boolean, then this IGT test has to change so that deciding whether an engine has
context isolation support must be done in UM instead.
There's a parallel kernel patch that changes the driver semantics of this param
ioctl return value so that it fits into what Iris expects, but they asked for
the relevant IGT test to be ready before going further into review.
> >
> > Skip all engine tests for which context isolation is not supported. Also
> > skip tests that involve an engine reset if both RCS and CCS engines are
> > present in the system. This is because they belong to the same reset
> > domain.
>
> This should be another patch itself as it is only for DG2, or
> am I missing something ?
>
> >
> > Signed-off-by: Adrian Larumbe <adrian.larumbe@collabora.com>
> > ---
> > tests/i915/gem_ctx_isolation.c | 109 ++++++++++++++++++++++++---------
> > 1 file changed, 80 insertions(+), 29 deletions(-)
> >
> > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> > index 95d13969fa61..36afbaf74b64 100644
> > --- a/tests/i915/gem_ctx_isolation.c
> > +++ b/tests/i915/gem_ctx_isolation.c
> > @@ -45,6 +45,7 @@ enum {
> > VCS2 = ENGINE(I915_ENGINE_CLASS_VIDEO, 2),
> > VCS3 = ENGINE(I915_ENGINE_CLASS_VIDEO, 3),
> > VECS0 = ENGINE(I915_ENGINE_CLASS_VIDEO_ENHANCE, 0),
> > + CCS0 = ENGINE(I915_ENGINE_CLASS_COMPUTE, 0),
> > };
> >
> > #define ALL ~0u
> > @@ -164,6 +165,8 @@ static const struct named_register {
> >
> > { "xCS_GPR", GEN9, ALL, 0x600, 32, .relative = true },
> >
> > + /* TODO: add CCS0 registers */
> > +
> > {}
> > }, ignore_registers[] = {
> > { "RCS timestamp", GEN6, ~0u, 0x2358 },
> > @@ -625,9 +628,40 @@ static void compare_regs(int fd, const struct intel_execution_engine2 *e,
> > num_errors, who);
> > }
> >
> > +static bool
> > +engine_has_context_isolation(const struct intel_execution_engine2 *e,
> > + int gen)
> > +{
> > + if (gen > 8)
> > + return true;
> > +
> > + if (gen >= 6 && gen <= 8 && e->class == I915_ENGINE_CLASS_RENDER)
> > + return true;
> > +
> > + return false;
> > +}
> > +
> > +static bool
> > +has_engine_class(const intel_ctx_cfg_t *cfg, unsigned int class)
> > +{
> > + const struct i915_engine_class_instance *eci;
> > + unsigned int i;
> > +
> > + igt_require(class <= I915_ENGINE_CLASS_COMPUTE);
> > +
> > + for (i = 0; i < cfg->num_engines; i++) {
> > + eci = &cfg->engines[i];
> > + if (eci->engine_class == class)
> > + return true;
> > + }
> > +
> > + return false;
> > +}
> > +
> > static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
> > const struct intel_execution_engine2 *e,
> > - unsigned int flags)
> > + unsigned int flags,
> > + int gen)
>
> Please drop this change, use fd for obtaining gen.
I did this because I was recalculating the gen value inside every single subtest
function, but I've done as you suggested in the latest revision.
> > {
> > static const uint32_t values[] = {
> > 0x0,
> > @@ -645,6 +679,7 @@ static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
> >
> > /* Sigh -- hsw: we need cmdparser access to our own registers! */
> > igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
> > + igt_require(engine_has_context_isolation(e, gen));
> --------------------------------------------------- ^
> Use fd here for getting gen.
>
> >
> > gem_quiescent_gpu(fd);
> >
> > @@ -727,7 +762,8 @@ static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
> >
> > static void isolation(int fd, const intel_ctx_cfg_t *cfg,
> > const struct intel_execution_engine2 *e,
> > - unsigned int flags)
> > + unsigned int flags,
> > + int gen)
> > {
> > static const uint32_t values[] = {
> > 0x0,
> > @@ -741,6 +777,8 @@ static void isolation(int fd, const intel_ctx_cfg_t *cfg,
> > unsigned int num_values =
> > flags & (DIRTY1 | DIRTY2) ? ARRAY_SIZE(values) : 1;
> >
> > + igt_require(engine_has_context_isolation(e, gen));
> > +
> > gem_quiescent_gpu(fd);
> >
> > for (int v = 0; v < num_values; v++) {
> > @@ -863,7 +901,8 @@ static void inject_reset_context(int fd, const intel_ctx_cfg_t *cfg,
> >
> > static void preservation(int fd, const intel_ctx_cfg_t *cfg,
> > const struct intel_execution_engine2 *e,
> > - unsigned int flags)
> > + unsigned int flags,
> > + int gen)
> > {
> > static const uint32_t values[] = {
> > 0x0,
> > @@ -880,6 +919,8 @@ static void preservation(int fd, const intel_ctx_cfg_t *cfg,
> > uint64_t ahnd[num_values + 1];
> > igt_spin_t *spin;
> >
> > + igt_require(engine_has_context_isolation(e, gen));
> > +
> > gem_quiescent_gpu(fd);
> >
> > ctx[num_values] = intel_ctx_create(fd, cfg);
> > @@ -900,8 +941,19 @@ static void preservation(int fd, const intel_ctx_cfg_t *cfg,
> > gem_close(fd, read_regs(fd, ahnd[num_values], ctx[num_values], e, flags));
> > igt_spin_free(fd, spin);
> >
> > - if (flags & RESET)
> > + if (flags & RESET) {
> > + /*
> > + * TODO: handle this differently if CSS and RCS ever became
> > + * part of different reset domains
> > + */
> > + igt_skip_on_f(has_engine_class(cfg, I915_ENGINE_CLASS_RENDER) &&
> > + has_engine_class(cfg, I915_ENGINE_CLASS_COMPUTE),
> > + "Both render and compute types of engines are present on the HW. \
> > + Skipping test because architecturally we don't make cross engine \
> > + isolation guarantees on those.\n");
> > +
>
> In comment you write about reset domain, yet in skip comment
> you added that there is no ctx isolation between these engine
> classes, so maybe we should skip this test also for non-reset ?
> If you want to keep it for reset as is, change message
> accordingly.
Here I refer specifically to cross-engine reset isolation, rather than engine
context isolation. Because they belong to the same reset domain, then resetting
one engine would affect the other, so test result would be undefined. That's why
I think when the test does not involve explicit resets, then it should go on as
usual.
> > inject_reset_context(fd, cfg, e);
> > + }
> >
> > switch (flags & SLEEP_MASK) {
> > case NOSLEEP:
> > @@ -960,7 +1012,7 @@ static unsigned int __has_context_isolation(int fd)
> > int value = 0;
> >
> > memset(&gp, 0, sizeof(gp));
> > - gp.param = 50; /* I915_PARAM_HAS_CONTEXT_ISOLATION */
> > + gp.param = I915_PARAM_HAS_CONTEXT_ISOLATION;
> > gp.value = &value;
> >
> > igt_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
> > @@ -969,21 +1021,19 @@ static unsigned int __has_context_isolation(int fd)
> > return value;
> > }
I've also decided to remove this function and its call at main's prelude because
it's no longer useful in deciding what engines support context isolation, as
it's meant to change soon to return just a boolean value.
> > -#define test_each_engine(e, i915, cfg, mask) \
> > +#define test_each_engine(e, i915, cfg) \
> > for_each_ctx_cfg_engine(i915, cfg, e) \
> > - for_each_if(mask & (1 << (e)->class)) \
> > - igt_dynamic_f("%s", (e)->name)
> > + igt_dynamic_f("%s", (e)->name)
> >
> > igt_main
> > {
> > - unsigned int has_context_isolation = 0;
> > + bool has_context_isolation = 0;
> > const struct intel_execution_engine2 *e;
> > intel_ctx_cfg_t cfg;
> > int i915 = -1;
> > + int gen;
> ------- ^
> This should be unsigned.
>
> Regards,
> Kamil
>
> >
> > igt_fixture {
> > - int gen;
> > -
> > i915 = drm_open_driver(DRIVER_INTEL);
> > igt_require_gem(i915);
> > igt_require(gem_has_contexts(i915));
> > @@ -993,6 +1043,7 @@ igt_main
> > igt_require(has_context_isolation);
> >
> > gen = intel_gen(intel_get_drm_devid(i915));
> > + igt_require(gen >= 2);
> >
> > igt_warn_on_f(gen > LAST_KNOWN_GEN,
> > "GEN not recognized! Test needs to be updated to run.\n");
> > @@ -1004,43 +1055,43 @@ igt_main
> > }
> >
> > igt_subtest_with_dynamic("nonpriv") {
> > - test_each_engine(e, i915, &cfg, has_context_isolation)
> > - nonpriv(i915, &cfg, e, 0);
> > + test_each_engine(e, i915, &cfg)
> > + nonpriv(i915, &cfg, e, 0, gen);
> > }
> >
> > igt_subtest_with_dynamic("nonpriv-switch") {
> > - test_each_engine(e, i915, &cfg, has_context_isolation)
> > - nonpriv(i915, &cfg, e, DIRTY2);
> > + test_each_engine(e, i915, &cfg)
> > + nonpriv(i915, &cfg, e, DIRTY2, gen);
> > }
> >
> > igt_subtest_with_dynamic("clean") {
> > - test_each_engine(e, i915, &cfg, has_context_isolation)
> > - isolation(i915, &cfg, e, 0);
> > + test_each_engine(e, i915, &cfg)
> > + isolation(i915, &cfg, e, 0, gen);
> > }
> >
> > igt_subtest_with_dynamic("dirty-create") {
> > - test_each_engine(e, i915, &cfg, has_context_isolation)
> > - isolation(i915, &cfg, e, DIRTY1);
> > + test_each_engine(e, i915, &cfg)
> > + isolation(i915, &cfg, e, DIRTY1, gen);
> > }
> >
> > igt_subtest_with_dynamic("dirty-switch") {
> > - test_each_engine(e, i915, &cfg, has_context_isolation)
> > - isolation(i915, &cfg, e, DIRTY2);
> > + test_each_engine(e, i915, &cfg)
> > + isolation(i915, &cfg, e, DIRTY2, gen);
> > }
> >
> > igt_subtest_with_dynamic("preservation") {
> > - test_each_engine(e, i915, &cfg, has_context_isolation)
> > - preservation(i915, &cfg, e, 0);
> > + test_each_engine(e, i915, &cfg)
> > + preservation(i915, &cfg, e, 0, gen);
> > }
> >
> > igt_subtest_with_dynamic("preservation-S3") {
> > - test_each_engine(e, i915, &cfg, has_context_isolation)
> > - preservation(i915, &cfg, e, S3);
> > + test_each_engine(e, i915, &cfg)
> > + preservation(i915, &cfg, e, S3, gen);
> > }
> >
> > igt_subtest_with_dynamic("preservation-S4") {
> > - test_each_engine(e, i915, &cfg, has_context_isolation)
> > - preservation(i915, &cfg, e, S4);
> > + test_each_engine(e, i915, &cfg)
> > + preservation(i915, &cfg, e, S4, gen);
> > }
> >
> > igt_fixture {
> > @@ -1050,8 +1101,8 @@ igt_main
> > igt_subtest_with_dynamic("preservation-reset") {
> > igt_hang_t hang = igt_allow_hang(i915, 0, 0);
> >
> > - test_each_engine(e, i915, &cfg, has_context_isolation)
> > - preservation(i915, &cfg, e, RESET);
> > + test_each_engine(e, i915, &cfg)
> > + preservation(i915, &cfg, e, RESET, gen);
> >
> > igt_disallow_hang(i915, hang);
> > }
> > --
> > 2.37.0
Adrian Larumbe
^ permalink raw reply [flat|nested] 8+ messages in thread
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2022-09-12 18:15 [igt-dev] [PATCH i-g-t v6 1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine Adrian Larumbe
2022-09-12 18:15 ` [igt-dev] [PATCH i-g-t v6 2/2] i915/gem_ctx_isolation:: change semantics of ctx isolation uAPI Adrian Larumbe
2022-09-14 19:54 ` Kamil Konieczny
2022-09-19 7:18 ` Adrian Larumbe
2022-10-19 14:05 ` Adrian Larumbe
2022-09-12 19:20 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,v6,1/2] lib/i915/i915_drm_local: Remove COMPUTE class engine Patchwork
2022-09-13 0:07 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-14 19:29 ` [igt-dev] [PATCH i-g-t v6 1/2] " Kamil Konieczny
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