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From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>,
	dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v5 12/15] drm/i915/huc: stall media submission until HuC is loaded
Date: Mon, 12 Sep 2022 17:57:36 -0700	[thread overview]
Message-ID: <20220913005739.798337-13-daniele.ceraolospurio@intel.com> (raw)
In-Reply-To: <20220913005739.798337-1-daniele.ceraolospurio@intel.com>

Wait on the fence to be signalled to avoid the submissions finding HuC
not yet loaded.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Acked-by: Tony Ye <tony.ye@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_huc.h |  6 ++++++
 drivers/gpu/drm/i915/i915_request.c    | 24 ++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 915d281c1c72..52db03620c60 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -81,6 +81,12 @@ static inline bool intel_huc_is_loaded_by_gsc(const struct intel_huc *huc)
 	return huc->fw.loaded_via_gsc;
 }
 
+static inline bool intel_huc_wait_required(struct intel_huc *huc)
+{
+	return intel_huc_is_used(huc) && intel_huc_is_loaded_by_gsc(huc) &&
+	       !intel_huc_is_authenticated(huc);
+}
+
 void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p);
 
 #endif
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 62fad16a55e8..77f45a3cb01f 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1621,6 +1621,20 @@ i915_request_await_object(struct i915_request *to,
 	return ret;
 }
 
+static void i915_request_await_huc(struct i915_request *rq)
+{
+	struct intel_huc *huc = &rq->context->engine->gt->uc.huc;
+
+	/* don't stall kernel submissions! */
+	if (!rcu_access_pointer(rq->context->gem_context))
+		return;
+
+	if (intel_huc_wait_required(huc))
+		i915_sw_fence_await_sw_fence(&rq->submit,
+					     &huc->delayed_load.fence,
+					     &rq->submitq);
+}
+
 static struct i915_request *
 __i915_request_ensure_parallel_ordering(struct i915_request *rq,
 					struct intel_timeline *timeline)
@@ -1702,6 +1716,16 @@ __i915_request_add_to_timeline(struct i915_request *rq)
 	struct intel_timeline *timeline = i915_request_timeline(rq);
 	struct i915_request *prev;
 
+	/*
+	 * Media workloads may require HuC, so stall them until HuC loading is
+	 * complete. Note that HuC not being loaded when a user submission
+	 * arrives can only happen when HuC is loaded via GSC and in that case
+	 * we still expect the window between us starting to accept submissions
+	 * and HuC loading completion to be small (a few hundred ms).
+	 */
+	if (rq->engine->class == VIDEO_DECODE_CLASS)
+		i915_request_await_huc(rq);
+
 	/*
 	 * Dependency tracking and request ordering along the timeline
 	 * is special cased so that we can eliminate redundant ordering
-- 
2.37.2


WARNING: multiple messages have this Message-ID (diff)
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Tony Ye <tony.ye@intel.com>,
	Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
	Alan Previn <alan.previn.teres.alexis@intel.com>,
	dri-devel@lists.freedesktop.org
Subject: [PATCH v5 12/15] drm/i915/huc: stall media submission until HuC is loaded
Date: Mon, 12 Sep 2022 17:57:36 -0700	[thread overview]
Message-ID: <20220913005739.798337-13-daniele.ceraolospurio@intel.com> (raw)
In-Reply-To: <20220913005739.798337-1-daniele.ceraolospurio@intel.com>

Wait on the fence to be signalled to avoid the submissions finding HuC
not yet loaded.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Acked-by: Tony Ye <tony.ye@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_huc.h |  6 ++++++
 drivers/gpu/drm/i915/i915_request.c    | 24 ++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 915d281c1c72..52db03620c60 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -81,6 +81,12 @@ static inline bool intel_huc_is_loaded_by_gsc(const struct intel_huc *huc)
 	return huc->fw.loaded_via_gsc;
 }
 
+static inline bool intel_huc_wait_required(struct intel_huc *huc)
+{
+	return intel_huc_is_used(huc) && intel_huc_is_loaded_by_gsc(huc) &&
+	       !intel_huc_is_authenticated(huc);
+}
+
 void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p);
 
 #endif
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 62fad16a55e8..77f45a3cb01f 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1621,6 +1621,20 @@ i915_request_await_object(struct i915_request *to,
 	return ret;
 }
 
+static void i915_request_await_huc(struct i915_request *rq)
+{
+	struct intel_huc *huc = &rq->context->engine->gt->uc.huc;
+
+	/* don't stall kernel submissions! */
+	if (!rcu_access_pointer(rq->context->gem_context))
+		return;
+
+	if (intel_huc_wait_required(huc))
+		i915_sw_fence_await_sw_fence(&rq->submit,
+					     &huc->delayed_load.fence,
+					     &rq->submitq);
+}
+
 static struct i915_request *
 __i915_request_ensure_parallel_ordering(struct i915_request *rq,
 					struct intel_timeline *timeline)
@@ -1702,6 +1716,16 @@ __i915_request_add_to_timeline(struct i915_request *rq)
 	struct intel_timeline *timeline = i915_request_timeline(rq);
 	struct i915_request *prev;
 
+	/*
+	 * Media workloads may require HuC, so stall them until HuC loading is
+	 * complete. Note that HuC not being loaded when a user submission
+	 * arrives can only happen when HuC is loaded via GSC and in that case
+	 * we still expect the window between us starting to accept submissions
+	 * and HuC loading completion to be small (a few hundred ms).
+	 */
+	if (rq->engine->class == VIDEO_DECODE_CLASS)
+		i915_request_await_huc(rq);
+
 	/*
 	 * Dependency tracking and request ordering along the timeline
 	 * is special cased so that we can eliminate redundant ordering
-- 
2.37.2


  parent reply	other threads:[~2022-09-13  0:59 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-13  0:57 [PATCH v5 00/15] drm/i915: HuC loading for DG2 Daniele Ceraolo Spurio
2022-09-13  0:57 ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-13  0:57 ` [PATCH v5 01/15] mei: add support to GSC extended header Daniele Ceraolo Spurio
2022-09-13  0:57   ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-24 12:15   ` Greg Kroah-Hartman
2022-09-24 12:15     ` [Intel-gfx] " Greg Kroah-Hartman
2022-09-13  0:57 ` [PATCH v5 02/15] mei: bus: enable sending gsc commands Daniele Ceraolo Spurio
2022-09-13  0:57   ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-24 12:15   ` Greg Kroah-Hartman
2022-09-24 12:15     ` [Intel-gfx] " Greg Kroah-Hartman
2022-09-13  0:57 ` [PATCH v5 03/15] mei: adjust extended header kdocs Daniele Ceraolo Spurio
2022-09-13  0:57   ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-24 12:15   ` Greg Kroah-Hartman
2022-09-24 12:15     ` [Intel-gfx] " Greg Kroah-Hartman
2022-09-13  0:57 ` [PATCH v5 04/15] mei: bus: extend bus API to support command streamer API Daniele Ceraolo Spurio
2022-09-13  0:57   ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-24 12:16   ` Greg Kroah-Hartman
2022-09-24 12:16     ` [Intel-gfx] " Greg Kroah-Hartman
2022-09-13  0:57 ` [PATCH v5 05/15] mei: pxp: add command streamer API to the PXP driver Daniele Ceraolo Spurio
2022-09-13  0:57   ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-24 12:16   ` Greg Kroah-Hartman
2022-09-24 12:16     ` [Intel-gfx] " Greg Kroah-Hartman
2022-09-13  0:57 ` [Intel-gfx] [PATCH v5 06/15] mei: pxp: support matching with a gfx discrete card Daniele Ceraolo Spurio
2022-09-13  0:57   ` Daniele Ceraolo Spurio
2022-09-24 12:16   ` Greg Kroah-Hartman
2022-09-24 12:16     ` [Intel-gfx] " Greg Kroah-Hartman
2022-09-13  0:57 ` [PATCH v5 07/15] drm/i915/pxp: load the pxp module when we have a gsc-loaded huc Daniele Ceraolo Spurio
2022-09-13  0:57   ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-13  0:57 ` [Intel-gfx] [PATCH v5 08/15] drm/i915/pxp: implement function for sending tee stream command Daniele Ceraolo Spurio
2022-09-13  0:57   ` Daniele Ceraolo Spurio
2022-09-13  0:57 ` [Intel-gfx] [PATCH v5 09/15] drm/i915/pxp: add huc authentication and loading command Daniele Ceraolo Spurio
2022-09-13  0:57   ` Daniele Ceraolo Spurio
2022-09-13  0:57 ` [Intel-gfx] [PATCH v5 10/15] drm/i915/dg2: setup HuC loading via GSC Daniele Ceraolo Spurio
2022-09-13  0:57   ` Daniele Ceraolo Spurio
2022-09-13  0:57 ` [PATCH v5 11/15] drm/i915/huc: track delayed HuC load with a fence Daniele Ceraolo Spurio
2022-09-13  0:57   ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-13  0:57 ` Daniele Ceraolo Spurio [this message]
2022-09-13  0:57   ` [PATCH v5 12/15] drm/i915/huc: stall media submission until HuC is loaded Daniele Ceraolo Spurio
2022-09-13 23:22   ` [PATCH] " Daniele Ceraolo Spurio
2022-09-13 23:22     ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-27 18:54     ` Teres Alexis, Alan Previn
2022-09-27 18:54       ` [Intel-gfx] " Teres Alexis, Alan Previn
2022-09-13  0:57 ` [PATCH v5 13/15] drm/i915/huc: better define HuC status getparam possible return values Daniele Ceraolo Spurio
2022-09-13  0:57   ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-13  0:57 ` [PATCH v5 14/15] drm/i915/huc: define gsc-compatible HuC fw for DG2 Daniele Ceraolo Spurio
2022-09-13  0:57   ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-13  0:57 ` [PATCH v5 15/15] HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI Daniele Ceraolo Spurio
2022-09-13  0:57   ` [Intel-gfx] " Daniele Ceraolo Spurio
2022-09-13  2:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: HuC loading for DG2 (rev5) Patchwork
2022-09-13  2:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-13  2:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-13 10:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-13 22:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: HuC loading for DG2 (rev6) Patchwork
2022-09-13 22:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-13 22:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-14  0:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: HuC loading for DG2 (rev7) Patchwork
2022-09-14  0:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-14  1:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-14 16:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-14 16:51 ` [PATCH v5 00/15] drm/i915: HuC loading for DG2 Winkler, Tomas
2022-09-14 16:51   ` [Intel-gfx] " Winkler, Tomas
2022-09-14 18:11   ` Greg Kroah-Hartman
2022-09-14 18:11     ` [Intel-gfx] " Greg Kroah-Hartman
2022-09-15 20:54     ` Winkler, Tomas
2022-09-15 20:54       ` Winkler, Tomas

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