* [Intel-gfx] [PATCH v4 0/3] Enable Pipewriteback
@ 2022-09-14 7:12 Kandpal, Suraj
2022-09-14 7:12 ` [Intel-gfx] [PATCH v4 1/3] drm/i915: Define WD trancoder for i915 Kandpal, Suraj
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Kandpal, Suraj @ 2022-09-14 7:12 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
A patch series was floated in the drm mailing list which aimed to change
the drm_connector and drm_encoder fields to pointer in the
drm_connector_writeback structure, this received a huge pushback from
the community but since i915 expects each connector present in the
drm_device list to be a intel_connector but drm_writeback framework
makes us have a connector which cannot be embedded in an intel_connector
structure.
[1]
https://patchwork.kernel.org/project/dri-devel/patch/20220202081702.22119-1-suraj.kandpal@intel.com/
[2]
https://patchwork.kernel.org/project/dri-devel/patch/20220202085429.22261-6-suraj.kandpal@intel.com/
Since no one had an issue with encoder field being changed into a
pointer it was decided to break the connector and encoder pointer
changes into two different series.The encoder field changes is
currently being worked upon by Abhinav Kumar and the changes have been
merged.
[3]https://patchwork.kernel.org/project/dri-devel/list/?series=633565
Going forward we use a drm_connector which is not embedded in
intel_connector.
We also create a intel_encoder to avoid changes to many
iterators but no intel_connector. We also changed all iterators that
---v2
solving BAT issues
---v3
-removing unecessary comments from i915_reg.h [Arun]
-moving wd_init into its own if condition [Arun]
-fixing comment styling and alignment in intel_wd.c [Arun]
-removing continue from loop and calling function if condition is met
[Arun]
-removing useless arguments from intel_queue_writeback_job and
intel_enabling_capture [Arun]
--v4
Adding Reviewed-by to patches which were previously reviewd
Suraj Kandpal (3):
drm/i915: Define WD trancoder for i915
drm/i915 : Changing intel_connector iterators
drm/i915: Enabling WD Transcoder
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 6 +
.../drm/i915/display/intel_crtc_state_dump.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +
drivers/gpu/drm/i915/display/intel_display.c | 68 +-
drivers/gpu/drm/i915/display/intel_display.h | 18 +-
.../drm/i915/display/intel_display_debugfs.c | 13 +-
.../drm/i915/display/intel_display_types.h | 32 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 6 +
.../drm/i915/display/intel_modeset_setup.c | 119 ++-
.../drm/i915/display/intel_modeset_verify.c | 17 +-
drivers/gpu/drm/i915/display/intel_opregion.c | 3 +
drivers/gpu/drm/i915/display/intel_wd.c | 695 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_wd.h | 48 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 8 +-
drivers/gpu/drm/i915/i915_pci.c | 7 +-
drivers/gpu/drm/i915/i915_reg.h | 137 ++++
19 files changed, 1132 insertions(+), 55 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_wd.c
create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h
--
2.25.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v4 1/3] drm/i915: Define WD trancoder for i915
2022-09-14 7:12 [Intel-gfx] [PATCH v4 0/3] Enable Pipewriteback Kandpal, Suraj
@ 2022-09-14 7:12 ` Kandpal, Suraj
2022-09-14 7:12 ` [Intel-gfx] [PATCH v4 2/3] drm/i915 : Changing intel_connector iterators Kandpal, Suraj
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Kandpal, Suraj @ 2022-09-14 7:12 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Suraj Kandpal <suraj.kandpal@intel.com>
Adding WD Types, WD transcoder to enum list and WD Transcoder offsets.
Adding i915 register definitions related to WD transcoder
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 6 +
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 139 ++++++++++++++++++
3 files changed, 146 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 884e8e67b17c..a1ed9c82e2ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -120,6 +120,8 @@ enum transcoder {
TRANSCODER_DSI_1,
TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
+ TRANSCODER_WD_0,
+ TRANSCODER_WD_1,
I915_MAX_TRANSCODERS
};
@@ -141,6 +143,10 @@ static inline const char *transcoder_name(enum transcoder transcoder)
return "DSI A";
case TRANSCODER_DSI_C:
return "DSI C";
+ case TRANSCODER_WD_0:
+ return "WD 0";
+ case TRANSCODER_WD_1:
+ return "WD 1";
default:
return "<invalid>";
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3b7945aad22a..5ee5560bb312 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -79,6 +79,7 @@ enum intel_output_type {
INTEL_OUTPUT_DSI = 9,
INTEL_OUTPUT_DDI = 10,
INTEL_OUTPUT_DP_MST = 11,
+ INTEL_OUTPUT_WD = 12,
};
enum hdmi_force_audio {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52462cbfdc66..6e1f818d7113 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1996,6 +1996,8 @@
#define TRANSCODER_EDP_OFFSET 0x6f000
#define TRANSCODER_DSI0_OFFSET 0x6b000
#define TRANSCODER_DSI1_OFFSET 0x6b800
+#define TRANSCODER_WD0_OFFSET 0x6e000
+#define TRANSCODER_WD1_OFFSET 0x6e800
#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
@@ -3656,6 +3658,11 @@
#define PIPE_DSI0_OFFSET 0x7b000
#define PIPE_DSI1_OFFSET 0x7b800
+/* WD 0 and 1 */
+#define PIPE_WD0_OFFSET 0x7e000
+#define PIPE_WD1_OFFSET 0x7d000
+
+
#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
@@ -4320,6 +4327,10 @@
#define _PIPEDSI0CONF 0x7b008
#define _PIPEDSI1CONF 0x7b808
+/* WD 0 and 1 */
+#define _PIPEWD0CONF 0x7e008
+#define _PIPEWD1CONF 0x7d008
+
/* Sprite A control */
#define _DVSACNTR 0x72180
#define DVS_ENABLE REG_BIT(31)
@@ -5545,6 +5556,7 @@
#define GEN8_DE_MISC_IER _MMIO(0x4446c)
#define GEN8_DE_MISC_GSE (1 << 27)
#define GEN8_DE_EDP_PSR (1 << 19)
+#define GEN8_DE_MISC_WD0 (1 << 23)
#define GEN8_PCU_ISR _MMIO(0x444e0)
#define GEN8_PCU_IMR _MMIO(0x444e4)
@@ -8282,6 +8294,133 @@ enum skl_power_gate {
#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
+#define TGL_ROOT_DEVICE_ID 0x9A00
+#define TGL_ROOT_DEVICE_MASK 0xFF00
+#define TGL_ROOT_DEVICE_SKU_MASK 0xF
+#define TGL_ROOT_DEVICE_SKU_ULX 0x2
+#define TGL_ROOT_DEVICE_SKU_ULT 0x4
+
+/* Gen12 WD */
+#define _MMIO_WD(tc, wd0, wd1) _MMIO_TRANS((tc) - TRANSCODER_WD_0, \
+ wd0, wd1)
+
+#define WD_TRANS_ENABLE (1 << 31)
+#define WD_TRANS_DISABLE 0
+#define WD_TRANS_ACTIVE (1 << 30)
+
+/* WD transcoder control */
+#define _WD_TRANS_FUNC_CTL_0 0x6e400
+#define _WD_TRANS_FUNC_CTL_1 0x6ec00
+#define WD_TRANS_FUNC_CTL(tc) _MMIO_WD(tc,\
+ _WD_TRANS_FUNC_CTL_0,\
+ _WD_TRANS_FUNC_CTL_1)
+
+#define TRANS_WD_FUNC_ENABLE (1 << 31)
+#define WD_TRIGGERED_CAP_MODE_ENABLE (1 << 30)
+#define START_TRIGGER_FRAME (1 << 29)
+#define STOP_TRIGGER_FRAME (1 << 28)
+#define WD_CTL_POINTER_ETEH (0 << 18)
+#define WD_CTL_POINTER_ETDH (1 << 18)
+#define WD_CTL_POINTER_DTDH (2 << 18)
+#define WD_INPUT_SELECT_MASK (7 << 12)
+#define WD_INPUT_PIPE_A (0 << 12)
+#define WD_INPUT_PIPE_B (5 << 12)
+#define WD_INPUT_PIPE_C (6 << 12)
+#define WD_INPUT_PIPE_D (7 << 12)
+
+#define WD_PIX_FMT_MASK (0x3 << 20)
+#define WD_PIX_FMT_YUYV (0x1 << 20)
+#define WD_PIX_FMT_XYUV8888 (0x2 << 20)
+#define WD_PIX_FMT_XBGR8888 (0x3 << 20)
+#define WD_PIX_FMT_Y410 (0x4 << 20)
+#define WD_PIX_FMT_YUV422 (0x5 << 20)
+#define WD_PIX_FMT_XBGR2101010 (0x6 << 20)
+#define WD_PIX_FMT_RGB565 (0x7 << 20)
+
+#define WD_FRAME_NUMBER_MASK 15
+
+#define _WD_STRIDE_0 0x6e510
+#define _WD_STRIDE_1 0x6ed10
+#define WD_STRIDE(tc) _MMIO_WD(tc,\
+ _WD_STRIDE_0,\
+ _WD_STRIDE_1)
+#define WD_STRIDE_SHIFT 6
+#define WD_STRIDE_MASK (0x3ff << WD_STRIDE_SHIFT)
+
+#define _WD_STREAMCAP_CTL0 0x6e590
+#define _WD_STREAMCAP_CTL1 0x6ed90
+#define WD_STREAMCAP_CTL(tc) _MMIO_WD(tc,\
+ _WD_STREAMCAP_CTL0,\
+ _WD_STREAMCAP_CTL1)
+
+#define WD_STREAM_CAP_MODE_EN (1 << 31)
+#define WD_STRAT_MASK (3 << 24)
+#define WD_SLICING_STRAT_1_1 (0 << 24)
+#define WD_SLICING_STRAT_2_1 (1 << 24)
+#define WD_SLICING_STRAT_4_1 (2 << 24)
+#define WD_SLICING_STRAT_8_1 (3 << 24)
+#define WD_STREAM_OVERRUN_STATUS 1
+
+#define _WD_SURF_0 0x6e514
+#define _WD_SURF_1 0x6ed14
+#define WD_SURF(tc) _MMIO_WD(tc,\
+ _WD_SURF_0,\
+ _WD_SURF_1)
+
+#define _WD_IMR_0 0x6e560
+#define _WD_IMR_1 0x6ed60
+#define WD_IMR(tc) _MMIO_WD(tc,\
+ _WD_IMR_0,\
+ _WD_IMR_1)
+#define WD_FRAME_COMPLETE_INT (1 << 7)
+#define WD_GTT_FAULT_INT (1 << 6)
+#define WD_VBLANK_INT (1 << 5)
+#define WD_OVERRUN_INT (1 << 4)
+#define WD_CAPTURING_INT (1 << 3)
+#define WD_WRITE_COMPLETE_INT (1 << 2)
+
+#define _WD_IIR_0 0x6e564
+#define _WD_IIR_1 0x6ed64
+#define WD_IIR(tc) _MMIO_WD(tc,\
+ _WD_IIR_0,\
+ _WD_IIR_1)
+
+#define _WD_FRAME_STATUS_0 0x6e56b
+#define _WD_FRAME_STATUS_1 0x6ed6b
+#define WD_FRAME_STATUS(tc) _MMIO_WD(tc,\
+ _WD_FRAME_STATUS_0,\
+ _WD_FRAME_STATUS_1)
+
+#define WD_FRAME_COMPLETE (1 << 31)
+#define WD_STATE_IDLE (0 << 24)
+#define WD_STATE_CAPSTART (1 << 24)
+#define WD_STATE_FRAME_START (2 << 24)
+#define WD_STATE_CAPACITIVE (3 << 24)
+#define WD_STATE_TG_DONE (4 << 24)
+#define WD_STATE_WDX_DONE (5 << 24)
+#define WD_STATE_QUICK_CAP (6 << 24)
+
+#define _WD_27_M_0 0x6e524
+#define _WD_27_M_1 0x6ed24
+#define WD_27_M(tc) _MMIO_WD(tc,\
+ _WD_27_M_0,\
+ _WD_27_M_1)
+
+#define _WD_27_N_0 0x6e528
+
+//Address looks wrong in bspec:
+#define _WD_27_N_1 0x6ec28
+#define WD_27_N(tc) _MMIO_WD(tc,\
+ _WD_27_N_0,\
+ _WD_27_N_1)
+
+#define _WD_TAIL_CFG_0 0x6e520
+#define _WD_TAIL_CFG_1 0x6ed20
+
+#define WD_TAIL_CFG(tc) _MMIO_WD(tc,\
+ _WD_TAIL_CFG_0,\
+ _WD_TAIL_CFG_1)
+
#define CLKREQ_POLICY _MMIO(0x101038)
#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v4 2/3] drm/i915 : Changing intel_connector iterators
2022-09-14 7:12 [Intel-gfx] [PATCH v4 0/3] Enable Pipewriteback Kandpal, Suraj
2022-09-14 7:12 ` [Intel-gfx] [PATCH v4 1/3] drm/i915: Define WD trancoder for i915 Kandpal, Suraj
@ 2022-09-14 7:12 ` Kandpal, Suraj
2022-09-14 7:12 ` [Intel-gfx] [PATCH v4 3/3] drm/i915: Enabling WD Transcoder Kandpal, Suraj
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Kandpal, Suraj @ 2022-09-14 7:12 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Suraj Kandpal <suraj.kandpal@intel.com>
Changing intel_connector iterators as with writeback introduction
not all drm_connector will be embedded within intel_connector.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 7 ++---
.../drm/i915/display/intel_display_types.h | 26 ++++++++++++++++++-
.../drm/i915/display/intel_modeset_setup.c | 16 +++++++++---
drivers/gpu/drm/i915/i915_reg.h | 2 --
4 files changed, 40 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index a1ed9c82e2ed..102bf7d47ccc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -52,6 +52,7 @@ struct intel_crtc_state;
struct intel_digital_port;
struct intel_dp;
struct intel_encoder;
+struct intel_connector;
struct intel_initial_plane_config;
struct intel_load_detect_pipe;
struct intel_plane;
@@ -469,16 +470,12 @@ enum hpd_pin {
for_each_if(intel_encoder_can_psr(intel_encoder))
#define for_each_intel_connector_iter(intel_connector, iter) \
- while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
+ while ((intel_connector = intel_connector_list_iter_next(iter)))
#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
for_each_if((intel_encoder)->base.crtc == (__crtc))
-#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
- list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
- for_each_if((intel_connector)->base.encoder == (__encoder))
-
#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
for ((__i) = 0; \
(__i) < (__state)->base.dev->mode_config.num_total_plane && \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5ee5560bb312..8eacb9133fce 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1498,12 +1498,14 @@ struct cxsr_latency {
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
-#define to_intel_connector(x) container_of(x, struct intel_connector, base)
+#define to_intel_wb_connector(x) container_of(x, struct intel_wb_connector, base)
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
+#define to_intel_connector(x) (((x->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)) ? \
+ NULL : container_of(x, struct intel_connector, base))
struct intel_hdmi {
i915_reg_t hdmi_reg;
@@ -2069,4 +2071,26 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
+static inline struct intel_connector *
+intel_connector_list_iter_next(struct drm_connector_list_iter *iter)
+{
+ struct drm_connector *connector;
+ bool flag = true;
+ /*
+ * Skipping connector that are Writeback connector as they will
+ * not be embedded in intel connector
+ */
+ while (flag) {
+ connector = drm_connector_list_iter_next(iter);
+ if (connector && !to_intel_connector(connector))
+ continue;
+
+ flag = false;
+
+ if (connector)
+ return to_intel_connector(connector);
+
+ }
+ return NULL;
+}
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index cbfabd58b75a..e1a90331c230 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -205,12 +205,22 @@ static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_connector *connector;
+ struct drm_connector_list_iter conn_iter;
+ bool found_connector = false;
- for_each_connector_on_encoder(dev, &encoder->base, connector)
- return connector;
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ if (&encoder->base == connector->base.encoder) {
+ found_connector = true;
+ break;
+ }
+ }
+ drm_connector_list_iter_end(&conn_iter);
+ if (found_connector)
+ return connector;
return NULL;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6e1f818d7113..a09f33b3fa4d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3658,11 +3658,9 @@
#define PIPE_DSI0_OFFSET 0x7b000
#define PIPE_DSI1_OFFSET 0x7b800
-/* WD 0 and 1 */
#define PIPE_WD0_OFFSET 0x7e000
#define PIPE_WD1_OFFSET 0x7d000
-
#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v4 3/3] drm/i915: Enabling WD Transcoder
2022-09-14 7:12 [Intel-gfx] [PATCH v4 0/3] Enable Pipewriteback Kandpal, Suraj
2022-09-14 7:12 ` [Intel-gfx] [PATCH v4 1/3] drm/i915: Define WD trancoder for i915 Kandpal, Suraj
2022-09-14 7:12 ` [Intel-gfx] [PATCH v4 2/3] drm/i915 : Changing intel_connector iterators Kandpal, Suraj
@ 2022-09-14 7:12 ` Kandpal, Suraj
2022-09-19 5:30 ` Murthy, Arun R
2022-09-14 9:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable Pipewriteback (rev4) Patchwork
` (2 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Kandpal, Suraj @ 2022-09-14 7:12 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Suraj Kandpal <suraj.kandpal@intel.com>
Adding support for writeback transcoder to start capturing frames using
interrupt mechanism
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 6 +
.../drm/i915/display/intel_crtc_state_dump.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +
drivers/gpu/drm/i915/display/intel_display.c | 68 +-
drivers/gpu/drm/i915/display/intel_display.h | 5 +
.../drm/i915/display/intel_display_debugfs.c | 13 +-
.../drm/i915/display/intel_display_types.h | 11 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 6 +
.../drm/i915/display/intel_modeset_setup.c | 103 ++-
.../drm/i915/display/intel_modeset_verify.c | 17 +-
drivers/gpu/drm/i915/display/intel_opregion.c | 3 +
drivers/gpu/drm/i915/display/intel_wd.c | 695 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_wd.h | 48 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 8 +-
drivers/gpu/drm/i915/i915_pci.c | 7 +-
18 files changed, 951 insertions(+), 49 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_wd.c
create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a26edcdadc21..f34db43cf58d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -304,6 +304,7 @@ i915-y += \
display/intel_tv.o \
display/intel_vdsc.o \
display/intel_vrr.o \
+ display/intel_wd.o \
display/vlv_dsi.o \
display/vlv_dsi_pll.o
diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c b/drivers/gpu/drm/i915/display/intel_acpi.c
index e78430001f07..ae08db164f73 100644
--- a/drivers/gpu/drm/i915/display/intel_acpi.c
+++ b/drivers/gpu/drm/i915/display/intel_acpi.c
@@ -247,6 +247,7 @@ static u32 acpi_display_type(struct intel_connector *connector)
case DRM_MODE_CONNECTOR_LVDS:
case DRM_MODE_CONNECTOR_eDP:
case DRM_MODE_CONNECTOR_DSI:
+ case DRM_MODE_CONNECTOR_WRITEBACK:
display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL;
break;
case DRM_MODE_CONNECTOR_Unknown:
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 6792a9056f46..66d552758720 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -491,6 +491,9 @@ void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
if (new_crtc_state->do_async_flip)
return;
+ if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
+ return;
+
if (intel_crtc_needs_vblank_work(new_crtc_state))
intel_crtc_vblank_work_init(new_crtc_state);
@@ -638,6 +641,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
if (new_crtc_state->do_async_flip)
return;
+ if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
+ return;
+
trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index e9212f69c360..8435065f3b7d 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -71,6 +71,7 @@ static const char * const output_type_str[] = {
OUTPUT_TYPE(DSI),
OUTPUT_TYPE(DDI),
OUTPUT_TYPE(DP_MST),
+ OUTPUT_TYPE(WD),
};
#undef OUTPUT_TYPE
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 643832d55c28..ea8e07a957ab 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1953,6 +1953,12 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
*/
if (encoder->type == INTEL_OUTPUT_DP_MST)
return;
+ /*
+ * WD transcoder is a virtual encoder hence sanization
+ * is not required for it
+ */
+ if (encoder->type == INTEL_OUTPUT_WD)
+ return;
if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
u8 pipe_mask;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2d0018ae34b1..15b2b7a6a110 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -115,6 +115,7 @@
#include "intel_sprite.h"
#include "intel_tc.h"
#include "intel_vga.h"
+#include "intel_wd.h"
#include "i9xx_plane.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
@@ -1511,6 +1512,10 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state)
continue;
intel_connector = to_intel_connector(connector);
+ /* intel_connector instance is not created for WD transcoder */
+ if (!intel_connector)
+ continue;
+
encoder = intel_connector_primary_encoder(intel_connector);
if (!encoder->update_prepare)
continue;
@@ -1540,6 +1545,10 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state)
continue;
intel_connector = to_intel_connector(connector);
+ /* intel_connector instance is not created for WD transcoder */
+ if (!intel_connector)
+ continue;
+
encoder = intel_connector_primary_encoder(intel_connector);
if (!encoder->update_complete)
continue;
@@ -1550,6 +1559,37 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state)
}
}
+static void intel_queue_writeback_job(struct intel_atomic_state *state)
+{
+ struct drm_connector_state *new_conn_state;
+ struct drm_connector *connector;
+ struct drm_writeback_connector *wb_conn;
+ int i;
+
+ for_each_new_connector_in_state(&state->base, connector, new_conn_state,
+ i) {
+ if (!new_conn_state->writeback_job)
+ continue;
+
+ wb_conn = drm_connector_to_writeback(connector);
+ drm_writeback_queue_job(wb_conn, new_conn_state);
+ }
+}
+
+static void intel_enable_writeback_capture(struct intel_atomic_state *state,struct intel_crtc_state *crtc_state)
+{
+ struct drm_connector_state *new_conn_state;
+ struct drm_connector *connector;
+ int i;
+
+ for_each_new_connector_in_state(&state->base, connector, new_conn_state,
+ i) {
+ if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
+ continue;
+ intel_wd_enable_capture(crtc_state, new_conn_state);
+ }
+}
+
static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -1650,8 +1690,12 @@ static void intel_encoders_post_disable(struct intel_atomic_state *state,
int i;
for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
- struct intel_encoder *encoder =
- to_intel_encoder(old_conn_state->best_encoder);
+ struct intel_encoder *encoder;
+
+ if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
+ continue;
+
+ encoder = to_intel_encoder(old_conn_state->best_encoder);
if (old_conn_state->crtc != &crtc->base)
continue;
@@ -1928,7 +1972,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
bdw_set_pipemisc(new_crtc_state);
if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
- !transcoder_is_dsi(cpu_transcoder))
+ !transcoder_is_dsi(cpu_transcoder) &&
+ !transcoder_is_wd(cpu_transcoder))
hsw_configure_cpu_transcoder(new_crtc_state);
crtc->active = true;
@@ -7528,6 +7573,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
}
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if ((new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD)))
+ intel_wd_set_vblank_event(state, crtc, new_crtc_state);
+ }
+
intel_encoders_update_prepare(state);
intel_dbuf_pre_plane_update(state);
@@ -7538,6 +7588,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_crtc_enable_flip_done(state, crtc);
}
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if ((new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD)))
+ {
+ intel_queue_writeback_job(state);
+ intel_enable_writeback_capture(state, new_crtc_state);
+ }
+ }
+
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.funcs.display->commit_modeset_enables(state);
@@ -7892,6 +7950,10 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
+ /* Initializing WD transcoder */
+ if (DISPLAY_VER(dev_priv) >= 12)
+ intel_wd_init(dev_priv, TRANSCODER_WD_0);
+
if (IS_DG2(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 102bf7d47ccc..1ee5e8600809 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -158,6 +158,11 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}
+static inline bool transcoder_is_wd(enum transcoder transcoder)
+{
+ return transcoder == TRANSCODER_WD_0 || transcoder == TRANSCODER_WD_1;
+}
+
/*
* Global legacy plane identifier. Valid only for primary/sprite
* planes on pre-g4x, and only for primary planes on g4x-bdw.
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index fe40e2a226d6..3ec11c937dbc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -550,7 +550,7 @@ static void intel_hdmi_info(struct seq_file *m,
static void intel_connector_info(struct seq_file *m,
struct drm_connector *connector)
{
- struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct intel_connector *intel_connector;
const struct drm_connector_state *conn_state = connector->state;
struct intel_encoder *encoder =
to_intel_encoder(conn_state->best_encoder);
@@ -573,6 +573,8 @@ static void intel_connector_info(struct seq_file *m,
if (!encoder)
return;
+ intel_connector = to_intel_connector(connector);
+
switch (connector->connector_type) {
case DRM_MODE_CONNECTOR_DisplayPort:
case DRM_MODE_CONNECTOR_eDP:
@@ -590,12 +592,15 @@ static void intel_connector_info(struct seq_file *m,
break;
}
- seq_puts(m, "\tHDCP version: ");
- intel_hdcp_info(m, intel_connector);
+ if (intel_connector) {
+ seq_puts(m, "\tHDCP version: ");
+ intel_hdcp_info(m, intel_connector);
+ }
seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc);
- intel_panel_info(m, intel_connector);
+ if (intel_connector)
+ intel_panel_info(m, intel_connector);
seq_printf(m, "\tmodes:\n");
list_for_each_entry(mode, &connector->modes, head)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8eacb9133fce..7931dbacaba7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -44,6 +44,7 @@
#include <drm/drm_vblank.h>
#include <drm/drm_vblank_work.h>
#include <drm/i915_mei_hdcp_interface.h>
+#include <drm/drm_writeback.h>
#include <media/cec-notifier.h>
#include "i915_vma.h"
@@ -1371,6 +1372,11 @@ struct intel_crtc {
bool cpu_fifo_underrun_disabled;
bool pch_fifo_underrun_disabled;
+ struct {
+ struct drm_pending_vblank_event *e;
+ atomic_t work_busy;
+ wait_queue_head_t wd_wait;
+ } wd;
/* per-pipe watermark state */
struct {
/* watermarks currently being used */
@@ -1498,7 +1504,6 @@ struct cxsr_latency {
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
-#define to_intel_wb_connector(x) container_of(x, struct intel_wb_connector, base)
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
@@ -2077,8 +2082,8 @@ intel_connector_list_iter_next(struct drm_connector_list_iter *iter)
struct drm_connector *connector;
bool flag = true;
/*
- * Skipping connector that are Writeback connector as they will
- * not be embedded in intel connector
+ * An intel_connector entity is not created for a writeback
+ * connector hence decoupling.
*/
while (flag) {
connector = drm_connector_list_iter_next(iter);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 52f2fe1735da..411f3366b9de 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -940,6 +940,9 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
intel_get_crtc_new_encoder(state, crtc_state);
int ret;
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD))
+ return 0;
+
if (DISPLAY_VER(dev_priv) < 11 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
@@ -968,6 +971,9 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD))
+ return 0;
+
if (DISPLAY_VER(dev_priv) < 11 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index e1a90331c230..15792a5dd04c 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -24,6 +24,7 @@
#include "intel_pch_display.h"
#include "intel_pm.h"
#include "skl_watermark.h"
+#include "intel_wd.h"
static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct drm_modeset_acquire_ctx *ctx)
@@ -111,17 +112,17 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915)
{
- struct intel_connector *connector;
+ struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
drm_connector_list_iter_begin(&i915->drm, &conn_iter);
- for_each_intel_connector_iter(connector, &conn_iter) {
- struct drm_connector_state *conn_state = connector->base.state;
+ drm_for_each_connector_iter(connector, &conn_iter) {
+ struct drm_connector_state *conn_state = connector->state;
struct intel_encoder *encoder =
- to_intel_encoder(connector->base.encoder);
+ to_intel_encoder(connector->encoder);
if (conn_state->crtc)
- drm_connector_put(&connector->base);
+ drm_connector_put(connector);
if (encoder) {
struct intel_crtc *crtc =
@@ -133,7 +134,7 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private
conn_state->crtc = &crtc->base;
conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
- drm_connector_get(&connector->base);
+ drm_connector_get(connector);
} else {
conn_state->best_encoder = NULL;
conn_state->crtc = NULL;
@@ -433,6 +434,8 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
struct intel_crtc *crtc;
struct intel_encoder *encoder;
struct intel_connector *connector;
+ struct drm_connector *_connector;
+ struct drm_encoder *_encoder;
struct drm_connector_list_iter conn_iter;
u8 active_pipes = 0;
@@ -509,38 +512,70 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
intel_dpll_readout_hw_state(i915);
drm_connector_list_iter_begin(&i915->drm, &conn_iter);
- for_each_intel_connector_iter(connector, &conn_iter) {
- if (connector->get_hw_state(connector)) {
- struct intel_crtc_state *crtc_state;
- struct intel_crtc *crtc;
-
- connector->base.dpms = DRM_MODE_DPMS_ON;
-
- encoder = intel_attached_encoder(connector);
- connector->base.encoder = &encoder->base;
-
- crtc = to_intel_crtc(encoder->base.crtc);
- crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
-
- if (crtc_state && crtc_state->hw.active) {
- /*
- * This has to be done during hardware readout
- * because anything calling .crtc_disable may
- * rely on the connector_mask being accurate.
- */
- crtc_state->uapi.connector_mask |=
- drm_connector_mask(&connector->base);
- crtc_state->uapi.encoder_mask |=
- drm_encoder_mask(&encoder->base);
+ drm_for_each_connector_iter(_connector, &conn_iter) {
+ struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ struct drm_writeback_connector *wb_conn;
+ struct intel_wd *intel_wd;
+
+ connector = to_intel_connector(_connector);
+ if (!connector) {
+ wb_conn = drm_connector_to_writeback(_connector);
+ intel_wd = wb_conn_to_intel_wd(wb_conn);
+ _encoder = &intel_wd->base.base;
+ _connector->encoder = _encoder;
+ encoder = to_intel_encoder(_encoder);
+ pipe = 0;
+ if (encoder->get_hw_state(encoder, &pipe)) {
+ _connector->dpms = DRM_MODE_DPMS_ON;
+ crtc = to_intel_crtc(_encoder->crtc);
+ crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
+
+ if (crtc_state && crtc_state->hw.active) {
+ /*
+ * This has to be done during hardware readout
+ * because anything calling .crtc_disable may
+ * rely on the connector_mask being accurate.
+ */
+ crtc_state->uapi.connector_mask |=
+ drm_connector_mask(&connector->base);
+ crtc_state->uapi.encoder_mask |=
+ drm_encoder_mask(&encoder->base);
+ }
+ } else {
+ _connector->dpms = DRM_MODE_DPMS_OFF;
+ _connector->encoder = NULL;
}
} else {
- connector->base.dpms = DRM_MODE_DPMS_OFF;
- connector->base.encoder = NULL;
+ if (connector->get_hw_state(connector)) {
+ connector->base.dpms = DRM_MODE_DPMS_OFF;
+ encoder = intel_attached_encoder(connector);
+ connector->base.encoder = &encoder->base;
+
+ crtc = to_intel_crtc(encoder->base.crtc);
+ crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
+
+ if (crtc_state && crtc_state->hw.active) {
+ /*
+ * This has to be done during hardware readout
+ * because anything calling .crtc_disable may
+ * rely on the connector_mask being accurate.
+ */
+ crtc_state->uapi.connector_mask |=
+ drm_connector_mask(&connector->base);
+ crtc_state->uapi.encoder_mask |=
+ drm_encoder_mask(&encoder->base);
+ }
+ } else {
+ connector->base.dpms = DRM_MODE_DPMS_OFF;
+ connector->base.encoder = NULL;
+ }
}
drm_dbg_kms(&i915->drm,
- "[CONNECTOR:%d:%s] hw state readout: %s\n",
- connector->base.base.id, connector->base.name,
- str_enabled_disabled(connector->base.encoder));
+ "[CONNECTOR:%d:%s] hw state readout: %s\n",
+ _connector->base.id, _connector->name,
+ str_enabled_disabled(_connector->encoder));
+
}
drm_connector_list_iter_end(&conn_iter);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 0fdcf2e6d57f..80e9840e2e5f 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -25,11 +25,16 @@
static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
- struct intel_connector *connector = to_intel_connector(conn_state->connector);
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct drm_connector *_connector = conn_state->connector;
+ struct intel_connector *connector;
+ struct drm_i915_private *i915 = to_i915(_connector->dev);
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
- connector->base.base.id, connector->base.name);
+ _connector->base.id, _connector->name);
+
+ connector = to_intel_connector(_connector);
+ if (!connector)
+ return;
if (connector->get_hw_state(connector)) {
struct intel_encoder *encoder = intel_attached_encoder(connector);
@@ -119,6 +124,9 @@ verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_stat
encoder->base.base.id,
encoder->base.name);
+ if (encoder->type == INTEL_OUTPUT_WD)
+ continue;
+
for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
new_conn_state, i) {
if (old_conn_state->best_encoder == &encoder->base)
@@ -177,6 +185,9 @@ verify_crtc_state(struct intel_crtc *crtc,
intel_crtc_get_pipe_config(pipe_config);
+ if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
+ return;
+
/* we keep both pipes enabled on 830 */
if (IS_I830(dev_priv) && pipe_config->hw.active)
pipe_config->hw.active = new_crtc_state->hw.active;
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index caa07ef34f21..1bcb4b58d992 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -374,6 +374,9 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
if (ret)
return ret;
+ if (intel_encoder->type == INTEL_OUTPUT_WD)
+ return 0;
+
if (intel_encoder->type == INTEL_OUTPUT_DSI)
port = 0;
else
diff --git a/drivers/gpu/drm/i915/display/intel_wd.c b/drivers/gpu/drm/i915/display/intel_wd.c
new file mode 100644
index 000000000000..e3e990f4f26f
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_wd.c
@@ -0,0 +1,695 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_fourcc.h>
+
+#include "intel_atomic.h"
+#include "intel_connector.h"
+#include "intel_wd.h"
+#include "intel_fb_pin.h"
+#include "intel_de.h"
+
+enum {
+ WD_CAPTURE_4_PIX,
+ WD_CAPTURE_2_PIX,
+} wd_capture_format;
+
+struct drm_writeback_job
+*intel_get_writeback_job_from_queue(struct intel_wd *intel_wd)
+{
+ struct drm_writeback_job *job;
+ struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev);
+ struct drm_writeback_connector *wb_conn =
+ &intel_wd->wb_conn;
+ unsigned long flags;
+
+ spin_lock_irqsave(&wb_conn->job_lock, flags);
+ job = list_first_entry_or_null(&wb_conn->job_queue,
+ struct drm_writeback_job,
+ list_entry);
+ spin_unlock_irqrestore(&wb_conn->job_lock, flags);
+ if (job == NULL) {
+ drm_dbg_kms(&i915->drm, "job queue is empty\n");
+ return NULL;
+ }
+
+ return job;
+}
+
+static const u32 wd_fmts[] = {
+ DRM_FORMAT_YUV444,
+ DRM_FORMAT_XYUV8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_Y410,
+ DRM_FORMAT_YUV422,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_RGB565,
+};
+
+static int intel_wd_get_format(int pixel_format)
+{
+ int wd_format = -EINVAL;
+
+ switch (pixel_format) {
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_XYUV8888:
+ case DRM_FORMAT_YUV444:
+ wd_format = WD_CAPTURE_4_PIX;
+ break;
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_RGB565:
+ wd_format = WD_CAPTURE_2_PIX;
+ break;
+ default:
+ DRM_ERROR("unsupported pixel format %x!\n",
+ pixel_format);
+ }
+
+ return wd_format;
+}
+
+static int intel_wd_verify_pix_format(int format)
+{
+ const struct drm_format_info *info = drm_format_info(format);
+ int pix_format = info->format;
+ int i = 0;
+
+ for (i = 0; i < ARRAY_SIZE(wd_fmts); i++)
+ if (pix_format == wd_fmts[i])
+ return 0;
+
+ return true;
+}
+
+static u32 intel_wd_get_stride(const struct intel_crtc_state *crtc_state,
+ int format)
+{
+ const struct drm_format_info *info = drm_format_info(format);
+ int wd_format;
+ int hactive, pixel_size;
+
+ wd_format = intel_wd_get_format(info->format);
+
+ switch (wd_format) {
+ case WD_CAPTURE_4_PIX:
+ pixel_size = 4;
+ break;
+ case WD_CAPTURE_2_PIX:
+ pixel_size = 2;
+ break;
+ default:
+ pixel_size = 1;
+ break;
+ }
+
+ hactive = crtc_state->hw.adjusted_mode.crtc_hdisplay;
+
+ return DIV_ROUND_UP(hactive * pixel_size, 64);
+}
+
+static int intel_wd_pin_fb(struct intel_wd *intel_wd,
+ struct drm_framebuffer *fb)
+{
+ const struct i915_gtt_view view = {
+ .type = I915_GTT_VIEW_NORMAL,
+ };
+ struct i915_vma *vma;
+
+ vma = intel_pin_and_fence_fb_obj(fb, false, &view, false,
+ &intel_wd->flags);
+
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ intel_wd->vma = vma;
+ return 0;
+}
+
+static void intel_configure_slicing_strategy(struct drm_i915_private *i915,
+ struct intel_wd *intel_wd,
+ u32 *tmp)
+{
+ *tmp &= ~WD_STRAT_MASK;
+ if (intel_wd->slicing_strategy == 1)
+ *tmp |= WD_SLICING_STRAT_1_1;
+ else if (intel_wd->slicing_strategy == 2)
+ *tmp |= WD_SLICING_STRAT_2_1;
+ else if (intel_wd->slicing_strategy == 3)
+ *tmp |= WD_SLICING_STRAT_4_1;
+ else if (intel_wd->slicing_strategy == 4)
+ *tmp |= WD_SLICING_STRAT_8_1;
+
+ intel_de_write(i915, WD_STREAMCAP_CTL(intel_wd->trans),
+ *tmp);
+}
+
+static enum drm_mode_status
+intel_wd_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ return MODE_OK;
+}
+
+static int intel_wd_get_modes(struct drm_connector *connector)
+{
+ return 0;
+}
+
+static void intel_wd_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct intel_crtc *intel_crtc =
+ to_intel_crtc(pipe_config->uapi.crtc);
+
+ if (intel_crtc) {
+ memcpy(pipe_config, intel_crtc->config,
+ sizeof(*pipe_config));
+ pipe_config->output_types |= BIT(INTEL_OUTPUT_WD);
+ }
+}
+
+static int intel_wd_compute_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state)
+{
+ struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
+ struct drm_writeback_job *job;
+
+ job = intel_get_writeback_job_from_queue(intel_wd);
+ if (job || conn_state->writeback_job) {
+ /*
+ * Saving reference of pipe/crtc for later use if
+ * writeback job is present
+ */
+ intel_wd->wd_crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ return 0;
+ }
+
+ return 0;
+}
+
+static void intel_wd_get_power_domains(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_display_power_get(i915, encoder->power_domain);
+
+ intel_wd->io_wakeref[0] = wakeref;
+}
+
+static bool intel_wd_get_hw_state(struct intel_encoder *encoder,
+ enum pipe *pipe)
+{
+ bool ret = false;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
+ struct intel_crtc *wd_crtc = intel_wd->wd_crtc;
+ intel_wakeref_t wakeref;
+ u32 tmp;
+
+ if (wd_crtc)
+ return false;
+
+ wakeref = intel_display_power_get_if_enabled(dev_priv,
+ encoder->power_domain);
+
+ if (!wakeref)
+ goto out;
+
+ tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
+ ret = tmp & WD_TRANS_ACTIVE;
+ if (ret) {
+ *pipe = wd_crtc->pipe;
+ return true;
+ }
+
+out:
+ intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
+ return false;
+}
+
+static int intel_wd_encoder_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_st,
+ struct drm_connector_state *conn_st)
+{
+ /* Check for the format and buffers and property validity */
+ struct drm_framebuffer *fb;
+ struct drm_writeback_job *job = conn_st->writeback_job;
+ struct drm_i915_private *i915 = to_i915(encoder->dev);
+ const struct drm_display_mode *mode = &crtc_st->mode;
+ int ret;
+
+ if (!job) {
+ drm_dbg_kms(&i915->drm, "No writeback job created returning\n");
+ return -EINVAL;
+ }
+
+ fb = job->fb;
+ if (!fb) {
+ drm_dbg_kms(&i915->drm, "Invalid framebuffer\n");
+ return -EINVAL;
+ }
+
+ if (fb->width != mode->hdisplay || fb->height != mode->vdisplay) {
+ drm_dbg_kms(&i915->drm, "Invalid framebuffer size %ux%u\n",
+ fb->width, fb->height);
+ return -EINVAL;
+ }
+
+ ret = intel_wd_verify_pix_format(fb->format->format);
+ if (ret) {
+ drm_dbg_kms(&i915->drm, "Unsupported framebuffer format %08x\n",
+ fb->format->format);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+
+static const struct drm_encoder_helper_funcs wd_encoder_helper_funcs = {
+ .atomic_check = intel_wd_encoder_atomic_check,
+};
+
+static void intel_wd_connector_destroy(struct drm_connector *connector)
+{
+ drm_connector_cleanup(connector);
+}
+
+static enum drm_connector_status
+intel_wd_connector_detect(struct drm_connector *connector, bool force)
+{
+ return connector_status_connected;
+}
+
+static const struct drm_connector_funcs wb_connector_funcs = {
+ .detect = intel_wd_connector_detect,
+ .reset = drm_atomic_helper_connector_reset,
+ .destroy = intel_wd_connector_destroy,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+};
+
+static const struct drm_connector_helper_funcs wb_connector_helper_funcs = {
+ .get_modes = intel_wd_get_modes,
+ .mode_valid = intel_wd_mode_valid,
+};
+
+static const struct drm_encoder_funcs drm_writeback_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static bool intel_fastset_dis(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ return false;
+}
+
+static void intel_wd_connector_init(struct intel_wd *intel_wd)
+{
+ drm_atomic_helper_connector_reset(&intel_wd->wb_conn.base);
+}
+
+static void intel_wd_disable_capture(struct intel_wd *intel_wd)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_wd->base.base.dev);
+ u32 tmp;
+
+ intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), 0xFF);
+ tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
+ tmp &= WD_TRANS_DISABLE;
+ intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp);
+ tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans));
+}
+
+void intel_wd_init(struct drm_i915_private *i915, enum transcoder trans)
+{
+ struct intel_wd *intel_wd;
+ struct intel_encoder *encoder;
+ struct drm_writeback_connector *wb_conn;
+ int n_formats = ARRAY_SIZE(wd_fmts);
+ struct drm_encoder *drm_enc;
+ int err, ret;
+
+ intel_wd = kzalloc(sizeof(*intel_wd), GFP_KERNEL);
+ if (!intel_wd)
+ return;
+
+ intel_wd_connector_init(intel_wd);
+ encoder = &intel_wd->base;
+ drm_enc = &encoder->base;
+ wb_conn = &intel_wd->wb_conn;
+ intel_wd->trans = trans;
+ intel_wd->triggered_cap_mode = 1;
+ intel_wd->frame_num = 1;
+ intel_wd->slicing_strategy = 1;
+ encoder->get_config = intel_wd_get_config;
+ encoder->compute_config = intel_wd_compute_config;
+ encoder->get_hw_state = intel_wd_get_hw_state;
+ encoder->type = INTEL_OUTPUT_WD;
+ encoder->cloneable = 0;
+ encoder->pipe_mask = ~0;
+ encoder->power_domain = POWER_DOMAIN_TRANSCODER_B;
+ encoder->get_power_domains = intel_wd_get_power_domains;
+ encoder->initial_fastset_check = intel_fastset_dis;
+
+ drm_encoder_helper_add(drm_enc,
+ &wd_encoder_helper_funcs);
+
+ drm_enc->possible_crtcs = ~0;
+ ret = drm_encoder_init(&i915->drm, drm_enc,
+ &drm_writeback_encoder_funcs,
+ DRM_MODE_ENCODER_VIRTUAL, NULL);
+
+ if (ret) {
+ drm_dbg_kms(&i915->drm,
+ "Writeback drm_encoder init Failed: %d\n",
+ ret);
+ goto cleanup;
+ }
+
+ err = drm_writeback_connector_init_with_encoder(&i915->drm,
+ wb_conn, drm_enc, &wb_connector_funcs,
+ wd_fmts, n_formats);
+
+ if (err != 0) {
+ drm_dbg_kms(&i915->drm,
+ "drm_writeback_connector_init: Failed: %d\n",
+ err);
+ goto cleanup;
+ }
+
+ wb_conn->base.encoder = drm_enc;
+ drm_connector_helper_add(&wb_conn->base, &wb_connector_helper_funcs);
+ wb_conn->base.status = connector_status_connected;
+ return;
+
+cleanup:
+ kfree(intel_wd);
+ return;
+}
+
+static void intel_wd_writeback_complete(struct intel_wd *intel_wd,
+ struct drm_writeback_job *job,
+ int status)
+{
+ struct drm_writeback_connector *wb_conn =
+ &intel_wd->wb_conn;
+ drm_writeback_signal_completion(wb_conn, status);
+}
+
+static int intel_wd_setup_transcoder(struct intel_wd *intel_wd,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct drm_writeback_job *job)
+{
+ struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ struct drm_framebuffer *fb;
+ struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+ struct drm_gem_object *wd_fb_obj;
+ int ret;
+ u32 stride, tmp;
+ u16 hactive, vactive;
+
+ fb = job->fb;
+ wd_fb_obj = fb->obj[0];
+ if (!wd_fb_obj) {
+ drm_dbg_kms(&dev_priv->drm, "No framebuffer gem object created\n");
+ return -EINVAL;
+ }
+
+ ret = intel_wd_pin_fb(intel_wd, fb);
+ drm_WARN_ON(&dev_priv->drm, ret != 0);
+ /* Write stride and surface registers in that particular order */
+ stride = intel_wd_get_stride(pipe_config, fb->format->format);
+
+ tmp = intel_de_read(dev_priv, WD_STRIDE(intel_wd->trans));
+ tmp &= ~WD_STRIDE_MASK;
+ tmp |= (stride << WD_STRIDE_SHIFT);
+
+ intel_de_write(dev_priv, WD_STRIDE(intel_wd->trans), tmp);
+
+ tmp = intel_de_read(dev_priv, WD_SURF(intel_wd->trans));
+
+ intel_de_write(dev_priv, WD_SURF(intel_wd->trans),
+ i915_ggtt_offset(intel_wd->vma));
+
+ tmp = intel_de_read_fw(dev_priv, WD_IIR(intel_wd->trans));
+ intel_de_write_fw(dev_priv, WD_IIR(intel_wd->trans), tmp);
+
+ tmp = ~(WD_GTT_FAULT_INT | WD_WRITE_COMPLETE_INT | WD_FRAME_COMPLETE_INT |
+ WD_VBLANK_INT | WD_OVERRUN_INT | WD_CAPTURING_INT);
+ intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), tmp);
+
+ if (intel_wd->stream_cap) {
+ tmp = intel_de_read(dev_priv,
+ WD_STREAMCAP_CTL(intel_wd->trans));
+ tmp |= WD_STREAM_CAP_MODE_EN;
+ intel_configure_slicing_strategy(dev_priv, intel_wd, &tmp);
+ }
+
+ hactive = pipe_config->uapi.mode.hdisplay;
+ vactive = pipe_config->uapi.mode.vdisplay;
+ tmp = intel_de_read(dev_priv, HTOTAL(intel_wd->trans));
+ tmp = intel_de_read(dev_priv, VTOTAL(intel_wd->trans));
+
+ /* minimum hactive as per bspec: 64 pixels */
+ if (hactive < 64)
+ drm_err(&dev_priv->drm, "hactive is less then 64 pixels\n");
+
+ intel_de_write(dev_priv, HTOTAL(intel_wd->trans), hactive - 1);
+ intel_de_write(dev_priv, VTOTAL(intel_wd->trans), vactive - 1);
+
+ tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans));
+ /* select pixel format */
+ tmp &= ~WD_PIX_FMT_MASK;
+
+ switch (fb->format->format) {
+ default:
+ fallthrough;
+ case DRM_FORMAT_YUYV:
+ tmp |= WD_PIX_FMT_YUYV;
+ break;
+ case DRM_FORMAT_XYUV8888:
+ tmp |= WD_PIX_FMT_XYUV8888;
+ break;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_XRGB8888:
+ tmp |= WD_PIX_FMT_XBGR8888;
+ break;
+ case DRM_FORMAT_Y410:
+ tmp |= WD_PIX_FMT_Y410;
+ break;
+ case DRM_FORMAT_YUV422:
+ tmp |= WD_PIX_FMT_YUV422;
+ break;
+ case DRM_FORMAT_XBGR2101010:
+ tmp |= WD_PIX_FMT_XBGR2101010;
+ break;
+ case DRM_FORMAT_RGB565:
+ tmp |= WD_PIX_FMT_RGB565;
+ break;
+ }
+
+ if (intel_wd->triggered_cap_mode)
+ tmp |= WD_TRIGGERED_CAP_MODE_ENABLE;
+
+ if (intel_wd->stream_cap)
+ tmp |= WD_CTL_POINTER_DTDH;
+
+ /* select input pipe */
+ tmp &= ~WD_INPUT_SELECT_MASK;
+ switch (pipe) {
+ default:
+ fallthrough;
+ case PIPE_A:
+ tmp |= WD_INPUT_PIPE_A;
+ break;
+ case PIPE_B:
+ tmp |= WD_INPUT_PIPE_B;
+ break;
+ case PIPE_C:
+ tmp |= WD_INPUT_PIPE_C;
+ break;
+ case PIPE_D:
+ tmp |= WD_INPUT_PIPE_D;
+ break;
+ }
+
+ /* enable DDI buffer */
+ if (!(tmp & TRANS_WD_FUNC_ENABLE))
+ tmp |= TRANS_WD_FUNC_ENABLE;
+
+ intel_de_write(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans), tmp);
+
+ tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
+ ret = tmp & WD_TRANS_ACTIVE;
+ if (!ret) {
+ /* enable the transcoder */
+ tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
+ tmp |= WD_TRANS_ENABLE;
+ intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp);
+
+ /* wait for transcoder to be enabled */
+ if (intel_de_wait_for_set(dev_priv, PIPECONF(intel_wd->trans),
+ WD_TRANS_ACTIVE, 10))
+ drm_err(&dev_priv->drm, "WD transcoder could not be enabled\n");
+ }
+
+ return 0;
+}
+
+static int intel_wd_capture(struct intel_wd *intel_wd,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct drm_writeback_job *job)
+{
+ u32 tmp;
+ struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev);
+ int ret = 0, status = 0;
+ struct intel_crtc *wd_crtc = intel_wd->wd_crtc;
+ unsigned long flags;
+
+ if (!job->out_fence)
+ drm_dbg_kms(&i915->drm, "Not able to get out_fence for job\n");
+
+ ret = intel_wd_setup_transcoder(intel_wd, pipe_config,
+ conn_state, job);
+
+ if (ret < 0) {
+ drm_dbg_kms(&i915->drm,
+ "WD transcoder setup not completed aborting capture\n");
+ return -1;
+ }
+
+ if (!wd_crtc) {
+ drm_err(&i915->drm, "CRTC not attached\n");
+ return -1;
+ }
+
+ tmp = intel_de_read_fw(i915, WD_TRANS_FUNC_CTL(intel_wd->trans));
+ tmp |= START_TRIGGER_FRAME;
+ tmp &= ~WD_FRAME_NUMBER_MASK;
+ tmp |= intel_wd->frame_num;
+ intel_de_write_fw(i915, WD_TRANS_FUNC_CTL(intel_wd->trans), tmp);
+
+ if (!intel_de_wait_for_set(i915, WD_IIR(intel_wd->trans),
+ WD_FRAME_COMPLETE_INT, 100)){
+ drm_dbg_kms(&i915->drm, "frame captured\n");
+ status = 0;
+ } else {
+ drm_dbg_kms(&i915->drm, "frame not captured triggering stop frame\n");
+ tmp = intel_de_read(i915, WD_TRANS_FUNC_CTL(intel_wd->trans));
+ tmp |= STOP_TRIGGER_FRAME;
+ intel_de_write(i915, WD_TRANS_FUNC_CTL(intel_wd->trans), tmp);
+ status = -1;
+ }
+
+ intel_wd_writeback_complete(intel_wd, job, status);
+ if (wd_crtc->wd.e) {
+ spin_lock_irqsave(&i915->drm.event_lock, flags);
+ drm_dbg_kms(&i915->drm, "send %p\n", wd_crtc->wd.e);
+ drm_crtc_send_vblank_event(&wd_crtc->base,
+ wd_crtc->wd.e);
+ spin_unlock_irqrestore(&i915->drm.event_lock, flags);
+ wd_crtc->wd.e = NULL;
+ } else {
+ drm_err(&i915->drm, "Event NULL! %p, %p\n", &i915->drm,
+ wd_crtc);
+ }
+ if (!intel_get_writeback_job_from_queue(intel_wd))
+ intel_wd_disable_capture(intel_wd);
+ return 0;
+}
+
+void intel_wd_enable_capture(struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state)
+{
+ struct drm_i915_private *i915 =
+ to_i915(conn_state->connector->dev);
+ struct drm_writeback_connector *wb_conn =
+ drm_connector_to_writeback(conn_state->connector);
+ struct intel_wd *intel_wd = wb_conn_to_intel_wd(wb_conn);
+ struct drm_writeback_job *job;
+
+ job = intel_get_writeback_job_from_queue(intel_wd);
+ if (!job) {
+ drm_dbg_kms(&i915->drm,
+ "job queue is empty not capturing any frame\n");
+ return;
+ }
+
+ intel_wd_capture(intel_wd, pipe_config,
+ conn_state, job);
+ intel_wd->frame_num += 1;
+}
+
+void intel_wd_set_vblank_event(struct intel_atomic_state *state, struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *intel_crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev);
+ struct drm_crtc_state *crtc_state = &intel_crtc_state->uapi;
+ struct intel_encoder *encoder;
+ struct intel_wd *intel_wd;
+ struct drm_connector_state *conn_state;
+ struct drm_connector *connector;
+ int i;
+
+ for_each_intel_encoder(&i915->drm, encoder) {
+ if (encoder->type != INTEL_OUTPUT_WD)
+ continue;
+
+ intel_wd = enc_to_intel_wd(encoder);
+ if (!intel_wd->wd_crtc)
+ return;
+ }
+
+ if (intel_wd && intel_crtc == intel_wd->wd_crtc) {
+ for_each_new_connector_in_state(&state->base, connector, conn_state,
+ i) {
+ if (!conn_state->writeback_job)
+ continue;
+
+ intel_crtc->wd.e = crtc_state->event;
+ crtc_state->event = NULL;
+ }
+ }
+}
+
+void intel_wd_handle_isr(struct drm_i915_private *i915)
+{
+ u32 iir_value = 0;
+ struct intel_encoder *encoder;
+ struct intel_wd *intel_wd;
+
+ iir_value = intel_de_read(i915, WD_IIR(TRANSCODER_WD_0));
+
+ for_each_intel_encoder(&i915->drm, encoder) {
+
+ if (encoder->type != INTEL_OUTPUT_WD)
+ continue;
+
+ intel_wd = enc_to_intel_wd(encoder);
+ if (!intel_wd->wd_crtc) {
+ drm_err(&i915->drm, "NO CRTC attached with WD\n");
+ goto clear_iir;
+ }
+ }
+
+ if (iir_value & WD_FRAME_COMPLETE_INT)
+ return;
+
+clear_iir:
+ intel_de_write(i915, WD_IIR(TRANSCODER_WD_0), iir_value);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_wd.h b/drivers/gpu/drm/i915/display/intel_wd.h
new file mode 100644
index 000000000000..0fcd1a746593
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_wd.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: MIT*/
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _INTEL_WD_H
+#define _INTEL_WD_H
+
+#include <drm/drm_crtc.h>
+
+#include "intel_display_types.h"
+
+#define I915_MAX_WD_TANSCODERS 2
+
+struct intel_wd {
+ struct intel_encoder base;
+ struct drm_writeback_connector wb_conn;
+ struct intel_crtc *wd_crtc;
+ intel_wakeref_t io_wakeref[I915_MAX_WD_TANSCODERS];
+ enum transcoder trans;
+ struct i915_vma *vma;
+ unsigned long flags;
+ struct drm_writeback_job *job;
+ int triggered_cap_mode;
+ int frame_num;
+ bool stream_cap;
+ bool start_capture;
+ int slicing_strategy;
+};
+
+static inline struct intel_wd *enc_to_intel_wd(struct intel_encoder *encoder)
+{
+ return container_of(&encoder->base, struct intel_wd, base.base);
+}
+
+static inline struct intel_wd *wb_conn_to_intel_wd(struct drm_writeback_connector *wb_conn)
+{
+ return container_of(wb_conn, struct intel_wd, wb_conn);
+}
+
+void intel_wd_init(struct drm_i915_private *dev_priv, enum transcoder trans);
+void intel_wd_enable_capture(struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state);
+void intel_wd_handle_isr(struct drm_i915_private *dev_priv);
+void intel_wd_set_vblank_event(struct intel_atomic_state *state, struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state);
+struct drm_writeback_job *intel_get_writeback_job_from_queue(struct intel_wd *intel_wd);
+#endif/* _INTEL_WD_H */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 55794b87a6c1..503a21c77d14 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -34,6 +34,7 @@
#include <linux/pm_qos.h>
+#include <drm/drm_writeback.h>
#include <drm/ttm/ttm_device.h>
#include "display/intel_display.h"
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 86a42d9e8041..ee0255d9eb64 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -42,6 +42,7 @@
#include "display/intel_hotplug.h"
#include "display/intel_lpe_audio.h"
#include "display/intel_psr.h"
+#include "display/intel_wd.h"
#include "gt/intel_breadcrumbs.h"
#include "gt/intel_gt.h"
@@ -2342,6 +2343,11 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
found = true;
}
+ if (iir & GEN8_DE_MISC_WD0) {
+ intel_wd_handle_isr(dev_priv);
+ found = true;
+ }
+
if (iir & GEN8_DE_EDP_PSR) {
struct intel_encoder *encoder;
u32 psr_iir;
@@ -3767,7 +3773,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
u32 de_pipe_enables;
u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
u32 de_port_enables;
- u32 de_misc_masked = GEN8_DE_EDP_PSR;
+ u32 de_misc_masked = GEN8_DE_EDP_PSR | GEN8_DE_MISC_WD0;
u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
enum pipe pipe;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 19fc00bcd7b9..d6eb63aefc47 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -868,7 +868,8 @@ static const struct intel_device_info jsl_info = {
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
- BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
+ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1) | \
+ BIT(TRANSCODER_WD_0), \
.display.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
@@ -876,6 +877,8 @@ static const struct intel_device_info jsl_info = {
[TRANSCODER_D] = PIPE_D_OFFSET, \
[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+ [TRANSCODER_WD_0] = PIPE_WD0_OFFSET, \
+ [TRANSCODER_WD_1] = PIPE_WD1_OFFSET, \
}, \
.display.trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
@@ -884,6 +887,8 @@ static const struct intel_device_info jsl_info = {
[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ [TRANSCODER_WD_0] = TRANSCODER_WD0_OFFSET, \
+ [TRANSCODER_WD_1] = TRANSCODER_WD1_OFFSET, \
}, \
TGL_CURSOR_OFFSETS, \
.has_global_mocs = 1, \
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable Pipewriteback (rev4)
2022-09-14 7:12 [Intel-gfx] [PATCH v4 0/3] Enable Pipewriteback Kandpal, Suraj
` (2 preceding siblings ...)
2022-09-14 7:12 ` [Intel-gfx] [PATCH v4 3/3] drm/i915: Enabling WD Transcoder Kandpal, Suraj
@ 2022-09-14 9:19 ` Patchwork
2022-09-14 9:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-14 23:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-09-14 9:19 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
== Series Details ==
Series: Enable Pipewriteback (rev4)
URL : https://patchwork.freedesktop.org/series/107440/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Enable Pipewriteback (rev4)
2022-09-14 7:12 [Intel-gfx] [PATCH v4 0/3] Enable Pipewriteback Kandpal, Suraj
` (3 preceding siblings ...)
2022-09-14 9:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable Pipewriteback (rev4) Patchwork
@ 2022-09-14 9:32 ` Patchwork
2022-09-14 23:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-09-14 9:32 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6135 bytes --]
== Series Details ==
Series: Enable Pipewriteback (rev4)
URL : https://patchwork.freedesktop.org/series/107440/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12132 -> Patchwork_107440v4
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/index.html
Participating hosts (41 -> 41)
------------------------------
Additional (2): fi-icl-u2 fi-tgl-dsi
Missing (2): fi-ctg-p8600 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_107440v4 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][1] ([i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-icl-u2/igt@gem_lmem_swapping@random-engines.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-bdw-5557u: [PASS][3] -> [DMESG-FAIL][4] ([i915#5334])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][5] -> [DMESG-FAIL][6] ([i915#4528])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/fi-blb-e6850/igt@i915_selftest@live@requests.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-blb-e6850/igt@i915_selftest@live@requests.html
- fi-pnv-d510: [PASS][7] -> [DMESG-FAIL][8] ([i915#4528])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/fi-pnv-d510/igt@i915_selftest@live@requests.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bdw-5557u: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-bdw-5557u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#4103])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2: NOTRUN -> [WARN][12] ([i915#6008])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-icl-u2/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][13] ([fdo#109285])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2: NOTRUN -> [SKIP][14] ([i915#3555])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#109295] / [i915#3301])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-blb-e6850: NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#2403] / [i915#4312])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/fi-blb-e6850/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6008]: https://gitlab.freedesktop.org/drm/intel/issues/6008
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
Build changes
-------------
* Linux: CI_DRM_12132 -> Patchwork_107440v4
CI-20190529: 20190529
CI_DRM_12132: 6c93e979e5426070b3de3df81c468548328d1162 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6653: 4f927248ebbf11f03f4c1ea2254f011e7575322f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107440v4: 6c93e979e5426070b3de3df81c468548328d1162 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
18cf26d67c27 drm/i915: Enabling WD Transcoder
f7257e124b02 drm/i915 : Changing intel_connector iterators
3a4a84a35929 drm/i915: Define WD trancoder for i915
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/index.html
[-- Attachment #2: Type: text/html, Size: 6999 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Enable Pipewriteback (rev4)
2022-09-14 7:12 [Intel-gfx] [PATCH v4 0/3] Enable Pipewriteback Kandpal, Suraj
` (4 preceding siblings ...)
2022-09-14 9:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-09-14 23:46 ` Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-09-14 23:46 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 35088 bytes --]
== Series Details ==
Series: Enable Pipewriteback (rev4)
URL : https://patchwork.freedesktop.org/series/107440/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12132_full -> Patchwork_107440v4_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_107440v4_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107440v4_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 10)
------------------------------
Missing (1): shard-rkl
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_107440v4_full:
### IGT changes ###
#### Warnings ####
* igt@kms_writeback@writeback-check-output:
- shard-tglb: [SKIP][1] ([i915#2437]) -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglb5/igt@kms_writeback@writeback-check-output.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglb3/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-tglb: [SKIP][3] ([i915#2437]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglb7/igt@kms_writeback@writeback-fb-id.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglb5/igt@kms_writeback@writeback-fb-id.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_schedule@wide@rcs0:
- {shard-tglu}: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglu-2/igt@gem_exec_schedule@wide@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglu-6/igt@gem_exec_schedule@wide@rcs0.html
* igt@kms_prime@basic-crc-vgem@second-to-first:
- {shard-tglu}: NOTRUN -> [FAIL][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglu-4/igt@kms_prime@basic-crc-vgem@second-to-first.html
* igt@kms_writeback@writeback-check-output:
- {shard-tglu}: [SKIP][8] ([i915#2437]) -> [DMESG-FAIL][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglu-4/igt@kms_writeback@writeback-check-output.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglu-3/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- {shard-tglu}: [SKIP][10] ([i915#2437]) -> [FAIL][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglu-2/igt@kms_writeback@writeback-fb-id.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglu-3/igt@kms_writeback@writeback-fb-id.html
Known issues
------------
Here are the changes found in Patchwork_107440v4_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-skl: ([PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35]) -> ([PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [FAIL][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60]) ([i915#5032])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl9/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl9/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl9/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl9/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl9/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl6/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl6/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl6/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl6/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl6/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl3/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl3/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl3/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl10/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl10/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl10/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl10/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl10/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl10/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl10/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl10/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl10/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl10/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl10/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl3/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl3/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl3/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl6/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl6/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl6/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl6/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl6/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl7/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl7/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl7/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl7/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl7/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl9/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl9/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl9/boot.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl9/boot.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-skl9/boot.html
#### Possible fixes ####
* boot:
- shard-apl: ([FAIL][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85]) ([i915#4386]) -> ([PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl1/boot.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl1/boot.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl1/boot.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl1/boot.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl2/boot.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl2/boot.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl2/boot.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl3/boot.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl3/boot.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl3/boot.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl4/boot.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl4/boot.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl4/boot.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl6/boot.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl6/boot.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl6/boot.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl6/boot.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl7/boot.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl7/boot.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl7/boot.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl7/boot.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl8/boot.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl8/boot.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl8/boot.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl8/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-iclb: NOTRUN -> [DMESG-WARN][111] ([i915#4991])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb8/igt@gem_create@create-massive.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][112] -> [TIMEOUT][113] ([i915#3070])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-iclb1/igt@gem_eio@unwedge-stress.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb6/igt@gem_eio@unwedge-stress.html
- shard-tglb: [PASS][114] -> [FAIL][115] ([i915#5784])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglb7/igt@gem_eio@unwedge-stress.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglb1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][116] -> [SKIP][117] ([i915#4525]) +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-iclb4/igt@gem_exec_balancer@parallel-bb-first.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb8/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][118] -> [FAIL][119] ([i915#2846])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-glk2/igt@gem_exec_fair@basic-deadline.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-glk1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][120] ([i915#2842])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-glk8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][121] -> [FAIL][122] ([i915#2842])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-iclb: NOTRUN -> [SKIP][123] ([fdo#109313])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb8/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][124] -> [SKIP][125] ([i915#2190])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglb1/igt@gem_huc_copy@huc-copy.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- shard-glk: NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#4613]) +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-glk8/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-apl: NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#4613]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl7/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][128] ([i915#2658])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl8/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_softpin@evict-single-offset:
- shard-apl: NOTRUN -> [FAIL][129] ([i915#4171])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl7/igt@gem_softpin@evict-single-offset.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][130] -> [DMESG-WARN][131] ([i915#5566] / [i915#716])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/igt@gen9_exec_parse@allowed-single.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [PASS][132] -> [INCOMPLETE][133] ([i915#6775])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglb1/igt@i915_module_load@reload-with-fault-injection.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglb5/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-glk: [PASS][134] -> [FAIL][135] ([i915#1888] / [i915#5138])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-glk9/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-glk7/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][136] ([fdo#109278]) +1 similar issue
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb8/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][137] ([fdo#109271] / [i915#3886]) +2 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl8/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-audio:
- shard-apl: NOTRUN -> [SKIP][138] ([fdo#109271] / [fdo#111827]) +6 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl2/igt@kms_chamelium@hdmi-audio.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-glk: NOTRUN -> [SKIP][139] ([fdo#109271] / [fdo#111827])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-glk8/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][140] ([i915#2672]) +4 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][141] ([i915#2587] / [i915#2672]) +2 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][142] ([fdo#109280])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][143] ([fdo#108145] / [i915#265]) +1 similar issue
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-2:
- shard-glk: NOTRUN -> [SKIP][144] ([fdo#109271]) +43 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-glk8/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-2.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-iclb: NOTRUN -> [SKIP][145] ([fdo#111068] / [i915#658])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb8/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-glk: NOTRUN -> [SKIP][146] ([fdo#109271] / [i915#658])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-glk8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [PASS][147] -> [SKIP][148] ([fdo#109642] / [fdo#111068] / [i915#658])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb1/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010:
- shard-apl: NOTRUN -> [SKIP][149] ([fdo#109271] / [i915#658]) +1 similar issue
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl7/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-apl: NOTRUN -> [SKIP][150] ([fdo#109271]) +114 similar issues
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl7/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-glk: NOTRUN -> [SKIP][151] ([fdo#109271] / [i915#2437])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-glk8/igt@kms_writeback@writeback-invalid-parameters.html
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][152] ([fdo#109291])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb8/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
* igt@sysfs_clients@fair-7:
- shard-apl: NOTRUN -> [SKIP][153] ([fdo#109271] / [i915#2994])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl8/igt@sysfs_clients@fair-7.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][154] ([i915#658]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-iclb4/igt@feature_discovery@psr2.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_eio@in-flight-immediate:
- shard-tglb: [TIMEOUT][156] ([i915#3063]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglb2/igt@gem_eio@in-flight-immediate.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglb6/igt@gem_eio@in-flight-immediate.html
* igt@gem_eio@reset-stress:
- shard-tglb: [FAIL][158] ([i915#5784]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglb1/igt@gem_eio@reset-stress.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglb5/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][160] ([i915#2842]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][162] ([i915#2842]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_whisper@basic-fds-forked:
- shard-iclb: [INCOMPLETE][164] ([i915#6695]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-iclb7/igt@gem_exec_whisper@basic-fds-forked.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb8/igt@gem_exec_whisper@basic-fds-forked.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [FAIL][166] ([i915#2346]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-apl: [DMESG-WARN][168] ([i915#180]) -> [PASS][169] +1 similar issue
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][170] ([fdo#109441]) -> [PASS][171] +1 similar issue
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-tglb: [SKIP][172] ([i915#2437]) -> [PASS][173] +1 similar issue
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglb5/igt@kms_writeback@writeback-pixel-formats.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglb3/igt@kms_writeback@writeback-pixel-formats.html
#### Warnings ####
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][174] ([i915#2920]) -> [SKIP][175] ([i915#658])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@runner@aborted:
- shard-apl: ([FAIL][176], [FAIL][177], [FAIL][178], [FAIL][179]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][180], [FAIL][181], [FAIL][182]) ([fdo#109271] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/igt@runner@aborted.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl7/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl1/igt@runner@aborted.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-apl4/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#6695]: https://gitlab.freedesktop.org/drm/intel/issues/6695
[i915#6775]: https://gitlab.freedesktop.org/drm/intel/issues/6775
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
Build changes
-------------
* Linux: CI_DRM_12132 -> Patchwork_107440v4
CI-20190529: 20190529
CI_DRM_12132: 6c93e979e5426070b3de3df81c468548328d1162 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6653: 4f927248ebbf11f03f4c1ea2254f011e7575322f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107440v4: 6c93e979e5426070b3de3df81c468548328d1162 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/index.html
[-- Attachment #2: Type: text/html, Size: 35942 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v4 3/3] drm/i915: Enabling WD Transcoder
2022-09-14 7:12 ` [Intel-gfx] [PATCH v4 3/3] drm/i915: Enabling WD Transcoder Kandpal, Suraj
@ 2022-09-19 5:30 ` Murthy, Arun R
2022-09-19 6:28 ` Kandpal, Suraj
0 siblings, 1 reply; 10+ messages in thread
From: Murthy, Arun R @ 2022-09-19 5:30 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx; +Cc: Nikula, Jani
> From: Suraj Kandpal <suraj.kandpal@intel.com>
>
> Adding support for writeback transcoder to start capturing frames using
> interrupt mechanism
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
> drivers/gpu/drm/i915/display/intel_crtc.c | 6 +
> .../drm/i915/display/intel_crtc_state_dump.c | 1 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +
> drivers/gpu/drm/i915/display/intel_display.c | 68 +-
> drivers/gpu/drm/i915/display/intel_display.h | 5 +
> .../drm/i915/display/intel_display_debugfs.c | 13 +-
> .../drm/i915/display/intel_display_types.h | 11 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 6 +
> .../drm/i915/display/intel_modeset_setup.c | 103 ++-
> .../drm/i915/display/intel_modeset_verify.c | 17 +-
> drivers/gpu/drm/i915/display/intel_opregion.c | 3 +
> drivers/gpu/drm/i915/display/intel_wd.c | 695 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_wd.h | 48 ++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_irq.c | 8 +-
> drivers/gpu/drm/i915/i915_pci.c | 7 +-
> 18 files changed, 951 insertions(+), 49 deletions(-) create mode 100644
> drivers/gpu/drm/i915/display/intel_wd.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index a26edcdadc21..f34db43cf58d 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -304,6 +304,7 @@ i915-y += \
> display/intel_tv.o \
> display/intel_vdsc.o \
> display/intel_vrr.o \
> + display/intel_wd.o \
> display/vlv_dsi.o \
> display/vlv_dsi_pll.o
>
> diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c
> b/drivers/gpu/drm/i915/display/intel_acpi.c
> index e78430001f07..ae08db164f73 100644
> --- a/drivers/gpu/drm/i915/display/intel_acpi.c
> +++ b/drivers/gpu/drm/i915/display/intel_acpi.c
> @@ -247,6 +247,7 @@ static u32 acpi_display_type(struct intel_connector
> *connector)
> case DRM_MODE_CONNECTOR_LVDS:
> case DRM_MODE_CONNECTOR_eDP:
> case DRM_MODE_CONNECTOR_DSI:
> + case DRM_MODE_CONNECTOR_WRITEBACK:
> display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL;
> break;
> case DRM_MODE_CONNECTOR_Unknown:
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 6792a9056f46..66d552758720 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -491,6 +491,9 @@ void intel_pipe_update_start(struct intel_crtc_state
> *new_crtc_state)
> if (new_crtc_state->do_async_flip)
> return;
>
> + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
> + return;
> +
> if (intel_crtc_needs_vblank_work(new_crtc_state))
> intel_crtc_vblank_work_init(new_crtc_state);
>
> @@ -638,6 +641,9 @@ void intel_pipe_update_end(struct intel_crtc_state
> *new_crtc_state)
> if (new_crtc_state->do_async_flip)
> return;
>
> + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
> + return;
> +
> trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index e9212f69c360..8435065f3b7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -71,6 +71,7 @@ static const char * const output_type_str[] = {
> OUTPUT_TYPE(DSI),
> OUTPUT_TYPE(DDI),
> OUTPUT_TYPE(DP_MST),
> + OUTPUT_TYPE(WD),
> };
>
> #undef OUTPUT_TYPE
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 643832d55c28..ea8e07a957ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1953,6 +1953,12 @@ void
> intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> */
> if (encoder->type == INTEL_OUTPUT_DP_MST)
> return;
> + /*
> + * WD transcoder is a virtual encoder hence sanization
> + * is not required for it
> + */
> + if (encoder->type == INTEL_OUTPUT_WD)
> + return;
>
> if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
> u8 pipe_mask;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 2d0018ae34b1..15b2b7a6a110 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -115,6 +115,7 @@
> #include "intel_sprite.h"
> #include "intel_tc.h"
> #include "intel_vga.h"
> +#include "intel_wd.h"
> #include "i9xx_plane.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> @@ -1511,6 +1512,10 @@ static void intel_encoders_update_prepare(struct
> intel_atomic_state *state)
> continue;
>
> intel_connector = to_intel_connector(connector);
> + /* intel_connector instance is not created for WD transcoder
> */
> + if (!intel_connector)
> + continue;
> +
> encoder =
> intel_connector_primary_encoder(intel_connector);
> if (!encoder->update_prepare)
> continue;
> @@ -1540,6 +1545,10 @@ static void
> intel_encoders_update_complete(struct intel_atomic_state *state)
> continue;
>
> intel_connector = to_intel_connector(connector);
> + /* intel_connector instance is not created for WD transcoder
> */
> + if (!intel_connector)
> + continue;
> +
> encoder =
> intel_connector_primary_encoder(intel_connector);
> if (!encoder->update_complete)
> continue;
> @@ -1550,6 +1559,37 @@ static void
> intel_encoders_update_complete(struct intel_atomic_state *state)
> }
> }
>
> +static void intel_queue_writeback_job(struct intel_atomic_state *state)
> +{
> + struct drm_connector_state *new_conn_state;
> + struct drm_connector *connector;
> + struct drm_writeback_connector *wb_conn;
> + int i;
> +
> + for_each_new_connector_in_state(&state->base, connector,
> new_conn_state,
> + i) {
> + if (!new_conn_state->writeback_job)
> + continue;
> +
> + wb_conn = drm_connector_to_writeback(connector);
> + drm_writeback_queue_job(wb_conn, new_conn_state);
> + }
> +}
> +
> +static void intel_enable_writeback_capture(struct intel_atomic_state
> +*state,struct intel_crtc_state *crtc_state) {
> + struct drm_connector_state *new_conn_state;
> + struct drm_connector *connector;
> + int i;
> +
> + for_each_new_connector_in_state(&state->base, connector,
> new_conn_state,
> + i) {
> + if (connector->connector_type !=
> DRM_MODE_CONNECTOR_WRITEBACK)
> + continue;
> + intel_wd_enable_capture(crtc_state, new_conn_state);
> + }
> +}
> +
> static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -1650,8 +1690,12 @@ static void intel_encoders_post_disable(struct
> intel_atomic_state *state,
> int i;
>
> for_each_old_connector_in_state(&state->base, conn,
> old_conn_state, i) {
> - struct intel_encoder *encoder =
> - to_intel_encoder(old_conn_state->best_encoder);
> + struct intel_encoder *encoder;
> +
> + if (conn->connector_type ==
> DRM_MODE_CONNECTOR_WRITEBACK)
> + continue;
> +
> + encoder = to_intel_encoder(old_conn_state->best_encoder);
>
> if (old_conn_state->crtc != &crtc->base)
> continue;
> @@ -1928,7 +1972,8 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
> bdw_set_pipemisc(new_crtc_state);
>
> if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
> - !transcoder_is_dsi(cpu_transcoder))
> + !transcoder_is_dsi(cpu_transcoder) &&
> + !transcoder_is_wd(cpu_transcoder))
> hsw_configure_cpu_transcoder(new_crtc_state);
>
> crtc->active = true;
> @@ -7528,6 +7573,11 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> }
> }
>
> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + if ((new_crtc_state->output_types &
> BIT(INTEL_OUTPUT_WD)))
> + intel_wd_set_vblank_event(state, crtc,
> new_crtc_state);
> + }
> +
> intel_encoders_update_prepare(state);
>
> intel_dbuf_pre_plane_update(state);
> @@ -7538,6 +7588,14 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> intel_crtc_enable_flip_done(state, crtc);
> }
>
> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + if ((new_crtc_state->output_types &
> BIT(INTEL_OUTPUT_WD)))
> + {
> + intel_queue_writeback_job(state);
> + intel_enable_writeback_capture(state,
> new_crtc_state);
> + }
> + }
> +
> /* Now enable the clocks, plane, pipe, and connectors that we set
> up. */
> dev_priv->display.funcs.display->commit_modeset_enables(state);
>
> @@ -7892,6 +7950,10 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> + /* Initializing WD transcoder */
> + if (DISPLAY_VER(dev_priv) >= 12)
> + intel_wd_init(dev_priv, TRANSCODER_WD_0);
> +
> if (IS_DG2(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 102bf7d47ccc..1ee5e8600809 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -158,6 +158,11 @@ static inline bool transcoder_is_dsi(enum
> transcoder transcoder)
> return transcoder == TRANSCODER_DSI_A || transcoder ==
> TRANSCODER_DSI_C; }
>
> +static inline bool transcoder_is_wd(enum transcoder transcoder) {
> + return transcoder == TRANSCODER_WD_0 || transcoder ==
> TRANSCODER_WD_1;
> +}
> +
> /*
> * Global legacy plane identifier. Valid only for primary/sprite
> * planes on pre-g4x, and only for primary planes on g4x-bdw.
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index fe40e2a226d6..3ec11c937dbc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -550,7 +550,7 @@ static void intel_hdmi_info(struct seq_file *m, static
> void intel_connector_info(struct seq_file *m,
> struct drm_connector *connector)
> {
> - struct intel_connector *intel_connector =
> to_intel_connector(connector);
> + struct intel_connector *intel_connector;
> const struct drm_connector_state *conn_state = connector->state;
> struct intel_encoder *encoder =
> to_intel_encoder(conn_state->best_encoder);
> @@ -573,6 +573,8 @@ static void intel_connector_info(struct seq_file *m,
> if (!encoder)
> return;
>
> + intel_connector = to_intel_connector(connector);
> +
> switch (connector->connector_type) {
> case DRM_MODE_CONNECTOR_DisplayPort:
> case DRM_MODE_CONNECTOR_eDP:
> @@ -590,12 +592,15 @@ static void intel_connector_info(struct seq_file *m,
> break;
> }
>
> - seq_puts(m, "\tHDCP version: ");
> - intel_hdcp_info(m, intel_connector);
> + if (intel_connector) {
> + seq_puts(m, "\tHDCP version: ");
> + intel_hdcp_info(m, intel_connector);
> + }
>
> seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc);
>
> - intel_panel_info(m, intel_connector);
> + if (intel_connector)
> + intel_panel_info(m, intel_connector);
>
> seq_printf(m, "\tmodes:\n");
> list_for_each_entry(mode, &connector->modes, head) diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8eacb9133fce..7931dbacaba7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -44,6 +44,7 @@
> #include <drm/drm_vblank.h>
> #include <drm/drm_vblank_work.h>
> #include <drm/i915_mei_hdcp_interface.h>
> +#include <drm/drm_writeback.h>
> #include <media/cec-notifier.h>
>
> #include "i915_vma.h"
> @@ -1371,6 +1372,11 @@ struct intel_crtc {
> bool cpu_fifo_underrun_disabled;
> bool pch_fifo_underrun_disabled;
>
> + struct {
> + struct drm_pending_vblank_event *e;
> + atomic_t work_busy;
> + wait_queue_head_t wd_wait;
> + } wd;
> /* per-pipe watermark state */
> struct {
> /* watermarks currently being used */ @@ -1498,7 +1504,6
> @@ struct cxsr_latency { #define to_intel_atomic_state(x) container_of(x,
> struct intel_atomic_state, base) #define to_intel_crtc(x) container_of(x,
> struct intel_crtc, base) #define to_intel_crtc_state(x) container_of(x, struct
> intel_crtc_state, uapi) -#define to_intel_wb_connector(x) container_of(x,
> struct intel_wb_connector, base) #define to_intel_encoder(x)
> container_of(x, struct intel_encoder, base) #define to_intel_framebuffer(x)
> container_of(x, struct intel_framebuffer, base) #define to_intel_plane(x)
> container_of(x, struct intel_plane, base) @@ -2077,8 +2082,8 @@
> intel_connector_list_iter_next(struct drm_connector_list_iter *iter)
> struct drm_connector *connector;
> bool flag = true;
> /*
> - * Skipping connector that are Writeback connector as they will
> - * not be embedded in intel connector
> + * An intel_connector entity is not created for a writeback
> + * connector hence decoupling.
> */
> while (flag) {
> connector = drm_connector_list_iter_next(iter);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 52f2fe1735da..411f3366b9de 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -940,6 +940,9 @@ static int hsw_crtc_compute_clock(struct
> intel_atomic_state *state,
> intel_get_crtc_new_encoder(state, crtc_state);
> int ret;
>
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD))
> + return 0;
> +
> if (DISPLAY_VER(dev_priv) < 11 &&
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> return 0;
> @@ -968,6 +971,9 @@ static int hsw_crtc_get_shared_dpll(struct
> intel_atomic_state *state,
> struct intel_encoder *encoder =
> intel_get_crtc_new_encoder(state, crtc_state);
>
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD))
> + return 0;
> +
> if (DISPLAY_VER(dev_priv) < 11 &&
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index e1a90331c230..15792a5dd04c 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -24,6 +24,7 @@
> #include "intel_pch_display.h"
> #include "intel_pm.h"
> #include "skl_watermark.h"
> +#include "intel_wd.h"
>
> static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
> struct drm_modeset_acquire_ctx
> *ctx) @@ -111,17 +112,17 @@ static void intel_crtc_disable_noatomic(struct
> intel_crtc *crtc,
>
> static void intel_modeset_update_connector_atomic_state(struct
> drm_i915_private *i915) {
> - struct intel_connector *connector;
> + struct drm_connector *connector;
> struct drm_connector_list_iter conn_iter;
>
> drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> - for_each_intel_connector_iter(connector, &conn_iter) {
> - struct drm_connector_state *conn_state = connector-
> >base.state;
> + drm_for_each_connector_iter(connector, &conn_iter) {
> + struct drm_connector_state *conn_state = connector->state;
> struct intel_encoder *encoder =
> - to_intel_encoder(connector->base.encoder);
> + to_intel_encoder(connector->encoder);
>
> if (conn_state->crtc)
> - drm_connector_put(&connector->base);
> + drm_connector_put(connector);
>
> if (encoder) {
> struct intel_crtc *crtc =
> @@ -133,7 +134,7 @@ static void
> intel_modeset_update_connector_atomic_state(struct drm_i915_private
> conn_state->crtc = &crtc->base;
> conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24)
> / 3;
>
> - drm_connector_get(&connector->base);
> + drm_connector_get(connector);
> } else {
> conn_state->best_encoder = NULL;
> conn_state->crtc = NULL;
> @@ -433,6 +434,8 @@ static void intel_modeset_readout_hw_state(struct
> drm_i915_private *i915)
> struct intel_crtc *crtc;
> struct intel_encoder *encoder;
> struct intel_connector *connector;
> + struct drm_connector *_connector;
> + struct drm_encoder *_encoder;
Usually in i915 for struct intel_connector *intel_connector, struct drm_connector *connector is used or
Struct intel_connector *connector, struct drm_connector *conn is used.
Using this _connector or _encoder will be a totally new notation. Can anyone of the above use used?
> struct drm_connector_list_iter conn_iter;
> u8 active_pipes = 0;
>
> @@ -509,38 +512,70 @@ static void
> intel_modeset_readout_hw_state(struct drm_i915_private *i915)
> intel_dpll_readout_hw_state(i915);
>
> drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> - for_each_intel_connector_iter(connector, &conn_iter) {
> - if (connector->get_hw_state(connector)) {
> - struct intel_crtc_state *crtc_state;
> - struct intel_crtc *crtc;
> -
> - connector->base.dpms = DRM_MODE_DPMS_ON;
> -
> - encoder = intel_attached_encoder(connector);
> - connector->base.encoder = &encoder->base;
> -
> - crtc = to_intel_crtc(encoder->base.crtc);
> - crtc_state = crtc ? to_intel_crtc_state(crtc-
> >base.state) : NULL;
> -
> - if (crtc_state && crtc_state->hw.active) {
> - /*
> - * This has to be done during hardware
> readout
> - * because anything calling .crtc_disable may
> - * rely on the connector_mask being
> accurate.
> - */
> - crtc_state->uapi.connector_mask |=
> - drm_connector_mask(&connector-
> >base);
> - crtc_state->uapi.encoder_mask |=
> - drm_encoder_mask(&encoder-
> >base);
> + drm_for_each_connector_iter(_connector, &conn_iter) {
> + struct intel_crtc_state *crtc_state;
> + struct intel_crtc *crtc;
> + struct drm_writeback_connector *wb_conn;
> + struct intel_wd *intel_wd;
> +
> + connector = to_intel_connector(_connector);
> + if (!connector) {
> + wb_conn =
> drm_connector_to_writeback(_connector);
> + intel_wd = wb_conn_to_intel_wd(wb_conn);
> + _encoder = &intel_wd->base.base;
> + _connector->encoder = _encoder;
> + encoder = to_intel_encoder(_encoder);
> + pipe = 0;
> + if (encoder->get_hw_state(encoder, &pipe)) {
> + _connector->dpms =
> DRM_MODE_DPMS_ON;
> + crtc = to_intel_crtc(_encoder->crtc);
> + crtc_state = crtc ? to_intel_crtc_state(crtc-
> >base.state) : NULL;
> +
> + if (crtc_state && crtc_state->hw.active) {
> + /*
> + * This has to be done during
> hardware readout
> + * because anything calling
> .crtc_disable may
> + * rely on the connector_mask being
> accurate.
> + */
> + crtc_state->uapi.connector_mask |=
> +
> drm_connector_mask(&connector->base);
> + crtc_state->uapi.encoder_mask |=
> +
> drm_encoder_mask(&encoder->base);
> + }
> + } else {
> + _connector->dpms =
> DRM_MODE_DPMS_OFF;
> + _connector->encoder = NULL;
> }
> } else {
> - connector->base.dpms = DRM_MODE_DPMS_OFF;
> - connector->base.encoder = NULL;
> + if (connector->get_hw_state(connector)) {
> + connector->base.dpms =
> DRM_MODE_DPMS_OFF;
> + encoder =
> intel_attached_encoder(connector);
> + connector->base.encoder = &encoder->base;
> +
> + crtc = to_intel_crtc(encoder->base.crtc);
> + crtc_state = crtc ? to_intel_crtc_state(crtc-
> >base.state) : NULL;
> +
> + if (crtc_state && crtc_state->hw.active) {
> + /*
> + * This has to be done during
> hardware readout
> + * because anything calling
> .crtc_disable may
> + * rely on the connector_mask being
> accurate.
> + */
> + crtc_state->uapi.connector_mask |=
> +
> drm_connector_mask(&connector->base);
> + crtc_state->uapi.encoder_mask |=
> +
> drm_encoder_mask(&encoder->base);
> + }
> + } else {
> + connector->base.dpms =
> DRM_MODE_DPMS_OFF;
> + connector->base.encoder = NULL;
> + }
> }
> drm_dbg_kms(&i915->drm,
> - "[CONNECTOR:%d:%s] hw state readout: %s\n",
> - connector->base.base.id, connector->base.name,
> - str_enabled_disabled(connector->base.encoder));
> + "[CONNECTOR:%d:%s] hw state readout:
> %s\n",
> + _connector->base.id, _connector->name,
> + str_enabled_disabled(_connector-
> >encoder));
> +
> }
> drm_connector_list_iter_end(&conn_iter);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index 0fdcf2e6d57f..80e9840e2e5f 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -25,11 +25,16 @@
> static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
> struct drm_connector_state
> *conn_state) {
> - struct intel_connector *connector = to_intel_connector(conn_state-
> >connector);
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct drm_connector *_connector = conn_state->connector;
> + struct intel_connector *connector;
> + struct drm_i915_private *i915 = to_i915(_connector->dev);
>
> drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
> - connector->base.base.id, connector->base.name);
> + _connector->base.id, _connector->name);
> +
> + connector = to_intel_connector(_connector);
> + if (!connector)
> + return;
>
> if (connector->get_hw_state(connector)) {
> struct intel_encoder *encoder =
> intel_attached_encoder(connector);
> @@ -119,6 +124,9 @@ verify_encoder_state(struct drm_i915_private
> *dev_priv, struct intel_atomic_stat
> encoder->base.base.id,
> encoder->base.name);
>
> + if (encoder->type == INTEL_OUTPUT_WD)
> + continue;
> +
> for_each_oldnew_connector_in_state(&state->base,
> connector, old_conn_state,
> new_conn_state, i) {
> if (old_conn_state->best_encoder == &encoder-
> >base) @@ -177,6 +185,9 @@ verify_crtc_state(struct intel_crtc *crtc,
>
> intel_crtc_get_pipe_config(pipe_config);
>
> + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
> + return;
> +
> /* we keep both pipes enabled on 830 */
> if (IS_I830(dev_priv) && pipe_config->hw.active)
> pipe_config->hw.active = new_crtc_state->hw.active; diff --git
> a/drivers/gpu/drm/i915/display/intel_opregion.c
> b/drivers/gpu/drm/i915/display/intel_opregion.c
> index caa07ef34f21..1bcb4b58d992 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -374,6 +374,9 @@ int intel_opregion_notify_encoder(struct
> intel_encoder *intel_encoder,
> if (ret)
> return ret;
>
> + if (intel_encoder->type == INTEL_OUTPUT_WD)
> + return 0;
> +
> if (intel_encoder->type == INTEL_OUTPUT_DSI)
> port = 0;
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_wd.c
> b/drivers/gpu/drm/i915/display/intel_wd.c
> new file mode 100644
> index 000000000000..e3e990f4f26f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_wd.c
> @@ -0,0 +1,695 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_fourcc.h>
> +
> +#include "intel_atomic.h"
> +#include "intel_connector.h"
> +#include "intel_wd.h"
> +#include "intel_fb_pin.h"
> +#include "intel_de.h"
> +
> +enum {
> + WD_CAPTURE_4_PIX,
> + WD_CAPTURE_2_PIX,
> +} wd_capture_format;
> +
> +struct drm_writeback_job
> +*intel_get_writeback_job_from_queue(struct intel_wd *intel_wd) {
> + struct drm_writeback_job *job;
> + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev);
> + struct drm_writeback_connector *wb_conn =
> + &intel_wd->wb_conn;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&wb_conn->job_lock, flags);
> + job = list_first_entry_or_null(&wb_conn->job_queue,
> + struct drm_writeback_job,
> + list_entry);
> + spin_unlock_irqrestore(&wb_conn->job_lock, flags);
> + if (job == NULL) {
> + drm_dbg_kms(&i915->drm, "job queue is empty\n");
> + return NULL;
> + }
> +
> + return job;
> +}
> +
> +static const u32 wd_fmts[] = {
> + DRM_FORMAT_YUV444,
> + DRM_FORMAT_XYUV8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_Y410,
> + DRM_FORMAT_YUV422,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_RGB565,
> +};
> +
> +static int intel_wd_get_format(int pixel_format) {
> + int wd_format = -EINVAL;
> +
> + switch (pixel_format) {
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_XBGR2101010:
> + case DRM_FORMAT_XYUV8888:
> + case DRM_FORMAT_YUV444:
> + wd_format = WD_CAPTURE_4_PIX;
> + break;
> + case DRM_FORMAT_YUV422:
> + case DRM_FORMAT_RGB565:
> + wd_format = WD_CAPTURE_2_PIX;
> + break;
> + default:
> + DRM_ERROR("unsupported pixel format %x!\n",
> + pixel_format);
> + }
> +
> + return wd_format;
> +}
> +
> +static int intel_wd_verify_pix_format(int format) {
> + const struct drm_format_info *info = drm_format_info(format);
> + int pix_format = info->format;
> + int i = 0;
> +
> + for (i = 0; i < ARRAY_SIZE(wd_fmts); i++)
> + if (pix_format == wd_fmts[i])
> + return 0;
> +
> + return true;
> +}
> +
> +static u32 intel_wd_get_stride(const struct intel_crtc_state *crtc_state,
> + int format)
> +{
> + const struct drm_format_info *info = drm_format_info(format);
> + int wd_format;
> + int hactive, pixel_size;
> +
> + wd_format = intel_wd_get_format(info->format);
> +
> + switch (wd_format) {
> + case WD_CAPTURE_4_PIX:
> + pixel_size = 4;
> + break;
> + case WD_CAPTURE_2_PIX:
> + pixel_size = 2;
> + break;
> + default:
> + pixel_size = 1;
> + break;
> + }
> +
> + hactive = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> +
> + return DIV_ROUND_UP(hactive * pixel_size, 64); }
> +
> +static int intel_wd_pin_fb(struct intel_wd *intel_wd,
> + struct drm_framebuffer *fb)
> +{
> + const struct i915_gtt_view view = {
> + .type = I915_GTT_VIEW_NORMAL,
> + };
> + struct i915_vma *vma;
> +
> + vma = intel_pin_and_fence_fb_obj(fb, false, &view, false,
> + &intel_wd->flags);
> +
> + if (IS_ERR(vma))
> + return PTR_ERR(vma);
> +
> + intel_wd->vma = vma;
> + return 0;
> +}
> +
> +static void intel_configure_slicing_strategy(struct drm_i915_private *i915,
> + struct intel_wd *intel_wd,
> + u32 *tmp)
> +{
> + *tmp &= ~WD_STRAT_MASK;
> + if (intel_wd->slicing_strategy == 1)
> + *tmp |= WD_SLICING_STRAT_1_1;
> + else if (intel_wd->slicing_strategy == 2)
> + *tmp |= WD_SLICING_STRAT_2_1;
> + else if (intel_wd->slicing_strategy == 3)
> + *tmp |= WD_SLICING_STRAT_4_1;
> + else if (intel_wd->slicing_strategy == 4)
> + *tmp |= WD_SLICING_STRAT_8_1;
> +
> + intel_de_write(i915, WD_STREAMCAP_CTL(intel_wd->trans),
> + *tmp);
> +}
> +
> +static enum drm_mode_status
> +intel_wd_mode_valid(struct drm_connector *connector,
> + struct drm_display_mode *mode)
> +{
> + return MODE_OK;
> +}
> +
> +static int intel_wd_get_modes(struct drm_connector *connector) {
> + return 0;
> +}
> +
> +static void intel_wd_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config) {
> + struct intel_crtc *intel_crtc =
> + to_intel_crtc(pipe_config->uapi.crtc);
> +
> + if (intel_crtc) {
> + memcpy(pipe_config, intel_crtc->config,
> + sizeof(*pipe_config));
> + pipe_config->output_types |= BIT(INTEL_OUTPUT_WD);
> + }
> +}
> +
> +static int intel_wd_compute_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config,
> + struct drm_connector_state *conn_state) {
> + struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
> + struct drm_writeback_job *job;
> +
> + job = intel_get_writeback_job_from_queue(intel_wd);
> + if (job || conn_state->writeback_job) {
> + /*
> + * Saving reference of pipe/crtc for later use if
> + * writeback job is present
> + */
> + intel_wd->wd_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + return 0;
> + }
> +
> + return 0;
> +}
> +
> +static void intel_wd_get_power_domains(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
> + intel_wakeref_t wakeref;
> +
> + wakeref = intel_display_power_get(i915, encoder->power_domain);
> +
> + intel_wd->io_wakeref[0] = wakeref;
> +}
> +
> +static bool intel_wd_get_hw_state(struct intel_encoder *encoder,
> + enum pipe *pipe)
> +{
> + bool ret = false;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
> + struct intel_crtc *wd_crtc = intel_wd->wd_crtc;
> + intel_wakeref_t wakeref;
> + u32 tmp;
> +
> + if (wd_crtc)
> + return false;
> +
> + wakeref = intel_display_power_get_if_enabled(dev_priv,
> + encoder->power_domain);
> +
> + if (!wakeref)
> + goto out;
> +
> + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> + ret = tmp & WD_TRANS_ACTIVE;
> + if (ret) {
> + *pipe = wd_crtc->pipe;
> + return true;
> + }
> +
> +out:
> + intel_display_power_put(dev_priv, encoder->power_domain,
> wakeref);
> + return false;
> +}
> +
> +static int intel_wd_encoder_atomic_check(struct drm_encoder *encoder,
> + struct drm_crtc_state *crtc_st,
> + struct drm_connector_state
> *conn_st) {
> + /* Check for the format and buffers and property validity */
> + struct drm_framebuffer *fb;
> + struct drm_writeback_job *job = conn_st->writeback_job;
> + struct drm_i915_private *i915 = to_i915(encoder->dev);
> + const struct drm_display_mode *mode = &crtc_st->mode;
> + int ret;
> +
> + if (!job) {
> + drm_dbg_kms(&i915->drm, "No writeback job created
> returning\n");
> + return -EINVAL;
> + }
> +
> + fb = job->fb;
> + if (!fb) {
> + drm_dbg_kms(&i915->drm, "Invalid framebuffer\n");
> + return -EINVAL;
> + }
> +
> + if (fb->width != mode->hdisplay || fb->height != mode->vdisplay) {
> + drm_dbg_kms(&i915->drm, "Invalid framebuffer size
> %ux%u\n",
> + fb->width, fb->height);
> + return -EINVAL;
> + }
> +
> + ret = intel_wd_verify_pix_format(fb->format->format);
> + if (ret) {
> + drm_dbg_kms(&i915->drm, "Unsupported framebuffer
> format %08x\n",
> + fb->format->format);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +
> +static const struct drm_encoder_helper_funcs wd_encoder_helper_funcs =
> {
> + .atomic_check = intel_wd_encoder_atomic_check, };
> +
> +static void intel_wd_connector_destroy(struct drm_connector *connector)
> +{
> + drm_connector_cleanup(connector);
> +}
> +
> +static enum drm_connector_status
> +intel_wd_connector_detect(struct drm_connector *connector, bool force)
> +{
> + return connector_status_connected;
> +}
> +
> +static const struct drm_connector_funcs wb_connector_funcs = {
> + .detect = intel_wd_connector_detect,
> + .reset = drm_atomic_helper_connector_reset,
> + .destroy = intel_wd_connector_destroy,
> + .fill_modes = drm_helper_probe_single_connector_modes,
> + .atomic_destroy_state =
> drm_atomic_helper_connector_destroy_state,
> + .atomic_duplicate_state =
> drm_atomic_helper_connector_duplicate_state,
> +};
> +
> +static const struct drm_connector_helper_funcs
> wb_connector_helper_funcs = {
> + .get_modes = intel_wd_get_modes,
> + .mode_valid = intel_wd_mode_valid,
> +};
> +
> +static const struct drm_encoder_funcs drm_writeback_encoder_funcs = {
> + .destroy = drm_encoder_cleanup,
> +};
> +
> +static bool intel_fastset_dis(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config) {
> + return false;
> +}
> +
> +static void intel_wd_connector_init(struct intel_wd *intel_wd) {
> + drm_atomic_helper_connector_reset(&intel_wd->wb_conn.base);
> +}
> +
> +static void intel_wd_disable_capture(struct intel_wd *intel_wd) {
> + struct drm_i915_private *dev_priv = to_i915(intel_wd-
> >base.base.dev);
> + u32 tmp;
> +
> + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), 0xFF);
> + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> + tmp &= WD_TRANS_DISABLE;
> + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp);
> + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd-
> >trans));
> +}
> +
> +void intel_wd_init(struct drm_i915_private *i915, enum transcoder
> +trans) {
> + struct intel_wd *intel_wd;
> + struct intel_encoder *encoder;
> + struct drm_writeback_connector *wb_conn;
> + int n_formats = ARRAY_SIZE(wd_fmts);
> + struct drm_encoder *drm_enc;
> + int err, ret;
> +
> + intel_wd = kzalloc(sizeof(*intel_wd), GFP_KERNEL);
> + if (!intel_wd)
> + return;
> +
> + intel_wd_connector_init(intel_wd);
> + encoder = &intel_wd->base;
> + drm_enc = &encoder->base;
> + wb_conn = &intel_wd->wb_conn;
> + intel_wd->trans = trans;
> + intel_wd->triggered_cap_mode = 1;
> + intel_wd->frame_num = 1;
> + intel_wd->slicing_strategy = 1;
> + encoder->get_config = intel_wd_get_config;
> + encoder->compute_config = intel_wd_compute_config;
> + encoder->get_hw_state = intel_wd_get_hw_state;
> + encoder->type = INTEL_OUTPUT_WD;
> + encoder->cloneable = 0;
> + encoder->pipe_mask = ~0;
> + encoder->power_domain = POWER_DOMAIN_TRANSCODER_B;
> + encoder->get_power_domains = intel_wd_get_power_domains;
> + encoder->initial_fastset_check = intel_fastset_dis;
> +
> + drm_encoder_helper_add(drm_enc,
> + &wd_encoder_helper_funcs);
> +
> + drm_enc->possible_crtcs = ~0;
> + ret = drm_encoder_init(&i915->drm, drm_enc,
> + &drm_writeback_encoder_funcs,
> + DRM_MODE_ENCODER_VIRTUAL, NULL);
> +
> + if (ret) {
> + drm_dbg_kms(&i915->drm,
> + "Writeback drm_encoder init Failed: %d\n",
> + ret);
> + goto cleanup;
> + }
> +
> + err = drm_writeback_connector_init_with_encoder(&i915->drm,
> + wb_conn, drm_enc, &wb_connector_funcs,
> + wd_fmts, n_formats);
> +
> + if (err != 0) {
> + drm_dbg_kms(&i915->drm,
> + "drm_writeback_connector_init: Failed: %d\n",
> + err);
> + goto cleanup;
> + }
> +
> + wb_conn->base.encoder = drm_enc;
> + drm_connector_helper_add(&wb_conn->base,
> &wb_connector_helper_funcs);
> + wb_conn->base.status = connector_status_connected;
> + return;
> +
> +cleanup:
> + kfree(intel_wd);
> + return;
> +}
> +
> +static void intel_wd_writeback_complete(struct intel_wd *intel_wd,
> + struct drm_writeback_job *job,
> + int status)
> +{
> + struct drm_writeback_connector *wb_conn =
> + &intel_wd->wb_conn;
> + drm_writeback_signal_completion(wb_conn, status); }
> +
> +static int intel_wd_setup_transcoder(struct intel_wd *intel_wd,
> + struct intel_crtc_state *pipe_config,
> + struct drm_connector_state *conn_state,
> + struct drm_writeback_job *job) {
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + enum pipe pipe = intel_crtc->pipe;
> + struct drm_framebuffer *fb;
> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> + struct drm_gem_object *wd_fb_obj;
> + int ret;
> + u32 stride, tmp;
> + u16 hactive, vactive;
> +
> + fb = job->fb;
> + wd_fb_obj = fb->obj[0];
> + if (!wd_fb_obj) {
> + drm_dbg_kms(&dev_priv->drm, "No framebuffer gem object
> created\n");
> + return -EINVAL;
> + }
> +
> + ret = intel_wd_pin_fb(intel_wd, fb);
> + drm_WARN_ON(&dev_priv->drm, ret != 0);
> + /* Write stride and surface registers in that particular order */
> + stride = intel_wd_get_stride(pipe_config, fb->format->format);
> +
> + tmp = intel_de_read(dev_priv, WD_STRIDE(intel_wd->trans));
> + tmp &= ~WD_STRIDE_MASK;
> + tmp |= (stride << WD_STRIDE_SHIFT);
> +
> + intel_de_write(dev_priv, WD_STRIDE(intel_wd->trans), tmp);
> +
> + tmp = intel_de_read(dev_priv, WD_SURF(intel_wd->trans));
> +
> + intel_de_write(dev_priv, WD_SURF(intel_wd->trans),
> + i915_ggtt_offset(intel_wd->vma));
> +
> + tmp = intel_de_read_fw(dev_priv, WD_IIR(intel_wd->trans));
> + intel_de_write_fw(dev_priv, WD_IIR(intel_wd->trans), tmp);
> +
> + tmp = ~(WD_GTT_FAULT_INT | WD_WRITE_COMPLETE_INT |
> WD_FRAME_COMPLETE_INT |
> + WD_VBLANK_INT | WD_OVERRUN_INT |
> WD_CAPTURING_INT);
> + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), tmp);
> +
> + if (intel_wd->stream_cap) {
> + tmp = intel_de_read(dev_priv,
> + WD_STREAMCAP_CTL(intel_wd->trans));
> + tmp |= WD_STREAM_CAP_MODE_EN;
> + intel_configure_slicing_strategy(dev_priv, intel_wd, &tmp);
> + }
> +
> + hactive = pipe_config->uapi.mode.hdisplay;
> + vactive = pipe_config->uapi.mode.vdisplay;
> + tmp = intel_de_read(dev_priv, HTOTAL(intel_wd->trans));
> + tmp = intel_de_read(dev_priv, VTOTAL(intel_wd->trans));
> +
> + /* minimum hactive as per bspec: 64 pixels */
> + if (hactive < 64)
> + drm_err(&dev_priv->drm, "hactive is less then 64 pixels\n");
> +
> + intel_de_write(dev_priv, HTOTAL(intel_wd->trans), hactive - 1);
> + intel_de_write(dev_priv, VTOTAL(intel_wd->trans), vactive - 1);
> +
> + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd-
> >trans));
> + /* select pixel format */
> + tmp &= ~WD_PIX_FMT_MASK;
> +
> + switch (fb->format->format) {
> + default:
> + fallthrough;
> + case DRM_FORMAT_YUYV:
> + tmp |= WD_PIX_FMT_YUYV;
> + break;
> + case DRM_FORMAT_XYUV8888:
> + tmp |= WD_PIX_FMT_XYUV8888;
> + break;
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_XRGB8888:
> + tmp |= WD_PIX_FMT_XBGR8888;
> + break;
> + case DRM_FORMAT_Y410:
> + tmp |= WD_PIX_FMT_Y410;
> + break;
> + case DRM_FORMAT_YUV422:
> + tmp |= WD_PIX_FMT_YUV422;
> + break;
> + case DRM_FORMAT_XBGR2101010:
> + tmp |= WD_PIX_FMT_XBGR2101010;
> + break;
> + case DRM_FORMAT_RGB565:
> + tmp |= WD_PIX_FMT_RGB565;
> + break;
> + }
> +
> + if (intel_wd->triggered_cap_mode)
> + tmp |= WD_TRIGGERED_CAP_MODE_ENABLE;
> +
> + if (intel_wd->stream_cap)
> + tmp |= WD_CTL_POINTER_DTDH;
> +
> + /* select input pipe */
> + tmp &= ~WD_INPUT_SELECT_MASK;
> + switch (pipe) {
> + default:
> + fallthrough;
> + case PIPE_A:
> + tmp |= WD_INPUT_PIPE_A;
> + break;
> + case PIPE_B:
> + tmp |= WD_INPUT_PIPE_B;
> + break;
> + case PIPE_C:
> + tmp |= WD_INPUT_PIPE_C;
> + break;
> + case PIPE_D:
> + tmp |= WD_INPUT_PIPE_D;
> + break;
> + }
> +
> + /* enable DDI buffer */
> + if (!(tmp & TRANS_WD_FUNC_ENABLE))
> + tmp |= TRANS_WD_FUNC_ENABLE;
> +
> + intel_de_write(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans),
> tmp);
> +
> + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> + ret = tmp & WD_TRANS_ACTIVE;
> + if (!ret) {
> + /* enable the transcoder */
> + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> + tmp |= WD_TRANS_ENABLE;
> + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp);
> +
> + /* wait for transcoder to be enabled */
> + if (intel_de_wait_for_set(dev_priv, PIPECONF(intel_wd-
> >trans),
> + WD_TRANS_ACTIVE, 10))
> + drm_err(&dev_priv->drm, "WD transcoder could not
> be enabled\n");
> + }
> +
> + return 0;
> +}
> +
> +static int intel_wd_capture(struct intel_wd *intel_wd,
> + struct intel_crtc_state *pipe_config,
> + struct drm_connector_state *conn_state,
> + struct drm_writeback_job *job)
> +{
> + u32 tmp;
> + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev);
> + int ret = 0, status = 0;
> + struct intel_crtc *wd_crtc = intel_wd->wd_crtc;
> + unsigned long flags;
> +
> + if (!job->out_fence)
> + drm_dbg_kms(&i915->drm, "Not able to get out_fence for
> job\n");
> +
> + ret = intel_wd_setup_transcoder(intel_wd, pipe_config,
> + conn_state, job);
> +
> + if (ret < 0) {
> + drm_dbg_kms(&i915->drm,
> + "WD transcoder setup not completed aborting
> capture\n");
> + return -1;
> + }
> +
> + if (!wd_crtc) {
> + drm_err(&i915->drm, "CRTC not attached\n");
> + return -1;
> + }
> +
> + tmp = intel_de_read_fw(i915, WD_TRANS_FUNC_CTL(intel_wd-
> >trans));
> + tmp |= START_TRIGGER_FRAME;
> + tmp &= ~WD_FRAME_NUMBER_MASK;
> + tmp |= intel_wd->frame_num;
> + intel_de_write_fw(i915, WD_TRANS_FUNC_CTL(intel_wd-
> >trans), tmp);
Why this tab space?
> +
> + if (!intel_de_wait_for_set(i915, WD_IIR(intel_wd->trans),
> + WD_FRAME_COMPLETE_INT, 100)){
> + drm_dbg_kms(&i915->drm, "frame captured\n");
> + status = 0;
> + } else {
> + drm_dbg_kms(&i915->drm, "frame not captured triggering
> stop frame\n");
> + tmp = intel_de_read(i915, WD_TRANS_FUNC_CTL(intel_wd-
> >trans));
> + tmp |= STOP_TRIGGER_FRAME;
> + intel_de_write(i915, WD_TRANS_FUNC_CTL(intel_wd->trans),
> tmp);
> + status = -1;
> + }
> +
> + intel_wd_writeback_complete(intel_wd, job, status);
> + if (wd_crtc->wd.e) {
> + spin_lock_irqsave(&i915->drm.event_lock, flags);
> + drm_dbg_kms(&i915->drm, "send %p\n", wd_crtc->wd.e);
Can this debug print be moved outside the spin_lock_irqsave.?
> + drm_crtc_send_vblank_event(&wd_crtc->base,
> + wd_crtc->wd.e);
> + spin_unlock_irqrestore(&i915->drm.event_lock, flags);
> + wd_crtc->wd.e = NULL;
> + } else {
> + drm_err(&i915->drm, "Event NULL! %p, %p\n", &i915->drm,
> + wd_crtc);
> + }
> + if (!intel_get_writeback_job_from_queue(intel_wd))
> + intel_wd_disable_capture(intel_wd);
> + return 0;
> +}
> +
> +void intel_wd_enable_capture(struct intel_crtc_state *pipe_config,
> + struct drm_connector_state *conn_state) {
> + struct drm_i915_private *i915 =
> + to_i915(conn_state->connector->dev);
> + struct drm_writeback_connector *wb_conn =
> + drm_connector_to_writeback(conn_state->connector);
> + struct intel_wd *intel_wd = wb_conn_to_intel_wd(wb_conn);
> + struct drm_writeback_job *job;
> +
> + job = intel_get_writeback_job_from_queue(intel_wd);
> + if (!job) {
> + drm_dbg_kms(&i915->drm,
> + "job queue is empty not capturing any frame\n");
> + return;
> + }
> +
> + intel_wd_capture(intel_wd, pipe_config,
> + conn_state, job);
> + intel_wd->frame_num += 1;
> +}
> +
> +void intel_wd_set_vblank_event(struct intel_atomic_state *state, struct
> intel_crtc *intel_crtc,
> + struct intel_crtc_state *intel_crtc_state) {
> + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev);
> + struct drm_crtc_state *crtc_state = &intel_crtc_state->uapi;
> + struct intel_encoder *encoder;
> + struct intel_wd *intel_wd;
> + struct drm_connector_state *conn_state;
> + struct drm_connector *connector;
> + int i;
> +
> + for_each_intel_encoder(&i915->drm, encoder) {
> + if (encoder->type != INTEL_OUTPUT_WD)
> + continue;
> +
> + intel_wd = enc_to_intel_wd(encoder);
> + if (!intel_wd->wd_crtc)
> + return;
> + }
> +
> + if (intel_wd && intel_crtc == intel_wd->wd_crtc) {
> + for_each_new_connector_in_state(&state->base, connector,
> conn_state,
> + i) {
> + if (!conn_state->writeback_job)
> + continue;
> +
> + intel_crtc->wd.e = crtc_state->event;
> + crtc_state->event = NULL;
> + }
> + }
> +}
> +
> +void intel_wd_handle_isr(struct drm_i915_private *i915) {
> + u32 iir_value = 0;
> + struct intel_encoder *encoder;
> + struct intel_wd *intel_wd;
> +
> + iir_value = intel_de_read(i915, WD_IIR(TRANSCODER_WD_0));
> +
> + for_each_intel_encoder(&i915->drm, encoder) {
> +
> + if (encoder->type != INTEL_OUTPUT_WD)
> + continue;
> +
> + intel_wd = enc_to_intel_wd(encoder);
> + if (!intel_wd->wd_crtc) {
> + drm_err(&i915->drm, "NO CRTC attached with
> WD\n");
> + goto clear_iir;
> + }
> + }
> +
> + if (iir_value & WD_FRAME_COMPLETE_INT)
> + return;
> +
> +clear_iir:
> + intel_de_write(i915, WD_IIR(TRANSCODER_WD_0), iir_value); }
> diff --git a/drivers/gpu/drm/i915/display/intel_wd.h
> b/drivers/gpu/drm/i915/display/intel_wd.h
> new file mode 100644
> index 000000000000..0fcd1a746593
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_wd.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: MIT*/
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef _INTEL_WD_H
> +#define _INTEL_WD_H
> +
> +#include <drm/drm_crtc.h>
> +
> +#include "intel_display_types.h"
> +
> +#define I915_MAX_WD_TANSCODERS 2
> +
> +struct intel_wd {
> + struct intel_encoder base;
> + struct drm_writeback_connector wb_conn;
> + struct intel_crtc *wd_crtc;
> + intel_wakeref_t io_wakeref[I915_MAX_WD_TANSCODERS];
> + enum transcoder trans;
> + struct i915_vma *vma;
> + unsigned long flags;
> + struct drm_writeback_job *job;
> + int triggered_cap_mode;
> + int frame_num;
> + bool stream_cap;
> + bool start_capture;
> + int slicing_strategy;
> +};
> +
> +static inline struct intel_wd *enc_to_intel_wd(struct intel_encoder
> +*encoder) {
> + return container_of(&encoder->base, struct intel_wd, base.base); }
> +
> +static inline struct intel_wd *wb_conn_to_intel_wd(struct
> +drm_writeback_connector *wb_conn) {
> + return container_of(wb_conn, struct intel_wd, wb_conn); }
> +
> +void intel_wd_init(struct drm_i915_private *dev_priv, enum transcoder
> +trans); void intel_wd_enable_capture(struct intel_crtc_state *pipe_config,
> + struct drm_connector_state *conn_state); void
> +intel_wd_handle_isr(struct drm_i915_private *dev_priv); void
> +intel_wd_set_vblank_event(struct intel_atomic_state *state, struct
> intel_crtc *crtc,
> + struct intel_crtc_state *crtc_state); struct
> drm_writeback_job
> +*intel_get_writeback_job_from_queue(struct intel_wd *intel_wd);
> +#endif/* _INTEL_WD_H */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 55794b87a6c1..503a21c77d14
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -34,6 +34,7 @@
>
> #include <linux/pm_qos.h>
>
> +#include <drm/drm_writeback.h>
> #include <drm/ttm/ttm_device.h>
>
> #include "display/intel_display.h"
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c index 86a42d9e8041..ee0255d9eb64
> 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -42,6 +42,7 @@
> #include "display/intel_hotplug.h"
> #include "display/intel_lpe_audio.h"
> #include "display/intel_psr.h"
> +#include "display/intel_wd.h"
>
> #include "gt/intel_breadcrumbs.h"
> #include "gt/intel_gt.h"
> @@ -2342,6 +2343,11 @@ gen8_de_misc_irq_handler(struct
> drm_i915_private *dev_priv, u32 iir)
> found = true;
> }
>
> + if (iir & GEN8_DE_MISC_WD0) {
> + intel_wd_handle_isr(dev_priv);
> + found = true;
> + }
> +
> if (iir & GEN8_DE_EDP_PSR) {
> struct intel_encoder *encoder;
> u32 psr_iir;
> @@ -3767,7 +3773,7 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
> u32 de_pipe_enables;
> u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
> u32 de_port_enables;
> - u32 de_misc_masked = GEN8_DE_EDP_PSR;
> + u32 de_misc_masked = GEN8_DE_EDP_PSR | GEN8_DE_MISC_WD0;
> u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
> enum pipe pipe;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c index 19fc00bcd7b9..d6eb63aefc47
> 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -868,7 +868,8 @@ static const struct intel_device_info jsl_info = {
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) |
> BIT(PIPE_D), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) |
> BIT(TRANSCODER_B) | \
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1) | \
> + BIT(TRANSCODER_WD_0), \
> .display.pipe_offsets = { \
> [TRANSCODER_A] = PIPE_A_OFFSET, \
> [TRANSCODER_B] = PIPE_B_OFFSET, \
> @@ -876,6 +877,8 @@ static const struct intel_device_info jsl_info = {
> [TRANSCODER_D] = PIPE_D_OFFSET, \
> [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> + [TRANSCODER_WD_0] = PIPE_WD0_OFFSET, \
> + [TRANSCODER_WD_1] = PIPE_WD1_OFFSET, \
> }, \
> .display.trans_offsets = { \
> [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ @@ -884,6
> +887,8 @@ static const struct intel_device_info jsl_info = {
> [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> + [TRANSCODER_WD_0] = TRANSCODER_WD0_OFFSET, \
> + [TRANSCODER_WD_1] = TRANSCODER_WD1_OFFSET, \
> }, \
> TGL_CURSOR_OFFSETS, \
> .has_global_mocs = 1, \
> --
> 2.25.1
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v4 3/3] drm/i915: Enabling WD Transcoder
2022-09-19 5:30 ` Murthy, Arun R
@ 2022-09-19 6:28 ` Kandpal, Suraj
2022-09-19 6:31 ` Murthy, Arun R
0 siblings, 1 reply; 10+ messages in thread
From: Kandpal, Suraj @ 2022-09-19 6:28 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: Nikula, Jani
Hi Arun,
> > From: Suraj Kandpal <suraj.kandpal@intel.com>
> >
> > Adding support for writeback transcoder to start capturing frames
> > using interrupt mechanism
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
> > drivers/gpu/drm/i915/display/intel_crtc.c | 6 +
> > .../drm/i915/display/intel_crtc_state_dump.c | 1 +
> > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +
> > drivers/gpu/drm/i915/display/intel_display.c | 68 +-
> > drivers/gpu/drm/i915/display/intel_display.h | 5 +
> > .../drm/i915/display/intel_display_debugfs.c | 13 +-
> > .../drm/i915/display/intel_display_types.h | 11 +-
> > drivers/gpu/drm/i915/display/intel_dpll.c | 6 +
> > .../drm/i915/display/intel_modeset_setup.c | 103 ++-
> > .../drm/i915/display/intel_modeset_verify.c | 17 +-
> > drivers/gpu/drm/i915/display/intel_opregion.c | 3 +
> > drivers/gpu/drm/i915/display/intel_wd.c | 695 ++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_wd.h | 48 ++
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_irq.c | 8 +-
> > drivers/gpu/drm/i915/i915_pci.c | 7 +-
> > 18 files changed, 951 insertions(+), 49 deletions(-) create mode
> > 100644 drivers/gpu/drm/i915/display/intel_wd.c
> > create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index a26edcdadc21..f34db43cf58d
> > 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -304,6 +304,7 @@ i915-y += \
> > display/intel_tv.o \
> > display/intel_vdsc.o \
> > display/intel_vrr.o \
> > + display/intel_wd.o \
> > display/vlv_dsi.o \
> > display/vlv_dsi_pll.o
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c
> > b/drivers/gpu/drm/i915/display/intel_acpi.c
> > index e78430001f07..ae08db164f73 100644
> > --- a/drivers/gpu/drm/i915/display/intel_acpi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_acpi.c
> > @@ -247,6 +247,7 @@ static u32 acpi_display_type(struct
> > intel_connector
> > *connector)
> > case DRM_MODE_CONNECTOR_LVDS:
> > case DRM_MODE_CONNECTOR_eDP:
> > case DRM_MODE_CONNECTOR_DSI:
> > + case DRM_MODE_CONNECTOR_WRITEBACK:
> > display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL;
> > break;
> > case DRM_MODE_CONNECTOR_Unknown:
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> > b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index 6792a9056f46..66d552758720 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -491,6 +491,9 @@ void intel_pipe_update_start(struct
> > intel_crtc_state
> > *new_crtc_state)
> > if (new_crtc_state->do_async_flip)
> > return;
> >
> > + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
> > + return;
> > +
> > if (intel_crtc_needs_vblank_work(new_crtc_state))
> > intel_crtc_vblank_work_init(new_crtc_state);
> >
> > @@ -638,6 +641,9 @@ void intel_pipe_update_end(struct
> intel_crtc_state
> > *new_crtc_state)
> > if (new_crtc_state->do_async_flip)
> > return;
> >
> > + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
> > + return;
> > +
> > trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
> >
> > /*
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > index e9212f69c360..8435065f3b7d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > @@ -71,6 +71,7 @@ static const char * const output_type_str[] = {
> > OUTPUT_TYPE(DSI),
> > OUTPUT_TYPE(DDI),
> > OUTPUT_TYPE(DP_MST),
> > + OUTPUT_TYPE(WD),
> > };
> >
> > #undef OUTPUT_TYPE
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 643832d55c28..ea8e07a957ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1953,6 +1953,12 @@ void
> > intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> > */
> > if (encoder->type == INTEL_OUTPUT_DP_MST)
> > return;
> > + /*
> > + * WD transcoder is a virtual encoder hence sanization
> > + * is not required for it
> > + */
> > + if (encoder->type == INTEL_OUTPUT_WD)
> > + return;
> >
> > if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
> > u8 pipe_mask;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 2d0018ae34b1..15b2b7a6a110 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -115,6 +115,7 @@
> > #include "intel_sprite.h"
> > #include "intel_tc.h"
> > #include "intel_vga.h"
> > +#include "intel_wd.h"
> > #include "i9xx_plane.h"
> > #include "skl_scaler.h"
> > #include "skl_universal_plane.h"
> > @@ -1511,6 +1512,10 @@ static void
> > intel_encoders_update_prepare(struct
> > intel_atomic_state *state)
> > continue;
> >
> > intel_connector = to_intel_connector(connector);
> > + /* intel_connector instance is not created for WD
> transcoder
> > */
> > + if (!intel_connector)
> > + continue;
> > +
> > encoder =
> > intel_connector_primary_encoder(intel_connector);
> > if (!encoder->update_prepare)
> > continue;
> > @@ -1540,6 +1545,10 @@ static void
> > intel_encoders_update_complete(struct intel_atomic_state *state)
> > continue;
> >
> > intel_connector = to_intel_connector(connector);
> > + /* intel_connector instance is not created for WD
> transcoder
> > */
> > + if (!intel_connector)
> > + continue;
> > +
> > encoder =
> > intel_connector_primary_encoder(intel_connector);
> > if (!encoder->update_complete)
> > continue;
> > @@ -1550,6 +1559,37 @@ static void
> > intel_encoders_update_complete(struct intel_atomic_state *state)
> > }
> > }
> >
> > +static void intel_queue_writeback_job(struct intel_atomic_state
> > +*state) {
> > + struct drm_connector_state *new_conn_state;
> > + struct drm_connector *connector;
> > + struct drm_writeback_connector *wb_conn;
> > + int i;
> > +
> > + for_each_new_connector_in_state(&state->base, connector,
> > new_conn_state,
> > + i) {
> > + if (!new_conn_state->writeback_job)
> > + continue;
> > +
> > + wb_conn = drm_connector_to_writeback(connector);
> > + drm_writeback_queue_job(wb_conn, new_conn_state);
> > + }
> > +}
> > +
> > +static void intel_enable_writeback_capture(struct intel_atomic_state
> > +*state,struct intel_crtc_state *crtc_state) {
> > + struct drm_connector_state *new_conn_state;
> > + struct drm_connector *connector;
> > + int i;
> > +
> > + for_each_new_connector_in_state(&state->base, connector,
> > new_conn_state,
> > + i) {
> > + if (connector->connector_type !=
> > DRM_MODE_CONNECTOR_WRITEBACK)
> > + continue;
> > + intel_wd_enable_capture(crtc_state, new_conn_state);
> > + }
> > +}
> > +
> > static void intel_encoders_pre_pll_enable(struct intel_atomic_state
> *state,
> > struct intel_crtc *crtc)
> > {
> > @@ -1650,8 +1690,12 @@ static void intel_encoders_post_disable(struct
> > intel_atomic_state *state,
> > int i;
> >
> > for_each_old_connector_in_state(&state->base, conn,
> old_conn_state,
> > i) {
> > - struct intel_encoder *encoder =
> > - to_intel_encoder(old_conn_state->best_encoder);
> > + struct intel_encoder *encoder;
> > +
> > + if (conn->connector_type ==
> > DRM_MODE_CONNECTOR_WRITEBACK)
> > + continue;
> > +
> > + encoder = to_intel_encoder(old_conn_state-
> >best_encoder);
> >
> > if (old_conn_state->crtc != &crtc->base)
> > continue;
> > @@ -1928,7 +1972,8 @@ static void hsw_crtc_enable(struct
> > intel_atomic_state *state,
> > bdw_set_pipemisc(new_crtc_state);
> >
> > if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
> > - !transcoder_is_dsi(cpu_transcoder))
> > + !transcoder_is_dsi(cpu_transcoder) &&
> > + !transcoder_is_wd(cpu_transcoder))
> > hsw_configure_cpu_transcoder(new_crtc_state);
> >
> > crtc->active = true;
> > @@ -7528,6 +7573,11 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > }
> > }
> >
> > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > + if ((new_crtc_state->output_types &
> > BIT(INTEL_OUTPUT_WD)))
> > + intel_wd_set_vblank_event(state, crtc,
> > new_crtc_state);
> > + }
> > +
> > intel_encoders_update_prepare(state);
> >
> > intel_dbuf_pre_plane_update(state);
> > @@ -7538,6 +7588,14 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > intel_crtc_enable_flip_done(state, crtc);
> > }
> >
> > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > + if ((new_crtc_state->output_types &
> > BIT(INTEL_OUTPUT_WD)))
> > + {
> > + intel_queue_writeback_job(state);
> > + intel_enable_writeback_capture(state,
> > new_crtc_state);
> > + }
> > + }
> > +
> > /* Now enable the clocks, plane, pipe, and connectors that we set
> > up. */
> > dev_priv->display.funcs.display->commit_modeset_enables(state);
> >
> > @@ -7892,6 +7950,10 @@ static void intel_setup_outputs(struct
> > drm_i915_private *dev_priv)
> > if (!HAS_DISPLAY(dev_priv))
> > return;
> >
> > + /* Initializing WD transcoder */
> > + if (DISPLAY_VER(dev_priv) >= 12)
> > + intel_wd_init(dev_priv, TRANSCODER_WD_0);
> > +
> > if (IS_DG2(dev_priv)) {
> > intel_ddi_init(dev_priv, PORT_A);
> > intel_ddi_init(dev_priv, PORT_B);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> > b/drivers/gpu/drm/i915/display/intel_display.h
> > index 102bf7d47ccc..1ee5e8600809 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -158,6 +158,11 @@ static inline bool transcoder_is_dsi(enum
> > transcoder transcoder)
> > return transcoder == TRANSCODER_DSI_A || transcoder ==
> > TRANSCODER_DSI_C; }
> >
> > +static inline bool transcoder_is_wd(enum transcoder transcoder) {
> > + return transcoder == TRANSCODER_WD_0 || transcoder ==
> > TRANSCODER_WD_1;
> > +}
> > +
> > /*
> > * Global legacy plane identifier. Valid only for primary/sprite
> > * planes on pre-g4x, and only for primary planes on g4x-bdw.
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index fe40e2a226d6..3ec11c937dbc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -550,7 +550,7 @@ static void intel_hdmi_info(struct seq_file *m,
> > static void intel_connector_info(struct seq_file *m,
> > struct drm_connector *connector) {
> > - struct intel_connector *intel_connector =
> > to_intel_connector(connector);
> > + struct intel_connector *intel_connector;
> > const struct drm_connector_state *conn_state = connector->state;
> > struct intel_encoder *encoder =
> > to_intel_encoder(conn_state->best_encoder);
> > @@ -573,6 +573,8 @@ static void intel_connector_info(struct seq_file
> *m,
> > if (!encoder)
> > return;
> >
> > + intel_connector = to_intel_connector(connector);
> > +
> > switch (connector->connector_type) {
> > case DRM_MODE_CONNECTOR_DisplayPort:
> > case DRM_MODE_CONNECTOR_eDP:
> > @@ -590,12 +592,15 @@ static void intel_connector_info(struct seq_file
> *m,
> > break;
> > }
> >
> > - seq_puts(m, "\tHDCP version: ");
> > - intel_hdcp_info(m, intel_connector);
> > + if (intel_connector) {
> > + seq_puts(m, "\tHDCP version: ");
> > + intel_hdcp_info(m, intel_connector);
> > + }
> >
> > seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc);
> >
> > - intel_panel_info(m, intel_connector);
> > + if (intel_connector)
> > + intel_panel_info(m, intel_connector);
> >
> > seq_printf(m, "\tmodes:\n");
> > list_for_each_entry(mode, &connector->modes, head) diff --git
> > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 8eacb9133fce..7931dbacaba7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -44,6 +44,7 @@
> > #include <drm/drm_vblank.h>
> > #include <drm/drm_vblank_work.h>
> > #include <drm/i915_mei_hdcp_interface.h>
> > +#include <drm/drm_writeback.h>
> > #include <media/cec-notifier.h>
> >
> > #include "i915_vma.h"
> > @@ -1371,6 +1372,11 @@ struct intel_crtc {
> > bool cpu_fifo_underrun_disabled;
> > bool pch_fifo_underrun_disabled;
> >
> > + struct {
> > + struct drm_pending_vblank_event *e;
> > + atomic_t work_busy;
> > + wait_queue_head_t wd_wait;
> > + } wd;
> > /* per-pipe watermark state */
> > struct {
> > /* watermarks currently being used */ @@ -1498,7 +1504,6
> @@ struct
> > cxsr_latency { #define to_intel_atomic_state(x) container_of(x,
> > struct intel_atomic_state, base) #define to_intel_crtc(x)
> > container_of(x, struct intel_crtc, base) #define
> > to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
> > -#define to_intel_wb_connector(x) container_of(x, struct
> > intel_wb_connector, base) #define to_intel_encoder(x) container_of(x,
> > struct intel_encoder, base) #define to_intel_framebuffer(x)
> > container_of(x, struct intel_framebuffer, base) #define
> > to_intel_plane(x) container_of(x, struct intel_plane, base) @@ -2077,8
> +2082,8 @@ intel_connector_list_iter_next(struct drm_connector_list_iter
> *iter)
> > struct drm_connector *connector;
> > bool flag = true;
> > /*
> > - * Skipping connector that are Writeback connector as they will
> > - * not be embedded in intel connector
> > + * An intel_connector entity is not created for a writeback
> > + * connector hence decoupling.
> > */
> > while (flag) {
> > connector = drm_connector_list_iter_next(iter);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> > b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index 52f2fe1735da..411f3366b9de 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -940,6 +940,9 @@ static int hsw_crtc_compute_clock(struct
> > intel_atomic_state *state,
> > intel_get_crtc_new_encoder(state, crtc_state);
> > int ret;
> >
> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD))
> > + return 0;
> > +
> > if (DISPLAY_VER(dev_priv) < 11 &&
> > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > return 0;
> > @@ -968,6 +971,9 @@ static int hsw_crtc_get_shared_dpll(struct
> > intel_atomic_state *state,
> > struct intel_encoder *encoder =
> > intel_get_crtc_new_encoder(state, crtc_state);
> >
> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD))
> > + return 0;
> > +
> > if (DISPLAY_VER(dev_priv) < 11 &&
> > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > return 0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index e1a90331c230..15792a5dd04c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -24,6 +24,7 @@
> > #include "intel_pch_display.h"
> > #include "intel_pm.h"
> > #include "skl_watermark.h"
> > +#include "intel_wd.h"
> >
> > static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
> > struct drm_modeset_acquire_ctx
> > *ctx) @@ -111,17 +112,17 @@ static void
> > intel_crtc_disable_noatomic(struct
> > intel_crtc *crtc,
> >
> > static void intel_modeset_update_connector_atomic_state(struct
> > drm_i915_private *i915) {
> > - struct intel_connector *connector;
> > + struct drm_connector *connector;
> > struct drm_connector_list_iter conn_iter;
> >
> > drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> > - for_each_intel_connector_iter(connector, &conn_iter) {
> > - struct drm_connector_state *conn_state = connector-
> > >base.state;
> > + drm_for_each_connector_iter(connector, &conn_iter) {
> > + struct drm_connector_state *conn_state = connector-
> >state;
> > struct intel_encoder *encoder =
> > - to_intel_encoder(connector->base.encoder);
> > + to_intel_encoder(connector->encoder);
> >
> > if (conn_state->crtc)
> > - drm_connector_put(&connector->base);
> > + drm_connector_put(connector);
> >
> > if (encoder) {
> > struct intel_crtc *crtc =
> > @@ -133,7 +134,7 @@ static void
> > intel_modeset_update_connector_atomic_state(struct drm_i915_private
> > conn_state->crtc = &crtc->base;
> > conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24)
> / 3;
> >
> > - drm_connector_get(&connector->base);
> > + drm_connector_get(connector);
> > } else {
> > conn_state->best_encoder = NULL;
> > conn_state->crtc = NULL;
> > @@ -433,6 +434,8 @@ static void
> intel_modeset_readout_hw_state(struct
> > drm_i915_private *i915)
> > struct intel_crtc *crtc;
> > struct intel_encoder *encoder;
> > struct intel_connector *connector;
> > + struct drm_connector *_connector;
> > + struct drm_encoder *_encoder;
>
> Usually in i915 for struct intel_connector *intel_connector, struct
> drm_connector *connector is used or Struct intel_connector *connector,
> struct drm_connector *conn is used.
> Using this _connector or _encoder will be a totally new notation. Can
> anyone of the above use used?
>
So this combo was chosen because of Jani's comment on one of the previous
Versions of the patches he commented
"These are the combos generally in use, from most preferred to least
preferred:
struct drm_encoder *_encoder;
struct intel_encoder *encoder
struct drm_encoder *encoder;
struct intel_encoder *intel_encoder
struct drm_encoder *drm_encoder
struct intel_encoder *encoder"
so would you still like to change the notation if so to which one of the above
> > struct drm_connector_list_iter conn_iter;
> > u8 active_pipes = 0;
> >
> > @@ -509,38 +512,70 @@ static void
> > intel_modeset_readout_hw_state(struct drm_i915_private *i915)
> > intel_dpll_readout_hw_state(i915);
> >
> > drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> > - for_each_intel_connector_iter(connector, &conn_iter) {
> > - if (connector->get_hw_state(connector)) {
> > - struct intel_crtc_state *crtc_state;
> > - struct intel_crtc *crtc;
> > -
> > - connector->base.dpms = DRM_MODE_DPMS_ON;
> > -
> > - encoder = intel_attached_encoder(connector);
> > - connector->base.encoder = &encoder->base;
> > -
> > - crtc = to_intel_crtc(encoder->base.crtc);
> > - crtc_state = crtc ? to_intel_crtc_state(crtc-
> > >base.state) : NULL;
> > -
> > - if (crtc_state && crtc_state->hw.active) {
> > - /*
> > - * This has to be done during hardware
> > readout
> > - * because anything calling .crtc_disable may
> > - * rely on the connector_mask being
> > accurate.
> > - */
> > - crtc_state->uapi.connector_mask |=
> > - drm_connector_mask(&connector-
> > >base);
> > - crtc_state->uapi.encoder_mask |=
> > - drm_encoder_mask(&encoder-
> > >base);
> > + drm_for_each_connector_iter(_connector, &conn_iter) {
> > + struct intel_crtc_state *crtc_state;
> > + struct intel_crtc *crtc;
> > + struct drm_writeback_connector *wb_conn;
> > + struct intel_wd *intel_wd;
> > +
> > + connector = to_intel_connector(_connector);
> > + if (!connector) {
> > + wb_conn =
> > drm_connector_to_writeback(_connector);
> > + intel_wd = wb_conn_to_intel_wd(wb_conn);
> > + _encoder = &intel_wd->base.base;
> > + _connector->encoder = _encoder;
> > + encoder = to_intel_encoder(_encoder);
> > + pipe = 0;
> > + if (encoder->get_hw_state(encoder, &pipe)) {
> > + _connector->dpms =
> > DRM_MODE_DPMS_ON;
> > + crtc = to_intel_crtc(_encoder->crtc);
> > + crtc_state = crtc ? to_intel_crtc_state(crtc-
> > >base.state) : NULL;
> > +
> > + if (crtc_state && crtc_state->hw.active) {
> > + /*
> > + * This has to be done during
> > hardware readout
> > + * because anything calling
> > .crtc_disable may
> > + * rely on the connector_mask being
> > accurate.
> > + */
> > + crtc_state->uapi.connector_mask |=
> > +
> > drm_connector_mask(&connector->base);
> > + crtc_state->uapi.encoder_mask |=
> > +
> > drm_encoder_mask(&encoder->base);
> > + }
> > + } else {
> > + _connector->dpms =
> > DRM_MODE_DPMS_OFF;
> > + _connector->encoder = NULL;
> > }
> > } else {
> > - connector->base.dpms = DRM_MODE_DPMS_OFF;
> > - connector->base.encoder = NULL;
> > + if (connector->get_hw_state(connector)) {
> > + connector->base.dpms =
> > DRM_MODE_DPMS_OFF;
> > + encoder =
> > intel_attached_encoder(connector);
> > + connector->base.encoder = &encoder->base;
> > +
> > + crtc = to_intel_crtc(encoder->base.crtc);
> > + crtc_state = crtc ? to_intel_crtc_state(crtc-
> > >base.state) : NULL;
> > +
> > + if (crtc_state && crtc_state->hw.active) {
> > + /*
> > + * This has to be done during
> > hardware readout
> > + * because anything calling
> > .crtc_disable may
> > + * rely on the connector_mask being
> > accurate.
> > + */
> > + crtc_state->uapi.connector_mask |=
> > +
> > drm_connector_mask(&connector->base);
> > + crtc_state->uapi.encoder_mask |=
> > +
> > drm_encoder_mask(&encoder->base);
> > + }
> > + } else {
> > + connector->base.dpms =
> > DRM_MODE_DPMS_OFF;
> > + connector->base.encoder = NULL;
> > + }
> > }
> > drm_dbg_kms(&i915->drm,
> > - "[CONNECTOR:%d:%s] hw state readout: %s\n",
> > - connector->base.base.id, connector->base.name,
> > - str_enabled_disabled(connector->base.encoder));
> > + "[CONNECTOR:%d:%s] hw state readout:
> > %s\n",
> > + _connector->base.id, _connector->name,
> > + str_enabled_disabled(_connector-
> > >encoder));
> > +
> > }
> > drm_connector_list_iter_end(&conn_iter);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > index 0fdcf2e6d57f..80e9840e2e5f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > @@ -25,11 +25,16 @@
> > static void intel_connector_verify_state(struct intel_crtc_state
> *crtc_state,
> > struct drm_connector_state
> > *conn_state) {
> > - struct intel_connector *connector = to_intel_connector(conn_state-
> > >connector);
> > - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > + struct drm_connector *_connector = conn_state->connector;
> > + struct intel_connector *connector;
> > + struct drm_i915_private *i915 = to_i915(_connector->dev);
> >
> > drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
> > - connector->base.base.id, connector->base.name);
> > + _connector->base.id, _connector->name);
> > +
> > + connector = to_intel_connector(_connector);
> > + if (!connector)
> > + return;
> >
> > if (connector->get_hw_state(connector)) {
> > struct intel_encoder *encoder =
> > intel_attached_encoder(connector);
> > @@ -119,6 +124,9 @@ verify_encoder_state(struct drm_i915_private
> > *dev_priv, struct intel_atomic_stat
> > encoder->base.base.id,
> > encoder->base.name);
> >
> > + if (encoder->type == INTEL_OUTPUT_WD)
> > + continue;
> > +
> > for_each_oldnew_connector_in_state(&state->base,
> > connector, old_conn_state,
> > new_conn_state, i) {
> > if (old_conn_state->best_encoder == &encoder-
> > >base) @@ -177,6 +185,9 @@ verify_crtc_state(struct intel_crtc *crtc,
> >
> > intel_crtc_get_pipe_config(pipe_config);
> >
> > + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
> > + return;
> > +
> > /* we keep both pipes enabled on 830 */
> > if (IS_I830(dev_priv) && pipe_config->hw.active)
> > pipe_config->hw.active = new_crtc_state->hw.active; diff --
> git
> > a/drivers/gpu/drm/i915/display/intel_opregion.c
> > b/drivers/gpu/drm/i915/display/intel_opregion.c
> > index caa07ef34f21..1bcb4b58d992 100644
> > --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> > +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> > @@ -374,6 +374,9 @@ int intel_opregion_notify_encoder(struct
> > intel_encoder *intel_encoder,
> > if (ret)
> > return ret;
> >
> > + if (intel_encoder->type == INTEL_OUTPUT_WD)
> > + return 0;
> > +
> > if (intel_encoder->type == INTEL_OUTPUT_DSI)
> > port = 0;
> > else
> > diff --git a/drivers/gpu/drm/i915/display/intel_wd.c
> > b/drivers/gpu/drm/i915/display/intel_wd.c
> > new file mode 100644
> > index 000000000000..e3e990f4f26f
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_wd.c
> > @@ -0,0 +1,695 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2022 Intel Corporation */
> > +
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_fourcc.h>
> > +
> > +#include "intel_atomic.h"
> > +#include "intel_connector.h"
> > +#include "intel_wd.h"
> > +#include "intel_fb_pin.h"
> > +#include "intel_de.h"
> > +
> > +enum {
> > + WD_CAPTURE_4_PIX,
> > + WD_CAPTURE_2_PIX,
> > +} wd_capture_format;
> > +
> > +struct drm_writeback_job
> > +*intel_get_writeback_job_from_queue(struct intel_wd *intel_wd) {
> > + struct drm_writeback_job *job;
> > + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev);
> > + struct drm_writeback_connector *wb_conn =
> > + &intel_wd->wb_conn;
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&wb_conn->job_lock, flags);
> > + job = list_first_entry_or_null(&wb_conn->job_queue,
> > + struct drm_writeback_job,
> > + list_entry);
> > + spin_unlock_irqrestore(&wb_conn->job_lock, flags);
> > + if (job == NULL) {
> > + drm_dbg_kms(&i915->drm, "job queue is empty\n");
> > + return NULL;
> > + }
> > +
> > + return job;
> > +}
> > +
> > +static const u32 wd_fmts[] = {
> > + DRM_FORMAT_YUV444,
> > + DRM_FORMAT_XYUV8888,
> > + DRM_FORMAT_XBGR8888,
> > + DRM_FORMAT_XRGB8888,
> > + DRM_FORMAT_Y410,
> > + DRM_FORMAT_YUV422,
> > + DRM_FORMAT_XBGR2101010,
> > + DRM_FORMAT_RGB565,
> > +};
> > +
> > +static int intel_wd_get_format(int pixel_format) {
> > + int wd_format = -EINVAL;
> > +
> > + switch (pixel_format) {
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_XBGR2101010:
> > + case DRM_FORMAT_XYUV8888:
> > + case DRM_FORMAT_YUV444:
> > + wd_format = WD_CAPTURE_4_PIX;
> > + break;
> > + case DRM_FORMAT_YUV422:
> > + case DRM_FORMAT_RGB565:
> > + wd_format = WD_CAPTURE_2_PIX;
> > + break;
> > + default:
> > + DRM_ERROR("unsupported pixel format %x!\n",
> > + pixel_format);
> > + }
> > +
> > + return wd_format;
> > +}
> > +
> > +static int intel_wd_verify_pix_format(int format) {
> > + const struct drm_format_info *info = drm_format_info(format);
> > + int pix_format = info->format;
> > + int i = 0;
> > +
> > + for (i = 0; i < ARRAY_SIZE(wd_fmts); i++)
> > + if (pix_format == wd_fmts[i])
> > + return 0;
> > +
> > + return true;
> > +}
> > +
> > +static u32 intel_wd_get_stride(const struct intel_crtc_state *crtc_state,
> > + int format)
> > +{
> > + const struct drm_format_info *info = drm_format_info(format);
> > + int wd_format;
> > + int hactive, pixel_size;
> > +
> > + wd_format = intel_wd_get_format(info->format);
> > +
> > + switch (wd_format) {
> > + case WD_CAPTURE_4_PIX:
> > + pixel_size = 4;
> > + break;
> > + case WD_CAPTURE_2_PIX:
> > + pixel_size = 2;
> > + break;
> > + default:
> > + pixel_size = 1;
> > + break;
> > + }
> > +
> > + hactive = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> > +
> > + return DIV_ROUND_UP(hactive * pixel_size, 64); }
> > +
> > +static int intel_wd_pin_fb(struct intel_wd *intel_wd,
> > + struct drm_framebuffer *fb)
> > +{
> > + const struct i915_gtt_view view = {
> > + .type = I915_GTT_VIEW_NORMAL,
> > + };
> > + struct i915_vma *vma;
> > +
> > + vma = intel_pin_and_fence_fb_obj(fb, false, &view, false,
> > + &intel_wd->flags);
> > +
> > + if (IS_ERR(vma))
> > + return PTR_ERR(vma);
> > +
> > + intel_wd->vma = vma;
> > + return 0;
> > +}
> > +
> > +static void intel_configure_slicing_strategy(struct drm_i915_private
> *i915,
> > + struct intel_wd *intel_wd,
> > + u32 *tmp)
> > +{
> > + *tmp &= ~WD_STRAT_MASK;
> > + if (intel_wd->slicing_strategy == 1)
> > + *tmp |= WD_SLICING_STRAT_1_1;
> > + else if (intel_wd->slicing_strategy == 2)
> > + *tmp |= WD_SLICING_STRAT_2_1;
> > + else if (intel_wd->slicing_strategy == 3)
> > + *tmp |= WD_SLICING_STRAT_4_1;
> > + else if (intel_wd->slicing_strategy == 4)
> > + *tmp |= WD_SLICING_STRAT_8_1;
> > +
> > + intel_de_write(i915, WD_STREAMCAP_CTL(intel_wd->trans),
> > + *tmp);
> > +}
> > +
> > +static enum drm_mode_status
> > +intel_wd_mode_valid(struct drm_connector *connector,
> > + struct drm_display_mode *mode)
> > +{
> > + return MODE_OK;
> > +}
> > +
> > +static int intel_wd_get_modes(struct drm_connector *connector) {
> > + return 0;
> > +}
> > +
> > +static void intel_wd_get_config(struct intel_encoder *encoder,
> > + struct intel_crtc_state *pipe_config) {
> > + struct intel_crtc *intel_crtc =
> > + to_intel_crtc(pipe_config->uapi.crtc);
> > +
> > + if (intel_crtc) {
> > + memcpy(pipe_config, intel_crtc->config,
> > + sizeof(*pipe_config));
> > + pipe_config->output_types |= BIT(INTEL_OUTPUT_WD);
> > + }
> > +}
> > +
> > +static int intel_wd_compute_config(struct intel_encoder *encoder,
> > + struct intel_crtc_state *pipe_config,
> > + struct drm_connector_state *conn_state) {
> > + struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
> > + struct drm_writeback_job *job;
> > +
> > + job = intel_get_writeback_job_from_queue(intel_wd);
> > + if (job || conn_state->writeback_job) {
> > + /*
> > + * Saving reference of pipe/crtc for later use if
> > + * writeback job is present
> > + */
> > + intel_wd->wd_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + return 0;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void intel_wd_get_power_domains(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state) {
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
> > + intel_wakeref_t wakeref;
> > +
> > + wakeref = intel_display_power_get(i915, encoder->power_domain);
> > +
> > + intel_wd->io_wakeref[0] = wakeref;
> > +}
> > +
> > +static bool intel_wd_get_hw_state(struct intel_encoder *encoder,
> > + enum pipe *pipe)
> > +{
> > + bool ret = false;
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
> > + struct intel_crtc *wd_crtc = intel_wd->wd_crtc;
> > + intel_wakeref_t wakeref;
> > + u32 tmp;
> > +
> > + if (wd_crtc)
> > + return false;
> > +
> > + wakeref = intel_display_power_get_if_enabled(dev_priv,
> > + encoder->power_domain);
> > +
> > + if (!wakeref)
> > + goto out;
> > +
> > + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> > + ret = tmp & WD_TRANS_ACTIVE;
> > + if (ret) {
> > + *pipe = wd_crtc->pipe;
> > + return true;
> > + }
> > +
> > +out:
> > + intel_display_power_put(dev_priv, encoder->power_domain,
> > wakeref);
> > + return false;
> > +}
> > +
> > +static int intel_wd_encoder_atomic_check(struct drm_encoder *encoder,
> > + struct drm_crtc_state *crtc_st,
> > + struct drm_connector_state
> > *conn_st) {
> > + /* Check for the format and buffers and property validity */
> > + struct drm_framebuffer *fb;
> > + struct drm_writeback_job *job = conn_st->writeback_job;
> > + struct drm_i915_private *i915 = to_i915(encoder->dev);
> > + const struct drm_display_mode *mode = &crtc_st->mode;
> > + int ret;
> > +
> > + if (!job) {
> > + drm_dbg_kms(&i915->drm, "No writeback job created
> > returning\n");
> > + return -EINVAL;
> > + }
> > +
> > + fb = job->fb;
> > + if (!fb) {
> > + drm_dbg_kms(&i915->drm, "Invalid framebuffer\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (fb->width != mode->hdisplay || fb->height != mode->vdisplay) {
> > + drm_dbg_kms(&i915->drm, "Invalid framebuffer size
> > %ux%u\n",
> > + fb->width, fb->height);
> > + return -EINVAL;
> > + }
> > +
> > + ret = intel_wd_verify_pix_format(fb->format->format);
> > + if (ret) {
> > + drm_dbg_kms(&i915->drm, "Unsupported framebuffer
> > format %08x\n",
> > + fb->format->format);
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +
> > +static const struct drm_encoder_helper_funcs wd_encoder_helper_funcs
> > +=
> > {
> > + .atomic_check = intel_wd_encoder_atomic_check, };
> > +
> > +static void intel_wd_connector_destroy(struct drm_connector
> > +*connector) {
> > + drm_connector_cleanup(connector);
> > +}
> > +
> > +static enum drm_connector_status
> > +intel_wd_connector_detect(struct drm_connector *connector, bool
> > +force) {
> > + return connector_status_connected;
> > +}
> > +
> > +static const struct drm_connector_funcs wb_connector_funcs = {
> > + .detect = intel_wd_connector_detect,
> > + .reset = drm_atomic_helper_connector_reset,
> > + .destroy = intel_wd_connector_destroy,
> > + .fill_modes = drm_helper_probe_single_connector_modes,
> > + .atomic_destroy_state =
> > drm_atomic_helper_connector_destroy_state,
> > + .atomic_duplicate_state =
> > drm_atomic_helper_connector_duplicate_state,
> > +};
> > +
> > +static const struct drm_connector_helper_funcs
> > wb_connector_helper_funcs = {
> > + .get_modes = intel_wd_get_modes,
> > + .mode_valid = intel_wd_mode_valid,
> > +};
> > +
> > +static const struct drm_encoder_funcs drm_writeback_encoder_funcs = {
> > + .destroy = drm_encoder_cleanup,
> > +};
> > +
> > +static bool intel_fastset_dis(struct intel_encoder *encoder,
> > + struct intel_crtc_state *pipe_config) {
> > + return false;
> > +}
> > +
> > +static void intel_wd_connector_init(struct intel_wd *intel_wd) {
> > + drm_atomic_helper_connector_reset(&intel_wd->wb_conn.base);
> > +}
> > +
> > +static void intel_wd_disable_capture(struct intel_wd *intel_wd) {
> > + struct drm_i915_private *dev_priv = to_i915(intel_wd-
> > >base.base.dev);
> > + u32 tmp;
> > +
> > + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), 0xFF);
> > + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> > + tmp &= WD_TRANS_DISABLE;
> > + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp);
> > + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd-
> > >trans));
> > +}
> > +
> > +void intel_wd_init(struct drm_i915_private *i915, enum transcoder
> > +trans) {
> > + struct intel_wd *intel_wd;
> > + struct intel_encoder *encoder;
> > + struct drm_writeback_connector *wb_conn;
> > + int n_formats = ARRAY_SIZE(wd_fmts);
> > + struct drm_encoder *drm_enc;
> > + int err, ret;
> > +
> > + intel_wd = kzalloc(sizeof(*intel_wd), GFP_KERNEL);
> > + if (!intel_wd)
> > + return;
> > +
> > + intel_wd_connector_init(intel_wd);
> > + encoder = &intel_wd->base;
> > + drm_enc = &encoder->base;
> > + wb_conn = &intel_wd->wb_conn;
> > + intel_wd->trans = trans;
> > + intel_wd->triggered_cap_mode = 1;
> > + intel_wd->frame_num = 1;
> > + intel_wd->slicing_strategy = 1;
> > + encoder->get_config = intel_wd_get_config;
> > + encoder->compute_config = intel_wd_compute_config;
> > + encoder->get_hw_state = intel_wd_get_hw_state;
> > + encoder->type = INTEL_OUTPUT_WD;
> > + encoder->cloneable = 0;
> > + encoder->pipe_mask = ~0;
> > + encoder->power_domain = POWER_DOMAIN_TRANSCODER_B;
> > + encoder->get_power_domains = intel_wd_get_power_domains;
> > + encoder->initial_fastset_check = intel_fastset_dis;
> > +
> > + drm_encoder_helper_add(drm_enc,
> > + &wd_encoder_helper_funcs);
> > +
> > + drm_enc->possible_crtcs = ~0;
> > + ret = drm_encoder_init(&i915->drm, drm_enc,
> > + &drm_writeback_encoder_funcs,
> > + DRM_MODE_ENCODER_VIRTUAL, NULL);
> > +
> > + if (ret) {
> > + drm_dbg_kms(&i915->drm,
> > + "Writeback drm_encoder init Failed: %d\n",
> > + ret);
> > + goto cleanup;
> > + }
> > +
> > + err = drm_writeback_connector_init_with_encoder(&i915->drm,
> > + wb_conn, drm_enc, &wb_connector_funcs,
> > + wd_fmts, n_formats);
> > +
> > + if (err != 0) {
> > + drm_dbg_kms(&i915->drm,
> > + "drm_writeback_connector_init: Failed: %d\n",
> > + err);
> > + goto cleanup;
> > + }
> > +
> > + wb_conn->base.encoder = drm_enc;
> > + drm_connector_helper_add(&wb_conn->base,
> > &wb_connector_helper_funcs);
> > + wb_conn->base.status = connector_status_connected;
> > + return;
> > +
> > +cleanup:
> > + kfree(intel_wd);
> > + return;
> > +}
> > +
> > +static void intel_wd_writeback_complete(struct intel_wd *intel_wd,
> > + struct drm_writeback_job *job,
> > + int status)
> > +{
> > + struct drm_writeback_connector *wb_conn =
> > + &intel_wd->wb_conn;
> > + drm_writeback_signal_completion(wb_conn, status); }
> > +
> > +static int intel_wd_setup_transcoder(struct intel_wd *intel_wd,
> > + struct intel_crtc_state *pipe_config,
> > + struct drm_connector_state *conn_state,
> > + struct drm_writeback_job *job) {
> > + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + enum pipe pipe = intel_crtc->pipe;
> > + struct drm_framebuffer *fb;
> > + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> > + struct drm_gem_object *wd_fb_obj;
> > + int ret;
> > + u32 stride, tmp;
> > + u16 hactive, vactive;
> > +
> > + fb = job->fb;
> > + wd_fb_obj = fb->obj[0];
> > + if (!wd_fb_obj) {
> > + drm_dbg_kms(&dev_priv->drm, "No framebuffer gem object
> > created\n");
> > + return -EINVAL;
> > + }
> > +
> > + ret = intel_wd_pin_fb(intel_wd, fb);
> > + drm_WARN_ON(&dev_priv->drm, ret != 0);
> > + /* Write stride and surface registers in that particular order */
> > + stride = intel_wd_get_stride(pipe_config, fb->format->format);
> > +
> > + tmp = intel_de_read(dev_priv, WD_STRIDE(intel_wd->trans));
> > + tmp &= ~WD_STRIDE_MASK;
> > + tmp |= (stride << WD_STRIDE_SHIFT);
> > +
> > + intel_de_write(dev_priv, WD_STRIDE(intel_wd->trans), tmp);
> > +
> > + tmp = intel_de_read(dev_priv, WD_SURF(intel_wd->trans));
> > +
> > + intel_de_write(dev_priv, WD_SURF(intel_wd->trans),
> > + i915_ggtt_offset(intel_wd->vma));
> > +
> > + tmp = intel_de_read_fw(dev_priv, WD_IIR(intel_wd->trans));
> > + intel_de_write_fw(dev_priv, WD_IIR(intel_wd->trans), tmp);
> > +
> > + tmp = ~(WD_GTT_FAULT_INT | WD_WRITE_COMPLETE_INT |
> > WD_FRAME_COMPLETE_INT |
> > + WD_VBLANK_INT | WD_OVERRUN_INT |
> > WD_CAPTURING_INT);
> > + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), tmp);
> > +
> > + if (intel_wd->stream_cap) {
> > + tmp = intel_de_read(dev_priv,
> > + WD_STREAMCAP_CTL(intel_wd->trans));
> > + tmp |= WD_STREAM_CAP_MODE_EN;
> > + intel_configure_slicing_strategy(dev_priv, intel_wd, &tmp);
> > + }
> > +
> > + hactive = pipe_config->uapi.mode.hdisplay;
> > + vactive = pipe_config->uapi.mode.vdisplay;
> > + tmp = intel_de_read(dev_priv, HTOTAL(intel_wd->trans));
> > + tmp = intel_de_read(dev_priv, VTOTAL(intel_wd->trans));
> > +
> > + /* minimum hactive as per bspec: 64 pixels */
> > + if (hactive < 64)
> > + drm_err(&dev_priv->drm, "hactive is less then 64 pixels\n");
> > +
> > + intel_de_write(dev_priv, HTOTAL(intel_wd->trans), hactive - 1);
> > + intel_de_write(dev_priv, VTOTAL(intel_wd->trans), vactive - 1);
> > +
> > + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd-
> > >trans));
> > + /* select pixel format */
> > + tmp &= ~WD_PIX_FMT_MASK;
> > +
> > + switch (fb->format->format) {
> > + default:
> > + fallthrough;
> > + case DRM_FORMAT_YUYV:
> > + tmp |= WD_PIX_FMT_YUYV;
> > + break;
> > + case DRM_FORMAT_XYUV8888:
> > + tmp |= WD_PIX_FMT_XYUV8888;
> > + break;
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_XRGB8888:
> > + tmp |= WD_PIX_FMT_XBGR8888;
> > + break;
> > + case DRM_FORMAT_Y410:
> > + tmp |= WD_PIX_FMT_Y410;
> > + break;
> > + case DRM_FORMAT_YUV422:
> > + tmp |= WD_PIX_FMT_YUV422;
> > + break;
> > + case DRM_FORMAT_XBGR2101010:
> > + tmp |= WD_PIX_FMT_XBGR2101010;
> > + break;
> > + case DRM_FORMAT_RGB565:
> > + tmp |= WD_PIX_FMT_RGB565;
> > + break;
> > + }
> > +
> > + if (intel_wd->triggered_cap_mode)
> > + tmp |= WD_TRIGGERED_CAP_MODE_ENABLE;
> > +
> > + if (intel_wd->stream_cap)
> > + tmp |= WD_CTL_POINTER_DTDH;
> > +
> > + /* select input pipe */
> > + tmp &= ~WD_INPUT_SELECT_MASK;
> > + switch (pipe) {
> > + default:
> > + fallthrough;
> > + case PIPE_A:
> > + tmp |= WD_INPUT_PIPE_A;
> > + break;
> > + case PIPE_B:
> > + tmp |= WD_INPUT_PIPE_B;
> > + break;
> > + case PIPE_C:
> > + tmp |= WD_INPUT_PIPE_C;
> > + break;
> > + case PIPE_D:
> > + tmp |= WD_INPUT_PIPE_D;
> > + break;
> > + }
> > +
> > + /* enable DDI buffer */
> > + if (!(tmp & TRANS_WD_FUNC_ENABLE))
> > + tmp |= TRANS_WD_FUNC_ENABLE;
> > +
> > + intel_de_write(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans),
> > tmp);
> > +
> > + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> > + ret = tmp & WD_TRANS_ACTIVE;
> > + if (!ret) {
> > + /* enable the transcoder */
> > + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> > + tmp |= WD_TRANS_ENABLE;
> > + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp);
> > +
> > + /* wait for transcoder to be enabled */
> > + if (intel_de_wait_for_set(dev_priv, PIPECONF(intel_wd-
> > >trans),
> > + WD_TRANS_ACTIVE, 10))
> > + drm_err(&dev_priv->drm, "WD transcoder could not
> > be enabled\n");
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int intel_wd_capture(struct intel_wd *intel_wd,
> > + struct intel_crtc_state *pipe_config,
> > + struct drm_connector_state *conn_state,
> > + struct drm_writeback_job *job) {
> > + u32 tmp;
> > + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev);
> > + int ret = 0, status = 0;
> > + struct intel_crtc *wd_crtc = intel_wd->wd_crtc;
> > + unsigned long flags;
> > +
> > + if (!job->out_fence)
> > + drm_dbg_kms(&i915->drm, "Not able to get out_fence for
> > job\n");
> > +
> > + ret = intel_wd_setup_transcoder(intel_wd, pipe_config,
> > + conn_state, job);
> > +
> > + if (ret < 0) {
> > + drm_dbg_kms(&i915->drm,
> > + "WD transcoder setup not completed aborting
> > capture\n");
> > + return -1;
> > + }
> > +
> > + if (!wd_crtc) {
> > + drm_err(&i915->drm, "CRTC not attached\n");
> > + return -1;
> > + }
> > +
> > + tmp = intel_de_read_fw(i915, WD_TRANS_FUNC_CTL(intel_wd-
> > >trans));
> > + tmp |= START_TRIGGER_FRAME;
> > + tmp &= ~WD_FRAME_NUMBER_MASK;
> > + tmp |= intel_wd->frame_num;
> > + intel_de_write_fw(i915, WD_TRANS_FUNC_CTL(intel_wd-
> > >trans), tmp);
> Why this tab space?
Have not given a tab space here
>
> > +
> > + if (!intel_de_wait_for_set(i915, WD_IIR(intel_wd->trans),
> > + WD_FRAME_COMPLETE_INT, 100)){
> > + drm_dbg_kms(&i915->drm, "frame captured\n");
> > + status = 0;
> > + } else {
> > + drm_dbg_kms(&i915->drm, "frame not captured triggering
> > stop frame\n");
> > + tmp = intel_de_read(i915, WD_TRANS_FUNC_CTL(intel_wd-
> > >trans));
> > + tmp |= STOP_TRIGGER_FRAME;
> > + intel_de_write(i915, WD_TRANS_FUNC_CTL(intel_wd-
> >trans),
> > tmp);
> > + status = -1;
> > + }
> > +
> > + intel_wd_writeback_complete(intel_wd, job, status);
> > + if (wd_crtc->wd.e) {
> > + spin_lock_irqsave(&i915->drm.event_lock, flags);
> > + drm_dbg_kms(&i915->drm, "send %p\n", wd_crtc->wd.e);
> Can this debug print be moved outside the spin_lock_irqsave.?
>
Causes an error to be thrown if I do as wd.e needs to be locked.
> > + drm_crtc_send_vblank_event(&wd_crtc->base,
> > + wd_crtc->wd.e);
> > + spin_unlock_irqrestore(&i915->drm.event_lock, flags);
> > + wd_crtc->wd.e = NULL;
> > + } else {
> > + drm_err(&i915->drm, "Event NULL! %p, %p\n", &i915->drm,
> > + wd_crtc);
> > + }
> > + if (!intel_get_writeback_job_from_queue(intel_wd))
> > + intel_wd_disable_capture(intel_wd);
> > + return 0;
> > +}
> > +
> > +void intel_wd_enable_capture(struct intel_crtc_state *pipe_config,
> > + struct drm_connector_state *conn_state) {
> > + struct drm_i915_private *i915 =
> > + to_i915(conn_state->connector->dev);
> > + struct drm_writeback_connector *wb_conn =
> > + drm_connector_to_writeback(conn_state->connector);
> > + struct intel_wd *intel_wd = wb_conn_to_intel_wd(wb_conn);
> > + struct drm_writeback_job *job;
> > +
> > + job = intel_get_writeback_job_from_queue(intel_wd);
> > + if (!job) {
> > + drm_dbg_kms(&i915->drm,
> > + "job queue is empty not capturing any frame\n");
> > + return;
> > + }
> > +
> > + intel_wd_capture(intel_wd, pipe_config,
> > + conn_state, job);
> > + intel_wd->frame_num += 1;
> > +}
> > +
> > +void intel_wd_set_vblank_event(struct intel_atomic_state *state,
> > +struct
> > intel_crtc *intel_crtc,
> > + struct intel_crtc_state *intel_crtc_state) {
> > + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev);
> > + struct drm_crtc_state *crtc_state = &intel_crtc_state->uapi;
> > + struct intel_encoder *encoder;
> > + struct intel_wd *intel_wd;
> > + struct drm_connector_state *conn_state;
> > + struct drm_connector *connector;
> > + int i;
> > +
> > + for_each_intel_encoder(&i915->drm, encoder) {
> > + if (encoder->type != INTEL_OUTPUT_WD)
> > + continue;
> > +
> > + intel_wd = enc_to_intel_wd(encoder);
> > + if (!intel_wd->wd_crtc)
> > + return;
> > + }
> > +
> > + if (intel_wd && intel_crtc == intel_wd->wd_crtc) {
> > + for_each_new_connector_in_state(&state->base, connector,
> > conn_state,
> > + i) {
> > + if (!conn_state->writeback_job)
> > + continue;
> > +
> > + intel_crtc->wd.e = crtc_state->event;
> > + crtc_state->event = NULL;
> > + }
> > + }
> > +}
> > +
> > +void intel_wd_handle_isr(struct drm_i915_private *i915) {
> > + u32 iir_value = 0;
> > + struct intel_encoder *encoder;
> > + struct intel_wd *intel_wd;
> > +
> > + iir_value = intel_de_read(i915, WD_IIR(TRANSCODER_WD_0));
> > +
> > + for_each_intel_encoder(&i915->drm, encoder) {
> > +
> > + if (encoder->type != INTEL_OUTPUT_WD)
> > + continue;
> > +
> > + intel_wd = enc_to_intel_wd(encoder);
> > + if (!intel_wd->wd_crtc) {
> > + drm_err(&i915->drm, "NO CRTC attached with
> > WD\n");
> > + goto clear_iir;
> > + }
> > + }
> > +
> > + if (iir_value & WD_FRAME_COMPLETE_INT)
> > + return;
> > +
> > +clear_iir:
> > + intel_de_write(i915, WD_IIR(TRANSCODER_WD_0), iir_value); }
> > diff --git a/drivers/gpu/drm/i915/display/intel_wd.h
> > b/drivers/gpu/drm/i915/display/intel_wd.h
> > new file mode 100644
> > index 000000000000..0fcd1a746593
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_wd.h
> > @@ -0,0 +1,48 @@
> > +/* SPDX-License-Identifier: MIT*/
> > +/*
> > + * Copyright © 2022 Intel Corporation */
> > +
> > +#ifndef _INTEL_WD_H
> > +#define _INTEL_WD_H
> > +
> > +#include <drm/drm_crtc.h>
> > +
> > +#include "intel_display_types.h"
> > +
> > +#define I915_MAX_WD_TANSCODERS 2
> > +
> > +struct intel_wd {
> > + struct intel_encoder base;
> > + struct drm_writeback_connector wb_conn;
> > + struct intel_crtc *wd_crtc;
> > + intel_wakeref_t io_wakeref[I915_MAX_WD_TANSCODERS];
> > + enum transcoder trans;
> > + struct i915_vma *vma;
> > + unsigned long flags;
> > + struct drm_writeback_job *job;
> > + int triggered_cap_mode;
> > + int frame_num;
> > + bool stream_cap;
> > + bool start_capture;
> > + int slicing_strategy;
> > +};
> > +
> > +static inline struct intel_wd *enc_to_intel_wd(struct intel_encoder
> > +*encoder) {
> > + return container_of(&encoder->base, struct intel_wd, base.base); }
> > +
> > +static inline struct intel_wd *wb_conn_to_intel_wd(struct
> > +drm_writeback_connector *wb_conn) {
> > + return container_of(wb_conn, struct intel_wd, wb_conn); }
> > +
> > +void intel_wd_init(struct drm_i915_private *dev_priv, enum transcoder
> > +trans); void intel_wd_enable_capture(struct intel_crtc_state
> *pipe_config,
> > + struct drm_connector_state *conn_state); void
> > +intel_wd_handle_isr(struct drm_i915_private *dev_priv); void
> > +intel_wd_set_vblank_event(struct intel_atomic_state *state, struct
> > intel_crtc *crtc,
> > + struct intel_crtc_state *crtc_state); struct
> > drm_writeback_job
> > +*intel_get_writeback_job_from_queue(struct intel_wd *intel_wd);
> > +#endif/* _INTEL_WD_H */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 55794b87a6c1..503a21c77d14
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -34,6 +34,7 @@
> >
> > #include <linux/pm_qos.h>
> >
> > +#include <drm/drm_writeback.h>
> > #include <drm/ttm/ttm_device.h>
> >
> > #include "display/intel_display.h"
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c index 86a42d9e8041..ee0255d9eb64
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -42,6 +42,7 @@
> > #include "display/intel_hotplug.h"
> > #include "display/intel_lpe_audio.h"
> > #include "display/intel_psr.h"
> > +#include "display/intel_wd.h"
> >
> > #include "gt/intel_breadcrumbs.h"
> > #include "gt/intel_gt.h"
> > @@ -2342,6 +2343,11 @@ gen8_de_misc_irq_handler(struct
> > drm_i915_private *dev_priv, u32 iir)
> > found = true;
> > }
> >
> > + if (iir & GEN8_DE_MISC_WD0) {
> > + intel_wd_handle_isr(dev_priv);
> > + found = true;
> > + }
> > +
> > if (iir & GEN8_DE_EDP_PSR) {
> > struct intel_encoder *encoder;
> > u32 psr_iir;
> > @@ -3767,7 +3773,7 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > u32 de_pipe_enables;
> > u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
> > u32 de_port_enables;
> > - u32 de_misc_masked = GEN8_DE_EDP_PSR;
> > + u32 de_misc_masked = GEN8_DE_EDP_PSR | GEN8_DE_MISC_WD0;
> > u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> > BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
> > enum pipe pipe;
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c index 19fc00bcd7b9..d6eb63aefc47
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -868,7 +868,8 @@ static const struct intel_device_info jsl_info = {
> > .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) |
> > BIT(PIPE_D), \
> > .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) |
> > BIT(TRANSCODER_B) | \
> > BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> > - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> > + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1) | \
> > + BIT(TRANSCODER_WD_0), \
> > .display.pipe_offsets = { \
> > [TRANSCODER_A] = PIPE_A_OFFSET, \
> > [TRANSCODER_B] = PIPE_B_OFFSET, \
> > @@ -876,6 +877,8 @@ static const struct intel_device_info jsl_info = {
> > [TRANSCODER_D] = PIPE_D_OFFSET, \
> > [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> > [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> > + [TRANSCODER_WD_0] = PIPE_WD0_OFFSET, \
> > + [TRANSCODER_WD_1] = PIPE_WD1_OFFSET, \
> > }, \
> > .display.trans_offsets = { \
> > [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ @@ -884,6
> > +887,8 @@ static const struct intel_device_info jsl_info = {
> > [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> > [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> > [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> > + [TRANSCODER_WD_0] = TRANSCODER_WD0_OFFSET, \
> > + [TRANSCODER_WD_1] = TRANSCODER_WD1_OFFSET, \
> > }, \
> > TGL_CURSOR_OFFSETS, \
> > .has_global_mocs = 1, \
> > --
> > 2.25.1
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v4 3/3] drm/i915: Enabling WD Transcoder
2022-09-19 6:28 ` Kandpal, Suraj
@ 2022-09-19 6:31 ` Murthy, Arun R
0 siblings, 0 replies; 10+ messages in thread
From: Murthy, Arun R @ 2022-09-19 6:31 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx; +Cc: Nikula, Jani
-----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Monday, September 19, 2022 11:58 AM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Borah, Chaitanya Kumar
> <chaitanya.kumar.borah@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> Subject: RE: [PATCH v4 3/3] drm/i915: Enabling WD Transcoder
>
> Hi Arun,
>
> > > From: Suraj Kandpal <suraj.kandpal@intel.com>
> > >
> > > Adding support for writeback transcoder to start capturing frames
> > > using interrupt mechanism
> > >
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
---------------------
> > > ---
> > > drivers/gpu/drm/i915/Makefile | 1 +
> > > drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
> > > drivers/gpu/drm/i915/display/intel_crtc.c | 6 +
> > > .../drm/i915/display/intel_crtc_state_dump.c | 1 +
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +
> > > drivers/gpu/drm/i915/display/intel_display.c | 68 +-
> > > drivers/gpu/drm/i915/display/intel_display.h | 5 +
> > > .../drm/i915/display/intel_display_debugfs.c | 13 +-
> > > .../drm/i915/display/intel_display_types.h | 11 +-
> > > drivers/gpu/drm/i915/display/intel_dpll.c | 6 +
> > > .../drm/i915/display/intel_modeset_setup.c | 103 ++-
> > > .../drm/i915/display/intel_modeset_verify.c | 17 +-
> > > drivers/gpu/drm/i915/display/intel_opregion.c | 3 +
> > > drivers/gpu/drm/i915/display/intel_wd.c | 695 ++++++++++++++++++
> > > drivers/gpu/drm/i915/display/intel_wd.h | 48 ++
> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > drivers/gpu/drm/i915/i915_irq.c | 8 +-
> > > drivers/gpu/drm/i915/i915_pci.c | 7 +-
> > > 18 files changed, 951 insertions(+), 49 deletions(-) create mode
> > > 100644 drivers/gpu/drm/i915/display/intel_wd.c
> > > create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h
> > >
> > > diff --git a/drivers/gpu/drm/i915/Makefile
> > > b/drivers/gpu/drm/i915/Makefile index a26edcdadc21..f34db43cf58d
> > > 100644
> > > --- a/drivers/gpu/drm/i915/Makefile
> > > +++ b/drivers/gpu/drm/i915/Makefile
> > > @@ -304,6 +304,7 @@ i915-y += \
> > > display/intel_tv.o \
> > > display/intel_vdsc.o \
> > > display/intel_vrr.o \
> > > + display/intel_wd.o \
> > > display/vlv_dsi.o \
> > > display/vlv_dsi_pll.o
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c
> > > b/drivers/gpu/drm/i915/display/intel_acpi.c
> > > index e78430001f07..ae08db164f73 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_acpi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_acpi.c
> > > @@ -247,6 +247,7 @@ static u32 acpi_display_type(struct
> > > intel_connector
> > > *connector)
> > > case DRM_MODE_CONNECTOR_LVDS:
> > > case DRM_MODE_CONNECTOR_eDP:
> > > case DRM_MODE_CONNECTOR_DSI:
> > > + case DRM_MODE_CONNECTOR_WRITEBACK:
> > > display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL;
> > > break;
> > > case DRM_MODE_CONNECTOR_Unknown:
> > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > index 6792a9056f46..66d552758720 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > @@ -491,6 +491,9 @@ void intel_pipe_update_start(struct
> > > intel_crtc_state
> > > *new_crtc_state)
> > > if (new_crtc_state->do_async_flip)
> > > return;
> > >
> > > + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
> > > + return;
> > > +
> > > if (intel_crtc_needs_vblank_work(new_crtc_state))
> > > intel_crtc_vblank_work_init(new_crtc_state);
> > >
> > > @@ -638,6 +641,9 @@ void intel_pipe_update_end(struct
> > intel_crtc_state
> > > *new_crtc_state)
> > > if (new_crtc_state->do_async_flip)
> > > return;
> > >
> > > + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
> > > + return;
> > > +
> > > trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
> > >
> > > /*
> > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > > b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > > index e9212f69c360..8435065f3b7d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > > @@ -71,6 +71,7 @@ static const char * const output_type_str[] = {
> > > OUTPUT_TYPE(DSI),
> > > OUTPUT_TYPE(DDI),
> > > OUTPUT_TYPE(DP_MST),
> > > + OUTPUT_TYPE(WD),
> > > };
> > >
> > > #undef OUTPUT_TYPE
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 643832d55c28..ea8e07a957ab 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -1953,6 +1953,12 @@ void
> > > intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> > > */
> > > if (encoder->type == INTEL_OUTPUT_DP_MST)
> > > return;
> > > + /*
> > > + * WD transcoder is a virtual encoder hence sanization
> > > + * is not required for it
> > > + */
> > > + if (encoder->type == INTEL_OUTPUT_WD)
> > > + return;
> > >
> > > if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
> > > u8 pipe_mask;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 2d0018ae34b1..15b2b7a6a110 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -115,6 +115,7 @@
> > > #include "intel_sprite.h"
> > > #include "intel_tc.h"
> > > #include "intel_vga.h"
> > > +#include "intel_wd.h"
> > > #include "i9xx_plane.h"
> > > #include "skl_scaler.h"
> > > #include "skl_universal_plane.h"
> > > @@ -1511,6 +1512,10 @@ static void
> > > intel_encoders_update_prepare(struct
> > > intel_atomic_state *state)
> > > continue;
> > >
> > > intel_connector = to_intel_connector(connector);
> > > + /* intel_connector instance is not created for WD
> > transcoder
> > > */
> > > + if (!intel_connector)
> > > + continue;
> > > +
> > > encoder =
> > > intel_connector_primary_encoder(intel_connector);
> > > if (!encoder->update_prepare)
> > > continue;
> > > @@ -1540,6 +1545,10 @@ static void
> > > intel_encoders_update_complete(struct intel_atomic_state *state)
> > > continue;
> > >
> > > intel_connector = to_intel_connector(connector);
> > > + /* intel_connector instance is not created for WD
> > transcoder
> > > */
> > > + if (!intel_connector)
> > > + continue;
> > > +
> > > encoder =
> > > intel_connector_primary_encoder(intel_connector);
> > > if (!encoder->update_complete)
> > > continue;
> > > @@ -1550,6 +1559,37 @@ static void
> > > intel_encoders_update_complete(struct intel_atomic_state *state)
> > > }
> > > }
> > >
> > > +static void intel_queue_writeback_job(struct intel_atomic_state
> > > +*state) {
> > > + struct drm_connector_state *new_conn_state;
> > > + struct drm_connector *connector;
> > > + struct drm_writeback_connector *wb_conn;
> > > + int i;
> > > +
> > > + for_each_new_connector_in_state(&state->base, connector,
> > > new_conn_state,
> > > + i) {
> > > + if (!new_conn_state->writeback_job)
> > > + continue;
> > > +
> > > + wb_conn = drm_connector_to_writeback(connector);
> > > + drm_writeback_queue_job(wb_conn, new_conn_state);
> > > + }
> > > +}
> > > +
> > > +static void intel_enable_writeback_capture(struct intel_atomic_state
> > > +*state,struct intel_crtc_state *crtc_state) {
> > > + struct drm_connector_state *new_conn_state;
> > > + struct drm_connector *connector;
> > > + int i;
> > > +
> > > + for_each_new_connector_in_state(&state->base, connector,
> > > new_conn_state,
> > > + i) {
> > > + if (connector->connector_type !=
> > > DRM_MODE_CONNECTOR_WRITEBACK)
> > > + continue;
> > > + intel_wd_enable_capture(crtc_state, new_conn_state);
> > > + }
> > > +}
> > > +
> > > static void intel_encoders_pre_pll_enable(struct intel_atomic_state
> > *state,
> > > struct intel_crtc *crtc)
> > > {
> > > @@ -1650,8 +1690,12 @@ static void intel_encoders_post_disable(struct
> > > intel_atomic_state *state,
> > > int i;
> > >
> > > for_each_old_connector_in_state(&state->base, conn,
> > old_conn_state,
> > > i) {
> > > - struct intel_encoder *encoder =
> > > - to_intel_encoder(old_conn_state->best_encoder);
> > > + struct intel_encoder *encoder;
> > > +
> > > + if (conn->connector_type ==
> > > DRM_MODE_CONNECTOR_WRITEBACK)
> > > + continue;
> > > +
> > > + encoder = to_intel_encoder(old_conn_state-
> > >best_encoder);
> > >
> > > if (old_conn_state->crtc != &crtc->base)
> > > continue;
> > > @@ -1928,7 +1972,8 @@ static void hsw_crtc_enable(struct
> > > intel_atomic_state *state,
> > > bdw_set_pipemisc(new_crtc_state);
> > >
> > > if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
> > > - !transcoder_is_dsi(cpu_transcoder))
> > > + !transcoder_is_dsi(cpu_transcoder) &&
> > > + !transcoder_is_wd(cpu_transcoder))
> > > hsw_configure_cpu_transcoder(new_crtc_state);
> > >
> > > crtc->active = true;
> > > @@ -7528,6 +7573,11 @@ static void intel_atomic_commit_tail(struct
> > > intel_atomic_state *state)
> > > }
> > > }
> > >
> > > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > > + if ((new_crtc_state->output_types &
> > > BIT(INTEL_OUTPUT_WD)))
> > > + intel_wd_set_vblank_event(state, crtc,
> > > new_crtc_state);
> > > + }
> > > +
> > > intel_encoders_update_prepare(state);
> > >
> > > intel_dbuf_pre_plane_update(state);
> > > @@ -7538,6 +7588,14 @@ static void intel_atomic_commit_tail(struct
> > > intel_atomic_state *state)
> > > intel_crtc_enable_flip_done(state, crtc);
> > > }
> > >
> > > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > > + if ((new_crtc_state->output_types &
> > > BIT(INTEL_OUTPUT_WD)))
> > > + {
> > > + intel_queue_writeback_job(state);
> > > + intel_enable_writeback_capture(state,
> > > new_crtc_state);
> > > + }
> > > + }
> > > +
> > > /* Now enable the clocks, plane, pipe, and connectors that we set
> > > up. */
> > > dev_priv->display.funcs.display->commit_modeset_enables(state);
> > >
> > > @@ -7892,6 +7950,10 @@ static void intel_setup_outputs(struct
> > > drm_i915_private *dev_priv)
> > > if (!HAS_DISPLAY(dev_priv))
> > > return;
> > >
> > > + /* Initializing WD transcoder */
> > > + if (DISPLAY_VER(dev_priv) >= 12)
> > > + intel_wd_init(dev_priv, TRANSCODER_WD_0);
> > > +
> > > if (IS_DG2(dev_priv)) {
> > > intel_ddi_init(dev_priv, PORT_A);
> > > intel_ddi_init(dev_priv, PORT_B);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> > > b/drivers/gpu/drm/i915/display/intel_display.h
> > > index 102bf7d47ccc..1ee5e8600809 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > > @@ -158,6 +158,11 @@ static inline bool transcoder_is_dsi(enum
> > > transcoder transcoder)
> > > return transcoder == TRANSCODER_DSI_A || transcoder ==
> > > TRANSCODER_DSI_C; }
> > >
> > > +static inline bool transcoder_is_wd(enum transcoder transcoder) {
> > > + return transcoder == TRANSCODER_WD_0 || transcoder ==
> > > TRANSCODER_WD_1;
> > > +}
> > > +
> > > /*
> > > * Global legacy plane identifier. Valid only for primary/sprite
> > > * planes on pre-g4x, and only for primary planes on g4x-bdw.
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > index fe40e2a226d6..3ec11c937dbc 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > @@ -550,7 +550,7 @@ static void intel_hdmi_info(struct seq_file *m,
> > > static void intel_connector_info(struct seq_file *m,
> > > struct drm_connector *connector) {
> > > - struct intel_connector *intel_connector =
> > > to_intel_connector(connector);
> > > + struct intel_connector *intel_connector;
> > > const struct drm_connector_state *conn_state = connector->state;
> > > struct intel_encoder *encoder =
> > > to_intel_encoder(conn_state->best_encoder);
> > > @@ -573,6 +573,8 @@ static void intel_connector_info(struct seq_file
> > *m,
> > > if (!encoder)
> > > return;
> > >
> > > + intel_connector = to_intel_connector(connector);
> > > +
> > > switch (connector->connector_type) {
> > > case DRM_MODE_CONNECTOR_DisplayPort:
> > > case DRM_MODE_CONNECTOR_eDP:
> > > @@ -590,12 +592,15 @@ static void intel_connector_info(struct seq_file
> > *m,
> > > break;
> > > }
> > >
> > > - seq_puts(m, "\tHDCP version: ");
> > > - intel_hdcp_info(m, intel_connector);
> > > + if (intel_connector) {
> > > + seq_puts(m, "\tHDCP version: ");
> > > + intel_hdcp_info(m, intel_connector);
> > > + }
> > >
> > > seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc);
> > >
> > > - intel_panel_info(m, intel_connector);
> > > + if (intel_connector)
> > > + intel_panel_info(m, intel_connector);
> > >
> > > seq_printf(m, "\tmodes:\n");
> > > list_for_each_entry(mode, &connector->modes, head) diff --git
> > > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 8eacb9133fce..7931dbacaba7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -44,6 +44,7 @@
> > > #include <drm/drm_vblank.h>
> > > #include <drm/drm_vblank_work.h>
> > > #include <drm/i915_mei_hdcp_interface.h>
> > > +#include <drm/drm_writeback.h>
> > > #include <media/cec-notifier.h>
> > >
> > > #include "i915_vma.h"
> > > @@ -1371,6 +1372,11 @@ struct intel_crtc {
> > > bool cpu_fifo_underrun_disabled;
> > > bool pch_fifo_underrun_disabled;
> > >
> > > + struct {
> > > + struct drm_pending_vblank_event *e;
> > > + atomic_t work_busy;
> > > + wait_queue_head_t wd_wait;
> > > + } wd;
> > > /* per-pipe watermark state */
> > > struct {
> > > /* watermarks currently being used */ @@ -1498,7 +1504,6
> > @@ struct
> > > cxsr_latency { #define to_intel_atomic_state(x) container_of(x,
> > > struct intel_atomic_state, base) #define to_intel_crtc(x)
> > > container_of(x, struct intel_crtc, base) #define
> > > to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
> > > -#define to_intel_wb_connector(x) container_of(x, struct
> > > intel_wb_connector, base) #define to_intel_encoder(x) container_of(x,
> > > struct intel_encoder, base) #define to_intel_framebuffer(x)
> > > container_of(x, struct intel_framebuffer, base) #define
> > > to_intel_plane(x) container_of(x, struct intel_plane, base) @@ -2077,8
> > +2082,8 @@ intel_connector_list_iter_next(struct drm_connector_list_iter
> > *iter)
> > > struct drm_connector *connector;
> > > bool flag = true;
> > > /*
> > > - * Skipping connector that are Writeback connector as they will
> > > - * not be embedded in intel connector
> > > + * An intel_connector entity is not created for a writeback
> > > + * connector hence decoupling.
> > > */
> > > while (flag) {
> > > connector = drm_connector_list_iter_next(iter);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> > > b/drivers/gpu/drm/i915/display/intel_dpll.c
> > > index 52f2fe1735da..411f3366b9de 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > > @@ -940,6 +940,9 @@ static int hsw_crtc_compute_clock(struct
> > > intel_atomic_state *state,
> > > intel_get_crtc_new_encoder(state, crtc_state);
> > > int ret;
> > >
> > > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD))
> > > + return 0;
> > > +
> > > if (DISPLAY_VER(dev_priv) < 11 &&
> > > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > > return 0;
> > > @@ -968,6 +971,9 @@ static int hsw_crtc_get_shared_dpll(struct
> > > intel_atomic_state *state,
> > > struct intel_encoder *encoder =
> > > intel_get_crtc_new_encoder(state, crtc_state);
> > >
> > > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_WD))
> > > + return 0;
> > > +
> > > if (DISPLAY_VER(dev_priv) < 11 &&
> > > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > > return 0;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > > b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > > index e1a90331c230..15792a5dd04c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > > @@ -24,6 +24,7 @@
> > > #include "intel_pch_display.h"
> > > #include "intel_pm.h"
> > > #include "skl_watermark.h"
> > > +#include "intel_wd.h"
> > >
> > > static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
> > > struct drm_modeset_acquire_ctx
> > > *ctx) @@ -111,17 +112,17 @@ static void
> > > intel_crtc_disable_noatomic(struct
> > > intel_crtc *crtc,
> > >
> > > static void intel_modeset_update_connector_atomic_state(struct
> > > drm_i915_private *i915) {
> > > - struct intel_connector *connector;
> > > + struct drm_connector *connector;
> > > struct drm_connector_list_iter conn_iter;
> > >
> > > drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> > > - for_each_intel_connector_iter(connector, &conn_iter) {
> > > - struct drm_connector_state *conn_state = connector-
> > > >base.state;
> > > + drm_for_each_connector_iter(connector, &conn_iter) {
> > > + struct drm_connector_state *conn_state = connector-
> > >state;
> > > struct intel_encoder *encoder =
> > > - to_intel_encoder(connector->base.encoder);
> > > + to_intel_encoder(connector->encoder);
> > >
> > > if (conn_state->crtc)
> > > - drm_connector_put(&connector->base);
> > > + drm_connector_put(connector);
> > >
> > > if (encoder) {
> > > struct intel_crtc *crtc =
> > > @@ -133,7 +134,7 @@ static void
> > > intel_modeset_update_connector_atomic_state(struct drm_i915_private
> > > conn_state->crtc = &crtc->base;
> > > conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24)
> > / 3;
> > >
> > > - drm_connector_get(&connector->base);
> > > + drm_connector_get(connector);
> > > } else {
> > > conn_state->best_encoder = NULL;
> > > conn_state->crtc = NULL;
> > > @@ -433,6 +434,8 @@ static void
> > intel_modeset_readout_hw_state(struct
> > > drm_i915_private *i915)
> > > struct intel_crtc *crtc;
> > > struct intel_encoder *encoder;
> > > struct intel_connector *connector;
> > > + struct drm_connector *_connector;
> > > + struct drm_encoder *_encoder;
> >
> > Usually in i915 for struct intel_connector *intel_connector, struct
> > drm_connector *connector is used or Struct intel_connector *connector,
> > struct drm_connector *conn is used.
> > Using this _connector or _encoder will be a totally new notation. Can
> > anyone of the above use used?
> >
> So this combo was chosen because of Jani's comment on one of the previous
> Versions of the patches he commented
> "These are the combos generally in use, from most preferred to least
> preferred:
>
> struct drm_encoder *_encoder;
> struct intel_encoder *encoder
>
> struct drm_encoder *encoder;
> struct intel_encoder *intel_encoder
>
> struct drm_encoder *drm_encoder
> struct intel_encoder *encoder"
>
> so would you still like to change the notation if so to which one of the above
>
> > > struct drm_connector_list_iter conn_iter;
> > > u8 active_pipes = 0;
> > >
> > > @@ -509,38 +512,70 @@ static void
> > > intel_modeset_readout_hw_state(struct drm_i915_private *i915)
> > > intel_dpll_readout_hw_state(i915);
> > >
> > > drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> > > - for_each_intel_connector_iter(connector, &conn_iter) {
> > > - if (connector->get_hw_state(connector)) {
> > > - struct intel_crtc_state *crtc_state;
> > > - struct intel_crtc *crtc;
> > > -
> > > - connector->base.dpms = DRM_MODE_DPMS_ON;
> > > -
> > > - encoder = intel_attached_encoder(connector);
> > > - connector->base.encoder = &encoder->base;
> > > -
> > > - crtc = to_intel_crtc(encoder->base.crtc);
> > > - crtc_state = crtc ? to_intel_crtc_state(crtc-
> > > >base.state) : NULL;
> > > -
> > > - if (crtc_state && crtc_state->hw.active) {
> > > - /*
> > > - * This has to be done during hardware
> > > readout
> > > - * because anything calling .crtc_disable may
> > > - * rely on the connector_mask being
> > > accurate.
> > > - */
> > > - crtc_state->uapi.connector_mask |=
> > > - drm_connector_mask(&connector-
> > > >base);
> > > - crtc_state->uapi.encoder_mask |=
> > > - drm_encoder_mask(&encoder-
> > > >base);
> > > + drm_for_each_connector_iter(_connector, &conn_iter) {
> > > + struct intel_crtc_state *crtc_state;
> > > + struct intel_crtc *crtc;
> > > + struct drm_writeback_connector *wb_conn;
> > > + struct intel_wd *intel_wd;
> > > +
> > > + connector = to_intel_connector(_connector);
> > > + if (!connector) {
> > > + wb_conn =
> > > drm_connector_to_writeback(_connector);
> > > + intel_wd = wb_conn_to_intel_wd(wb_conn);
> > > + _encoder = &intel_wd->base.base;
> > > + _connector->encoder = _encoder;
> > > + encoder = to_intel_encoder(_encoder);
> > > + pipe = 0;
> > > + if (encoder->get_hw_state(encoder, &pipe)) {
> > > + _connector->dpms =
> > > DRM_MODE_DPMS_ON;
> > > + crtc = to_intel_crtc(_encoder->crtc);
> > > + crtc_state = crtc ? to_intel_crtc_state(crtc-
> > > >base.state) : NULL;
> > > +
> > > + if (crtc_state && crtc_state->hw.active) {
> > > + /*
> > > + * This has to be done during
> > > hardware readout
> > > + * because anything calling
> > > .crtc_disable may
> > > + * rely on the connector_mask being
> > > accurate.
> > > + */
> > > + crtc_state->uapi.connector_mask |=
> > > +
> > > drm_connector_mask(&connector->base);
> > > + crtc_state->uapi.encoder_mask |=
> > > +
> > > drm_encoder_mask(&encoder->base);
> > > + }
> > > + } else {
> > > + _connector->dpms =
> > > DRM_MODE_DPMS_OFF;
> > > + _connector->encoder = NULL;
> > > }
> > > } else {
> > > - connector->base.dpms = DRM_MODE_DPMS_OFF;
> > > - connector->base.encoder = NULL;
> > > + if (connector->get_hw_state(connector)) {
> > > + connector->base.dpms =
> > > DRM_MODE_DPMS_OFF;
> > > + encoder =
> > > intel_attached_encoder(connector);
> > > + connector->base.encoder = &encoder->base;
> > > +
> > > + crtc = to_intel_crtc(encoder->base.crtc);
> > > + crtc_state = crtc ? to_intel_crtc_state(crtc-
> > > >base.state) : NULL;
> > > +
> > > + if (crtc_state && crtc_state->hw.active) {
> > > + /*
> > > + * This has to be done during
> > > hardware readout
> > > + * because anything calling
> > > .crtc_disable may
> > > + * rely on the connector_mask being
> > > accurate.
> > > + */
> > > + crtc_state->uapi.connector_mask |=
> > > +
> > > drm_connector_mask(&connector->base);
> > > + crtc_state->uapi.encoder_mask |=
> > > +
> > > drm_encoder_mask(&encoder->base);
> > > + }
> > > + } else {
> > > + connector->base.dpms =
> > > DRM_MODE_DPMS_OFF;
> > > + connector->base.encoder = NULL;
> > > + }
> > > }
> > > drm_dbg_kms(&i915->drm,
> > > - "[CONNECTOR:%d:%s] hw state readout: %s\n",
> > > - connector->base.base.id, connector->base.name,
> > > - str_enabled_disabled(connector->base.encoder));
> > > + "[CONNECTOR:%d:%s] hw state readout:
> > > %s\n",
> > > + _connector->base.id, _connector->name,
> > > + str_enabled_disabled(_connector-
> > > >encoder));
> > > +
> > > }
> > > drm_connector_list_iter_end(&conn_iter);
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > > b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > > index 0fdcf2e6d57f..80e9840e2e5f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > > @@ -25,11 +25,16 @@
> > > static void intel_connector_verify_state(struct intel_crtc_state
> > *crtc_state,
> > > struct drm_connector_state
> > > *conn_state) {
> > > - struct intel_connector *connector = to_intel_connector(conn_state-
> > > >connector);
> > > - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > > + struct drm_connector *_connector = conn_state->connector;
> > > + struct intel_connector *connector;
> > > + struct drm_i915_private *i915 = to_i915(_connector->dev);
> > >
> > > drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
> > > - connector->base.base.id, connector->base.name);
> > > + _connector->base.id, _connector->name);
> > > +
> > > + connector = to_intel_connector(_connector);
> > > + if (!connector)
> > > + return;
> > >
> > > if (connector->get_hw_state(connector)) {
> > > struct intel_encoder *encoder =
> > > intel_attached_encoder(connector);
> > > @@ -119,6 +124,9 @@ verify_encoder_state(struct drm_i915_private
> > > *dev_priv, struct intel_atomic_stat
> > > encoder->base.base.id,
> > > encoder->base.name);
> > >
> > > + if (encoder->type == INTEL_OUTPUT_WD)
> > > + continue;
> > > +
> > > for_each_oldnew_connector_in_state(&state->base,
> > > connector, old_conn_state,
> > > new_conn_state, i) {
> > > if (old_conn_state->best_encoder == &encoder-
> > > >base) @@ -177,6 +185,9 @@ verify_crtc_state(struct intel_crtc *crtc,
> > >
> > > intel_crtc_get_pipe_config(pipe_config);
> > >
> > > + if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
> > > + return;
> > > +
> > > /* we keep both pipes enabled on 830 */
> > > if (IS_I830(dev_priv) && pipe_config->hw.active)
> > > pipe_config->hw.active = new_crtc_state->hw.active; diff --
> > git
> > > a/drivers/gpu/drm/i915/display/intel_opregion.c
> > > b/drivers/gpu/drm/i915/display/intel_opregion.c
> > > index caa07ef34f21..1bcb4b58d992 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> > > @@ -374,6 +374,9 @@ int intel_opregion_notify_encoder(struct
> > > intel_encoder *intel_encoder,
> > > if (ret)
> > > return ret;
> > >
> > > + if (intel_encoder->type == INTEL_OUTPUT_WD)
> > > + return 0;
> > > +
> > > if (intel_encoder->type == INTEL_OUTPUT_DSI)
> > > port = 0;
> > > else
> > > diff --git a/drivers/gpu/drm/i915/display/intel_wd.c
> > > b/drivers/gpu/drm/i915/display/intel_wd.c
> > > new file mode 100644
> > > index 000000000000..e3e990f4f26f
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/i915/display/intel_wd.c
> > > @@ -0,0 +1,695 @@
> > > +// SPDX-License-Identifier: MIT
> > > +/*
> > > + * Copyright © 2022 Intel Corporation */
> > > +
> > > +#include <drm/drm_atomic_helper.h>
> > > +#include <drm/drm_fourcc.h>
> > > +
> > > +#include "intel_atomic.h"
> > > +#include "intel_connector.h"
> > > +#include "intel_wd.h"
> > > +#include "intel_fb_pin.h"
> > > +#include "intel_de.h"
> > > +
> > > +enum {
> > > + WD_CAPTURE_4_PIX,
> > > + WD_CAPTURE_2_PIX,
> > > +} wd_capture_format;
> > > +
> > > +struct drm_writeback_job
> > > +*intel_get_writeback_job_from_queue(struct intel_wd *intel_wd) {
> > > + struct drm_writeback_job *job;
> > > + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev);
> > > + struct drm_writeback_connector *wb_conn =
> > > + &intel_wd->wb_conn;
> > > + unsigned long flags;
> > > +
> > > + spin_lock_irqsave(&wb_conn->job_lock, flags);
> > > + job = list_first_entry_or_null(&wb_conn->job_queue,
> > > + struct drm_writeback_job,
> > > + list_entry);
> > > + spin_unlock_irqrestore(&wb_conn->job_lock, flags);
> > > + if (job == NULL) {
> > > + drm_dbg_kms(&i915->drm, "job queue is empty\n");
> > > + return NULL;
> > > + }
> > > +
> > > + return job;
> > > +}
> > > +
> > > +static const u32 wd_fmts[] = {
> > > + DRM_FORMAT_YUV444,
> > > + DRM_FORMAT_XYUV8888,
> > > + DRM_FORMAT_XBGR8888,
> > > + DRM_FORMAT_XRGB8888,
> > > + DRM_FORMAT_Y410,
> > > + DRM_FORMAT_YUV422,
> > > + DRM_FORMAT_XBGR2101010,
> > > + DRM_FORMAT_RGB565,
> > > +};
> > > +
> > > +static int intel_wd_get_format(int pixel_format) {
> > > + int wd_format = -EINVAL;
> > > +
> > > + switch (pixel_format) {
> > > + case DRM_FORMAT_XBGR8888:
> > > + case DRM_FORMAT_XRGB8888:
> > > + case DRM_FORMAT_XBGR2101010:
> > > + case DRM_FORMAT_XYUV8888:
> > > + case DRM_FORMAT_YUV444:
> > > + wd_format = WD_CAPTURE_4_PIX;
> > > + break;
> > > + case DRM_FORMAT_YUV422:
> > > + case DRM_FORMAT_RGB565:
> > > + wd_format = WD_CAPTURE_2_PIX;
> > > + break;
> > > + default:
> > > + DRM_ERROR("unsupported pixel format %x!\n",
> > > + pixel_format);
> > > + }
> > > +
> > > + return wd_format;
> > > +}
> > > +
> > > +static int intel_wd_verify_pix_format(int format) {
> > > + const struct drm_format_info *info = drm_format_info(format);
> > > + int pix_format = info->format;
> > > + int i = 0;
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(wd_fmts); i++)
> > > + if (pix_format == wd_fmts[i])
> > > + return 0;
> > > +
> > > + return true;
> > > +}
> > > +
> > > +static u32 intel_wd_get_stride(const struct intel_crtc_state *crtc_state,
> > > + int format)
> > > +{
> > > + const struct drm_format_info *info = drm_format_info(format);
> > > + int wd_format;
> > > + int hactive, pixel_size;
> > > +
> > > + wd_format = intel_wd_get_format(info->format);
> > > +
> > > + switch (wd_format) {
> > > + case WD_CAPTURE_4_PIX:
> > > + pixel_size = 4;
> > > + break;
> > > + case WD_CAPTURE_2_PIX:
> > > + pixel_size = 2;
> > > + break;
> > > + default:
> > > + pixel_size = 1;
> > > + break;
> > > + }
> > > +
> > > + hactive = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> > > +
> > > + return DIV_ROUND_UP(hactive * pixel_size, 64); }
> > > +
> > > +static int intel_wd_pin_fb(struct intel_wd *intel_wd,
> > > + struct drm_framebuffer *fb)
> > > +{
> > > + const struct i915_gtt_view view = {
> > > + .type = I915_GTT_VIEW_NORMAL,
> > > + };
> > > + struct i915_vma *vma;
> > > +
> > > + vma = intel_pin_and_fence_fb_obj(fb, false, &view, false,
> > > + &intel_wd->flags);
> > > +
> > > + if (IS_ERR(vma))
> > > + return PTR_ERR(vma);
> > > +
> > > + intel_wd->vma = vma;
> > > + return 0;
> > > +}
> > > +
> > > +static void intel_configure_slicing_strategy(struct drm_i915_private
> > *i915,
> > > + struct intel_wd *intel_wd,
> > > + u32 *tmp)
> > > +{
> > > + *tmp &= ~WD_STRAT_MASK;
> > > + if (intel_wd->slicing_strategy == 1)
> > > + *tmp |= WD_SLICING_STRAT_1_1;
> > > + else if (intel_wd->slicing_strategy == 2)
> > > + *tmp |= WD_SLICING_STRAT_2_1;
> > > + else if (intel_wd->slicing_strategy == 3)
> > > + *tmp |= WD_SLICING_STRAT_4_1;
> > > + else if (intel_wd->slicing_strategy == 4)
> > > + *tmp |= WD_SLICING_STRAT_8_1;
> > > +
> > > + intel_de_write(i915, WD_STREAMCAP_CTL(intel_wd->trans),
> > > + *tmp);
> > > +}
> > > +
> > > +static enum drm_mode_status
> > > +intel_wd_mode_valid(struct drm_connector *connector,
> > > + struct drm_display_mode *mode)
> > > +{
> > > + return MODE_OK;
> > > +}
> > > +
> > > +static int intel_wd_get_modes(struct drm_connector *connector) {
> > > + return 0;
> > > +}
> > > +
> > > +static void intel_wd_get_config(struct intel_encoder *encoder,
> > > + struct intel_crtc_state *pipe_config) {
> > > + struct intel_crtc *intel_crtc =
> > > + to_intel_crtc(pipe_config->uapi.crtc);
> > > +
> > > + if (intel_crtc) {
> > > + memcpy(pipe_config, intel_crtc->config,
> > > + sizeof(*pipe_config));
> > > + pipe_config->output_types |= BIT(INTEL_OUTPUT_WD);
> > > + }
> > > +}
> > > +
> > > +static int intel_wd_compute_config(struct intel_encoder *encoder,
> > > + struct intel_crtc_state *pipe_config,
> > > + struct drm_connector_state *conn_state) {
> > > + struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
> > > + struct drm_writeback_job *job;
> > > +
> > > + job = intel_get_writeback_job_from_queue(intel_wd);
> > > + if (job || conn_state->writeback_job) {
> > > + /*
> > > + * Saving reference of pipe/crtc for later use if
> > > + * writeback job is present
> > > + */
> > > + intel_wd->wd_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > > + return 0;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static void intel_wd_get_power_domains(struct intel_encoder *encoder,
> > > + struct intel_crtc_state *crtc_state) {
> > > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > + struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
> > > + intel_wakeref_t wakeref;
> > > +
> > > + wakeref = intel_display_power_get(i915, encoder->power_domain);
> > > +
> > > + intel_wd->io_wakeref[0] = wakeref;
> > > +}
> > > +
> > > +static bool intel_wd_get_hw_state(struct intel_encoder *encoder,
> > > + enum pipe *pipe)
> > > +{
> > > + bool ret = false;
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > + struct intel_wd *intel_wd = enc_to_intel_wd(encoder);
> > > + struct intel_crtc *wd_crtc = intel_wd->wd_crtc;
> > > + intel_wakeref_t wakeref;
> > > + u32 tmp;
> > > +
> > > + if (wd_crtc)
> > > + return false;
> > > +
> > > + wakeref = intel_display_power_get_if_enabled(dev_priv,
> > > + encoder->power_domain);
> > > +
> > > + if (!wakeref)
> > > + goto out;
> > > +
> > > + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> > > + ret = tmp & WD_TRANS_ACTIVE;
> > > + if (ret) {
> > > + *pipe = wd_crtc->pipe;
> > > + return true;
> > > + }
> > > +
> > > +out:
> > > + intel_display_power_put(dev_priv, encoder->power_domain,
> > > wakeref);
> > > + return false;
> > > +}
> > > +
> > > +static int intel_wd_encoder_atomic_check(struct drm_encoder
> *encoder,
> > > + struct drm_crtc_state *crtc_st,
> > > + struct drm_connector_state
> > > *conn_st) {
> > > + /* Check for the format and buffers and property validity */
> > > + struct drm_framebuffer *fb;
> > > + struct drm_writeback_job *job = conn_st->writeback_job;
> > > + struct drm_i915_private *i915 = to_i915(encoder->dev);
> > > + const struct drm_display_mode *mode = &crtc_st->mode;
> > > + int ret;
> > > +
> > > + if (!job) {
> > > + drm_dbg_kms(&i915->drm, "No writeback job created
> > > returning\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + fb = job->fb;
> > > + if (!fb) {
> > > + drm_dbg_kms(&i915->drm, "Invalid framebuffer\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + if (fb->width != mode->hdisplay || fb->height != mode->vdisplay) {
> > > + drm_dbg_kms(&i915->drm, "Invalid framebuffer size
> > > %ux%u\n",
> > > + fb->width, fb->height);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + ret = intel_wd_verify_pix_format(fb->format->format);
> > > + if (ret) {
> > > + drm_dbg_kms(&i915->drm, "Unsupported framebuffer
> > > format %08x\n",
> > > + fb->format->format);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +
> > > +static const struct drm_encoder_helper_funcs
> wd_encoder_helper_funcs
> > > +=
> > > {
> > > + .atomic_check = intel_wd_encoder_atomic_check, };
> > > +
> > > +static void intel_wd_connector_destroy(struct drm_connector
> > > +*connector) {
> > > + drm_connector_cleanup(connector);
> > > +}
> > > +
> > > +static enum drm_connector_status
> > > +intel_wd_connector_detect(struct drm_connector *connector, bool
> > > +force) {
> > > + return connector_status_connected;
> > > +}
> > > +
> > > +static const struct drm_connector_funcs wb_connector_funcs = {
> > > + .detect = intel_wd_connector_detect,
> > > + .reset = drm_atomic_helper_connector_reset,
> > > + .destroy = intel_wd_connector_destroy,
> > > + .fill_modes = drm_helper_probe_single_connector_modes,
> > > + .atomic_destroy_state =
> > > drm_atomic_helper_connector_destroy_state,
> > > + .atomic_duplicate_state =
> > > drm_atomic_helper_connector_duplicate_state,
> > > +};
> > > +
> > > +static const struct drm_connector_helper_funcs
> > > wb_connector_helper_funcs = {
> > > + .get_modes = intel_wd_get_modes,
> > > + .mode_valid = intel_wd_mode_valid,
> > > +};
> > > +
> > > +static const struct drm_encoder_funcs drm_writeback_encoder_funcs =
> {
> > > + .destroy = drm_encoder_cleanup,
> > > +};
> > > +
> > > +static bool intel_fastset_dis(struct intel_encoder *encoder,
> > > + struct intel_crtc_state *pipe_config) {
> > > + return false;
> > > +}
> > > +
> > > +static void intel_wd_connector_init(struct intel_wd *intel_wd) {
> > > + drm_atomic_helper_connector_reset(&intel_wd->wb_conn.base);
> > > +}
> > > +
> > > +static void intel_wd_disable_capture(struct intel_wd *intel_wd) {
> > > + struct drm_i915_private *dev_priv = to_i915(intel_wd-
> > > >base.base.dev);
> > > + u32 tmp;
> > > +
> > > + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), 0xFF);
> > > + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> > > + tmp &= WD_TRANS_DISABLE;
> > > + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp);
> > > + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd-
> > > >trans));
> > > +}
> > > +
> > > +void intel_wd_init(struct drm_i915_private *i915, enum transcoder
> > > +trans) {
> > > + struct intel_wd *intel_wd;
> > > + struct intel_encoder *encoder;
> > > + struct drm_writeback_connector *wb_conn;
> > > + int n_formats = ARRAY_SIZE(wd_fmts);
> > > + struct drm_encoder *drm_enc;
> > > + int err, ret;
> > > +
> > > + intel_wd = kzalloc(sizeof(*intel_wd), GFP_KERNEL);
> > > + if (!intel_wd)
> > > + return;
> > > +
> > > + intel_wd_connector_init(intel_wd);
> > > + encoder = &intel_wd->base;
> > > + drm_enc = &encoder->base;
> > > + wb_conn = &intel_wd->wb_conn;
> > > + intel_wd->trans = trans;
> > > + intel_wd->triggered_cap_mode = 1;
> > > + intel_wd->frame_num = 1;
> > > + intel_wd->slicing_strategy = 1;
> > > + encoder->get_config = intel_wd_get_config;
> > > + encoder->compute_config = intel_wd_compute_config;
> > > + encoder->get_hw_state = intel_wd_get_hw_state;
> > > + encoder->type = INTEL_OUTPUT_WD;
> > > + encoder->cloneable = 0;
> > > + encoder->pipe_mask = ~0;
> > > + encoder->power_domain = POWER_DOMAIN_TRANSCODER_B;
> > > + encoder->get_power_domains = intel_wd_get_power_domains;
> > > + encoder->initial_fastset_check = intel_fastset_dis;
> > > +
> > > + drm_encoder_helper_add(drm_enc,
> > > + &wd_encoder_helper_funcs);
> > > +
> > > + drm_enc->possible_crtcs = ~0;
> > > + ret = drm_encoder_init(&i915->drm, drm_enc,
> > > + &drm_writeback_encoder_funcs,
> > > + DRM_MODE_ENCODER_VIRTUAL, NULL);
> > > +
> > > + if (ret) {
> > > + drm_dbg_kms(&i915->drm,
> > > + "Writeback drm_encoder init Failed: %d\n",
> > > + ret);
> > > + goto cleanup;
> > > + }
> > > +
> > > + err = drm_writeback_connector_init_with_encoder(&i915->drm,
> > > + wb_conn, drm_enc, &wb_connector_funcs,
> > > + wd_fmts, n_formats);
> > > +
> > > + if (err != 0) {
> > > + drm_dbg_kms(&i915->drm,
> > > + "drm_writeback_connector_init: Failed: %d\n",
> > > + err);
> > > + goto cleanup;
> > > + }
> > > +
> > > + wb_conn->base.encoder = drm_enc;
> > > + drm_connector_helper_add(&wb_conn->base,
> > > &wb_connector_helper_funcs);
> > > + wb_conn->base.status = connector_status_connected;
> > > + return;
> > > +
> > > +cleanup:
> > > + kfree(intel_wd);
> > > + return;
> > > +}
> > > +
> > > +static void intel_wd_writeback_complete(struct intel_wd *intel_wd,
> > > + struct drm_writeback_job *job,
> > > + int status)
> > > +{
> > > + struct drm_writeback_connector *wb_conn =
> > > + &intel_wd->wb_conn;
> > > + drm_writeback_signal_completion(wb_conn, status); }
> > > +
> > > +static int intel_wd_setup_transcoder(struct intel_wd *intel_wd,
> > > + struct intel_crtc_state *pipe_config,
> > > + struct drm_connector_state *conn_state,
> > > + struct drm_writeback_job *job) {
> > > + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > > + enum pipe pipe = intel_crtc->pipe;
> > > + struct drm_framebuffer *fb;
> > > + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> > > + struct drm_gem_object *wd_fb_obj;
> > > + int ret;
> > > + u32 stride, tmp;
> > > + u16 hactive, vactive;
> > > +
> > > + fb = job->fb;
> > > + wd_fb_obj = fb->obj[0];
> > > + if (!wd_fb_obj) {
> > > + drm_dbg_kms(&dev_priv->drm, "No framebuffer gem object
> > > created\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + ret = intel_wd_pin_fb(intel_wd, fb);
> > > + drm_WARN_ON(&dev_priv->drm, ret != 0);
> > > + /* Write stride and surface registers in that particular order */
> > > + stride = intel_wd_get_stride(pipe_config, fb->format->format);
> > > +
> > > + tmp = intel_de_read(dev_priv, WD_STRIDE(intel_wd->trans));
> > > + tmp &= ~WD_STRIDE_MASK;
> > > + tmp |= (stride << WD_STRIDE_SHIFT);
> > > +
> > > + intel_de_write(dev_priv, WD_STRIDE(intel_wd->trans), tmp);
> > > +
> > > + tmp = intel_de_read(dev_priv, WD_SURF(intel_wd->trans));
> > > +
> > > + intel_de_write(dev_priv, WD_SURF(intel_wd->trans),
> > > + i915_ggtt_offset(intel_wd->vma));
> > > +
> > > + tmp = intel_de_read_fw(dev_priv, WD_IIR(intel_wd->trans));
> > > + intel_de_write_fw(dev_priv, WD_IIR(intel_wd->trans), tmp);
> > > +
> > > + tmp = ~(WD_GTT_FAULT_INT | WD_WRITE_COMPLETE_INT |
> > > WD_FRAME_COMPLETE_INT |
> > > + WD_VBLANK_INT | WD_OVERRUN_INT |
> > > WD_CAPTURING_INT);
> > > + intel_de_write_fw(dev_priv, WD_IMR(intel_wd->trans), tmp);
> > > +
> > > + if (intel_wd->stream_cap) {
> > > + tmp = intel_de_read(dev_priv,
> > > + WD_STREAMCAP_CTL(intel_wd->trans));
> > > + tmp |= WD_STREAM_CAP_MODE_EN;
> > > + intel_configure_slicing_strategy(dev_priv, intel_wd, &tmp);
> > > + }
> > > +
> > > + hactive = pipe_config->uapi.mode.hdisplay;
> > > + vactive = pipe_config->uapi.mode.vdisplay;
> > > + tmp = intel_de_read(dev_priv, HTOTAL(intel_wd->trans));
> > > + tmp = intel_de_read(dev_priv, VTOTAL(intel_wd->trans));
> > > +
> > > + /* minimum hactive as per bspec: 64 pixels */
> > > + if (hactive < 64)
> > > + drm_err(&dev_priv->drm, "hactive is less then 64 pixels\n");
> > > +
> > > + intel_de_write(dev_priv, HTOTAL(intel_wd->trans), hactive - 1);
> > > + intel_de_write(dev_priv, VTOTAL(intel_wd->trans), vactive - 1);
> > > +
> > > + tmp = intel_de_read(dev_priv, WD_TRANS_FUNC_CTL(intel_wd-
> > > >trans));
> > > + /* select pixel format */
> > > + tmp &= ~WD_PIX_FMT_MASK;
> > > +
> > > + switch (fb->format->format) {
> > > + default:
> > > + fallthrough;
> > > + case DRM_FORMAT_YUYV:
> > > + tmp |= WD_PIX_FMT_YUYV;
> > > + break;
> > > + case DRM_FORMAT_XYUV8888:
> > > + tmp |= WD_PIX_FMT_XYUV8888;
> > > + break;
> > > + case DRM_FORMAT_XBGR8888:
> > > + case DRM_FORMAT_XRGB8888:
> > > + tmp |= WD_PIX_FMT_XBGR8888;
> > > + break;
> > > + case DRM_FORMAT_Y410:
> > > + tmp |= WD_PIX_FMT_Y410;
> > > + break;
> > > + case DRM_FORMAT_YUV422:
> > > + tmp |= WD_PIX_FMT_YUV422;
> > > + break;
> > > + case DRM_FORMAT_XBGR2101010:
> > > + tmp |= WD_PIX_FMT_XBGR2101010;
> > > + break;
> > > + case DRM_FORMAT_RGB565:
> > > + tmp |= WD_PIX_FMT_RGB565;
> > > + break;
> > > + }
> > > +
> > > + if (intel_wd->triggered_cap_mode)
> > > + tmp |= WD_TRIGGERED_CAP_MODE_ENABLE;
> > > +
> > > + if (intel_wd->stream_cap)
> > > + tmp |= WD_CTL_POINTER_DTDH;
> > > +
> > > + /* select input pipe */
> > > + tmp &= ~WD_INPUT_SELECT_MASK;
> > > + switch (pipe) {
> > > + default:
> > > + fallthrough;
> > > + case PIPE_A:
> > > + tmp |= WD_INPUT_PIPE_A;
> > > + break;
> > > + case PIPE_B:
> > > + tmp |= WD_INPUT_PIPE_B;
> > > + break;
> > > + case PIPE_C:
> > > + tmp |= WD_INPUT_PIPE_C;
> > > + break;
> > > + case PIPE_D:
> > > + tmp |= WD_INPUT_PIPE_D;
> > > + break;
> > > + }
> > > +
> > > + /* enable DDI buffer */
> > > + if (!(tmp & TRANS_WD_FUNC_ENABLE))
> > > + tmp |= TRANS_WD_FUNC_ENABLE;
> > > +
> > > + intel_de_write(dev_priv, WD_TRANS_FUNC_CTL(intel_wd->trans),
> > > tmp);
> > > +
> > > + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> > > + ret = tmp & WD_TRANS_ACTIVE;
> > > + if (!ret) {
> > > + /* enable the transcoder */
> > > + tmp = intel_de_read(dev_priv, PIPECONF(intel_wd->trans));
> > > + tmp |= WD_TRANS_ENABLE;
> > > + intel_de_write(dev_priv, PIPECONF(intel_wd->trans), tmp);
> > > +
> > > + /* wait for transcoder to be enabled */
> > > + if (intel_de_wait_for_set(dev_priv, PIPECONF(intel_wd-
> > > >trans),
> > > + WD_TRANS_ACTIVE, 10))
> > > + drm_err(&dev_priv->drm, "WD transcoder could not
> > > be enabled\n");
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int intel_wd_capture(struct intel_wd *intel_wd,
> > > + struct intel_crtc_state *pipe_config,
> > > + struct drm_connector_state *conn_state,
> > > + struct drm_writeback_job *job) {
> > > + u32 tmp;
> > > + struct drm_i915_private *i915 = to_i915(intel_wd->base.base.dev);
> > > + int ret = 0, status = 0;
> > > + struct intel_crtc *wd_crtc = intel_wd->wd_crtc;
> > > + unsigned long flags;
> > > +
> > > + if (!job->out_fence)
> > > + drm_dbg_kms(&i915->drm, "Not able to get out_fence for
> > > job\n");
> > > +
> > > + ret = intel_wd_setup_transcoder(intel_wd, pipe_config,
> > > + conn_state, job);
> > > +
> > > + if (ret < 0) {
> > > + drm_dbg_kms(&i915->drm,
> > > + "WD transcoder setup not completed aborting
> > > capture\n");
> > > + return -1;
> > > + }
> > > +
> > > + if (!wd_crtc) {
> > > + drm_err(&i915->drm, "CRTC not attached\n");
> > > + return -1;
> > > + }
> > > +
> > > + tmp = intel_de_read_fw(i915, WD_TRANS_FUNC_CTL(intel_wd-
> > > >trans));
> > > + tmp |= START_TRIGGER_FRAME;
> > > + tmp &= ~WD_FRAME_NUMBER_MASK;
> > > + tmp |= intel_wd->frame_num;
> > > + intel_de_write_fw(i915, WD_TRANS_FUNC_CTL(intel_wd-
> > > >trans), tmp);
> > Why this tab space?
> Have not given a tab space here
> >
> > > +
> > > + if (!intel_de_wait_for_set(i915, WD_IIR(intel_wd->trans),
> > > + WD_FRAME_COMPLETE_INT, 100)){
> > > + drm_dbg_kms(&i915->drm, "frame captured\n");
> > > + status = 0;
> > > + } else {
> > > + drm_dbg_kms(&i915->drm, "frame not captured triggering
> > > stop frame\n");
> > > + tmp = intel_de_read(i915, WD_TRANS_FUNC_CTL(intel_wd-
> > > >trans));
> > > + tmp |= STOP_TRIGGER_FRAME;
> > > + intel_de_write(i915, WD_TRANS_FUNC_CTL(intel_wd-
> > >trans),
> > > tmp);
> > > + status = -1;
> > > + }
> > > +
> > > + intel_wd_writeback_complete(intel_wd, job, status);
> > > + if (wd_crtc->wd.e) {
> > > + spin_lock_irqsave(&i915->drm.event_lock, flags);
> > > + drm_dbg_kms(&i915->drm, "send %p\n", wd_crtc->wd.e);
> > Can this debug print be moved outside the spin_lock_irqsave.?
> >
> Causes an error to be thrown if I do as wd.e needs to be locked.
> > > + drm_crtc_send_vblank_event(&wd_crtc->base,
> > > + wd_crtc->wd.e);
> > > + spin_unlock_irqrestore(&i915->drm.event_lock, flags);
> > > + wd_crtc->wd.e = NULL;
> > > + } else {
> > > + drm_err(&i915->drm, "Event NULL! %p, %p\n", &i915->drm,
> > > + wd_crtc);
> > > + }
> > > + if (!intel_get_writeback_job_from_queue(intel_wd))
> > > + intel_wd_disable_capture(intel_wd);
> > > + return 0;
> > > +}
> > > +
> > > +void intel_wd_enable_capture(struct intel_crtc_state *pipe_config,
> > > + struct drm_connector_state *conn_state) {
> > > + struct drm_i915_private *i915 =
> > > + to_i915(conn_state->connector->dev);
> > > + struct drm_writeback_connector *wb_conn =
> > > + drm_connector_to_writeback(conn_state->connector);
> > > + struct intel_wd *intel_wd = wb_conn_to_intel_wd(wb_conn);
> > > + struct drm_writeback_job *job;
> > > +
> > > + job = intel_get_writeback_job_from_queue(intel_wd);
> > > + if (!job) {
> > > + drm_dbg_kms(&i915->drm,
> > > + "job queue is empty not capturing any frame\n");
> > > + return;
> > > + }
> > > +
> > > + intel_wd_capture(intel_wd, pipe_config,
> > > + conn_state, job);
> > > + intel_wd->frame_num += 1;
> > > +}
> > > +
> > > +void intel_wd_set_vblank_event(struct intel_atomic_state *state,
> > > +struct
> > > intel_crtc *intel_crtc,
> > > + struct intel_crtc_state *intel_crtc_state) {
> > > + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev);
> > > + struct drm_crtc_state *crtc_state = &intel_crtc_state->uapi;
> > > + struct intel_encoder *encoder;
> > > + struct intel_wd *intel_wd;
> > > + struct drm_connector_state *conn_state;
> > > + struct drm_connector *connector;
> > > + int i;
> > > +
> > > + for_each_intel_encoder(&i915->drm, encoder) {
> > > + if (encoder->type != INTEL_OUTPUT_WD)
> > > + continue;
> > > +
> > > + intel_wd = enc_to_intel_wd(encoder);
> > > + if (!intel_wd->wd_crtc)
> > > + return;
> > > + }
> > > +
> > > + if (intel_wd && intel_crtc == intel_wd->wd_crtc) {
> > > + for_each_new_connector_in_state(&state->base, connector,
> > > conn_state,
> > > + i) {
> > > + if (!conn_state->writeback_job)
> > > + continue;
> > > +
> > > + intel_crtc->wd.e = crtc_state->event;
> > > + crtc_state->event = NULL;
> > > + }
> > > + }
> > > +}
> > > +
> > > +void intel_wd_handle_isr(struct drm_i915_private *i915) {
> > > + u32 iir_value = 0;
> > > + struct intel_encoder *encoder;
> > > + struct intel_wd *intel_wd;
> > > +
> > > + iir_value = intel_de_read(i915, WD_IIR(TRANSCODER_WD_0));
> > > +
> > > + for_each_intel_encoder(&i915->drm, encoder) {
> > > +
> > > + if (encoder->type != INTEL_OUTPUT_WD)
> > > + continue;
> > > +
> > > + intel_wd = enc_to_intel_wd(encoder);
> > > + if (!intel_wd->wd_crtc) {
> > > + drm_err(&i915->drm, "NO CRTC attached with
> > > WD\n");
> > > + goto clear_iir;
> > > + }
> > > + }
> > > +
> > > + if (iir_value & WD_FRAME_COMPLETE_INT)
> > > + return;
> > > +
> > > +clear_iir:
> > > + intel_de_write(i915, WD_IIR(TRANSCODER_WD_0), iir_value); }
> > > diff --git a/drivers/gpu/drm/i915/display/intel_wd.h
> > > b/drivers/gpu/drm/i915/display/intel_wd.h
> > > new file mode 100644
> > > index 000000000000..0fcd1a746593
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/i915/display/intel_wd.h
> > > @@ -0,0 +1,48 @@
> > > +/* SPDX-License-Identifier: MIT*/
> > > +/*
> > > + * Copyright © 2022 Intel Corporation */
> > > +
> > > +#ifndef _INTEL_WD_H
> > > +#define _INTEL_WD_H
> > > +
> > > +#include <drm/drm_crtc.h>
> > > +
> > > +#include "intel_display_types.h"
> > > +
> > > +#define I915_MAX_WD_TANSCODERS 2
> > > +
> > > +struct intel_wd {
> > > + struct intel_encoder base;
> > > + struct drm_writeback_connector wb_conn;
> > > + struct intel_crtc *wd_crtc;
> > > + intel_wakeref_t io_wakeref[I915_MAX_WD_TANSCODERS];
> > > + enum transcoder trans;
> > > + struct i915_vma *vma;
> > > + unsigned long flags;
> > > + struct drm_writeback_job *job;
> > > + int triggered_cap_mode;
> > > + int frame_num;
> > > + bool stream_cap;
> > > + bool start_capture;
> > > + int slicing_strategy;
> > > +};
> > > +
> > > +static inline struct intel_wd *enc_to_intel_wd(struct intel_encoder
> > > +*encoder) {
> > > + return container_of(&encoder->base, struct intel_wd, base.base); }
> > > +
> > > +static inline struct intel_wd *wb_conn_to_intel_wd(struct
> > > +drm_writeback_connector *wb_conn) {
> > > + return container_of(wb_conn, struct intel_wd, wb_conn); }
> > > +
> > > +void intel_wd_init(struct drm_i915_private *dev_priv, enum transcoder
> > > +trans); void intel_wd_enable_capture(struct intel_crtc_state
> > *pipe_config,
> > > + struct drm_connector_state *conn_state); void
> > > +intel_wd_handle_isr(struct drm_i915_private *dev_priv); void
> > > +intel_wd_set_vblank_event(struct intel_atomic_state *state, struct
> > > intel_crtc *crtc,
> > > + struct intel_crtc_state *crtc_state); struct
> > > drm_writeback_job
> > > +*intel_get_writeback_job_from_queue(struct intel_wd *intel_wd);
> > > +#endif/* _INTEL_WD_H */
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h index 55794b87a6c1..503a21c77d14
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -34,6 +34,7 @@
> > >
> > > #include <linux/pm_qos.h>
> > >
> > > +#include <drm/drm_writeback.h>
> > > #include <drm/ttm/ttm_device.h>
> > >
> > > #include "display/intel_display.h"
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c index 86a42d9e8041..ee0255d9eb64
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -42,6 +42,7 @@
> > > #include "display/intel_hotplug.h"
> > > #include "display/intel_lpe_audio.h"
> > > #include "display/intel_psr.h"
> > > +#include "display/intel_wd.h"
> > >
> > > #include "gt/intel_breadcrumbs.h"
> > > #include "gt/intel_gt.h"
> > > @@ -2342,6 +2343,11 @@ gen8_de_misc_irq_handler(struct
> > > drm_i915_private *dev_priv, u32 iir)
> > > found = true;
> > > }
> > >
> > > + if (iir & GEN8_DE_MISC_WD0) {
> > > + intel_wd_handle_isr(dev_priv);
> > > + found = true;
> > > + }
> > > +
> > > if (iir & GEN8_DE_EDP_PSR) {
> > > struct intel_encoder *encoder;
> > > u32 psr_iir;
> > > @@ -3767,7 +3773,7 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > u32 de_pipe_enables;
> > > u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
> > > u32 de_port_enables;
> > > - u32 de_misc_masked = GEN8_DE_EDP_PSR;
> > > + u32 de_misc_masked = GEN8_DE_EDP_PSR | GEN8_DE_MISC_WD0;
> > > u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> > > BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
> > > enum pipe pipe;
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c index 19fc00bcd7b9..d6eb63aefc47
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -868,7 +868,8 @@ static const struct intel_device_info jsl_info = {
> > > .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) |
> > > BIT(PIPE_D), \
> > > .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) |
> > > BIT(TRANSCODER_B) | \
> > > BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> > > - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> > > + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1) | \
> > > + BIT(TRANSCODER_WD_0), \
> > > .display.pipe_offsets = { \
> > > [TRANSCODER_A] = PIPE_A_OFFSET, \
> > > [TRANSCODER_B] = PIPE_B_OFFSET, \
> > > @@ -876,6 +877,8 @@ static const struct intel_device_info jsl_info = {
> > > [TRANSCODER_D] = PIPE_D_OFFSET, \
> > > [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> > > [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> > > + [TRANSCODER_WD_0] = PIPE_WD0_OFFSET, \
> > > + [TRANSCODER_WD_1] = PIPE_WD1_OFFSET, \
> > > }, \
> > > .display.trans_offsets = { \
> > > [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ @@ -884,6
> > > +887,8 @@ static const struct intel_device_info jsl_info = {
> > > [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> > > [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> > > [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> > > + [TRANSCODER_WD_0] = TRANSCODER_WD0_OFFSET, \
> > > + [TRANSCODER_WD_1] = TRANSCODER_WD1_OFFSET, \
> > > }, \
> > > TGL_CURSOR_OFFSETS, \
> > > .has_global_mocs = 1, \
> > > --
> > > 2.25.1
> >
> > Thanks and Regards,
> > Arun R Murthy
> > --------------------
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-09-19 6:31 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-14 7:12 [Intel-gfx] [PATCH v4 0/3] Enable Pipewriteback Kandpal, Suraj
2022-09-14 7:12 ` [Intel-gfx] [PATCH v4 1/3] drm/i915: Define WD trancoder for i915 Kandpal, Suraj
2022-09-14 7:12 ` [Intel-gfx] [PATCH v4 2/3] drm/i915 : Changing intel_connector iterators Kandpal, Suraj
2022-09-14 7:12 ` [Intel-gfx] [PATCH v4 3/3] drm/i915: Enabling WD Transcoder Kandpal, Suraj
2022-09-19 5:30 ` Murthy, Arun R
2022-09-19 6:28 ` Kandpal, Suraj
2022-09-19 6:31 ` Murthy, Arun R
2022-09-14 9:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable Pipewriteback (rev4) Patchwork
2022-09-14 9:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-14 23:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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