* [PATCH v3 0/4] Add dp-intf and dp nodes
@ 2022-09-16 2:50 ` Bo-Chen Chen
0 siblings, 0 replies; 10+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 2:50 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, matthias.bgg
Cc: angelogioacchino.delregno, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
This series add MediaTek dp-intf nodes and dp nodes.
This series is based on linux-next-20220915.
Changes for v3:
1. Update commit message for "arm64: dts: mediatek: cherry: Add edptx and dptx support".
Changes for v2:
1. Update commit messages.
2. reorder the place of "status = "disabled";"
3. reorder the place of dp-intf.
Bo-Chen Chen (4):
arm64: dts: mt8195: Add dp-intf nodes
arm64: dts: mt8195: Add edptx and dptx nodes
arm64: dts: mediatek: cherry: Add dp-intf ports
arm64: dts: mediatek: cherry: Add edptx and dptx support
.../boot/dts/mediatek/mt8195-cherry.dtsi | 86 +++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 48 +++++++++++
2 files changed, 134 insertions(+)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 1/4] arm64: dts: mt8195: Add dp-intf nodes
2022-09-16 2:50 ` Bo-Chen Chen
@ 2022-09-16 2:50 ` Bo-Chen Chen
-1 siblings, 0 replies; 10+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 2:50 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, matthias.bgg
Cc: angelogioacchino.delregno, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
Dp-intfs provide the pixel data to edptx and dptx. To support edptx
and dptx, we need to add dp-intf0 and dp-intf1 nodes.
Dp-intf0 is for edptx and dp-intf1 is for dptx.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..82d28e9f60c3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2067,6 +2067,17 @@
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
};
+ dp_intf0: dp-intf@1c015000 {
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c015000 0 0x1000>;
+ interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
+ <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL1>;
+ clock-names = "engine", "pixel", "pll";
+ status = "disabled";
+ };
+
mutex: mutex@1c016000 {
compatible = "mediatek,mt8195-disp-mutex";
reg = <0 0x1c016000 0 0x1000>;
@@ -2155,5 +2166,17 @@
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
+
+ dp_intf1: dp-intf@1c113000 {
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c113000 0 0x1000>;
+ interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
+ <&vdosys1 CLK_VDO1_DPINTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL2>;
+ clock-names = "engine", "pixel", "pll";
+ status = "disabled";
+ };
};
};
--
2.18.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v3 1/4] arm64: dts: mt8195: Add dp-intf nodes
@ 2022-09-16 2:50 ` Bo-Chen Chen
0 siblings, 0 replies; 10+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 2:50 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, matthias.bgg
Cc: angelogioacchino.delregno, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
Dp-intfs provide the pixel data to edptx and dptx. To support edptx
and dptx, we need to add dp-intf0 and dp-intf1 nodes.
Dp-intf0 is for edptx and dp-intf1 is for dptx.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..82d28e9f60c3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2067,6 +2067,17 @@
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
};
+ dp_intf0: dp-intf@1c015000 {
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c015000 0 0x1000>;
+ interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
+ <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL1>;
+ clock-names = "engine", "pixel", "pll";
+ status = "disabled";
+ };
+
mutex: mutex@1c016000 {
compatible = "mediatek,mt8195-disp-mutex";
reg = <0 0x1c016000 0 0x1000>;
@@ -2155,5 +2166,17 @@
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
+
+ dp_intf1: dp-intf@1c113000 {
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c113000 0 0x1000>;
+ interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
+ <&vdosys1 CLK_VDO1_DPINTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL2>;
+ clock-names = "engine", "pixel", "pll";
+ status = "disabled";
+ };
};
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 2/4] arm64: dts: mt8195: Add edptx and dptx nodes
2022-09-16 2:50 ` Bo-Chen Chen
@ 2022-09-16 2:50 ` Bo-Chen Chen
-1 siblings, 0 replies; 10+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 2:50 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, matthias.bgg
Cc: angelogioacchino.delregno, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
In MT8195, we use edptx as the internal display interface and use
dptx as the external display interface. Therefore, we need to add
these nodes to support the internal display and the external display.
- Add dp calibration data in the efuse node.
- Add edptx and dptx nodes for MT8195.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 82d28e9f60c3..83567d90ede6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1241,6 +1241,9 @@
reg = <0x189 0x2>;
bits = <7 5>;
};
+ dp_calibration: dp-data@1ac {
+ reg = <0x1ac 0x10>;
+ };
};
u3phy2: t-phy@11c40000 {
@@ -2178,5 +2181,27 @@
clock-names = "engine", "pixel", "pll";
status = "disabled";
};
+
+ edp_tx: edp-tx@1c500000 {
+ compatible = "mediatek,mt8195-edp-tx";
+ reg = <0 0x1c500000 0 0x8000>;
+ nvmem-cells = <&dp_calibration>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
+ interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
+ max-linkrate-mhz = <8100>;
+ status = "disabled";
+ };
+
+ dp_tx: dp-tx@1c600000 {
+ compatible = "mediatek,mt8195-dp-tx";
+ reg = <0 0x1c600000 0 0x8000>;
+ nvmem-cells = <&dp_calibration>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
+ interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
+ max-linkrate-mhz = <8100>;
+ status = "disabled";
+ };
};
};
--
2.18.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v3 2/4] arm64: dts: mt8195: Add edptx and dptx nodes
@ 2022-09-16 2:50 ` Bo-Chen Chen
0 siblings, 0 replies; 10+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 2:50 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, matthias.bgg
Cc: angelogioacchino.delregno, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
In MT8195, we use edptx as the internal display interface and use
dptx as the external display interface. Therefore, we need to add
these nodes to support the internal display and the external display.
- Add dp calibration data in the efuse node.
- Add edptx and dptx nodes for MT8195.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 82d28e9f60c3..83567d90ede6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1241,6 +1241,9 @@
reg = <0x189 0x2>;
bits = <7 5>;
};
+ dp_calibration: dp-data@1ac {
+ reg = <0x1ac 0x10>;
+ };
};
u3phy2: t-phy@11c40000 {
@@ -2178,5 +2181,27 @@
clock-names = "engine", "pixel", "pll";
status = "disabled";
};
+
+ edp_tx: edp-tx@1c500000 {
+ compatible = "mediatek,mt8195-edp-tx";
+ reg = <0 0x1c500000 0 0x8000>;
+ nvmem-cells = <&dp_calibration>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
+ interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
+ max-linkrate-mhz = <8100>;
+ status = "disabled";
+ };
+
+ dp_tx: dp-tx@1c600000 {
+ compatible = "mediatek,mt8195-dp-tx";
+ reg = <0 0x1c600000 0 0x8000>;
+ nvmem-cells = <&dp_calibration>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
+ interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
+ max-linkrate-mhz = <8100>;
+ status = "disabled";
+ };
};
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 3/4] arm64: dts: mediatek: cherry: Add dp-intf ports
2022-09-16 2:50 ` Bo-Chen Chen
@ 2022-09-16 2:50 ` Bo-Chen Chen
-1 siblings, 0 replies; 10+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 2:50 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, matthias.bgg
Cc: angelogioacchino.delregno, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
Dp-intfs provide the pixel data to edptx and dptx. To support edptx
and dptx, we need to add dp-intf0 and dp-intf1 ports.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 9b62e161db26..303dc32c64dc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -120,6 +120,24 @@
};
};
+&dp_intf0 {
+ status = "okay";
+
+ port {
+ dp_intf0_out: endpoint {
+ };
+ };
+};
+
+&dp_intf1 {
+ status = "okay";
+
+ port {
+ dp_intf1_out: endpoint {
+ };
+ };
+};
+
&i2c0 {
status = "okay";
--
2.18.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v3 3/4] arm64: dts: mediatek: cherry: Add dp-intf ports
@ 2022-09-16 2:50 ` Bo-Chen Chen
0 siblings, 0 replies; 10+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 2:50 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, matthias.bgg
Cc: angelogioacchino.delregno, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
Dp-intfs provide the pixel data to edptx and dptx. To support edptx
and dptx, we need to add dp-intf0 and dp-intf1 ports.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 9b62e161db26..303dc32c64dc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -120,6 +120,24 @@
};
};
+&dp_intf0 {
+ status = "okay";
+
+ port {
+ dp_intf0_out: endpoint {
+ };
+ };
+};
+
+&dp_intf1 {
+ status = "okay";
+
+ port {
+ dp_intf1_out: endpoint {
+ };
+ };
+};
+
&i2c0 {
status = "okay";
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support
2022-09-16 2:50 ` Bo-Chen Chen
@ 2022-09-16 2:50 ` Bo-Chen Chen
-1 siblings, 0 replies; 10+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 2:50 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, matthias.bgg
Cc: angelogioacchino.delregno, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
In cherry projects, we use edptx as the internal display interface
and use dptx as the external display interface. To support this, we
need to add more properties.
- Add pinctrls for edptx and dptx.
- Add ports for edptx and dptx.
The port connections for the internal and external display:
dp-intf0 -> edptx -> panel
dp-intf1 -> dptx
The edptx endpoint is kept empty for now, as the panel addition will
come in a later commit.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../boot/dts/mediatek/mt8195-cherry.dtsi | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 303dc32c64dc..560103e29017 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -125,6 +125,7 @@
port {
dp_intf0_out: endpoint {
+ remote-endpoint = <&edp_in>;
};
};
};
@@ -134,6 +135,59 @@
port {
dp_intf1_out: endpoint {
+ remote-endpoint = <&dptx_in>;
+ };
+ };
+};
+
+&edp_tx {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edptx_pins_default>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ edp_in: endpoint {
+ remote-endpoint = <&dp_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ edp_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
+&dp_tx {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&dptx_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dptx_in: endpoint {
+ remote-endpoint = <&dp_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dptx_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ };
};
};
};
@@ -497,6 +551,20 @@
};
};
+ edptx_pins_default: edptx-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>;
+ bias-pull-up;
+ };
+ };
+
+ dptx_pin: dptx-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>;
+ bias-pull-up;
+ };
+ };
+
i2c0_pins: i2c0-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
--
2.18.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v3 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support
@ 2022-09-16 2:50 ` Bo-Chen Chen
0 siblings, 0 replies; 10+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 2:50 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, matthias.bgg
Cc: angelogioacchino.delregno, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
In cherry projects, we use edptx as the internal display interface
and use dptx as the external display interface. To support this, we
need to add more properties.
- Add pinctrls for edptx and dptx.
- Add ports for edptx and dptx.
The port connections for the internal and external display:
dp-intf0 -> edptx -> panel
dp-intf1 -> dptx
The edptx endpoint is kept empty for now, as the panel addition will
come in a later commit.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../boot/dts/mediatek/mt8195-cherry.dtsi | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 303dc32c64dc..560103e29017 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -125,6 +125,7 @@
port {
dp_intf0_out: endpoint {
+ remote-endpoint = <&edp_in>;
};
};
};
@@ -134,6 +135,59 @@
port {
dp_intf1_out: endpoint {
+ remote-endpoint = <&dptx_in>;
+ };
+ };
+};
+
+&edp_tx {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edptx_pins_default>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ edp_in: endpoint {
+ remote-endpoint = <&dp_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ edp_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
+&dp_tx {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&dptx_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dptx_in: endpoint {
+ remote-endpoint = <&dp_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dptx_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ };
};
};
};
@@ -497,6 +551,20 @@
};
};
+ edptx_pins_default: edptx-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>;
+ bias-pull-up;
+ };
+ };
+
+ dptx_pin: dptx-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>;
+ bias-pull-up;
+ };
+ };
+
i2c0_pins: i2c0-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
--
2.18.0
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