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* [PATCH] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30
@ 2022-09-16  9:17 ` Quentin Schulz
  0 siblings, 0 replies; 6+ messages in thread
From: Quentin Schulz @ 2022-09-16  9:17 UTC (permalink / raw)
  Cc: robh+dt, krzysztof.kozlowski+dt, heiko, linus.walleij, david,
	jbx6244, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel, foss+kernel, Quentin Schulz

From: Quentin Schulz <quentin.schulz@theobroma-systems.com>

The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are
2-channel I2S/PCM controllers handled by the same controller driver, and
i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller
driver.

This adds the device tree node required to enable I2S0 on PX30.

This was tested in a 2-channel I2S with TX BCLK/LRCK for both TX and RX
(rockchip,trcm-sync-tx-only) setup on a soon-to-be-released board.

Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
---
 arch/arm64/boot/dts/rockchip/px30.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 214f94fea3dc..bfa3580429d1 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -365,6 +365,28 @@ uart0: serial@ff030000 {
 		status = "disabled";
 	};
 
+	i2s0_8ch: i2s@ff060000 {
+		compatible = "rockchip,px30-i2s-tdm";
+		reg = <0x0 0xff060000 0x0 0x1000>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		dmas = <&dmac 16>, <&dmac 17>;
+		dma-names = "tx", "rx";
+		rockchip,grf = <&grf>;
+		resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
+		reset-names = "tx-m", "rx-m";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
+			     &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
+			     &i2s0_8ch_sdo0 &i2s0_8ch_sdi0
+			     &i2s0_8ch_sdo1 &i2s0_8ch_sdi1
+			     &i2s0_8ch_sdo2 &i2s0_8ch_sdi2
+			     &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
 	i2s1_2ch: i2s@ff070000 {
 		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 		reg = <0x0 0xff070000 0x0 0x1000>;
-- 
2.37.3


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30
@ 2022-09-16  9:17 ` Quentin Schulz
  0 siblings, 0 replies; 6+ messages in thread
From: Quentin Schulz @ 2022-09-16  9:17 UTC (permalink / raw)
  Cc: robh+dt, krzysztof.kozlowski+dt, heiko, linus.walleij, david,
	jbx6244, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel, foss+kernel, Quentin Schulz

From: Quentin Schulz <quentin.schulz@theobroma-systems.com>

The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are
2-channel I2S/PCM controllers handled by the same controller driver, and
i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller
driver.

This adds the device tree node required to enable I2S0 on PX30.

This was tested in a 2-channel I2S with TX BCLK/LRCK for both TX and RX
(rockchip,trcm-sync-tx-only) setup on a soon-to-be-released board.

Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
---
 arch/arm64/boot/dts/rockchip/px30.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 214f94fea3dc..bfa3580429d1 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -365,6 +365,28 @@ uart0: serial@ff030000 {
 		status = "disabled";
 	};
 
+	i2s0_8ch: i2s@ff060000 {
+		compatible = "rockchip,px30-i2s-tdm";
+		reg = <0x0 0xff060000 0x0 0x1000>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		dmas = <&dmac 16>, <&dmac 17>;
+		dma-names = "tx", "rx";
+		rockchip,grf = <&grf>;
+		resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
+		reset-names = "tx-m", "rx-m";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
+			     &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
+			     &i2s0_8ch_sdo0 &i2s0_8ch_sdi0
+			     &i2s0_8ch_sdo1 &i2s0_8ch_sdi1
+			     &i2s0_8ch_sdo2 &i2s0_8ch_sdi2
+			     &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
 	i2s1_2ch: i2s@ff070000 {
 		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 		reg = <0x0 0xff070000 0x0 0x1000>;
-- 
2.37.3


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30
@ 2022-09-16  9:17 ` Quentin Schulz
  0 siblings, 0 replies; 6+ messages in thread
From: Quentin Schulz @ 2022-09-16  9:17 UTC (permalink / raw)
  Cc: robh+dt, krzysztof.kozlowski+dt, heiko, linus.walleij, david,
	jbx6244, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel, foss+kernel, Quentin Schulz

From: Quentin Schulz <quentin.schulz@theobroma-systems.com>

The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are
2-channel I2S/PCM controllers handled by the same controller driver, and
i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller
driver.

This adds the device tree node required to enable I2S0 on PX30.

This was tested in a 2-channel I2S with TX BCLK/LRCK for both TX and RX
(rockchip,trcm-sync-tx-only) setup on a soon-to-be-released board.

Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
---
 arch/arm64/boot/dts/rockchip/px30.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 214f94fea3dc..bfa3580429d1 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -365,6 +365,28 @@ uart0: serial@ff030000 {
 		status = "disabled";
 	};
 
+	i2s0_8ch: i2s@ff060000 {
+		compatible = "rockchip,px30-i2s-tdm";
+		reg = <0x0 0xff060000 0x0 0x1000>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		dmas = <&dmac 16>, <&dmac 17>;
+		dma-names = "tx", "rx";
+		rockchip,grf = <&grf>;
+		resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
+		reset-names = "tx-m", "rx-m";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
+			     &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
+			     &i2s0_8ch_sdo0 &i2s0_8ch_sdi0
+			     &i2s0_8ch_sdo1 &i2s0_8ch_sdi1
+			     &i2s0_8ch_sdo2 &i2s0_8ch_sdi2
+			     &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
 	i2s1_2ch: i2s@ff070000 {
 		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 		reg = <0x0 0xff070000 0x0 0x1000>;
-- 
2.37.3


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30
  2022-09-16  9:17 ` Quentin Schulz
  (?)
@ 2022-09-16 10:58   ` Heiko Stuebner
  -1 siblings, 0 replies; 6+ messages in thread
From: Heiko Stuebner @ 2022-09-16 10:58 UTC (permalink / raw)
  To: Quentin Schulz
  Cc: Heiko Stuebner, jbx6244, linus.walleij, krzysztof.kozlowski+dt,
	linux-kernel, robh+dt, linux-rockchip, Quentin Schulz,
	devicetree, david, linux-arm-kernel

On Fri, 16 Sep 2022 11:17:46 +0200, Quentin Schulz wrote:
> The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are
> 2-channel I2S/PCM controllers handled by the same controller driver, and
> i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller
> driver.
> 
> This adds the device tree node required to enable I2S0 on PX30.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30
      commit: 27c92c60d1e6d37e2c34fc18e1e36186fade2186

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30
@ 2022-09-16 10:58   ` Heiko Stuebner
  0 siblings, 0 replies; 6+ messages in thread
From: Heiko Stuebner @ 2022-09-16 10:58 UTC (permalink / raw)
  To: Quentin Schulz
  Cc: Heiko Stuebner, jbx6244, linus.walleij, krzysztof.kozlowski+dt,
	linux-kernel, robh+dt, linux-rockchip, Quentin Schulz,
	devicetree, david, linux-arm-kernel

On Fri, 16 Sep 2022 11:17:46 +0200, Quentin Schulz wrote:
> The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are
> 2-channel I2S/PCM controllers handled by the same controller driver, and
> i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller
> driver.
> 
> This adds the device tree node required to enable I2S0 on PX30.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30
      commit: 27c92c60d1e6d37e2c34fc18e1e36186fade2186

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30
@ 2022-09-16 10:58   ` Heiko Stuebner
  0 siblings, 0 replies; 6+ messages in thread
From: Heiko Stuebner @ 2022-09-16 10:58 UTC (permalink / raw)
  To: Quentin Schulz
  Cc: Heiko Stuebner, jbx6244, linus.walleij, krzysztof.kozlowski+dt,
	linux-kernel, robh+dt, linux-rockchip, Quentin Schulz,
	devicetree, david, linux-arm-kernel

On Fri, 16 Sep 2022 11:17:46 +0200, Quentin Schulz wrote:
> The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are
> 2-channel I2S/PCM controllers handled by the same controller driver, and
> i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller
> driver.
> 
> This adds the device tree node required to enable I2S0 on PX30.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30
      commit: 27c92c60d1e6d37e2c34fc18e1e36186fade2186

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-09-16 11:06 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-16  9:17 [PATCH] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30 Quentin Schulz
2022-09-16  9:17 ` Quentin Schulz
2022-09-16  9:17 ` Quentin Schulz
2022-09-16 10:58 ` Heiko Stuebner
2022-09-16 10:58   ` Heiko Stuebner
2022-09-16 10:58   ` Heiko Stuebner

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