* [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa
@ 2022-09-18 12:17 Jit Loon Lim
2022-09-18 12:17 ` [PATCH 2/9] drivers: clk: dm: Add memory " Jit Loon Lim
` (8 more replies)
0 siblings, 9 replies; 10+ messages in thread
From: Jit Loon Lim @ 2022-09-18 12:17 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Add clock manager driver for Diamond Mesa. Provides clock
initialization and get_rate functions.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
drivers/clk/altera/clk-dm.c | 504 +++++++++++++++++++++++++++
drivers/clk/altera/clk-dm.h | 217 ++++++++++++
include/dt-bindings/clock/dm-clock.h | 71 ++++
3 files changed, 792 insertions(+)
create mode 100644 drivers/clk/altera/clk-dm.c
create mode 100644 drivers/clk/altera/clk-dm.h
create mode 100644 include/dt-bindings/clock/dm-clock.h
diff --git a/drivers/clk/altera/clk-dm.c b/drivers/clk/altera/clk-dm.c
new file mode 100644
index 0000000000..1076240b41
--- /dev/null
+++ b/drivers/clk/altera/clk-dm.c
@@ -0,0 +1,504 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/util.h>
+#include <dt-bindings/clock/dm-clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_plat {
+ void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+#ifndef CONFIG_TARGET_SOCFPGA_DM
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+ cm_wait_for_fsm();
+}
+#endif
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+#ifndef CONFIG_TARGET_SOCFPGA_DM
+#ifdef CONFIG_SPL_BUILD
+ /* Always force clock manager into boot mode before any configuration */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
+#else
+ /* Skip clock configuration in SSBL if it's not in boot mode */
+ if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
+ return;
+#endif
+#endif
+
+ /* Put both PLLs in bypass */
+ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+ clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* Put both PLLs in Reset */
+ CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+#ifndef CONFIG_TARGET_SOCFPGA_DM
+ /* setup main PLL */
+ CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
+
+ /* setup peripheral */
+ CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
+ CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
+#endif
+
+ /* Take both PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+#ifndef CONFIG_TARGET_SOCFPGA_DM
+ CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
+ CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
+ CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR);
+ CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR);
+ CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR);
+#endif
+
+ /* Configure ping pong counters in altera group */
+ CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
+ CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
+
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |
+ CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ CLKMGR_MAINPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |
+ CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ CLKMGR_PERPLL_PLLGLOB);
+
+ /* Take all PLLs out of bypass */
+ clk_write_bypass_mainpll(plat, 0);
+ clk_write_bypass_perpll(plat, 0);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
+ CLKMGR_INTER_PERPLLLOST_MASK |
+ CLKMGR_INTER_MAINPLLLOST_MASK);
+
+ /* Take all ping pong counters out of reset */
+ CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
+ CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK);
+
+#ifndef CONFIG_TARGET_SOCFPGA_DM
+ /* Out of boot mode */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
+#endif
+}
+
+static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u32 reg)
+{
+ u32 clksrc = CM_REG_READL(plat, reg);
+
+ return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
+}
+
+static u64 clk_get_pll_output_hz(struct socfpga_clk_plat *plat,
+ u32 pllglob_reg, u32 plldiv_reg)
+{
+ u64 clock = 0;
+ u32 clklsrc, divf, divr, divq, power = 1;
+
+ /* Get input clock frequency */
+ clklsrc = (CM_REG_READL(plat, pllglob_reg) &
+ CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
+ CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
+
+ switch (clklsrc) {
+ case CLKMGR_VCO_PSRC_EOSC1:
+ clock = cm_get_osc_clk_hz();
+ break;
+ case CLKMGR_VCO_PSRC_INTOSC:
+ clock = cm_get_intosc_clk_hz();
+ break;
+ case CLKMGR_VCO_PSRC_F2S:
+ clock = cm_get_fpga_clk_hz();
+ break;
+ }
+
+ /* Calculate pll out clock frequency */
+ divf = (CM_REG_READL(plat, plldiv_reg) &
+ CLKMGR_PLLDIV_FDIV_MASK) >>
+ CLKMGR_PLLDIV_FDIV_OFFSET;
+
+ divr = (CM_REG_READL(plat, plldiv_reg) &
+ CLKMGR_PLLDIV_REFCLKDIV_MASK) >>
+ CLKMGR_PLLDIV_REFCLKDIV_OFFSET;
+
+ divq = (CM_REG_READL(plat, plldiv_reg) &
+ CLKMGR_PLLDIV_OUTDIV_QDIV_MASK) >>
+ CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET;
+
+ while (divq) {
+ power *= 2;
+ divq--;
+ }
+
+ return ((clock * 2 * (divf + 1)) / ((divr + 1) * power));
+}
+
+static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg,
+ u32 main_div, u32 per_div)
+{
+ u64 clock = 0;
+ u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
+
+ switch (clklsrc) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = clk_get_pll_output_hz(plat,
+ CLKMGR_MAINPLL_PLLGLOB,
+ CLKMGR_MAINPLL_PLLDIV);
+ clock /= 1 + main_div;
+ break;
+
+ case CLKMGR_CLKSRC_PER:
+ clock = clk_get_pll_output_hz(plat,
+ CLKMGR_PERPLL_PLLGLOB,
+ CLKMGR_PERPLL_PLLDIV);
+ clock /= 1 + per_div;
+ break;
+
+ case CLKMGR_CLKSRC_OSC1:
+ clock = cm_get_osc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_INTOSC:
+ clock = cm_get_intosc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_FPGA:
+ clock = cm_get_fpga_clk_hz();
+ break;
+ default:
+ return 0;
+ }
+
+ return clock;
+}
+
+static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u32 mainpll_c0cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
+ CLKMGR_PLLOUTDIV_C0CNT_MASK) >>
+ CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
+
+ u32 perpll_c0cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
+ CLKMGR_PLLOUTDIV_C0CNT_MASK) >>
+ CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
+
+ u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
+ mainpll_c0cnt, perpll_c0cnt);
+
+ clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
+ CLKMGR_CLKCNT_MSK);
+
+ return clock;
+}
+
+static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u32 mainpll_c1cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
+ CLKMGR_PLLOUTDIV_C1CNT_MASK) >>
+ CLKMGR_PLLOUTDIV_C1CNT_OFFSET;
+
+ u32 perpll_c1cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
+ CLKMGR_PLLOUTDIV_C1CNT_MASK) >>
+ CLKMGR_PLLOUTDIV_C1CNT_OFFSET;
+
+ return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
+ mainpll_c1cnt, perpll_c1cnt);
+}
+
+static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u64 clock = clk_get_l3_main_clk_hz(plat);
+
+ clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+ CLKMGR_NOCDIV_L4MAIN_OFFSET) &
+ CLKMGR_NOCDIV_DIVIDER_MASK);
+
+ return clock;
+}
+
+static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u32 mainpll_c3cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
+ CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
+ CLKMGR_PLLOUTDIV_C3CNT_OFFSET;
+
+ u32 perpll_c3cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
+ CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
+ CLKMGR_PLLOUTDIV_C3CNT_OFFSET;
+
+ u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
+ mainpll_c3cnt, perpll_c3cnt);
+
+ clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) &
+ CLKMGR_CLKCNT_MSK);
+
+ return clock / 4;
+}
+
+#ifndef CONFIG_TARGET_SOCFPGA_DM
+static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u64 clock = clk_get_l3_main_clk_hz(plat);
+
+ clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+ CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
+ CLKMGR_NOCDIV_DIVIDER_MASK);
+
+ return clock;
+}
+#endif
+
+static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u64 clock = clk_get_l3_main_clk_hz(plat);
+
+ clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+ CLKMGR_NOCDIV_L4MPCLK_OFFSET) &
+ CLKMGR_NOCDIV_DIVIDER_MASK);
+
+ return clock;
+}
+
+static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
+{
+ if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
+ return clk_get_l3_main_clk_hz(plat) / 2;
+
+ return clk_get_l3_main_clk_hz(plat) / 4;
+}
+
+static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
+{
+ bool emacsel_a;
+ u32 ctl;
+ u32 ctr_reg;
+ u32 clock;
+ u32 div;
+ u32 reg;
+
+ /* Get EMAC clock source */
+ ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
+ if (emac_id == DM_EMAC0_CLK)
+ ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
+ CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
+ else if (emac_id == DM_EMAC1_CLK)
+ ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
+ CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
+ else if (emac_id == DM_EMAC2_CLK)
+ ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
+ CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
+ else
+ return 0;
+
+ if (ctl) {
+ /* EMAC B source */
+ emacsel_a = false;
+ ctr_reg = CLKMGR_ALTR_EMACBCTR;
+ } else {
+ /* EMAC A source */
+ emacsel_a = true;
+ ctr_reg = CLKMGR_ALTR_EMACACTR;
+ }
+
+ reg = CM_REG_READL(plat, ctr_reg);
+ clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK)
+ >> CLKMGR_ALT_EMACCTR_SRC_OFFSET;
+ div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK)
+ >> CLKMGR_ALT_EMACCTR_CNT_OFFSET;
+
+ switch (clock) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = clk_get_pll_output_hz(plat,
+ CLKMGR_MAINPLL_PLLGLOB,
+ CLKMGR_MAINPLL_PLLDIV);
+
+ if (emacsel_a) {
+ clock /= 1 + ((CM_REG_READL(plat,
+ CLKMGR_MAINPLL_PLLOUTDIV) &
+ CLKMGR_PLLOUTDIV_C2CNT_MASK) >>
+ CLKMGR_PLLOUTDIV_C2CNT_OFFSET);
+ } else {
+ clock /= 1 + ((CM_REG_READL(plat,
+ CLKMGR_MAINPLL_PLLOUTDIV) &
+ CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
+ CLKMGR_PLLOUTDIV_C3CNT_OFFSET);
+ }
+ break;
+
+ case CLKMGR_CLKSRC_PER:
+ clock = clk_get_pll_output_hz(plat,
+ CLKMGR_PERPLL_PLLGLOB,
+ CLKMGR_PERPLL_PLLDIV);
+ if (emacsel_a) {
+ clock /= 1 + ((CM_REG_READL(plat,
+ CLKMGR_PERPLL_PLLOUTDIV) &
+ CLKMGR_PLLOUTDIV_C2CNT_MASK) >>
+ CLKMGR_PLLOUTDIV_C2CNT_OFFSET);
+ } else {
+ clock /= 1 + ((CM_REG_READL(plat,
+ CLKMGR_PERPLL_PLLOUTDIV) &
+ CLKMGR_PLLOUTDIV_C3CNT_MASK >>
+ CLKMGR_PLLOUTDIV_C3CNT_OFFSET));
+ }
+ break;
+
+ case CLKMGR_CLKSRC_OSC1:
+ clock = cm_get_osc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_INTOSC:
+ clock = cm_get_intosc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_FPGA:
+ clock = cm_get_fpga_clk_hz();
+ break;
+ }
+
+ clock /= 1 + div;
+
+ return clock;
+}
+
+static ulong socfpga_clk_get_rate(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+
+ switch (clk->id) {
+ case DM_MPU_CLK:
+ return clk_get_mpu_clk_hz(plat);
+ case DM_L4_MAIN_CLK:
+ return clk_get_l4_main_clk_hz(plat);
+ case DM_L4_SYS_FREE_CLK:
+ return clk_get_l4_sys_free_clk_hz(plat);
+ case DM_L4_MP_CLK:
+ return clk_get_l4_mp_clk_hz(plat);
+ case DM_L4_SP_CLK:
+#ifndef CONFIG_TARGET_SOCFPGA_DM
+ return clk_get_l4_sp_clk_hz(plat);
+#else
+ return 76800;
+#endif
+ case DM_SDMMC_CLK:
+ return clk_get_sdmmc_clk_hz(plat);
+ case DM_EMAC0_CLK:
+ case DM_EMAC1_CLK:
+ case DM_EMAC2_CLK:
+ return clk_get_emac_clk_hz(plat, clk->id);
+ case DM_USB_CLK:
+ case DM_NAND_X_CLK:
+ return clk_get_l4_mp_clk_hz(plat);
+ case DM_NAND_CLK:
+ return clk_get_l4_mp_clk_hz(plat) / 4;
+ default:
+ return -ENXIO;
+ }
+}
+
+static int socfpga_clk_enable(struct clk *clk)
+{
+ return 0;
+}
+
+static int socfpga_clk_probe(struct udevice *dev)
+{
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+
+ clk_basic_init(dev, cm_default_cfg);
+
+ return 0;
+}
+
+static int socfpga_clk_of_to_plat(struct udevice *dev)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->regs = (void __iomem *)addr;
+
+ return 0;
+}
+
+static struct clk_ops socfpga_clk_ops = {
+ .enable = socfpga_clk_enable,
+ .get_rate = socfpga_clk_get_rate,
+};
+
+static const struct udevice_id socfpga_clk_match[] = {
+ { .compatible = "intel,dm-clkmgr" },
+ {}
+};
+
+U_BOOT_DRIVER(socfpga_dm_clk) = {
+ .name = "clk-dm",
+ .id = UCLASS_CLK,
+ .of_match = socfpga_clk_match,
+ .ops = &socfpga_clk_ops,
+ .probe = socfpga_clk_probe,
+ .of_to_plat = socfpga_clk_of_to_plat,
+ .plat_auto = sizeof(struct socfpga_clk_plat),
+};
diff --git a/drivers/clk/altera/clk-dm.h b/drivers/clk/altera/clk-dm.h
new file mode 100644
index 0000000000..89d3a92a34
--- /dev/null
+++ b/drivers/clk/altera/clk-dm.h
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLK_DM_
+#define _CLK_DM_
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#define CM_REG_READL(plat, reg) \
+ readl((plat)->regs + (reg))
+
+#define CM_REG_WRITEL(plat, data, reg) \
+ writel(data, (plat)->regs + (reg))
+
+#define CM_REG_CLRBITS(plat, reg, clear) \
+ clrbits_le32((plat)->regs + (reg), (clear))
+
+#define CM_REG_SETBITS(plat, reg, set) \
+ setbits_le32((plat)->regs + (reg), (set))
+
+struct cm_config {
+ /* main group */
+ u32 main_pll_mpuclk;
+ u32 main_pll_nocclk;
+ u32 main_pll_nocdiv;
+ u32 main_pll_pllglob;
+ u32 main_pll_plldiv;
+ u32 main_pll_plloutdiv;
+ u32 spare_1[4];
+
+ /* peripheral group */
+ u32 per_pll_emacctl;
+ u32 per_pll_gpiodiv;
+ u32 per_pll_pllglob;
+ u32 per_pll_plldiv;
+ u32 per_pll_plloutdiv;
+ u32 spare_2[4];
+
+ /* altera group */
+ u32 alt_emacactr;
+ u32 alt_emacbctr;
+ u32 alt_emacptpctr;
+ u32 alt_gpiodbctr;
+ u32 alt_sdmmcctr;
+ u32 alt_s2fuser0ctr;
+ u32 alt_s2fuser1ctr;
+ u32 alt_psirefctr;
+
+ /* incoming clock */
+ u32 hps_osc_clk_hz;
+ u32 fpga_clk_hz;
+ u32 spare_3[3];
+
+ /* memory clock group */
+ u32 mem_memdiv;
+ u32 mem_pllglob;
+ u32 mem_plldiv;
+ u32 mem_plloutdiv;
+ u32 spare_4[4];
+};
+
+/* Clock Manager registers */
+#define CLKMGR_CTRL 0
+#define CLKMGR_STAT 4
+#define CLKMGR_TESTIOCTRL 8
+#define CLKMGR_INTRGEN 0x0c
+#define CLKMGR_INTRMSK 0x10
+#define CLKMGR_INTRCLR 0x14
+#define CLKMGR_INTRSTS 0x18
+#define CLKMGR_INTRSTK 0x1c
+#define CLKMGR_INTRRAW 0x20
+
+/* Clock Manager Main PPL group registers */
+#define CLKMGR_MAINPLL_EN 0x24
+#define CLKMGR_MAINPLL_ENS 0x28
+#define CLKMGR_MAINPLL_ENR 0x2c
+#define CLKMGR_MAINPLL_BYPASS 0x30
+#define CLKMGR_MAINPLL_BYPASSS 0x34
+#define CLKMGR_MAINPLL_BYPASSR 0x38
+#define CLKMGR_MAINPLL_MPUCLK 0x3c
+#define CLKMGR_MAINPLL_NOCCLK 0x40
+#define CLKMGR_MAINPLL_NOCDIV 0x44
+#define CLKMGR_MAINPLL_PLLGLOB 0x48
+#define CLKMGR_MAINPLL_PLLCTRL 0x4c
+#define CLKMGR_MAINPLL_PLLDIV 0x50
+#define CLKMGR_MAINPLL_PLLOUTDIV 0x54
+#define CLKMGR_MAINPLL_LOSTLOCK 0x58
+
+/* Clock Manager Peripheral PPL group registers */
+#define CLKMGR_PERPLL_EN 0x7c
+#define CLKMGR_PERPLL_ENS 0x80
+#define CLKMGR_PERPLL_ENR 0x84
+#define CLKMGR_PERPLL_BYPASS 0x88
+#define CLKMGR_PERPLL_BYPASSS 0x8c
+#define CLKMGR_PERPLL_BYPASSR 0x90
+#define CLKMGR_PERPLL_EMACCTL 0x94
+#define CLKMGR_PERPLL_GPIODIV 0x98
+#define CLKMGR_PERPLL_PLLGLOB 0x9c
+#define CLKMGR_PERPLL_PLLCTRL 0xa0
+#define CLKMGR_PERPLL_PLLDIV 0xa4
+#define CLKMGR_PERPLL_PLLOUTDIV 0xa8
+#define CLKMGR_PERPLL_LOSTLOCK 0xac
+
+/* Clock Manager Altera group registers */
+#define CLKMGR_ALTR_EMACACTR 0xd4
+#define CLKMGR_ALTR_EMACBCTR 0xd8
+#define CLKMGR_ALTR_EMACPTPCTR 0xdc
+#define CLKMGR_ALTR_GPIODBCTR 0xe0
+#define CLKMGR_ALTR_SDMMCCTR 0xe4
+#define CLKMGR_ALTR_S2FUSER0CTR 0xe8
+#define CLKMGR_ALTR_S2FUSER1CTR 0xec
+#define CLKMGR_ALTR_PSIREFCTR 0xf0
+#define CLKMGR_ALTR_EXTCNTRST 0xf4
+
+#define CLKMGR_CTRL_BOOTMODE BIT(0)
+
+#define CLKMGR_STAT_BUSY BIT(0)
+#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
+#define CLKMGR_STAT_MAIN_TRANS BIT(9)
+#define CLKMGR_STAT_PERPLL_LOCKED BIT(16)
+#define CLKMGR_STAT_PERF_TRANS BIT(17)
+#define CLKMGR_STAT_BOOTMODE BIT(24)
+#define CLKMGR_STAT_BOOTCLKSRC BIT(25)
+
+#define CLKMGR_STAT_ALLPLL_LOCKED_MASK \
+ (CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED)
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
+#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
+#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
+
+#define CLKMGR_CLKSRC_MASK GENMASK(18, 16)
+#define CLKMGR_CLKSRC_OFFSET 16
+#define CLKMGR_CLKSRC_MAIN 0
+#define CLKMGR_CLKSRC_PER 1
+#define CLKMGR_CLKSRC_OSC1 2
+#define CLKMGR_CLKSRC_INTOSC 3
+#define CLKMGR_CLKSRC_FPGA 4
+#define CLKMGR_CLKCNT_MSK GENMASK(10, 0)
+
+#define CLKMGR_BYPASS_MAINPLL_ALL 0x7
+#define CLKMGR_BYPASS_PERPLL_ALL 0x7f
+
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
+#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
+#define CLKMGR_NOCDIV_DIVIDER_MASK 0x3
+
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16)
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
+#define CLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASK BIT(28)
+#define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29)
+
+#define CLKMGR_VCO_PSRC_EOSC1 0
+#define CLKMGR_VCO_PSRC_INTOSC 1
+#define CLKMGR_VCO_PSRC_F2S 2
+
+#define CLKMGR_PLLCTRL_BYPASS_MASK BIT(0)
+#define CLKMGR_PLLCTRL_RST_N_MASK BIT(1)
+
+#define CLKMGR_PLLDIV_REFCLKDIV_MASK GENMASK(5, 0)
+#define CLKMGR_PLLDIV_FDIV_MASK GENMASK(16, 8)
+#define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24)
+#define CLKMGR_PLLDIV_RANGE_MASK GENMASK(30, 28)
+
+#define CLKMGR_PLLDIV_REFCLKDIV_OFFSET 0
+#define CLKMGR_PLLDIV_FDIV_OFFSET 8
+#define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24
+#define CLKMGR_PLLDIV_RANGE_OFFSET 28
+
+#define CLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0)
+#define CLKMGR_PLLOUTDIV_C1CNT_MASK GENMASK(12, 8)
+#define CLKMGR_PLLOUTDIV_C2CNT_MASK GENMASK(20, 16)
+#define CLKMGR_PLLOUTDIV_C3CNT_MASK GENMASK(28, 24)
+
+#define CLKMGR_PLLOUTDIV_C0CNT_OFFSET 0
+#define CLKMGR_PLLOUTDIV_C1CNT_OFFSET 8
+#define CLKMGR_PLLOUTDIV_C2CNT_OFFSET 16
+#define CLKMGR_PLLOUTDIV_C3CNT_OFFSET 24
+
+#define CLKMGR_PLLCX_EN_SET_MSK BIT(27)
+#define CLKMGR_PLLCX_MUTE_SET_MSK BIT(28)
+
+#define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16)
+#define CLKMGR_VCOCALIB_MSCNT_OFFSET 16
+#define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0)
+#define CLKMGR_VCOCALIB_MSCNT_CONST 100
+#define CLKMGR_VCOCALIB_HSCNT_CONST 4
+
+#define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0)
+
+#define CLKMGR_LOSTLOCK_SET_MASK BIT(0)
+
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK BIT(27)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET 28
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK BIT(28)
+
+#define CLKMGR_ALT_EMACCTR_SRC_OFFSET 16
+#define CLKMGR_ALT_EMACCTR_SRC_MASK GENMASK(18, 16)
+#define CLKMGR_ALT_EMACCTR_CNT_OFFSET 0
+#define CLKMGR_ALT_EMACCTR_CNT_MASK GENMASK(10, 0)
+
+#define CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK GENMASK(15, 0)
+
+#endif /* _CLK_DM_ */
diff --git a/include/dt-bindings/clock/dm-clock.h b/include/dt-bindings/clock/dm-clock.h
new file mode 100644
index 0000000000..d624ac723c
--- /dev/null
+++ b/include/dt-bindings/clock/dm-clock.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020, Intel Corporation
+ */
+
+#ifndef __DM_CLOCK_H
+#define __DM_CLOCK_H
+
+/* fixed rate clocks */
+#define DM_OSC1 0
+#define DM_CB_INTOSC_HS_DIV2_CLK 1
+#define DM_CB_INTOSC_LS_CLK 2
+#define DM_L4_SYS_FREE_CLK 3
+#define DM_F2S_FREE_CLK 4
+
+/* PLL clocks */
+#define DM_MAIN_PLL_CLK 5
+#define DM_MAIN_PLL_C0_CLK 6
+#define DM_MAIN_PLL_C1_CLK 7
+#define DM_MAIN_PLL_C2_CLK 8
+#define DM_MAIN_PLL_C3_CLK 9
+#define DM_PERIPH_PLL_CLK 10
+#define DM_PERIPH_PLL_C0_CLK 11
+#define DM_PERIPH_PLL_C1_CLK 12
+#define DM_PERIPH_PLL_C2_CLK 13
+#define DM_PERIPH_PLL_C3_CLK 14
+#define DM_MPU_FREE_CLK 15
+#define DM_MPU_CCU_CLK 16
+#define DM_BOOT_CLK 17
+
+/* fixed factor clocks */
+#define DM_L3_MAIN_FREE_CLK 18
+#define DM_NOC_FREE_CLK 19
+#define DM_S2F_USR0_CLK 20
+#define DM_NOC_CLK 21
+#define DM_EMAC_A_FREE_CLK 22
+#define DM_EMAC_B_FREE_CLK 23
+#define DM_EMAC_PTP_FREE_CLK 24
+#define DM_GPIO_DB_FREE_CLK 25
+#define DM_SDMMC_FREE_CLK 26
+#define DM_S2F_USER0_FREE_CLK 27
+#define DM_S2F_USER1_FREE_CLK 28
+#define DM_PSI_REF_FREE_CLK 29
+
+/* Gate clocks */
+#define DM_MPU_CLK 30
+#define DM_MPU_PERIPH_CLK 31
+#define DM_L4_MAIN_CLK 32
+#define DM_L4_MP_CLK 33
+#define DM_L4_SP_CLK 34
+#define DM_CS_AT_CLK 35
+#define DM_CS_TRACE_CLK 36
+#define DM_CS_PDBG_CLK 37
+#define DM_CS_TIMER_CLK 38
+#define DM_S2F_USER0_CLK 39
+#define DM_EMAC0_CLK 40
+#define DM_EMAC1_CLK 41
+#define DM_EMAC2_CLK 42
+#define DM_EMAC_PTP_CLK 43
+#define DM_GPIO_DB_CLK 44
+#define DM_NAND_CLK 45
+#define DM_PSI_REF_CLK 46
+#define DM_S2F_USER1_CLK 47
+#define DM_SDMMC_CLK 48
+#define DM_SPI_M_CLK 49
+#define DM_USB_CLK 50
+#define DM_NAND_X_CLK 51
+#define DM_NAND_ECC_CLK 52
+#define DM_NUM_CLKS 53
+
+#endif /* __DM_CLOCK_H */
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/9] drivers: clk: dm: Add memory clock driver for Diamond Mesa
2022-09-18 12:17 [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Jit Loon Lim
@ 2022-09-18 12:17 ` Jit Loon Lim
2022-09-18 12:17 ` [PATCH 3/9] arm: socfpga: dm: Add clock manager " Jit Loon Lim
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Jit Loon Lim @ 2022-09-18 12:17 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Add memory clock manager driver for Diamond Mesa. Provides
clock initialization and enable functions.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
drivers/clk/altera/clk-mem-dm.c | 135 ++++++++++++++++++++++++++++++++
drivers/clk/altera/clk-mem-dm.h | 84 ++++++++++++++++++++
2 files changed, 219 insertions(+)
create mode 100644 drivers/clk/altera/clk-mem-dm.c
create mode 100644 drivers/clk/altera/clk-mem-dm.h
diff --git a/drivers/clk/altera/clk-mem-dm.c b/drivers/clk/altera/clk-mem-dm.c
new file mode 100644
index 0000000000..bf70c87226
--- /dev/null
+++ b/drivers/clk/altera/clk-mem-dm.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/io.h>
+#include "clk-mem-dm.h"
+#include <clk-uclass.h>
+#include <dt-bindings/clock/dm-clock.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_mem_clk_plat {
+ void __iomem *regs;
+};
+
+void clk_mem_wait_for_lock(struct socfpga_mem_clk_plat *plat, u32 mask)
+{
+ u32 inter_val;
+ u32 retry = 0;
+
+ do {
+ inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) & mask;
+
+ /* Wait for stable lock */
+ if (inter_val == mask)
+ retry++;
+ else
+ retry = 0;
+
+ if (retry >= 10)
+ return;
+ } while (1);
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_mem_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+ /* Put PLLs in bypass */
+ clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
+
+ /* Put PLLs in Reset */
+ CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup mem PLL */
+ CM_REG_WRITEL(plat, cfg->mem_memdiv, MEMCLKMGR_MEMPLL_MEMDIV);
+ CM_REG_WRITEL(plat, cfg->mem_pllglob, MEMCLKMGR_MEMPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
+
+ /* Take PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+}
+
+static int socfpga_mem_clk_enable(struct clk *clk)
+{
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(clk->dev);
+
+ clk_mem_basic_init(clk->dev, cm_default_cfg);
+
+ clk_mem_wait_for_lock(plat, MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, MEMCLKMGR_MEMPLL_PLLGLOB) |
+ MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ MEMCLKMGR_MEMPLL_PLLGLOB);
+
+ /* Take all PLLs out of bypass */
+ clk_mem_write_bypass_mempll(plat, 0);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
+ MEMCLKMGR_INTER_MEMPLLLOST_MASK);
+
+ /* Take all ping pong counters out of reset */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_EXTCNTRST,
+ MEMCLKMGR_EXTCNTRST_ALLCNTRST);
+
+ return 0;
+}
+
+static int socfpga_mem_clk_of_to_plat(struct udevice *dev)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->regs = (void __iomem *)addr;
+
+ return 0;
+}
+
+static struct clk_ops socfpga_mem_clk_ops = {
+ .enable = socfpga_mem_clk_enable
+};
+
+static const struct udevice_id socfpga_mem_clk_match[] = {
+ { .compatible = "intel,dm-mem-clkmgr" },
+ {}
+};
+
+U_BOOT_DRIVER(socfpga_dm_mem_clk) = {
+ .name = "mem-clk-dm",
+ .id = UCLASS_CLK,
+ .of_match = socfpga_mem_clk_match,
+ .ops = &socfpga_mem_clk_ops,
+ .of_to_plat = socfpga_mem_clk_of_to_plat,
+ .plat_auto = sizeof(struct socfpga_mem_clk_plat),
+};
diff --git a/drivers/clk/altera/clk-mem-dm.h b/drivers/clk/altera/clk-mem-dm.h
new file mode 100644
index 0000000000..0ea195397a
--- /dev/null
+++ b/drivers/clk/altera/clk-mem-dm.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLK_MEM_DM_
+#define _CLK_MEM_DM_
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+/* Clock Manager registers */
+#define MEMCLKMGR_STAT 4
+#define MEMCLKMGR_INTRGEN 8
+#define MEMCLKMGR_INTRMSK 0x0C
+#define MEMCLKMGR_INTRCLR 0x10
+#define MEMCLKMGR_INTRSTS 0x14
+#define MEMCLKMGR_INTRSTK 0x18
+#define MEMCLKMGR_INTRRAW 0x1C
+
+/* Memory Clock Manager PPL group registers */
+#define MEMCLKMGR_MEMPLL_EN 0x20
+#define MEMCLKMGR_MEMPLL_ENS 0x24
+#define MEMCLKMGR_MEMPLL_ENR 0x28
+#define MEMCLKMGR_MEMPLL_BYPASS 0x2c
+#define MEMCLKMGR_MEMPLL_BYPASSS 0x30
+#define MEMCLKMGR_MEMPLL_BYPASSR 0x34
+#define MEMCLKMGR_MEMPLL_MEMDIV 0x38
+#define MEMCLKMGR_MEMPLL_PLLGLOB 0x3c
+#define MEMCLKMGR_MEMPLL_PLLCTRL 0x40
+#define MEMCLKMGR_MEMPLL_PLLDIV 0x44
+#define MEMCLKMGR_MEMPLL_PLLOUTDIV 0x48
+#define MEMCLKMGR_MEMPLL_EXTCNTRST 0x4c
+
+#define MEMCLKMGR_CTRL_BOOTMODE BIT(0)
+
+#define MEMCLKMGR_STAT_MEMPLL_LOCKED BIT(8)
+
+#define MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK \
+ (MEMCLKMGR_STAT_MEMPLL_LOCKED)
+
+#define MEMCLKMGR_INTER_MEMPLLLOCKED_MASK 0x00000001
+#define MEMCLKMGR_INTER_MEMPLLLOST_MASK 0x00000004
+
+#define MEMCLKMGR_BYPASS_MEMPLL_ALL 0x1
+
+#define MEMCLKMGR_MEMDIV_MPFEDIV_OFFSET 0
+#define MEMCLKMGR_MEMDIV_APBDIV_OFFSET 4
+#define MEMCLKMGR_MEMDIV_DFICTRLDIV_OFFSET 8
+#define MEMCLKMGR_MEMDIV_DFIDIV_OFFSET 12
+#define MEMCLKMGR_MEMDIV_DFICTRLDIV_MASK 0x1
+#define MEMCLKMGR_MEMDIV_DIVIDER_MASK 0x3
+
+#define MEMCLKMGR_PLLGLOB_PSRC_MASK GENMASK(17, 16)
+#define MEMCLKMGR_PLLGLOB_PSRC_OFFSET 16
+#define MEMCLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASK BIT(28)
+#define MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29)
+
+#define MEMCLKMGR_PSRC_EOSC1 0
+#define MEMCLKMGR_PSRC_INTOSC 1
+#define MEMCLKMGR_PSRC_F2S 2
+
+#define MEMCLKMGR_PLLCTRL_BYPASS_MASK BIT(0)
+#define MEMCLKMGR_PLLCTRL_RST_N_MASK BIT(1)
+
+#define MEMCLKMGR_PLLDIV_DIVR_MASK GENMASK(5, 0)
+#define MEMCLKMGR_PLLDIV_DIVF_MASK GENMASK(16, 8)
+#define MEMCLKMGR_PLLDIV_DIVQ_MASK GENMASK(26, 24)
+#define MEMCLKMGR_PLLDIV_RANGE_MASK GENMASK(30, 28)
+
+#define MEMCLKMGR_PLLDIV_DIVR_OFFSET 0
+#define MEMCLKMGR_PLLDIV_DIVF_OFFSET 8
+#define MEMCLKMGR_PLLDIV_DIVQ_QDIV_OFFSET 24
+#define MEMCLKMGR_PLLDIV_RANGE_OFFSET 28
+
+#define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0)
+#define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0
+
+#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7)
+#define MEMCLKMGR_EXTCNTRST_ALLCNTRST \
+ (MEMCLKMGR_EXTCNTRST_C0CNTRST)
+
+#endif /* _CLK_MEM_DM_ */
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/9] arm: socfpga: dm: Add clock manager for Diamond Mesa
2022-09-18 12:17 [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Jit Loon Lim
2022-09-18 12:17 ` [PATCH 2/9] drivers: clk: dm: Add memory " Jit Loon Lim
@ 2022-09-18 12:17 ` Jit Loon Lim
2022-09-18 12:17 ` [PATCH 4/9] ddr: altera: dm: Add SDRAM driver " Jit Loon Lim
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Jit Loon Lim @ 2022-09-18 12:17 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Add clock manager driver for Diamond Mesa.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
arch/arm/mach-socfpga/clock_manager_dm.c | 79 +++++++++++++++++++
.../include/mach/clock_manager_dm.h | 14 ++++
2 files changed, 93 insertions(+)
create mode 100644 arch/arm/mach-socfpga/clock_manager_dm.c
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
diff --git a/arch/arm/mach-socfpga/clock_manager_dm.c b/arch/arm/mach-socfpga/clock_manager_dm.c
new file mode 100644
index 0000000000..47a7693845
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_dm.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/dm-clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+ struct udevice *dev;
+ struct clk clk;
+ ulong rate;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(socfpga_dm_clk),
+ &dev);
+ if (ret)
+ return 0;
+
+ clk.id = id;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ return 0;
+
+ rate = clk_get_rate(&clk);
+
+ clk_free(&clk);
+
+ if ((rate == (unsigned long)-ENXIO) ||
+ (rate == (unsigned long)-EIO)) {
+ debug("%s id %u: clk_get_rate err: %ld\n",
+ __func__, id, rate);
+ return 0;
+ }
+
+ return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+ return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ return cm_get_rate_dm(DM_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+ return cm_get_rate_dm(DM_L4_SYS_FREE_CLK);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+ printf("MPU %10d kHz\n",
+ cm_get_rate_dm_khz(DM_MPU_CLK));
+ printf("L4 Main %8d kHz\n",
+ cm_get_rate_dm_khz(DM_L4_MAIN_CLK));
+ printf("L4 sys free %8d kHz\n",
+ cm_get_rate_dm_khz(DM_L4_SYS_FREE_CLK));
+ printf("L4 MP %8d kHz\n",
+ cm_get_rate_dm_khz(DM_L4_MP_CLK));
+ printf("L4 SP %8d kHz\n",
+ cm_get_rate_dm_khz(DM_L4_SP_CLK));
+ printf("SDMMC %8d kHz\n",
+ cm_get_rate_dm_khz(DM_SDMMC_CLK));
+}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
new file mode 100644
index 0000000000..a355fda692
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLOCK_MANAGER_DM_
+#define _CLOCK_MANAGER_DM_
+
+unsigned long cm_get_mpu_clk_hz(void);
+
+#include <asm/arch/clock_manager_soc64.h>
+#include "../../../../../drivers/clk/altera/clk-dm.h"
+
+#endif /* _CLOCK_MANAGER_DM_ */
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/9] ddr: altera: dm: Add SDRAM driver for Diamond Mesa
2022-09-18 12:17 [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Jit Loon Lim
2022-09-18 12:17 ` [PATCH 2/9] drivers: clk: dm: Add memory " Jit Loon Lim
2022-09-18 12:17 ` [PATCH 3/9] arm: socfpga: dm: Add clock manager " Jit Loon Lim
@ 2022-09-18 12:17 ` Jit Loon Lim
2022-09-18 12:17 ` [PATCH 5/9] arm: socfpga: dm: Add SPL " Jit Loon Lim
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Jit Loon Lim @ 2022-09-18 12:17 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Add SDRAM driver for Diamond Mesa.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/include/mach/misc.h | 4 +
arch/arm/mach-socfpga/misc_soc64.c | 70 +-
drivers/ddr/altera/sdram_dm.c | 1227 +++++++++++++++++++++
3 files changed, 1300 insertions(+), 1 deletion(-)
create mode 100644 drivers/ddr/altera/sdram_dm.c
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 8460acb00d..f366f51001 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -44,6 +44,10 @@ void socfpga_sdram_remap_zero(void);
int is_fpga_config_ready(void);
#endif
+#if defined(CONFIG_TARGET_SOCFPGA_DM)
+bool is_ddr_init_skipped(void);
+#endif
+
void do_bridge_reset(int enable, unsigned int mask);
void force_periph_program(unsigned int status);
bool is_regular_boot_valid(void);
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index 2acdfad07b..e61276d8ed 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2020 Intel Corporation <www.intel.com>
*
*/
@@ -20,6 +20,14 @@
DECLARE_GLOBAL_DATA_PTR;
+/* Reset type */
+enum reset_type {
+ por_reset,
+ warm_reset,
+ cold_reset,
+ rsu_reset
+};
+
/*
* FPGA programming support for SoC FPGA Stratix 10
*/
@@ -89,3 +97,63 @@ void do_bridge_reset(int enable, unsigned int mask)
socfpga_bridges_reset(enable);
}
+
+/* Only applicable to DM */
+#ifdef CONFIG_TARGET_SOCFPGA_DM
+static bool is_ddr_retention_enabled(u32 boot_scratch_cold0_reg)
+{
+ return boot_scratch_cold0_reg &
+ ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK;
+}
+
+static bool is_ddr_bitstream_sha_matching(u32 boot_scratch_cold0_reg)
+{
+ return boot_scratch_cold0_reg & ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK;
+}
+
+static enum reset_type get_reset_type(u32 boot_scratch_cold0_reg)
+{
+ return (boot_scratch_cold0_reg &
+ ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK) >>
+ ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT;
+}
+
+bool is_ddr_init_skipped(void)
+{
+ u32 reg = readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+
+ if (get_reset_type(reg) == por_reset) {
+ debug("%s: POR reset is triggered\n", __func__);
+ debug("%s: DDR init is required\n", __func__);
+ return false;
+ }
+
+ if (get_reset_type(reg) == warm_reset) {
+ debug("%s: Warm reset is triggered\n", __func__);
+ debug("%s: DDR init is skipped\n", __func__);
+ return true;
+ }
+
+ if ((get_reset_type(reg) == cold_reset) ||
+ (get_reset_type(reg) == rsu_reset)) {
+ debug("%s: Cold/RSU reset is triggered\n", __func__);
+
+ if (is_ddr_retention_enabled(reg)) {
+ debug("%s: DDR retention bit is set\n", __func__);
+
+ if (is_ddr_bitstream_sha_matching(reg)) {
+ debug("%s: Matching in DDR bistream\n",
+ __func__);
+ debug("%s: DDR init is skipped\n", __func__);
+ return true;
+ }
+
+ debug("%s: Mismatch in DDR bistream\n", __func__);
+ }
+ }
+
+ debug("%s: DDR init is required\n", __func__);
+ return false;
+}
+#endif
diff --git a/drivers/ddr/altera/sdram_dm.c b/drivers/ddr/altera/sdram_dm.c
new file mode 100644
index 0000000000..2254961f79
--- /dev/null
+++ b/drivers/ddr/altera/sdram_dm.c
@@ -0,0 +1,1227 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <div64.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <hang.h>
+#include <ram.h>
+#include <reset.h>
+#include "sdram_soc64.h"
+#include <wait_bit.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/handoff_soc64.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+#include <linux/err.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Memory reset manager */
+#define MEM_RST_MGR_STATUS 0x8
+
+/* Register and bit in memory reset manager */
+#define MEM_RST_MGR_STATUS_RESET_COMPLETE BIT(0)
+#define MEM_RST_MGR_STATUS_PWROKIN_STATUS BIT(1)
+#define MEM_RST_MGR_STATUS_CONTROLLER_RST BIT(2)
+#define MEM_RST_MGR_STATUS_AXI_RST BIT(3)
+
+#define TIMEOUT_200MS 200
+#define TIMEOUT_5000MS 5000
+
+/* DDR4 umctl2 */
+#define DDR4_STAT_OFFSET 0x4
+#define DDR4_STAT_SELFREF_TYPE (BIT(5) | BIT(4))
+#define DDR4_STAT_SELFREF_TYPE_SHIFT 4
+#define DDR4_STAT_OPERATING_MODE (BIT(2) | BIT(1) | BIT(0))
+
+#define DDR4_MRCTRL0_OFFSET 0x10
+#define DDR4_MRCTRL0_MR_TYPE BIT(0)
+#define DDR4_MRCTRL0_MPR_EN BIT(1)
+#define DDR4_MRCTRL0_MR_RANK (BIT(5) | BIT(4))
+#define DDR4_MRCTRL0_MR_RANK_SHIFT 4
+#define DDR4_MRCTRL0_MR_ADDR (BIT(15) | BIT(14) | BIT(13) | BIT(12))
+#define DDR4_MRCTRL0_MR_ADDR_SHIFT 12
+#define DDR4_MRCTRL0_MR_WR BIT(31)
+
+#define DDR4_MRCTRL1_OFFSET 0x14
+#define DDR4_MRCTRL1_MR_DATA 0x3FFFF
+
+#define DDR4_MRSTAT_OFFSET 0x18
+#define DDR4_MRSTAT_MR_WR_BUSY BIT(0)
+
+#define DDR4_MRCTRL2_OFFSET 0x1C
+
+#define DDR4_PWRCTL_OFFSET 0x30
+#define DDR4_PWRCTL_SELFREF_EN BIT(0)
+#define DDR4_PWRCTL_POWERDOWN_EN BIT(1)
+#define DDR4_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3)
+#define DDR4_PWRCTL_SELFREF_SW BIT(5)
+
+#define DDR4_PWRTMG_OFFSET 0x34
+#define DDR4_HWLPCTL_OFFSET 0x38
+#define DDR4_RFSHCTL0_OFFSET 0x50
+#define DDR4_RFSHCTL1_OFFSET 0x54
+
+#define DDR4_RFSHCTL3_OFFSET 0x60
+#define DDR4_RFSHCTL3_DIS_AUTO_REFRESH BIT(0)
+#define DDR4_RFSHCTL3_REFRESH_MODE (BIT(6) | BIT(5) | BIT(4))
+#define DDR4_RFSHCTL3_REFRESH_MODE_SHIFT 4
+
+#define DDR4_ECCCFG0_OFFSET 0x70
+#define DDR4_ECC_MODE (BIT(2) | BIT(1) | BIT(0))
+#define DDR4_DIS_SCRUB BIT(4)
+
+#define DDR4_CRCPARCTL1_OFFSET 0x04
+#define DDR4_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE BIT(8)
+#define DDR4_CRCPARCTL1_ALERT_WAIT_FOR_SW BIT(9)
+
+#define DDR4_CRCPARCTL0_OFFSET 0xC0
+#define DDR4_CRCPARCTL0_DFI_ALERT_ERR_INIT_CLR BIT(1)
+
+#define DDR4_CRCPARSTAT_OFFSET 0xCC
+#define DDR4_CRCPARSTAT_DFI_ALERT_ERR_INT BIT(16)
+#define DDR4_CRCPARSTAT_DFI_ALERT_ERR_FATL_INT BIT(17)
+#define DDR4_CRCPARSTAT_DFI_ALERT_ERR_NO_SW BIT(19)
+#define DDR4_CRCPARSTAT_CMD_IN_ERR_WINDOW BIT(29)
+
+#define DDR4_DFIMISC_OFFSET 0x1B0
+#define DDR4_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
+#define DDR4_DFIMISC_DFI_INIT_START BIT(5)
+
+#define DDR4_DFISTAT_OFFSET 0x1BC
+#define DDR4_DFI_INIT_COMPLETE BIT(0)
+
+#define DDR4_DBG0_OFFSET 0x300
+
+#define DDR4_DBG1_OFFSET 0x304
+#define DDR4_DBG1_DISDQ BIT(0)
+#define DDR4_DBG1_DIS_HIF BIT(1)
+
+#define DDR4_DBGCAM_OFFSET 0x308
+#define DDR4_DBGCAM_DBG_RD_Q_EMPTY BIT(25)
+#define DDR4_DBGCAM_DBG_WR_Q_EMPTY BIT(26)
+#define DDR4_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28)
+#define DDR4_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29)
+
+#define DDR4_SWCTL_OFFSET 0x320
+#define DDR4_SWCTL_SW_DONE BIT(0)
+
+#define DDR4_SWSTAT_OFFSET 0x324
+#define DDR4_SWSTAT_SW_DONE_ACK BIT(0)
+
+#define DDR4_PSTAT_OFFSET 0x3FC
+#define DDR4_PSTAT_RD_PORT_BUSY_0 BIT(0)
+#define DDR4_PSTAT_WR_PORT_BUSY_0 BIT(16)
+
+#define DDR4_PCTRL0_OFFSET 0x490
+#define DDR4_PCTRL0_PORT_EN BIT(0)
+
+#define DDR4_SBRCTL_OFFSET 0xF24
+#define DDR4_SBRCTL_SCRUB_INTERVAL 0x1FFF00
+#define DDR4_SBRCTL_SCRUB_EN BIT(0)
+#define DDR4_SBRCTL_SCRUB_WRITE BIT(2)
+#define DDR_SBRCTL_SCRUB_BURST_1 BIT(4)
+
+#define DDR4_SBRSTAT_OFFSET 0xF28
+#define DDR4_SBRSTAT_SCRUB_BUSY BIT(0)
+#define DDR4_SBRSTAT_SCRUB_DONE BIT(1)
+
+#define DDR4_SBRWDATA0_OFFSET 0xF2C
+#define DDR4_SBRWDATA1_OFFSET 0xF30
+#define DDR4_SBRSTART0_OFFSET 0xF38
+#define DDR4_SBRSTART1_OFFSET 0xF3C
+#define DDR4_SBRRANGE0_OFFSET 0xF40
+#define DDR4_SBRRANGE1_OFFSET 0xF44
+
+/* DDR PHY */
+#define DDR_PHY_TXODTDRVSTREN_B0_P0 0x2009A
+#define DDR_PHY_RXPBDLYTG0_R0 0x200D0
+#define DDR_PHY_CALRATE_OFFSET 0x40110
+#define DDR_PHY_CALZAP_OFFSET 0x40112
+#define DDR_PHY_SEQ0BDLY0_P0_OFFSET 0x40016
+#define DDR_PHY_SEQ0BDLY1_P0_OFFSET 0x40018
+#define DDR_PHY_SEQ0BDLY2_P0_OFFSET 0x4001A
+#define DDR_PHY_SEQ0BDLY3_P0_OFFSET 0x4001C
+#define DDR_PHY_SEQ0DISABLEFLAG0_OFFSET 0x120018
+#define DDR_PHY_SEQ0DISABLEFLAG1_OFFSET 0x12001A
+#define DDR_PHY_SEQ0DISABLEFLAG2_OFFSET 0x12001C
+#define DDR_PHY_SEQ0DISABLEFLAG3_OFFSET 0x12001E
+#define DDR_PHY_SEQ0DISABLEFLAG4_OFFSET 0x120020
+#define DDR_PHY_SEQ0DISABLEFLAG5_OFFSET 0x120022
+#define DDR_PHY_SEQ0DISABLEFLAG6_OFFSET 0x120024
+#define DDR_PHY_SEQ0DISABLEFLAG7_OFFSET 0x120026
+#define DDR_PHY_UCCLKHCLKENABLES_OFFSET 0x180100
+
+#define DDR_PHY_APBONLY0_OFFSET 0x1A0000
+#define DDR_PHY_MICROCONTMUXSEL BIT(0)
+
+#define DDR_PHY_MICRORESET_OFFSET 0x1A0132
+#define DDR_PHY_MICRORESET_STALL BIT(0)
+#define DDR_PHY_MICRORESET_RESET BIT(3)
+
+#define DDR_PHY_TXODTDRVSTREN_B0_P1 0x22009A
+
+/* Operating mode */
+#define INIT_OPM 0x000
+#define NORMAL_OPM 0x001
+#define PWR_D0WN_OPM 0x010
+#define SELF_SELFREF_OPM 0x011
+#define DDR4_DEEP_PWR_DOWN_OPM 0x100
+
+/* Refresh mode */
+#define FIXED_1X 0
+#define FIXED_2X BIT(0)
+#define FIXED_4X BIT(4)
+
+/* Address of mode register */
+#define MR0 0x0000
+#define MR1 0x0001
+#define MR2 0x0010
+#define MR3 0x0011
+#define MR4 0x0100
+#define MR5 0x0101
+#define MR6 0x0110
+#define MR7 0x0111
+
+/* MR rank */
+#define RANK0 0x1
+#define RANK1 0x2
+#define ALL_RANK 0x3
+
+#define MR5_BIT4 BIT(4)
+
+#ifdef CONFIG_TARGET_SOCFPGA_DM
+#define PSI_LL_SLAVE_APS_PER_OFST 0x00000000
+#define alt_write_hword(addr, val) (writew(val, addr))
+#define SDM_HPS_PERI_ADDR_TRANSLATION(_HPS_OFFSET_) \
+ (PSI_LL_SLAVE_APS_PER_OFST + (_HPS_OFFSET_))
+#define DDR_PHY_BASE 0xF8800000
+#define SNPS_PHY_TRANSLATION(_PHY_OFFSET_) \
+ (PSI_LL_SLAVE_APS_PER_OFST + ((DDR_PHY_BASE + ((_PHY_OFFSET_) << 1))))
+#define dwc_ddrphy_apb_wr(dest, data) \
+ alt_write_hword(SNPS_PHY_TRANSLATION(dest), data)
+#define b_max 1
+#define timing_group_max 4
+#endif
+
+/* DDR handoff structure */
+struct ddr_handoff {
+ phys_addr_t mem_reset_base;
+ phys_addr_t umctl2_handoff_base;
+ phys_addr_t umctl2_base;
+ size_t umctl2_total_length;
+ size_t umctl2_handoff_length;
+ phys_addr_t phy_handoff_base;
+ phys_addr_t phy_base;
+ size_t phy_total_length;
+ size_t phy_handoff_length;
+ phys_addr_t phy_engine_handoff_base;
+ size_t phy_engine_total_length;
+ size_t phy_engine_handoff_length;
+};
+
+static int clr_ca_parity_error_status(struct ddr_handoff *ddr_handoff_info)
+{
+ int ret;
+
+ debug("%s: Clear C/A parity error status in MR5[4]\n", __func__);
+
+ /* Set mode register MRS */
+ clrbits_le32(ddr_handoff_info->umctl2_base + DDR4_MRCTRL0_OFFSET,
+ DDR4_MRCTRL0_MPR_EN);
+
+ /* Set mode register to write operation */
+ setbits_le32(ddr_handoff_info->umctl2_base + DDR4_MRCTRL0_OFFSET,
+ DDR4_MRCTRL0_MR_TYPE);
+
+ /* Set the address of mode rgister to 0x101(MR5) */
+ setbits_le32(ddr_handoff_info->umctl2_base + DDR4_MRCTRL0_OFFSET,
+ (MR5 << DDR4_MRCTRL0_MR_ADDR_SHIFT) &
+ DDR4_MRCTRL0_MR_ADDR);
+
+ /* Set MR rank to rank 1 */
+ setbits_le32(ddr_handoff_info->umctl2_base + DDR4_MRCTRL0_OFFSET,
+ (RANK1 << DDR4_MRCTRL0_MR_RANK_SHIFT) &
+ DDR4_MRCTRL0_MR_RANK);
+
+ /* Clear C/A parity error status in MR5[4] */
+ clrbits_le32(ddr_handoff_info->umctl2_base + DDR4_MRCTRL1_OFFSET,
+ MR5_BIT4);
+
+ /* Trigger mode register read or write operation */
+ setbits_le32(ddr_handoff_info->umctl2_base + DDR4_MRCTRL0_OFFSET,
+ DDR4_MRCTRL0_MR_WR);
+
+ /* Wait for retry done */
+ ret = wait_for_bit_le32((const void *)(ddr_handoff_info->umctl2_base +
+ DDR4_MRSTAT_OFFSET), DDR4_MRSTAT_MR_WR_BUSY,
+ false, TIMEOUT_200MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" no outstanding MR transaction\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ddr4_retry_software_sequence(struct ddr_handoff *ddr_handoff_info)
+{
+ u32 value;
+ int ret;
+
+ /* Check software can perform MRS/MPR/PDA? */
+ value = readl(ddr_handoff_info->umctl2_base + DDR4_CRCPARSTAT_OFFSET) &
+ DDR4_CRCPARSTAT_DFI_ALERT_ERR_NO_SW;
+
+ if (value) {
+ debug("%s: Software can't perform MRS/MPR/PDA\n", __func__);
+
+ /* Clear interrupt bit for DFI alert error */
+ setbits_le32(ddr_handoff_info->umctl2_base +
+ DDR4_CRCPARCTL0_OFFSET,
+ DDR4_CRCPARCTL0_DFI_ALERT_ERR_INIT_CLR);
+
+ /* Wait for retry done */
+ ret = wait_for_bit_le32((const void *)
+ (ddr_handoff_info->umctl2_base +
+ DDR4_MRSTAT_OFFSET),
+ DDR4_MRSTAT_MR_WR_BUSY,
+ false, TIMEOUT_200MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" no outstanding MR transaction\n");
+ return ret;
+ }
+
+ if (clr_ca_parity_error_status(ddr_handoff_info))
+ return ret;
+ } else {
+ debug("%s: Software can perform MRS/MPR/PDA\n", __func__);
+
+ ret = wait_for_bit_le32((const void *)
+ (ddr_handoff_info->umctl2_base +
+ DDR4_MRSTAT_OFFSET),
+ DDR4_MRSTAT_MR_WR_BUSY,
+ false, TIMEOUT_200MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" no outstanding MR transaction\n");
+ return ret;
+ }
+
+ if (clr_ca_parity_error_status(ddr_handoff_info))
+ return ret;
+
+ /* Clear interrupt bit for DFI alert error */
+ setbits_le32(ddr_handoff_info->umctl2_base +
+ DDR4_CRCPARCTL0_OFFSET,
+ DDR4_CRCPARCTL0_DFI_ALERT_ERR_INIT_CLR);
+ }
+
+ return 0;
+}
+
+static int ensure_retry_procedure_complete(struct ddr_handoff *ddr_handoff_info)
+{
+ u32 value;
+ u32 start = get_timer(0);
+ int ret;
+
+ /* Check parity/crc/error window is emptied ? */
+ value = readl(ddr_handoff_info->umctl2_base + DDR4_CRCPARSTAT_OFFSET) &
+ DDR4_CRCPARSTAT_CMD_IN_ERR_WINDOW;
+
+ /* Polling until parity/crc/error window is emptied */
+ while (value) {
+ if (get_timer(start) > TIMEOUT_200MS) {
+ debug("%s: Timeout while waiting for",
+ __func__);
+ debug(" parity/crc/error window empty\n");
+ return -ETIMEDOUT;
+ }
+
+ /* Check software intervention is enabled? */
+ value = readl(ddr_handoff_info->umctl2_base +
+ DDR4_CRCPARCTL1_OFFSET) &
+ DDR4_CRCPARCTL1_ALERT_WAIT_FOR_SW;
+ if (value) {
+ debug("%s: Software intervention is enabled\n",
+ __func__);
+
+ /* Check dfi alert error interrupt is set? */
+ value = readl(ddr_handoff_info->umctl2_base +
+ DDR4_CRCPARSTAT_OFFSET) &
+ DDR4_CRCPARSTAT_DFI_ALERT_ERR_INT;
+
+ if (value) {
+ ret =
+ ddr4_retry_software_sequence(ddr_handoff_info);
+ debug("%s: DFI alert error interrupt ",
+ __func__);
+ debug("is set\n");
+
+ if (ret)
+ return ret;
+ }
+
+ /*
+ * Check fatal parity error interrupt is set?
+ */
+ value = readl(ddr_handoff_info->umctl2_base +
+ DDR4_CRCPARSTAT_OFFSET) &
+ DDR4_CRCPARSTAT_DFI_ALERT_ERR_FATL_INT;
+ if (value) {
+ printf("%s: Fatal parity error ",
+ __func__);
+ printf("interrupt is set, Hang it!!\n");
+ hang();
+ }
+ }
+
+ value = readl(ddr_handoff_info->umctl2_base +
+ DDR4_CRCPARSTAT_OFFSET) &
+ DDR4_CRCPARSTAT_CMD_IN_ERR_WINDOW;
+
+ udelay(1);
+ WATCHDOG_RESET();
+ }
+
+ return 0;
+}
+
+static int enable_quasi_dynamic_reg_grp3(struct ddr_handoff *ddr_handoff_info)
+{
+ u32 i, value, backup;
+ int ret;
+
+ /* Disable input traffic per port */
+ clrbits_le32(ddr_handoff_info->umctl2_base + DDR4_PCTRL0_OFFSET,
+ DDR4_PCTRL0_PORT_EN);
+
+ /* Polling AXI port until idle */
+ ret = wait_for_bit_le32((const void *)(ddr_handoff_info->umctl2_base +
+ DDR4_PSTAT_OFFSET), DDR4_PSTAT_WR_PORT_BUSY_0 |
+ DDR4_PSTAT_RD_PORT_BUSY_0, false,
+ TIMEOUT_200MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" controller idle\n");
+ return ret;
+ }
+
+ /* Backup user setting */
+ backup = readl(ddr_handoff_info->umctl2_base + DDR4_DBG1_OFFSET);
+
+ /* Disable input traffic to the controller */
+ setbits_le32(ddr_handoff_info->umctl2_base + DDR4_DBG1_OFFSET,
+ DDR4_DBG1_DIS_HIF);
+
+ /*
+ * Ensure CAM/data pipelines are empty.
+ * Poll until CAM/data pipelines are set at least twice,
+ * timeout at 200ms
+ */
+ for (i = 0; i < 2; i++) {
+ ret = wait_for_bit_le32((const void *)
+ (ddr_handoff_info->umctl2_base +
+ DDR4_DBGCAM_OFFSET),
+ DDR4_DBGCAM_WR_DATA_PIPELINE_EMPTY |
+ DDR4_DBGCAM_RD_DATA_PIPELINE_EMPTY |
+ DDR4_DBGCAM_DBG_WR_Q_EMPTY |
+ DDR4_DBGCAM_DBG_RD_Q_EMPTY, true,
+ TIMEOUT_200MS, false);
+ if (ret) {
+ debug("%s: loop(%u): Timeout while waiting for",
+ __func__, i + 1);
+ debug(" CAM/data pipelines are empty\n");
+
+ /* Restore user setting */
+ writel(backup, ddr_handoff_info->umctl2_base +
+ DDR4_DBG1_OFFSET);
+
+ return ret;
+ }
+ }
+
+ /* Check DDR4 retry is enabled ? */
+ value = readl(ddr_handoff_info->umctl2_base + DDR4_CRCPARCTL1_OFFSET) &
+ DDR4_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE;
+
+ if (value) {
+ debug("%s: DDR4 retry is enabled\n", __func__);
+
+ ret = ensure_retry_procedure_complete(ddr_handoff_info);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" retry procedure complete\n");
+
+ /* Restore user setting */
+ writel(backup, ddr_handoff_info->umctl2_base +
+ DDR4_DBG1_OFFSET);
+
+ return ret;
+ }
+ }
+
+ /* Restore user setting */
+ writel(backup, ddr_handoff_info->umctl2_base + DDR4_DBG1_OFFSET);
+
+ debug("%s: Quasi-dynamic group 3 registers are enabled\n", __func__);
+
+ return 0;
+}
+
+static int scrubbing_ddr_config(struct ddr_handoff *ddr_handoff_info)
+{
+ u32 backup[7];
+ int ret;
+
+ /* Reset to default value, prevent scrubber stop due to lower power */
+ writel(0, ddr_handoff_info->umctl2_base + DDR4_PWRCTL_OFFSET);
+
+ /* Disable input traffic per port */
+ clrbits_le32(ddr_handoff_info->umctl2_base + DDR4_PCTRL0_OFFSET,
+ DDR4_PCTRL0_PORT_EN);
+
+ /* Backup user settings */
+ backup[0] = readl(ddr_handoff_info->umctl2_base + DDR4_SBRCTL_OFFSET);
+ backup[1] = readl(ddr_handoff_info->umctl2_base +
+ DDR4_SBRWDATA0_OFFSET);
+ backup[2] = readl(ddr_handoff_info->umctl2_base +
+ DDR4_SBRWDATA1_OFFSET);
+ backup[3] = readl(ddr_handoff_info->umctl2_base +
+ DDR4_SBRSTART0_OFFSET);
+ backup[4] = readl(ddr_handoff_info->umctl2_base +
+ DDR4_SBRSTART1_OFFSET);
+ backup[5] = readl(ddr_handoff_info->umctl2_base +
+ DDR4_SBRRANGE0_OFFSET);
+ backup[6] = readl(ddr_handoff_info->umctl2_base +
+ DDR4_SBRRANGE1_OFFSET);
+
+ /* Scrub_burst = 1, scrub_mode = 1(performs writes) */
+ writel(DDR_SBRCTL_SCRUB_BURST_1 | DDR4_SBRCTL_SCRUB_WRITE,
+ ddr_handoff_info->umctl2_base + DDR4_SBRCTL_OFFSET);
+
+ /* Zeroing whole DDR */
+ writel(0, ddr_handoff_info->umctl2_base +
+ DDR4_SBRWDATA0_OFFSET);
+ writel(0, ddr_handoff_info->umctl2_base +
+ DDR4_SBRWDATA1_OFFSET);
+ writel(0, ddr_handoff_info->umctl2_base + DDR4_SBRSTART0_OFFSET);
+ writel(0, ddr_handoff_info->umctl2_base + DDR4_SBRSTART1_OFFSET);
+ writel(0, ddr_handoff_info->umctl2_base + DDR4_SBRRANGE0_OFFSET);
+ writel(0, ddr_handoff_info->umctl2_base + DDR4_SBRRANGE1_OFFSET);
+
+#ifdef CONFIG_TARGET_SOCFPGA_DM
+ writel(0x0FFFFFFF, ddr_handoff_info->umctl2_base +
+ DDR4_SBRRANGE0_OFFSET);
+#endif
+
+ /* Enables scrubber */
+ setbits_le32(ddr_handoff_info->umctl2_base + DDR4_SBRCTL_OFFSET,
+ DDR4_SBRCTL_SCRUB_EN);
+
+ /* Polling all scrub writes commands have been sent */
+ ret = wait_for_bit_le32((const void *)(ddr_handoff_info->umctl2_base +
+ DDR4_SBRSTAT_OFFSET), DDR4_SBRSTAT_SCRUB_DONE,
+ true, TIMEOUT_5000MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" sending all scrub commands\n");
+ return ret;
+ }
+
+ /* Polling all scrub writes data have been sent */
+ ret = wait_for_bit_le32((const void *)(ddr_handoff_info->umctl2_base +
+ DDR4_SBRSTAT_OFFSET), DDR4_SBRSTAT_SCRUB_BUSY,
+ false, TIMEOUT_5000MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" sending all scrub data\n");
+ return ret;
+ }
+
+ /* Disables scrubber */
+ clrbits_le32(ddr_handoff_info->umctl2_base + DDR4_SBRCTL_OFFSET,
+ DDR4_SBRCTL_SCRUB_EN);
+
+ /* Restore user settings */
+ writel(backup[0], ddr_handoff_info->umctl2_base + DDR4_SBRCTL_OFFSET);
+ writel(backup[1], ddr_handoff_info->umctl2_base +
+ DDR4_SBRWDATA0_OFFSET);
+ writel(backup[2], ddr_handoff_info->umctl2_base +
+ DDR4_SBRWDATA1_OFFSET);
+ writel(backup[3], ddr_handoff_info->umctl2_base +
+ DDR4_SBRSTART0_OFFSET);
+ writel(backup[4], ddr_handoff_info->umctl2_base +
+ DDR4_SBRSTART1_OFFSET);
+ writel(backup[5], ddr_handoff_info->umctl2_base +
+ DDR4_SBRRANGE0_OFFSET);
+ writel(backup[6], ddr_handoff_info->umctl2_base +
+ DDR4_SBRRANGE1_OFFSET);
+
+ return 0;
+}
+
+static int init_umctl2(struct ddr_handoff *ddr_handoff_info, u32 *user_backup)
+{
+ u32 handoff_table[ddr_handoff_info->umctl2_handoff_length];
+ u32 i, value, expected_value;
+ u32 start = get_timer(0);
+ int ret;
+
+ printf("Initializing DDR controller ...\n");
+
+ /* Prevent controller from issuing read/write to SDRAM */
+ setbits_le32(ddr_handoff_info->umctl2_base + DDR4_DBG1_OFFSET,
+ DDR4_DBG1_DISDQ);
+
+ /* Put SDRAM into self-refresh */
+ setbits_le32(ddr_handoff_info->umctl2_base + DDR4_PWRCTL_OFFSET,
+ DDR4_PWRCTL_SELFREF_EN);
+
+ /* Enable quasi-dynamic programing of the controller registers */
+ clrbits_le32(ddr_handoff_info->umctl2_base + DDR4_SWCTL_OFFSET,
+ DDR4_SWCTL_SW_DONE);
+
+ /* Ensure the controller is in initialization mode */
+ ret = wait_for_bit_le32((const void *)(ddr_handoff_info->umctl2_base +
+ DDR4_STAT_OFFSET), DDR4_STAT_OPERATING_MODE,
+ false, TIMEOUT_200MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" init operating mode\n");
+ return ret;
+ }
+
+ debug("%s: Handoff table address = 0x%p table length = 0x%08x\n",
+ __func__, (u32 *)handoff_table,
+ (u32)ddr_handoff_info->umctl2_handoff_length);
+
+ handoff_read((void *)ddr_handoff_info->umctl2_handoff_base,
+ handoff_table, ddr_handoff_info->umctl2_handoff_length,
+ little_endian);
+
+ for (i = 0; i < ddr_handoff_info->umctl2_handoff_length; i = i + 2) {
+ debug("%s: Absolute addr: 0x%08llx APB offset: 0x%08x",
+ __func__, handoff_table[i] +
+ ddr_handoff_info->umctl2_base, handoff_table[i]);
+ debug(" wr = 0x%08x ", handoff_table[i + 1]);
+
+ writel(handoff_table[i + 1], (uintptr_t)(handoff_table[i] +
+ ddr_handoff_info->umctl2_base));
+
+ debug("rd = 0x%08x\n", readl((uintptr_t)(handoff_table[i] +
+ ddr_handoff_info->umctl2_base)));
+ }
+
+ /* Backup user settings, restore after DDR up running */
+ *user_backup = readl(ddr_handoff_info->umctl2_base +
+ DDR4_PWRCTL_OFFSET);
+
+ /* Polling granularity of refresh mode change to fixed 2x (DDR4) */
+ value = readl(ddr_handoff_info->umctl2_base + DDR4_RFSHCTL3_OFFSET) &
+ DDR4_RFSHCTL3_REFRESH_MODE;
+
+ expected_value = FIXED_2X << DDR4_RFSHCTL3_REFRESH_MODE_SHIFT;
+
+ while (value != expected_value) {
+ if (get_timer(start) > TIMEOUT_200MS) {
+ debug("%s: loop(%u): Timeout while waiting for",
+ __func__, i + 1);
+ debug(" fine granularity refresh mode change to ");
+ debug("fixed 2x\n");
+ debug("%s: expected_value = 0x%x value= 0x%x\n",
+ __func__, expected_value, value);
+ return -ETIMEDOUT;
+ }
+
+ value = readl(ddr_handoff_info->umctl2_base +
+ DDR4_RFSHCTL3_OFFSET) &
+ DDR4_RFSHCTL3_REFRESH_MODE;
+ }
+
+ /* Disable self resfresh */
+ clrbits_le32(ddr_handoff_info->umctl2_base + DDR4_PWRCTL_OFFSET,
+ DDR4_PWRCTL_SELFREF_EN);
+
+ /* Complete quasi-dynamic register programming */
+ setbits_le32(ddr_handoff_info->umctl2_base + DDR4_SWCTL_OFFSET,
+ DDR4_SWCTL_SW_DONE);
+
+ /* Enable controller from issuing read/write to SDRAM */
+ clrbits_le32(ddr_handoff_info->umctl2_base + DDR4_DBG1_OFFSET,
+ DDR4_DBG1_DISDQ);
+
+ /* Release the controller from reset */
+ setbits_le32((uintptr_t)(readl(ddr_handoff_info->mem_reset_base) +
+ MEM_RST_MGR_STATUS), MEM_RST_MGR_STATUS_AXI_RST |
+ MEM_RST_MGR_STATUS_CONTROLLER_RST |
+ MEM_RST_MGR_STATUS_RESET_COMPLETE);
+
+ printf("DDR controller configuration is completed\n");
+
+ return 0;
+}
+
+static int init_phy(struct ddr_handoff *ddr_handoff_info)
+{
+ u32 handoff_table[ddr_handoff_info->phy_handoff_length];
+ u32 i, value;
+ int ret;
+
+ printf("Initializing DDR PHY ...\n");
+
+ /* Check DDR4 retry is enabled ? */
+ value = readl(ddr_handoff_info->umctl2_base + DDR4_CRCPARCTL1_OFFSET) &
+ DDR4_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE;
+
+ if (value) {
+ debug("%s: DDR4 retry is enabled\n", __func__);
+ debug("%s: Disable auto refresh is not supported\n", __func__);
+ } else {
+ /* Disable auto refresh */
+ setbits_le32(ddr_handoff_info->umctl2_base +
+ DDR4_RFSHCTL3_OFFSET,
+ DDR4_RFSHCTL3_DIS_AUTO_REFRESH);
+ }
+
+ /* Disable selfref_en & powerdown_en, nvr disable dfi dram clk */
+ clrbits_le32(ddr_handoff_info->umctl2_base + DDR4_PWRCTL_OFFSET,
+ DDR4_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |
+ DDR4_PWRCTL_POWERDOWN_EN | DDR4_PWRCTL_SELFREF_EN);
+
+ /* Enable quasi-dynamic programing of the controller registers */
+ clrbits_le32(ddr_handoff_info->umctl2_base + DDR4_SWCTL_OFFSET,
+ DDR4_SWCTL_SW_DONE);
+
+ ret = enable_quasi_dynamic_reg_grp3(ddr_handoff_info);
+ if (ret)
+ return ret;
+
+ /* Masking dfi init complete */
+ clrbits_le32(ddr_handoff_info->umctl2_base + DDR4_DFIMISC_OFFSET,
+ DDR4_DFIMISC_DFI_INIT_COMPLETE_EN);
+
+ /* Complete quasi-dynamic register programming */
+ setbits_le32(ddr_handoff_info->umctl2_base + DDR4_SWCTL_OFFSET,
+ DDR4_SWCTL_SW_DONE);
+
+ /* Polling programming done */
+ ret = wait_for_bit_le32((const void *)(ddr_handoff_info->umctl2_base +
+ DDR4_SWSTAT_OFFSET), DDR4_SWSTAT_SW_DONE_ACK,
+ true, TIMEOUT_200MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" programming done\n");
+ return ret;
+ }
+
+ debug("%s: Handoff table address = 0x%p table length = 0x%08x\n",
+ __func__, (u32 *)handoff_table,
+ (u32)ddr_handoff_info->umctl2_handoff_length);
+
+ /* Execute PHY configuration handoff */
+ handoff_read((void *)ddr_handoff_info->phy_handoff_base, handoff_table,
+ (u32)ddr_handoff_info->phy_handoff_length, little_endian);
+
+ for (i = 0; i < ddr_handoff_info->phy_handoff_length; i = i + 2) {
+ /*
+ * Convert PHY odd offset to even offset that supported by
+ * ARM processor.
+ */
+ value = handoff_table[i] << 1;
+ debug("%s: Absolute addr: 0x%08llx, APB offset: 0x%08x ",
+ __func__, value + ddr_handoff_info->phy_base, value);
+ debug("PHY offset: 0x%08x", handoff_table[i]);
+ debug(" wr = 0x%08x ", handoff_table[i + 1]);
+ writew(handoff_table[i + 1], (uintptr_t)(value +
+ ddr_handoff_info->phy_base));
+ debug("rd = 0x%08x\n", readw((uintptr_t)(value +
+ ddr_handoff_info->phy_base)));
+ }
+
+#ifdef CONFIG_TARGET_SOCFPGA_DM
+ u8 numdbyte = 0x0009;
+ u8 byte, lane;
+ u32 b_addr, c_addr;
+
+ /* Program TxOdtDrvStren bx_p0 */
+ for (byte = 0; byte < numdbyte; byte++) {
+ c_addr = byte << 13;
+
+ for (lane = 0; lane <= b_max ; lane++) {
+ b_addr = lane << 9;
+ writew(0x00, (uintptr_t)
+ (ddr_handoff_info->phy_base +
+ DDR_PHY_TXODTDRVSTREN_B0_P0 + c_addr +
+ b_addr));
+ }
+ }
+
+ /* Program TxOdtDrvStren bx_p1 */
+ for (byte = 0; byte < numdbyte; byte++) {
+ c_addr = byte << 13;
+
+ for (lane = 0; lane <= b_max ; lane++) {
+ b_addr = lane << 9;
+ writew(0x00, (uintptr_t)
+ (ddr_handoff_info->phy_base +
+ DDR_PHY_TXODTDRVSTREN_B0_P1 + c_addr +
+ b_addr));
+ }
+ }
+
+ /*
+ * [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz,
+ * Programming ARdPtrInitVal to 0x2
+ * DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0
+ */
+ dwc_ddrphy_apb_wr(0x2002e, 0x3);
+
+ /* [phyinit_C_initPhyConfig] Pstate=1,
+ * Memclk=1067MHz, Programming ARdPtrInitVal to 0x2
+ * DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1
+ */
+ dwc_ddrphy_apb_wr(0x12002e, 0x3);
+
+ /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */
+ dwc_ddrphy_apb_wr(0x200f0, 0x6666);
+
+ /* DWC_DDRPHYA_DBYTE0_DFIMRL_p0 */
+ dwc_ddrphy_apb_wr(0x10020, 0x4);
+ /* DWC_DDRPHYA_DBYTE1_DFIMRL_p0 */
+ dwc_ddrphy_apb_wr(0x11020, 0x4);
+ /* DWC_DDRPHYA_DBYTE2_DFIMRL_p0 */
+ dwc_ddrphy_apb_wr(0x12020, 0x4);
+ /* DWC_DDRPHYA_DBYTE3_DFIMRL_p0 */
+ dwc_ddrphy_apb_wr(0x13020, 0x4); //
+ /* DWC_DDRPHYA_DBYTE4_DFIMRL_p0 */
+ dwc_ddrphy_apb_wr(0x14020, 0x4);
+ /* DWC_DDRPHYA_DBYTE5_DFIMRL_p0 */
+ dwc_ddrphy_apb_wr(0x15020, 0x4);
+ /* DWC_DDRPHYA_DBYTE6_DFIMRL_p0 */
+ dwc_ddrphy_apb_wr(0x16020, 0x4);
+ /* DWC_DDRPHYA_DBYTE7_DFIMRL_p0 */
+ dwc_ddrphy_apb_wr(0x17020, 0x4);
+ /* DWC_DDRPHYA_DBYTE8_DFIMRL_p0 */
+ dwc_ddrphy_apb_wr(0x18020, 0x4);
+ /* DWC_DDRPHYA_MASTER0_HwtMRL_p0 */
+ dwc_ddrphy_apb_wr(0x20020, 0x4);
+#endif
+
+ printf("DDR PHY configuration is completed\n");
+
+ return 0;
+}
+
+static void phy_init_engine(struct ddr_handoff *ddr_handoff_info)
+{
+ u32 i, value;
+ u32 handoff_table[ddr_handoff_info->phy_engine_handoff_length];
+
+ printf("Load PHY Init Engine ...\n");
+
+ /* Execute PIE production code handoff */
+ handoff_read((void *)ddr_handoff_info->phy_engine_handoff_base,
+ handoff_table,
+ (u32)ddr_handoff_info->phy_engine_handoff_length,
+ little_endian);
+
+ for (i = 0; i < ddr_handoff_info->phy_engine_handoff_length;
+ i = i + 2) {
+ debug("Handoff addr: 0x%8llx ", handoff_table[i] +
+ ddr_handoff_info->phy_base);
+
+ /*
+ * Convert PHY odd offset to even offset that supported by
+ * ARM processor.
+ */
+ value = handoff_table[i] << 1;
+ debug("%s: Absolute addr: 0x%08llx, APB offset: 0x%08x ",
+ __func__, value + ddr_handoff_info->phy_base, value);
+ debug("PHY offset: 0x%08x", handoff_table[i]);
+ debug(" wr = 0x%08x ", handoff_table[i + 1]);
+
+ writew(handoff_table[i + 1], (uintptr_t)(value +
+ ddr_handoff_info->phy_base));
+
+ debug("rd = 0x%08x\n", readw((uintptr_t)(value +
+ ddr_handoff_info->phy_base)));
+ }
+
+#ifdef CONFIG_TARGET_SOCFPGA_DM
+ u8 numdbyte = 0x0009;
+ u8 byte, timing_group;
+ u32 b_addr, c_addr;
+
+ /* Enable access to the PHY configuration registers */
+ clrbits_le16(ddr_handoff_info->phy_base + DDR_PHY_APBONLY0_OFFSET,
+ DDR_PHY_MICROCONTMUXSEL);
+
+ /* Program RXPBDLYTG0 bx_p0 */
+ for (byte = 0; byte < numdbyte; byte++) {
+ c_addr = byte << 9;
+
+ for (timing_group = 0; timing_group <= timing_group_max;
+ timing_group++) {
+ b_addr = timing_group << 1;
+ writew(0x00, (uintptr_t)
+ (ddr_handoff_info->phy_base +
+ DDR_PHY_RXPBDLYTG0_R0 + c_addr +
+ b_addr));
+ }
+ }
+
+ /* Isolate the APB access from internal CSRs */
+ setbits_le16(ddr_handoff_info->phy_base + DDR_PHY_APBONLY0_OFFSET,
+ DDR_PHY_MICROCONTMUXSEL);
+#endif
+
+ printf("End of loading PHY Init Engine\n");
+}
+
+int populate_ddr_handoff(struct ddr_handoff *ddr_handoff_info)
+{
+ /* DDR handoff */
+ ddr_handoff_info->mem_reset_base = SOC64_HANDOFF_DDR_MEMRESET_BASE;
+ debug("%s: DDR memory reset base = 0x%x\n", __func__,
+ (u32)ddr_handoff_info->mem_reset_base);
+ debug("%s: DDR memory reset address = 0x%x\n", __func__,
+ readl(ddr_handoff_info->mem_reset_base));
+
+ /* DDR controller handoff */
+ ddr_handoff_info->umctl2_handoff_base =
+ SOC64_HANDOFF_DDR_UMCTL2_SECTION;
+ debug("%s: umctl2 handoff base = 0x%x\n", __func__,
+ (u32)ddr_handoff_info->umctl2_handoff_base);
+
+ ddr_handoff_info->umctl2_base = readl(SOC64_HANDOFF_DDR_UMCTL2_BASE);
+ debug("%s: umctl2 base = 0x%x\n", __func__,
+ (u32)ddr_handoff_info->umctl2_base);
+
+ ddr_handoff_info->umctl2_total_length =
+ readl(ddr_handoff_info->umctl2_handoff_base +
+ SOC64_HANDOFF_OFFSET_LENGTH);
+ debug("%s: Umctl2 total length in byte = 0x%x\n", __func__,
+ (u32)ddr_handoff_info->umctl2_total_length);
+
+ ddr_handoff_info->umctl2_handoff_length =
+ get_handoff_size((void *)ddr_handoff_info->umctl2_handoff_base,
+ little_endian);
+ debug("%s: Umctl2 handoff length in word(32-bit) = 0x%x\n", __func__,
+ (u32)ddr_handoff_info->umctl2_handoff_length);
+
+ if (ddr_handoff_info->umctl2_handoff_length < 0)
+ return ddr_handoff_info->umctl2_handoff_length;
+
+ /* DDR PHY handoff */
+ ddr_handoff_info->phy_handoff_base =
+ ddr_handoff_info->umctl2_handoff_base +
+ ddr_handoff_info->umctl2_total_length;
+ debug("%s: PHY handoff base = 0x%x\n", __func__,
+ (u32)ddr_handoff_info->phy_handoff_base);
+
+ ddr_handoff_info->phy_base =
+ readl(ddr_handoff_info->phy_handoff_base +
+ SOC64_HANDOFF_DDR_PHY_BASE_OFFSET);
+ debug("%s: PHY base = 0x%x\n", __func__,
+ (u32)ddr_handoff_info->phy_base);
+
+ ddr_handoff_info->phy_total_length =
+ readl(ddr_handoff_info->phy_handoff_base +
+ SOC64_HANDOFF_OFFSET_LENGTH);
+ debug("%s: PHY total length in byte = 0x%x\n", __func__,
+ (u32)ddr_handoff_info->phy_total_length);
+
+ ddr_handoff_info->phy_handoff_length =
+ get_handoff_size((void *)ddr_handoff_info->phy_handoff_base,
+ little_endian);
+ debug("%s: PHY handoff length in word(32-bit) = 0x%x\n", __func__,
+ (u32)ddr_handoff_info->phy_handoff_length);
+
+ if (ddr_handoff_info->phy_handoff_length < 0)
+ return ddr_handoff_info->phy_handoff_length;
+
+ /* DDR PHY Engine handoff */
+ ddr_handoff_info->phy_engine_handoff_base =
+ ddr_handoff_info->phy_handoff_base +
+ ddr_handoff_info->phy_total_length;
+ debug("%s: PHY base = 0x%x\n", __func__,
+ (u32)ddr_handoff_info->phy_engine_handoff_base);
+
+ ddr_handoff_info->phy_engine_total_length =
+ readl(ddr_handoff_info->phy_engine_handoff_base +
+ SOC64_HANDOFF_OFFSET_LENGTH);
+ debug("%s: PHY engine total length in byte = 0x%x\n", __func__,
+ (u32)ddr_handoff_info->phy_engine_total_length);
+
+ ddr_handoff_info->phy_engine_handoff_length =
+ get_handoff_size((void *)ddr_handoff_info->phy_engine_handoff_base,
+ little_endian);
+ debug("%s: PHY engine handoff length in word(32-bit) = 0x%x\n",
+ __func__, (u32)ddr_handoff_info->phy_engine_handoff_length);
+
+ if (ddr_handoff_info->phy_engine_handoff_length < 0)
+ return ddr_handoff_info->phy_engine_handoff_length;
+
+ return 0;
+}
+
+int enable_ddr_clock(struct udevice *dev)
+{
+ struct clk *ddr_clk;
+ int ret;
+
+ /* Enable clock before init DDR */
+ ddr_clk = devm_clk_get(dev, "mem_clk");
+ if (!IS_ERR(ddr_clk)) {
+ ret = clk_enable(ddr_clk);
+ if (ret) {
+ printf("%s: Failed to enable DDR clock\n", __func__);
+ return ret;
+ }
+ } else {
+ ret = PTR_ERR(ddr_clk);
+ debug("%s: Failed to get DDR clock from dts\n", __func__);
+ return ret;
+ }
+
+ printf("%s: DDR clock is enabled\n", __func__);
+
+ return 0;
+}
+
+int sdram_mmr_init_full(struct udevice *dev)
+{
+ u32 value, user_backup;
+ u32 start = get_timer(0);
+ int ret;
+ struct bd_info bd;
+ struct ddr_handoff ddr_handoff_info;
+ struct altera_sdram_priv *priv = dev_get_priv(dev);
+
+ if (!is_ddr_init_skipped()) {
+ printf("%s: SDRAM init in progress ...\n", __func__);
+
+ ret = populate_ddr_handoff(&ddr_handoff_info);
+ if (ret) {
+ debug("%s: Failed to populate DDR handoff\n", __func__);
+ return ret;
+ }
+
+ /*
+ * Polling reset complete, must be high to ensure DDR subsystem
+ * in complete reset state before init DDR clock and DDR
+ * controller
+ */
+ ret = wait_for_bit_le32((const void *)((uintptr_t)(readl
+ (ddr_handoff_info.mem_reset_base) +
+ MEM_RST_MGR_STATUS)),
+ MEM_RST_MGR_STATUS_RESET_COMPLETE, true,
+ TIMEOUT_200MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" reset complete done\n");
+ return ret;
+ }
+
+ ret = enable_ddr_clock(dev);
+ if (ret)
+ return ret;
+
+ /* Initialize DDR controller */
+ ret = init_umctl2(&ddr_handoff_info, &user_backup);
+ if (ret) {
+ debug("%s: Failed to inilialize DDR controller\n",
+ __func__);
+ return ret;
+ }
+
+ /* Initialize DDR PHY */
+ ret = init_phy(&ddr_handoff_info);
+ if (ret) {
+ debug("%s: Failed to inilialize DDR PHY\n", __func__);
+ return ret;
+ }
+
+ /* Reset ARC processor when no using for security purpose */
+ setbits_le16(ddr_handoff_info.phy_base +
+ DDR_PHY_MICRORESET_OFFSET,
+ DDR_PHY_MICRORESET_RESET);
+
+ /* DDR freq set to support DDR4-3200 */
+ phy_init_engine(&ddr_handoff_info);
+
+ /* Trigger memory controller to init SDRAM */
+ /* Enable quasi-dynamic programing of controller registers */
+ clrbits_le32(ddr_handoff_info.umctl2_base + DDR4_SWCTL_OFFSET,
+ DDR4_SWCTL_SW_DONE);
+
+ ret = enable_quasi_dynamic_reg_grp3(&ddr_handoff_info);
+ if (ret)
+ return ret;
+
+ /* Start DFI init sequence */
+ setbits_le32(ddr_handoff_info.umctl2_base + DDR4_DFIMISC_OFFSET,
+ DDR4_DFIMISC_DFI_INIT_START);
+
+ /* Complete quasi-dynamic register programming */
+ setbits_le32(ddr_handoff_info.umctl2_base + DDR4_SWCTL_OFFSET,
+ DDR4_SWCTL_SW_DONE);
+
+ /* Polling programming done */
+ ret = wait_for_bit_le32((const void *)
+ (ddr_handoff_info.umctl2_base +
+ DDR4_SWSTAT_OFFSET),
+ DDR4_SWSTAT_SW_DONE_ACK, true,
+ TIMEOUT_200MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" programming done\n");
+ return ret;
+ }
+
+ /* Polling DFI init complete */
+ ret = wait_for_bit_le32((const void *)
+ (ddr_handoff_info.umctl2_base +
+ DDR4_DFISTAT_OFFSET),
+ DDR4_DFI_INIT_COMPLETE, true,
+ TIMEOUT_200MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" DFI init done\n");
+ return ret;
+ }
+
+ debug("DFI init completed.\n");
+
+ /* Enable quasi-dynamic programing of controller registers */
+ clrbits_le32(ddr_handoff_info.umctl2_base + DDR4_SWCTL_OFFSET,
+ DDR4_SWCTL_SW_DONE);
+
+ ret = enable_quasi_dynamic_reg_grp3(&ddr_handoff_info);
+ if (ret)
+ return ret;
+
+ /* Stop DFI init sequence */
+ clrbits_le32(ddr_handoff_info.umctl2_base + DDR4_DFIMISC_OFFSET,
+ DDR4_DFIMISC_DFI_INIT_START);
+
+ /* Unmasking dfi init complete */
+ setbits_le32(ddr_handoff_info.umctl2_base + DDR4_DFIMISC_OFFSET,
+ DDR4_DFIMISC_DFI_INIT_COMPLETE_EN);
+
+ /* Software exit from self-refresh */
+ clrbits_le32(ddr_handoff_info.umctl2_base + DDR4_PWRCTL_OFFSET,
+ DDR4_PWRCTL_SELFREF_SW);
+
+ /* Complete quasi-dynamic register programming */
+ setbits_le32(ddr_handoff_info.umctl2_base + DDR4_SWCTL_OFFSET,
+ DDR4_SWCTL_SW_DONE);
+
+ /* Polling programming done */
+ ret = wait_for_bit_le32((const void *)
+ (ddr_handoff_info.umctl2_base +
+ DDR4_SWSTAT_OFFSET),
+ DDR4_SWSTAT_SW_DONE_ACK, true,
+ TIMEOUT_200MS, false);
+ if (ret) {
+ debug("%s: Timeout while waiting for", __func__);
+ debug(" programming done\n");
+ return ret;
+ }
+
+ debug("DDR programming done\n");
+
+ /* Polling until SDRAM entered normal operating mode */
+ value = readl(ddr_handoff_info.umctl2_base + DDR4_STAT_OFFSET) &
+ DDR4_STAT_OPERATING_MODE;
+ while (value != NORMAL_OPM) {
+ if (get_timer(start) > TIMEOUT_200MS) {
+ debug("%s: Timeout while waiting for",
+ __func__);
+ debug(" DDR enters normal operating mode\n");
+ return -ETIMEDOUT;
+ }
+
+ value = readl(ddr_handoff_info.umctl2_base +
+ DDR4_STAT_OFFSET) &
+ DDR4_STAT_OPERATING_MODE;
+
+ udelay(1);
+ WATCHDOG_RESET();
+ }
+
+ debug("DDR entered normal operating mode\n");
+
+ /* Enabling auto refresh */
+ clrbits_le32(ddr_handoff_info.umctl2_base +
+ DDR4_RFSHCTL3_OFFSET,
+ DDR4_RFSHCTL3_DIS_AUTO_REFRESH);
+
+ /* Checking ECC is enabled? */
+ value = readl(ddr_handoff_info.umctl2_base +
+ DDR4_ECCCFG0_OFFSET) & DDR4_ECC_MODE;
+ if (value) {
+ printf("%s: ECC is enabled\n", __func__);
+ ret = scrubbing_ddr_config(&ddr_handoff_info);
+ if (ret) {
+ debug("%s: Failed to enable ECC\n", __func__);
+ return ret;
+ }
+ }
+
+ /* Restore user settings */
+ writel(user_backup, ddr_handoff_info.umctl2_base +
+ DDR4_PWRCTL_OFFSET);
+
+ /* Enable input traffic per port */
+ setbits_le32(ddr_handoff_info.umctl2_base + DDR4_PCTRL0_OFFSET,
+ DDR4_PCTRL0_PORT_EN);
+
+ printf("%s: DDR init success\n", __func__);
+ }
+
+ /* Get bank configuration from devicetree */
+ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
+ (phys_size_t *)&gd->ram_size, &bd);
+ if (ret) {
+ debug("%s: Failed to decode memory node\n", __func__);
+ return -1;
+ }
+
+ printf("DDR: %lld MiB\n", gd->ram_size >> 20);
+
+ priv->info.base = bd.bi_dram[0].start;
+ priv->info.size = gd->ram_size;
+
+ /* This enables nonsecure access to DDR */
+ /* mpuregion0addr_limit */
+ FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
+ FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
+ FW_MPU_DDR_SCR_WRITEL(((gd->ram_size - 1) >> SZ_32) &
+ FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD,
+ FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
+
+ /* nonmpuregion0addr_limit */
+ FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
+ FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
+
+ /* Enable mpuregion0enable and nonmpuregion0enable */
+ FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
+ FW_MPU_DDR_SCR_EN_SET);
+
+ return 0;
+}
\ No newline at end of file
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 5/9] arm: socfpga: dm: Add SPL for Diamond Mesa
2022-09-18 12:17 [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Jit Loon Lim
` (2 preceding siblings ...)
2022-09-18 12:17 ` [PATCH 4/9] ddr: altera: dm: Add SDRAM driver " Jit Loon Lim
@ 2022-09-18 12:17 ` Jit Loon Lim
2022-09-18 12:17 ` [PATCH 6/9] board: intel: dm: Add socdk board support " Jit Loon Lim
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Jit Loon Lim @ 2022-09-18 12:17 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Add SPL for Diamond Mesa.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
arch/arm/mach-socfpga/spl_dm.c | 97 ++++++++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 arch/arm/mach-socfpga/spl_dm.c
diff --git a/arch/arm/mach-socfpga/spl_dm.c b/arch/arm/mach-socfpga/spl_dm.c
new file mode 100644
index 0000000000..0be8f29dbb
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_dm.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/smmu_s10.h>
+#include <asm/arch/system_manager.h>
+#include <watchdog.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+ struct udevice *dev;
+
+ ret = spl_early_init();
+ if (ret)
+ hang();
+
+ socfpga_get_managers_addr();
+
+ /* Ensure watchdog is paused when debugging is happening */
+ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+ socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+#ifdef CONFIG_HW_WATCHDOG
+ /* Enable watchdog before initializing the HW */
+ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+ hw_watchdog_init();
+#endif
+
+ /* ensure all processors are not released prior Linux boot */
+ writeq(0, CPU_RELEASE_ADDR);
+
+ timer_init();
+
+ sysmgr_pinmux_init();
+
+ preloader_console_init();
+
+ ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (ret) {
+ printf("Clock init failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 1, &dev);
+ if (ret) {
+ printf("Memory clock init failed: %d\n", ret);
+ hang();
+ }
+
+ print_reset_info();
+ cm_print_clock_quick_summary();
+
+ firewall_setup();
+
+ /* Setup and Initialize SMMU */
+ socfpga_init_smmu();
+
+ ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
+ if (ret) {
+ printf("CCU init failed: %d\n", ret);
+ hang();
+ }
+
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ hang();
+ }
+#endif
+
+ mbox_init();
+
+#ifdef CONFIG_CADENCE_QSPI
+ mbox_qspi_open();
+#endif
+}
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 6/9] board: intel: dm: Add socdk board support for Diamond Mesa
2022-09-18 12:17 [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Jit Loon Lim
` (3 preceding siblings ...)
2022-09-18 12:17 ` [PATCH 5/9] arm: socfpga: dm: Add SPL " Jit Loon Lim
@ 2022-09-18 12:17 ` Jit Loon Lim
2022-09-18 12:17 ` [PATCH 7/9] arm: dts: dm: Add base dtsi and devkit dts " Jit Loon Lim
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Jit Loon Lim @ 2022-09-18 12:17 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Add socdk board support for Diamond Mesa.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
board/intel/dm-socdk/MAINTAINERS | 7 +++++++
board/intel/dm-socdk/Makefile | 7 +++++++
board/intel/dm-socdk/socfpga.c | 7 +++++++
3 files changed, 21 insertions(+)
create mode 100644 board/intel/dm-socdk/MAINTAINERS
create mode 100644 board/intel/dm-socdk/Makefile
create mode 100644 board/intel/dm-socdk/socfpga.c
diff --git a/board/intel/dm-socdk/MAINTAINERS b/board/intel/dm-socdk/MAINTAINERS
new file mode 100644
index 0000000000..f41bbcf2d5
--- /dev/null
+++ b/board/intel/dm-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Chee Tien Fong <tien.fong.chee@intel.com>
+M: Lim Siew Chin <elly.siew.chin.lim@intel.com>
+S: Maintained
+F: board/intel/dm-socdk/
+F: include/configs/socfpga_dm_socdk.h
+F: configs/socfpga_dm_atf_defconfig
diff --git a/board/intel/dm-socdk/Makefile b/board/intel/dm-socdk/Makefile
new file mode 100644
index 0000000000..09f07b8b2f
--- /dev/null
+++ b/board/intel/dm-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2020 Intel Corporation <www.intel.com>
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := socfpga.o
diff --git a/board/intel/dm-socdk/socfpga.c b/board/intel/dm-socdk/socfpga.c
new file mode 100644
index 0000000000..ce87e2307d
--- /dev/null
+++ b/board/intel/dm-socdk/socfpga.c
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 7/9] arm: dts: dm: Add base dtsi and devkit dts for Diamond Mesa
2022-09-18 12:17 [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Jit Loon Lim
` (4 preceding siblings ...)
2022-09-18 12:17 ` [PATCH 6/9] board: intel: dm: Add socdk board support " Jit Loon Lim
@ 2022-09-18 12:17 ` Jit Loon Lim
2022-09-18 12:17 ` [PATCH 8/9] configs: dm: Add Diamond Mesa CONFIGs Jit Loon Lim
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Jit Loon Lim @ 2022-09-18 12:17 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Add base dtsi and devkit dts for Diamond Mesa.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
arch/arm/dts/socfpga_dm-u-boot.dtsi | 102 ++++
arch/arm/dts/socfpga_dm.dtsi | 640 ++++++++++++++++++++++
arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi | 50 ++
arch/arm/dts/socfpga_dm_socdk.dts | 144 +++++
4 files changed, 936 insertions(+)
create mode 100644 arch/arm/dts/socfpga_dm-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_dm.dtsi
create mode 100644 arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_dm_socdk.dts
diff --git a/arch/arm/dts/socfpga_dm-u-boot.dtsi b/arch/arm/dts/socfpga_dm-u-boot.dtsi
new file mode 100644
index 0000000000..d576b98b4f
--- /dev/null
+++ b/arch/arm/dts/socfpga_dm-u-boot.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ */
+
+#include "socfpga_soc64_fit-u-boot.dtsi"
+
+/{
+ memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ auto-size;
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+
+ ccu: cache-controller@f7000000 {
+ compatible = "arteris,ncore-ccu";
+ reg = <0xf7000000 0x100900>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&clkmgr {
+ u-boot,dm-pre-reloc;
+};
+
+&gmac1 {
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+};
+
+&gmac2 {
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+};
+
+&i2c0 {
+ reset-names = "i2c";
+};
+
+&i2c1 {
+ reset-names = "i2c";
+};
+
+&i2c2 {
+ reset-names = "i2c";
+};
+
+&i2c3 {
+ reset-names = "i2c";
+};
+
+&memclkmgr {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc {
+ resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
+&rst {
+ compatible = "altr,rst-mgr";
+ altr,modrst-offset = <0x20>;
+ u-boot,dm-pre-reloc;
+};
+
+&sdr {
+ compatible = "intel,sdr-ctl-dm";
+ resets = <&rst DDRSCH_RESET>;
+ clocks = <&memclkmgr>;
+ clock-names = "mem_clk";
+ u-boot,dm-pre-reloc;
+};
+
+&sysmgr {
+ compatible = "altr,sys-mgr", "syscon";
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&watchdog0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_dm.dtsi b/arch/arm/dts/socfpga_dm.dtsi
new file mode 100644
index 0000000000..49de6f4a5c
--- /dev/null
+++ b/arch/arm/dts/socfpga_dm.dtsi
@@ -0,0 +1,640 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Intel Corporation
+ */
+
+/dts-v1/;
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/dm-clock.h>
+
+/ {
+ compatible = "intel,socfpga-dm";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ service_reserved: svcbuffer@0 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x0 0x0 0x1000000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x3>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 170 4>,
+ <0 171 4>,
+ <0 172 4>,
+ <0 173 4>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
+ interrupt-parent = <&intc>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ intc: intc@fffc1000 {
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0xfffc1000 0x0 0x1000>,
+ <0x0 0xfffc2000 0x0 0x2000>,
+ <0x0 0xfffc4000 0x0 0x2000>,
+ <0x0 0xfffc6000 0x0 0x2000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ device_type = "soc";
+ interrupt-parent = <&intc>;
+ ranges = <0 0 0 0xffffffff>;
+
+ base_fpga_region {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "fpga-region";
+ fpga-mgr = <&fpga_mgr>;
+ };
+
+ clkmgr: clock-controller@ffd10000 {
+ compatible = "intel,dm-clkmgr";
+ reg = <0xffd10000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clocks {
+ cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ cb_intosc_ls_clk: cb-intosc-ls-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ f2s_free_clk: f2s-free-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ dram_eosc_clk: dram-eosc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ osc1: osc1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ qspi_clk: qspi-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+ gmac0: ethernet@ff800000 {
+ compatible = "altr,socfpga-stmmac",
+ "snps,dwmac-3.74a",
+ "snps,dwmac";
+ reg = <0xff800000 0x2000>;
+ interrupts = <0 90 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ tx-fifo-depth = <16384>;
+ rx-fifo-depth = <16384>;
+ snps,multicast-filter-bins = <256>;
+ iommus = <&smmu 1>;
+ altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+ clocks = <&clkmgr DM_EMAC0_CLK>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gmac1: ethernet@ff802000 {
+ compatible = "altr,socfpga-stmmac",
+ "snps,dwmac-3.74a",
+ "snps,dwmac";
+ reg = <0xff802000 0x2000>;
+ interrupts = <0 91 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ tx-fifo-depth = <16384>;
+ rx-fifo-depth = <16384>;
+ snps,multicast-filter-bins = <256>;
+ iommus = <&smmu 2>;
+ altr,sysmgr-syscon = <&sysmgr 0x48 8>;
+ clocks = <&clkmgr DM_EMAC1_CLK>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gmac2: ethernet@ff804000 {
+ compatible = "altr,socfpga-stmmac",
+ "snps,dwmac-3.74a",
+ "snps,dwmac";
+ reg = <0xff804000 0x2000>;
+ interrupts = <0 92 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ tx-fifo-depth = <16384>;
+ rx-fifo-depth = <16384>;
+ snps,multicast-filter-bins = <256>;
+ iommus = <&smmu 3>;
+ altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
+ clocks = <&clkmgr DM_EMAC2_CLK>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gpio0: gpio@ffc03200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xffc03200 0x100>;
+ resets = <&rst GPIO0_RESET>;
+ status = "disabled";
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <24>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 110 4>;
+ };
+ };
+
+ gpio1: gpio@ffc03300 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xffc03300 0x100>;
+ resets = <&rst GPIO1_RESET>;
+ status = "disabled";
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <24>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 111 4>;
+ };
+ };
+
+ i2c0: i2c@ffc02800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc02800 0x100>;
+ interrupts = <0 103 4>;
+ resets = <&rst I2C0_RESET>;
+ clocks = <&clkmgr DM_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@ffc02900 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc02900 0x100>;
+ interrupts = <0 104 4>;
+ resets = <&rst I2C1_RESET>;
+ clocks = <&clkmgr DM_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ffc02a00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc02a00 0x100>;
+ interrupts = <0 105 4>;
+ resets = <&rst I2C2_RESET>;
+ clocks = <&clkmgr DM_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ffc02b00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc02b00 0x100>;
+ interrupts = <0 106 4>;
+ resets = <&rst I2C3_RESET>;
+ clocks = <&clkmgr DM_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@ffc02c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc02c00 0x100>;
+ interrupts = <0 107 4>;
+ resets = <&rst I2C4_RESET>;
+ clocks = <&clkmgr DM_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ memclkmgr: mem-clock-controller@f8040000 {
+ compatible = "intel,dm-mem-clkmgr";
+ reg = <0xf8040000 0x1000>;
+ #clock-cells = <0>;
+ clocks = <&dram_eosc_clk>, <&f2s_free_clk>;
+ };
+
+ mmc: dwmmc0@ff808000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "altr,socfpga-dw-mshc";
+ reg = <0xff808000 0x1000>;
+ interrupts = <0 96 4>;
+ fifo-depth = <0x400>;
+ resets = <&rst SDMMC_RESET>;
+ reset-names = "reset";
+ clocks = <&clkmgr DM_L4_MP_CLK>,
+ <&clkmgr DM_SDMMC_CLK>;
+ clock-names = "biu", "ciu";
+ iommus = <&smmu 5>;
+ status = "disabled";
+ };
+
+ nand: nand@ffb90000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "altr,socfpga-denali-nand";
+ reg = <0xffb90000 0x10000>,
+ <0xffb80000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ interrupts = <0 97 4>;
+ resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
+ status = "disabled";
+ };
+
+ ocram: sram@ffe00000 {
+ compatible = "mmio-sram";
+ reg = <0xffe00000 0x40000>;
+ };
+
+ pdma: pdma@ffda0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xffda0000 0x1000>;
+ interrupts = <0 81 4>,
+ <0 82 4>,
+ <0 83 4>,
+ <0 84 4>,
+ <0 85 4>,
+ <0 86 4>,
+ <0 87 4>,
+ <0 88 4>,
+ <0 89 4>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
+ reset-names = "dma", "dma-ocp";
+ clocks = <&clkmgr DM_L4_MAIN_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ rst: rstmgr@ffd11000 {
+ #reset-cells = <1>;
+ compatible = "altr,rst-mgr";
+ reg = <0xffd11000 0x100>;
+ };
+
+ smmu: iommu@fa000000 {
+ compatible = "arm,mmu-500", "arm,smmu-v2";
+ reg = <0xfa000000 0x40000>;
+ #global-interrupts = <2>;
+ #iommu-cells = <1>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 128 4>, /* Global Secure Fault */
+ <0 129 4>, /* Global Non-secure Fault */
+ /* Non-secure Context Interrupts (32) */
+ <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
+ <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
+ <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
+ <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
+ <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
+ <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
+ <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
+ <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
+ stream-match-mask = <0x7ff0>;
+ status = "disabled";
+ };
+
+ spi0: spi@ffda4000 {
+ compatible = "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xffda4000 0x1000>;
+ interrupts = <0 99 4>;
+ resets = <&rst SPIM0_RESET>;
+ reg-io-width = <4>;
+ num-cs = <4>;
+ clocks = <&clkmgr DM_L4_MAIN_CLK>;
+ status = "disabled";
+ };
+
+ spi1: spi@ffda5000 {
+ compatible = "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xffda5000 0x1000>;
+ interrupts = <0 100 4>;
+ resets = <&rst SPIM1_RESET>;
+ reg-io-width = <4>;
+ num-cs = <4>;
+ clocks = <&clkmgr DM_L4_MAIN_CLK>;
+ status = "disabled";
+ };
+
+ sysmgr: sysmgr@ffd12000 {
+ compatible = "altr,sys-mgr-s10","altr,sys-mgr";
+ reg = <0xffd12000 0x500>;
+ };
+
+ /* Local timer */
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ timer0: timer0@ffc03000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 113 4>;
+ reg = <0xffc03000 0x100>;
+ clocks = <&clkmgr DM_L4_SP_CLK>;
+ clock-names = "timer";
+ };
+
+ timer1: timer1@ffc03100 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 114 4>;
+ reg = <0xffc03100 0x100>;
+ clocks = <&clkmgr DM_L4_SP_CLK>;
+ clock-names = "timer";
+ };
+
+ timer2: timer2@ffd00000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 115 4>;
+ reg = <0xffd00000 0x100>;
+ clocks = <&clkmgr DM_L4_SP_CLK>;
+ clock-names = "timer";
+ };
+
+ timer3: timer3@ffd00100 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 116 4>;
+ reg = <0xffd00100 0x100>;
+ clocks = <&clkmgr DM_L4_SP_CLK>;
+ clock-names = "timer";
+ };
+
+ uart0: serial0@ffc02000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xffc02000 0x100>;
+ interrupts = <0 108 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&rst UART0_RESET>;
+ status = "disabled";
+ clocks = <&clkmgr DM_L4_SP_CLK>;
+ clock-frequency = <100000000>;
+ };
+
+ uart1: serial1@ffc02100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xffc02100 0x100>;
+ interrupts = <0 109 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&rst UART1_RESET>;
+ clocks = <&clkmgr DM_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ usbphy0: usbphy@0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ status = "okay";
+ };
+
+ usb0: usb@ffb00000 {
+ compatible = "snps,dwc2";
+ reg = <0xffb00000 0x40000>;
+ interrupts = <0 93 4>;
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
+ reset-names = "dwc2", "dwc2-ecc";
+ clocks = <&clkmgr DM_USB_CLK>;
+ iommus = <&smmu 6>;
+ status = "disabled";
+ };
+
+ usb1: usb@ffb40000 {
+ compatible = "snps,dwc2";
+ reg = <0xffb40000 0x40000>;
+ interrupts = <0 94 4>;
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+ reset-names = "dwc2", "dwc2-ecc";
+ iommus = <&smmu 7>;
+ clocks = <&clkmgr DM_USB_CLK>;
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@ffd00200 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd00200 0x100>;
+ interrupts = <0 117 4>;
+ resets = <&rst WATCHDOG0_RESET>;
+ clocks = <&clkmgr DM_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog1: watchdog@ffd00300 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd00300 0x100>;
+ interrupts = <0 118 4>;
+ resets = <&rst WATCHDOG1_RESET>;
+ clocks = <&clkmgr DM_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog2: watchdog@ffd00400 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd00400 0x100>;
+ interrupts = <0 125 4>;
+ resets = <&rst WATCHDOG2_RESET>;
+ clocks = <&clkmgr DM_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog3: watchdog@ffd00500 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd00500 0x100>;
+ interrupts = <0 126 4>;
+ resets = <&rst WATCHDOG3_RESET>;
+ clocks = <&clkmgr DM_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ sdr: sdr@f8011100 {
+ compatible = "altr,sdr-ctl", "syscon";
+ reg = <0xf8011100 0xc0>;
+ };
+
+ eccmgr {
+ compatible = "altr,socfpga-s10-ecc-manager",
+ "altr,socfpga-a10-ecc-manager";
+ altr,sysmgr-syscon = <&sysmgr>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <0 15 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ranges;
+
+ sdramedac {
+ compatible = "altr,sdram-edac-s10";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <16 4>;
+ };
+
+ ocram-ecc@ff8cc000 {
+ compatible = "altr,socfpga-s10-ocram-ecc",
+ "altr,socfpga-a10-ocram-ecc";
+ reg = <0xff8cc000 0x100>;
+ altr,ecc-parent = <&ocram>;
+ interrupts = <1 4>;
+ };
+
+ usb0-ecc@ff8c4000 {
+ compatible = "altr,socfpga-s10-usb-ecc",
+ "altr,socfpga-usb-ecc";
+ reg = <0xff8c4000 0x100>;
+ altr,ecc-parent = <&usb0>;
+ interrupts = <2 4>;
+ };
+
+ emac0-rx-ecc@ff8c0000 {
+ compatible = "altr,socfpga-s10-eth-mac-ecc",
+ "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0000 0x100>;
+ altr,ecc-parent = <&gmac0>;
+ interrupts = <4 4>;
+ };
+
+ emac0-tx-ecc@ff8c0400 {
+ compatible = "altr,socfpga-s10-eth-mac-ecc",
+ "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0400 0x100>;
+ altr,ecc-parent = <&gmac0>;
+ interrupts = <5 4>;
+ };
+
+ sdmmca-ecc@ff8c8c00 {
+ compatible = "altr,socfpga-s10-sdmmc-ecc",
+ "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c8c00 0x100>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <14 4>,
+ <15 4>;
+ };
+ };
+
+ qspi: spi@ff8d2000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff8d2000 0x100>,
+ <0xff900000 0x100000>;
+ interrupts = <0 3 4>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
+
+ status = "disabled";
+ };
+
+ firmware {
+ svc {
+ compatible = "intel,stratix10-svc";
+ method = "smc";
+ memory-region = <&service_reserved>;
+
+ fpga_mgr: fpga-mgr {
+ compatible = "intel,stratix10-soc-fpga-mgr";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
new file mode 100644
index 0000000000..9dbcaf2eb0
--- /dev/null
+++ b/arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ */
+
+#include "socfpga_dm-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = &qspi;
+ i2c0 = &i2c1;
+ };
+
+ memory {
+ /* 8GB */
+ reg = <0 0x00000000 0 0x80000000>,
+ <2 0x80000000 1 0x80000000>;
+ };
+};
+
+&flash0 {
+ compatible = "jedec,spi-nor";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&nand {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc {
+ drvsel = <3>;
+ smplsel = <0>;
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ status = "okay";
+};
+
+&watchdog0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_dm_socdk.dts b/arch/arm/dts/socfpga_dm_socdk.dts
new file mode 100644
index 0000000000..7db2c39867
--- /dev/null
+++ b/arch/arm/dts/socfpga_dm_socdk.dts
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Intel Corporation
+ */
+#include "socfpga_dm.dtsi"
+
+/ {
+ model = "SoCFPGA Diamond Mesa SoCDK";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:4800n8";
+ u-boot,boot0 = <&mmc>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ hps1 {
+ label = "hps_led1";
+ gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ hps2 {
+ label = "hps_led2";
+ gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+
+ soc {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+ };
+ };
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <4>;
+
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <900>; /* 0ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ };
+ };
+};
+
+&mmc {
+ status = "okay";
+ cap-sd-highspeed;
+ broken-cd;
+ bus-width = <4>;
+};
+
+&uart0 {
+ status = "okay";
+ clock-frequency = <76800>;
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ flash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mt25qu02g";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x034B0000>;
+ };
+
+ qspi_rootfs: partition@34B0000 {
+ label = "Root Filesystem - JFFS2";
+ reg = <0x034B0000 0x0EB50000>;
+ };
+ };
+ };
+};
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 8/9] configs: dm: Add Diamond Mesa CONFIGs
2022-09-18 12:17 [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Jit Loon Lim
` (5 preceding siblings ...)
2022-09-18 12:17 ` [PATCH 7/9] arm: dts: dm: Add base dtsi and devkit dts " Jit Loon Lim
@ 2022-09-18 12:17 ` Jit Loon Lim
2022-09-18 12:17 ` [PATCH 9/9] arm: socfpga: dm: Enable Intel Diamond Mesa bulid Jit Loon Lim
2022-09-28 17:14 ` [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Sean Anderson
8 siblings, 0 replies; 10+ messages in thread
From: Jit Loon Lim @ 2022-09-18 12:17 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Add CONFIGs for Diamond Mesa.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
include/configs/socfpga_dm_socdk.h | 50 ++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 include/configs/socfpga_dm_socdk.h
diff --git a/include/configs/socfpga_dm_socdk.h b/include/configs/socfpga_dm_socdk.h
new file mode 100644
index 0000000000..0adcbfd97e
--- /dev/null
+++ b/include/configs/socfpga_dm_socdk.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_DM_H__
+#define __CONFIG_SOCFGPA_DM_H__
+
+#include <configs/socfpga_soc64_common.h>
+
+#undef CONFIG_BOOTARGS
+#ifdef CONFIG_SOCFPGA_SECURE_VAB_AUTH
+#define CONFIG_BOOTARGS "earlycon panic=-1 mem=2048M"
+#else
+#define CONFIG_BOOTARGS "earlycon panic=-1 earlyprintk=ttyS0,4800"
+#endif
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
+ "fdt_addr=1100000\0" \
+ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@ff8d2000 status okay;" \
+ "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
+ " ${qspi_clock}; fi; \0" \
+ "scriptaddr=0x02100000\0" \
+ "scriptfile=u-boot.scr\0" \
+ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+ "then source ${scriptaddr}; fi\0"
+
+#endif /* __CONFIG_SOCFGPA_DM_H__ */
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 9/9] arm: socfpga: dm: Enable Intel Diamond Mesa bulid
2022-09-18 12:17 [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Jit Loon Lim
` (6 preceding siblings ...)
2022-09-18 12:17 ` [PATCH 8/9] configs: dm: Add Diamond Mesa CONFIGs Jit Loon Lim
@ 2022-09-18 12:17 ` Jit Loon Lim
2022-09-28 17:14 ` [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Sean Anderson
8 siblings, 0 replies; 10+ messages in thread
From: Jit Loon Lim @ 2022-09-18 12:17 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Enable build for Intel Diamond Mesa.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
arch/arm/mach-socfpga/Kconfig | 18 ++++++++
arch/arm/mach-socfpga/Makefile | 31 +++++++++++++
configs/socfpga_dm_atf_defconfig | 77 ++++++++++++++++++++++++++++++++
configs/socfpga_dm_defconfig | 62 +++++++++++++++++++++++++
configs/socfpga_dm_vab_defconfig | 77 ++++++++++++++++++++++++++++++++
5 files changed, 265 insertions(+)
create mode 100644 configs/socfpga_dm_atf_defconfig
create mode 100644 configs/socfpga_dm_defconfig
create mode 100644 configs/socfpga_dm_vab_defconfig
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index df44530e83..cc8fcc8a5d 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -81,6 +81,22 @@ config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
+config TARGET_SOCFPGA_DM
+ bool
+ select TARGET_SOCFPGA_SOC64
+ select ARMV8_MULTIENTRY
+ select ARMV8_SET_SMPEN
+ select BINMAN if SPL_ATF
+ select CLK
+ select FPGA_INTEL_SDM_MAILBOX
+ select NCORE_CACHE
+ select SPL_ALTERA_SDRAM
+ select SPL_CLK if SPL
+
+config TARGET_SOCFPGA_DM_SOCDK
+ bool "Intel SOCFPGA SoCDK (Diamond Mesa)"
+ select TARGET_SOCFPGA_DM
+
config TARGET_SOCFPGA_GEN5
bool
select SPL_ALTERA_SDRAM
@@ -209,6 +225,7 @@ config SYS_BOARD
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
+ default "dm-socdk" if TARGET_SOCFPGA_DM_SOCDK
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
@@ -253,6 +270,7 @@ config SYS_CONFIG_NAME
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
+ default "socfpga_dm_socdk" if TARGET_SOCFPGA_DM_SOCDK
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index ec38b64dd4..fab8ab579b 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -71,6 +71,32 @@ obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_DM
+obj-y += clock_manager_dm.o
+obj-y += lowlevel_init_soc64.o
+obj-y += mailbox_s10.o
+obj-y += misc_soc64.o
+obj-y += mmu-arm64_s10.o
+obj-y += reset_manager_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
+obj-y += smmu_s10.o
+obj-y += system_manager_soc64.o
+obj-y += timer_s10.o
+obj-y += wrap_handoff_soc64.o
+obj-y += wrap_pll_config_soc64.o
+ifndef CONFIG_SPL_BUILD
+obj-y += rsu.o
+obj-y += rsu_ll_qspi.o
+obj-y += rsu_misc.o
+obj-y += rsu_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o
+endif
+endif
+
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
@@ -95,6 +121,11 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_N5X
obj-y += spl_n5x.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_DM
+obj-y += firewall.o
+obj-y += spl_dm.o
+obj-y += spl_soc64.o
+endif
else
obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
obj-$(CONFIG_SPL_ATF) += smc_api.o
diff --git a/configs/socfpga_dm_atf_defconfig b/configs/socfpga_dm_atf_defconfig
new file mode 100644
index 0000000000..5673888e6f
--- /dev/null
+++ b/configs/socfpga_dm_atf_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_TARGET_SOCFPGA_DM_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_dm"
+CONFIG_SPL_FS_FAT=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_dm_socdk"
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon panic=-1"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run fatscript;run mmcload;run linux_qspi_enable;rsu dtb;run mmcboot"
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_DM # "
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_I2C is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_MTD is not set
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_USB is not set
+# CONFIG_CMD_DHCP is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_CMD_PING is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
+CONFIG_ENV_IS_NOWHERE=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_DWAPB_GPIO is not set
+# CONFIG_DM_I2C is not set
+# CONFIG_SYS_I2C_DW is not set
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_PANIC_HANG=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_BAUDRATE=4800
\ No newline at end of file
diff --git a/configs/socfpga_dm_defconfig b/configs/socfpga_dm_defconfig
new file mode 100644
index 0000000000..e37f5248e1
--- /dev/null
+++ b/configs/socfpga_dm_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x1000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_TARGET_SOCFPGA_DM_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_dm"
+CONFIG_SPL_FS_FAT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_ARMV8_PSCI=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_dm_socdk"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; rsu dtb; run mmcboot"
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_DM # "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=4800
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_PANIC_HANG=y
\ No newline at end of file
diff --git a/configs/socfpga_dm_vab_defconfig b/configs/socfpga_dm_vab_defconfig
new file mode 100644
index 0000000000..955b51aeee
--- /dev/null
+++ b/configs/socfpga_dm_vab_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
+CONFIG_DM_GPIO=y
+CONFIG_SOCFPGA_SECURE_VAB_AUTH=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_TARGET_SOCFPGA_DM_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_dm"
+CONFIG_SPL_FS_FAT=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_dm_socdk"
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run fatscript;run mmcfitload;run mmcfitboot"
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_DM # "
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_I2C is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_MTD is not set
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_USB is not set
+# CONFIG_CMD_DHCP is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_CMD_PING is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
+CONFIG_ENV_IS_NOWHERE=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_DWAPB_GPIO is not set
+# CONFIG_DM_I2C is not set
+# CONFIG_SYS_I2C_DW is not set
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_PANIC_HANG=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_BAUDRATE=4800
\ No newline at end of file
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa
2022-09-18 12:17 [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Jit Loon Lim
` (7 preceding siblings ...)
2022-09-18 12:17 ` [PATCH 9/9] arm: socfpga: dm: Enable Intel Diamond Mesa bulid Jit Loon Lim
@ 2022-09-28 17:14 ` Sean Anderson
8 siblings, 0 replies; 10+ messages in thread
From: Sean Anderson @ 2022-09-28 17:14 UTC (permalink / raw)
To: Jit Loon Lim, u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Sieu Mun Tang
On 9/18/22 08:17, Jit Loon Lim wrote:
> From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
>
> Add clock manager driver for Diamond Mesa. Provides clock
> initialization and get_rate functions.
It appears that you are doing a static configuration of the
clocks (with no provision for later modifying clocks). Can
you add some comments to the commit message regarding rates
for the major clocks and why you chose them?
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
> ---
> drivers/clk/altera/clk-dm.c | 504 +++++++++++++++++++++++++++
> drivers/clk/altera/clk-dm.h | 217 ++++++++++++
> include/dt-bindings/clock/dm-clock.h | 71 ++++
> 3 files changed, 792 insertions(+)
> create mode 100644 drivers/clk/altera/clk-dm.c
> create mode 100644 drivers/clk/altera/clk-dm.h
> create mode 100644 include/dt-bindings/clock/dm-clock.h
Please reconsider the prefix "DM" as it typically means "Driver
Model" in the rest of U-Boot. diamond_? dmesa_? diamesa_?
This commit also needs to add clk-dm.o to drivers/clk/altera/Makefile.
>
> diff --git a/drivers/clk/altera/clk-dm.c b/drivers/clk/altera/clk-dm.c
> new file mode 100644
> index 0000000000..1076240b41
> --- /dev/null
> +++ b/drivers/clk/altera/clk-dm.c
> @@ -0,0 +1,504 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation <www.intel.com>
Is this accurate?
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock_manager.h>
> +#include <asm/io.h>
> +#include <clk-uclass.h>
This should come after common.h.
> +#include <dm.h>
> +#include <dm/lists.h>
> +#include <dm/util.h>
> +#include <dt-bindings/clock/dm-clock.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct socfpga_clk_plat {
> + void __iomem *regs;
> +};
> +
> +/*
> + * function to write the bypass register which requires a poll of the
> + * busy bit
> + */
> +static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
> +{
> + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
> + cm_wait_for_fsm();
> +}
> +
> +static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
> +{
> + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
> + cm_wait_for_fsm();
> +}
> +
> +#ifndef CONFIG_TARGET_SOCFPGA_DM
> +/* function to write the ctrl register which requires a poll of the busy bit */
> +static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
> +{
> + CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
> + cm_wait_for_fsm();
> +}
> +#endif
You can define this unconditionally...
> +
> +/*
> + * Setup clocks while making no assumptions about previous state of the clocks.
> + */
> +static void clk_basic_init(struct udevice *dev,
> + const struct cm_config * const cfg)
> +{
> + struct socfpga_clk_plat *plat = dev_get_plat(dev);
> +
> + if (!cfg)
> + return;
> +
> +#ifndef CONFIG_TARGET_SOCFPGA_DM
> +#ifdef CONFIG_SPL_BUILD
> + /* Always force clock manager into boot mode before any configuration */
> + clk_write_ctrl(plat,
> + CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
> +#else
> + /* Skip clock configuration in SSBL if it's not in boot mode */
> + if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
> + return;
> +#endif
> +#endif
...and then use regular ifs here. e.g.
if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_DM)) {
if (spl_phase() == PHASE_SPL)
...
else
...
}
> +
> + /* Put both PLLs in bypass */
> + clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
> + clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
> +
> + /* Put both PLLs in Reset */
> + CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
> + CLKMGR_PLLCTRL_BYPASS_MASK);
> + CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
> + CLKMGR_PLLCTRL_BYPASS_MASK);
> +
> +#ifndef CONFIG_TARGET_SOCFPGA_DM
> + /* setup main PLL */
> + CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB);
> + CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV);
> + CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV);
> + CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
> + CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
> + CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
> +
> + /* setup peripheral */
> + CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB);
> + CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV);
> + CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV);
> + CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
> + CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
> +#endif
I think you can do the same kind of thing here.
That said, what other target are you planning to support? Can you document
it in the commit message or somewhere in the code?
> +
> + /* Take both PLL out of reset and power up */
> + CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
> + CLKMGR_PLLCTRL_BYPASS_MASK);
> + CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
> + CLKMGR_PLLCTRL_BYPASS_MASK);
> +
> + cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
> +
> +#ifndef CONFIG_TARGET_SOCFPGA_DM
> + CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
> + CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
> + CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
> + CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
> + CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
> + CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR);
> + CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR);
> + CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR);
> +#endif
> +
> + /* Configure ping pong counters in altera group */
> + CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
> + CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
> +
> + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |
> + CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
> + CLKMGR_MAINPLL_PLLGLOB);
> + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |
> + CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
> + CLKMGR_PERPLL_PLLGLOB);
> +
> + /* Take all PLLs out of bypass */
> + clk_write_bypass_mainpll(plat, 0);
> + clk_write_bypass_perpll(plat, 0);
> +
> + /* Clear the loss of lock bits (write 1 to clear) */
> + CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
> + CLKMGR_INTER_PERPLLLOST_MASK |
> + CLKMGR_INTER_MAINPLLLOST_MASK);
> +
> + /* Take all ping pong counters out of reset */
> + CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
> + CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK);
> +
> +#ifndef CONFIG_TARGET_SOCFPGA_DM
> + /* Out of boot mode */
> + clk_write_ctrl(plat,
> + CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
> +#endif
> +}
> +
> +static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u32 reg)
> +{
> + u32 clksrc = CM_REG_READL(plat, reg);
> +
> + return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
> +}
> +
> +static u64 clk_get_pll_output_hz(struct socfpga_clk_plat *plat,
> + u32 pllglob_reg, u32 plldiv_reg)
As a general note, I would expect this to be named something like
dm_pll_get_rate()
(using your existing dm_ prefix), since it is implicit that all rates are in Hz.
> +{
> + u64 clock = 0;
> + u32 clklsrc, divf, divr, divq, power = 1;
> +
> + /* Get input clock frequency */
> + clklsrc = (CM_REG_READL(plat, pllglob_reg) &
> + CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
> + CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
> +
> + switch (clklsrc) {
> + case CLKMGR_VCO_PSRC_EOSC1:
> + clock = cm_get_osc_clk_hz();
> + break;
> + case CLKMGR_VCO_PSRC_INTOSC:
> + clock = cm_get_intosc_clk_hz();
> + break;
> + case CLKMGR_VCO_PSRC_F2S:
> + clock = cm_get_fpga_clk_hz();
> + break;
> + }
> +
> + /* Calculate pll out clock frequency */
> + divf = (CM_REG_READL(plat, plldiv_reg) &
> + CLKMGR_PLLDIV_FDIV_MASK) >>
> + CLKMGR_PLLDIV_FDIV_OFFSET;
> +
> + divr = (CM_REG_READL(plat, plldiv_reg) &
> + CLKMGR_PLLDIV_REFCLKDIV_MASK) >>
> + CLKMGR_PLLDIV_REFCLKDIV_OFFSET;
> +
> + divq = (CM_REG_READL(plat, plldiv_reg) &
> + CLKMGR_PLLDIV_OUTDIV_QDIV_MASK) >>
> + CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET;
> +
> + while (divq) {
> + power *= 2;
> + divq--;
> + }
> +
> + return ((clock * 2 * (divf + 1)) / ((divr + 1) * power));
> +}
> +
> +static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg,
> + u32 main_div, u32 per_div)
> +{
> + u64 clock = 0;
> + u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
> +
> + switch (clklsrc) {
> + case CLKMGR_CLKSRC_MAIN:
> + clock = clk_get_pll_output_hz(plat,
> + CLKMGR_MAINPLL_PLLGLOB,
> + CLKMGR_MAINPLL_PLLDIV);
> + clock /= 1 + main_div;
> + break;
> +
> + case CLKMGR_CLKSRC_PER:
> + clock = clk_get_pll_output_hz(plat,
> + CLKMGR_PERPLL_PLLGLOB,
> + CLKMGR_PERPLL_PLLDIV);
> + clock /= 1 + per_div;
> + break;
> +
> + case CLKMGR_CLKSRC_OSC1:
> + clock = cm_get_osc_clk_hz();
> + break;
> +
> + case CLKMGR_CLKSRC_INTOSC:
> + clock = cm_get_intosc_clk_hz();
> + break;
> +
> + case CLKMGR_CLKSRC_FPGA:
> + clock = cm_get_fpga_clk_hz();
> + break;
> + default:
> + return 0;
> + }
> +
> + return clock;
> +}
> +
> +static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + u32 mainpll_c0cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
> + CLKMGR_PLLOUTDIV_C0CNT_MASK) >>
> + CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
> +
> + u32 perpll_c0cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
> + CLKMGR_PLLOUTDIV_C0CNT_MASK) >>
> + CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
> +
> + u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
> + mainpll_c0cnt, perpll_c0cnt);
> +
> + clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
> + CLKMGR_CLKCNT_MSK);
> +
> + return clock;
> +}
> +
> +static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + u32 mainpll_c1cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
> + CLKMGR_PLLOUTDIV_C1CNT_MASK) >>
> + CLKMGR_PLLOUTDIV_C1CNT_OFFSET;
> +
> + u32 perpll_c1cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
> + CLKMGR_PLLOUTDIV_C1CNT_MASK) >>
> + CLKMGR_PLLOUTDIV_C1CNT_OFFSET;
> +
> + return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
> + mainpll_c1cnt, perpll_c1cnt);
> +}
> +
> +static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + u64 clock = clk_get_l3_main_clk_hz(plat);
> +
> + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
> + CLKMGR_NOCDIV_L4MAIN_OFFSET) &
> + CLKMGR_NOCDIV_DIVIDER_MASK);
> +
> + return clock;
> +}
> +
> +static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + u32 mainpll_c3cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
> + CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
> + CLKMGR_PLLOUTDIV_C3CNT_OFFSET;
> +
> + u32 perpll_c3cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
> + CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
> + CLKMGR_PLLOUTDIV_C3CNT_OFFSET;
> +
> + u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
> + mainpll_c3cnt, perpll_c3cnt);
> +
> + clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) &
> + CLKMGR_CLKCNT_MSK);
> +
> + return clock / 4;
> +}
> +
> +#ifndef CONFIG_TARGET_SOCFPGA_DM
> +static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + u64 clock = clk_get_l3_main_clk_hz(plat);
> +
> + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
> + CLKMGR_NOCDIV_DIVIDER_MASK);
> +
> + return clock;
> +}
> +#endif
> +
> +static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + u64 clock = clk_get_l3_main_clk_hz(plat);
> +
> + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
> + CLKMGR_NOCDIV_L4MPCLK_OFFSET) &
> + CLKMGR_NOCDIV_DIVIDER_MASK);
> +
> + return clock;
> +}
> +
> +static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
> + return clk_get_l3_main_clk_hz(plat) / 2;
> +
> + return clk_get_l3_main_clk_hz(plat) / 4;
> +}
> +
> +static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
> +{
> + bool emacsel_a;
> + u32 ctl;
> + u32 ctr_reg;
> + u32 clock;
> + u32 div;
> + u32 reg;
> +
> + /* Get EMAC clock source */
> + ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
> + if (emac_id == DM_EMAC0_CLK)
> + ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
> + CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
> + else if (emac_id == DM_EMAC1_CLK)
> + ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
> + CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
> + else if (emac_id == DM_EMAC2_CLK)
> + ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
> + CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
> + else
> + return 0;
> +
> + if (ctl) {
> + /* EMAC B source */
> + emacsel_a = false;
> + ctr_reg = CLKMGR_ALTR_EMACBCTR;
> + } else {
> + /* EMAC A source */
> + emacsel_a = true;
> + ctr_reg = CLKMGR_ALTR_EMACACTR;
> + }
> +
> + reg = CM_REG_READL(plat, ctr_reg);
> + clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK)
> + >> CLKMGR_ALT_EMACCTR_SRC_OFFSET;
> + div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK)
> + >> CLKMGR_ALT_EMACCTR_CNT_OFFSET;
> +
> + switch (clock) {
> + case CLKMGR_CLKSRC_MAIN:
> + clock = clk_get_pll_output_hz(plat,
> + CLKMGR_MAINPLL_PLLGLOB,
> + CLKMGR_MAINPLL_PLLDIV);
> +
> + if (emacsel_a) {
> + clock /= 1 + ((CM_REG_READL(plat,
> + CLKMGR_MAINPLL_PLLOUTDIV) &
> + CLKMGR_PLLOUTDIV_C2CNT_MASK) >>
> + CLKMGR_PLLOUTDIV_C2CNT_OFFSET);
> + } else {
> + clock /= 1 + ((CM_REG_READL(plat,
> + CLKMGR_MAINPLL_PLLOUTDIV) &
> + CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
> + CLKMGR_PLLOUTDIV_C3CNT_OFFSET);
> + }
> + break;
> +
> + case CLKMGR_CLKSRC_PER:
> + clock = clk_get_pll_output_hz(plat,
> + CLKMGR_PERPLL_PLLGLOB,
> + CLKMGR_PERPLL_PLLDIV);
> + if (emacsel_a) {
> + clock /= 1 + ((CM_REG_READL(plat,
> + CLKMGR_PERPLL_PLLOUTDIV) &
> + CLKMGR_PLLOUTDIV_C2CNT_MASK) >>
> + CLKMGR_PLLOUTDIV_C2CNT_OFFSET);
> + } else {
> + clock /= 1 + ((CM_REG_READL(plat,
> + CLKMGR_PERPLL_PLLOUTDIV) &
> + CLKMGR_PLLOUTDIV_C3CNT_MASK >>
> + CLKMGR_PLLOUTDIV_C3CNT_OFFSET));
> + }
> + break;
> +
> + case CLKMGR_CLKSRC_OSC1:
> + clock = cm_get_osc_clk_hz();
> + break;
> +
> + case CLKMGR_CLKSRC_INTOSC:
> + clock = cm_get_intosc_clk_hz();
> + break;
> +
> + case CLKMGR_CLKSRC_FPGA:
> + clock = cm_get_fpga_clk_hz();
> + break;
> + }
> +
> + clock /= 1 + div;
> +
> + return clock;
> +}
> +
> +static ulong socfpga_clk_get_rate(struct clk *clk)
> +{
> + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
> +
> + switch (clk->id) {
> + case DM_MPU_CLK:
> + return clk_get_mpu_clk_hz(plat);
> + case DM_L4_MAIN_CLK:
> + return clk_get_l4_main_clk_hz(plat);
> + case DM_L4_SYS_FREE_CLK:
> + return clk_get_l4_sys_free_clk_hz(plat);
> + case DM_L4_MP_CLK:
> + return clk_get_l4_mp_clk_hz(plat);
> + case DM_L4_SP_CLK:
> +#ifndef CONFIG_TARGET_SOCFPGA_DM
> + return clk_get_l4_sp_clk_hz(plat);
> +#else
> + return 76800;
> +#endif
> + case DM_SDMMC_CLK:
> + return clk_get_sdmmc_clk_hz(plat);
> + case DM_EMAC0_CLK:
> + case DM_EMAC1_CLK:
> + case DM_EMAC2_CLK:
> + return clk_get_emac_clk_hz(plat, clk->id);
> + case DM_USB_CLK:
> + case DM_NAND_X_CLK:
> + return clk_get_l4_mp_clk_hz(plat);
> + case DM_NAND_CLK:
> + return clk_get_l4_mp_clk_hz(plat) / 4;
> + default:
> + return -ENXIO;
ENOENT please
> + }
> +}
> +
> +static int socfpga_clk_enable(struct clk *clk)
> +{
> + return 0;
> +}
> +
> +static int socfpga_clk_probe(struct udevice *dev)
> +{
> + const struct cm_config *cm_default_cfg = cm_get_default_config();
> +
> + clk_basic_init(dev, cm_default_cfg);
> +
> + return 0;
> +}
> +
> +static int socfpga_clk_of_to_plat(struct udevice *dev)
> +{
> + struct socfpga_clk_plat *plat = dev_get_plat(dev);
> + fdt_addr_t addr;
> +
> + addr = devfdt_get_addr(dev);
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> + plat->regs = (void __iomem *)addr;
> +
> + return 0;
> +}
> +
> +static struct clk_ops socfpga_clk_ops = {
> + .enable = socfpga_clk_enable,
> + .get_rate = socfpga_clk_get_rate,
> +};
> +
> +static const struct udevice_id socfpga_clk_match[] = {
> + { .compatible = "intel,dm-clkmgr" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(socfpga_dm_clk) = {
> + .name = "clk-dm",
> + .id = UCLASS_CLK,
> + .of_match = socfpga_clk_match,
> + .ops = &socfpga_clk_ops,
> + .probe = socfpga_clk_probe,
> + .of_to_plat = socfpga_clk_of_to_plat,
> + .plat_auto = sizeof(struct socfpga_clk_plat),
> +};
> diff --git a/drivers/clk/altera/clk-dm.h b/drivers/clk/altera/clk-dm.h
> new file mode 100644
> index 0000000000..89d3a92a34
> --- /dev/null
> +++ b/drivers/clk/altera/clk-dm.h
> @@ -0,0 +1,217 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020 Intel Corporation <www.intel.com>
> + */
> +
> +#ifndef _CLK_DM_
> +#define _CLK_DM_
> +
> +#ifndef __ASSEMBLY__
> +#include <linux/bitops.h>
> +#endif
> +
> +#define CM_REG_READL(plat, reg) \
> + readl((plat)->regs + (reg))
> +
> +#define CM_REG_WRITEL(plat, data, reg) \
> + writel(data, (plat)->regs + (reg))
> +
> +#define CM_REG_CLRBITS(plat, reg, clear) \
> + clrbits_le32((plat)->regs + (reg), (clear))
> +
> +#define CM_REG_SETBITS(plat, reg, set) \
> + setbits_le32((plat)->regs + (reg), (set))
Can you use inline functions here instead?
> +struct cm_config {
> + /* main group */
> + u32 main_pll_mpuclk;
> + u32 main_pll_nocclk;
> + u32 main_pll_nocdiv;
> + u32 main_pll_pllglob;
> + u32 main_pll_plldiv;
> + u32 main_pll_plloutdiv;
> + u32 spare_1[4];
Are these reserved fields? If so, please name them as such.
> +
> + /* peripheral group */
> + u32 per_pll_emacctl;
> + u32 per_pll_gpiodiv;
> + u32 per_pll_pllglob;
> + u32 per_pll_plldiv;
> + u32 per_pll_plloutdiv;
> + u32 spare_2[4];
> +
> + /* altera group */
> + u32 alt_emacactr;
> + u32 alt_emacbctr;
> + u32 alt_emacptpctr;
> + u32 alt_gpiodbctr;
> + u32 alt_sdmmcctr;
> + u32 alt_s2fuser0ctr;
> + u32 alt_s2fuser1ctr;
> + u32 alt_psirefctr;
> +
> + /* incoming clock */
> + u32 hps_osc_clk_hz;
> + u32 fpga_clk_hz;
> + u32 spare_3[3];
> +
> + /* memory clock group */
> + u32 mem_memdiv;
> + u32 mem_pllglob;
> + u32 mem_plldiv;
> + u32 mem_plloutdiv;
> + u32 spare_4[4];
> +};
> +
> +/* Clock Manager registers */
> +#define CLKMGR_CTRL 0
> +#define CLKMGR_STAT 4
> +#define CLKMGR_TESTIOCTRL 8
> +#define CLKMGR_INTRGEN 0x0c
> +#define CLKMGR_INTRMSK 0x10
> +#define CLKMGR_INTRCLR 0x14
> +#define CLKMGR_INTRSTS 0x18
> +#define CLKMGR_INTRSTK 0x1c
> +#define CLKMGR_INTRRAW 0x20
> +
> +/* Clock Manager Main PPL group registers */
> +#define CLKMGR_MAINPLL_EN 0x24
> +#define CLKMGR_MAINPLL_ENS 0x28
> +#define CLKMGR_MAINPLL_ENR 0x2c
> +#define CLKMGR_MAINPLL_BYPASS 0x30
> +#define CLKMGR_MAINPLL_BYPASSS 0x34
> +#define CLKMGR_MAINPLL_BYPASSR 0x38
> +#define CLKMGR_MAINPLL_MPUCLK 0x3c
> +#define CLKMGR_MAINPLL_NOCCLK 0x40
> +#define CLKMGR_MAINPLL_NOCDIV 0x44
> +#define CLKMGR_MAINPLL_PLLGLOB 0x48
> +#define CLKMGR_MAINPLL_PLLCTRL 0x4c
> +#define CLKMGR_MAINPLL_PLLDIV 0x50
> +#define CLKMGR_MAINPLL_PLLOUTDIV 0x54
> +#define CLKMGR_MAINPLL_LOSTLOCK 0x58
> +
> +/* Clock Manager Peripheral PPL group registers */
> +#define CLKMGR_PERPLL_EN 0x7c
> +#define CLKMGR_PERPLL_ENS 0x80
> +#define CLKMGR_PERPLL_ENR 0x84
> +#define CLKMGR_PERPLL_BYPASS 0x88
> +#define CLKMGR_PERPLL_BYPASSS 0x8c
> +#define CLKMGR_PERPLL_BYPASSR 0x90
> +#define CLKMGR_PERPLL_EMACCTL 0x94
> +#define CLKMGR_PERPLL_GPIODIV 0x98
> +#define CLKMGR_PERPLL_PLLGLOB 0x9c
> +#define CLKMGR_PERPLL_PLLCTRL 0xa0
> +#define CLKMGR_PERPLL_PLLDIV 0xa4
> +#define CLKMGR_PERPLL_PLLOUTDIV 0xa8
> +#define CLKMGR_PERPLL_LOSTLOCK 0xac
> +
> +/* Clock Manager Altera group registers */
> +#define CLKMGR_ALTR_EMACACTR 0xd4
> +#define CLKMGR_ALTR_EMACBCTR 0xd8
> +#define CLKMGR_ALTR_EMACPTPCTR 0xdc
> +#define CLKMGR_ALTR_GPIODBCTR 0xe0
> +#define CLKMGR_ALTR_SDMMCCTR 0xe4
> +#define CLKMGR_ALTR_S2FUSER0CTR 0xe8
> +#define CLKMGR_ALTR_S2FUSER1CTR 0xec
> +#define CLKMGR_ALTR_PSIREFCTR 0xf0
> +#define CLKMGR_ALTR_EXTCNTRST 0xf4
> +
> +#define CLKMGR_CTRL_BOOTMODE BIT(0)
> +
> +#define CLKMGR_STAT_BUSY BIT(0)
> +#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
> +#define CLKMGR_STAT_MAIN_TRANS BIT(9)
> +#define CLKMGR_STAT_PERPLL_LOCKED BIT(16)
> +#define CLKMGR_STAT_PERF_TRANS BIT(17)
> +#define CLKMGR_STAT_BOOTMODE BIT(24)
> +#define CLKMGR_STAT_BOOTCLKSRC BIT(25)
> +
> +#define CLKMGR_STAT_ALLPLL_LOCKED_MASK \
> + (CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED)
> +
> +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
> +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
> +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
> +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
BIT()?
> +#define CLKMGR_CLKSRC_MASK GENMASK(18, 16)
> +#define CLKMGR_CLKSRC_OFFSET 16
> +#define CLKMGR_CLKSRC_MAIN 0
> +#define CLKMGR_CLKSRC_PER 1
> +#define CLKMGR_CLKSRC_OSC1 2
> +#define CLKMGR_CLKSRC_INTOSC 3
> +#define CLKMGR_CLKSRC_FPGA 4
> +#define CLKMGR_CLKCNT_MSK GENMASK(10, 0)
> +
> +#define CLKMGR_BYPASS_MAINPLL_ALL 0x7
> +#define CLKMGR_BYPASS_PERPLL_ALL 0x7f
GENMASK()?
> +#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
> +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
> +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
> +#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
> +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
> +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
> +#define CLKMGR_NOCDIV_DIVIDER_MASK 0x3
> +
> +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16)
> +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
> +#define CLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASK BIT(28)
> +#define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29)
> +
> +#define CLKMGR_VCO_PSRC_EOSC1 0
> +#define CLKMGR_VCO_PSRC_INTOSC 1
> +#define CLKMGR_VCO_PSRC_F2S 2
> +
> +#define CLKMGR_PLLCTRL_BYPASS_MASK BIT(0)
> +#define CLKMGR_PLLCTRL_RST_N_MASK BIT(1)
> +
> +#define CLKMGR_PLLDIV_REFCLKDIV_MASK GENMASK(5, 0)
> +#define CLKMGR_PLLDIV_FDIV_MASK GENMASK(16, 8)
> +#define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24)
> +#define CLKMGR_PLLDIV_RANGE_MASK GENMASK(30, 28)
> +
> +#define CLKMGR_PLLDIV_REFCLKDIV_OFFSET 0
> +#define CLKMGR_PLLDIV_FDIV_OFFSET 8
> +#define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24
> +#define CLKMGR_PLLDIV_RANGE_OFFSET 28
> +
> +#define CLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0)
> +#define CLKMGR_PLLOUTDIV_C1CNT_MASK GENMASK(12, 8)
> +#define CLKMGR_PLLOUTDIV_C2CNT_MASK GENMASK(20, 16)
> +#define CLKMGR_PLLOUTDIV_C3CNT_MASK GENMASK(28, 24)
> +
> +#define CLKMGR_PLLOUTDIV_C0CNT_OFFSET 0
> +#define CLKMGR_PLLOUTDIV_C1CNT_OFFSET 8
> +#define CLKMGR_PLLOUTDIV_C2CNT_OFFSET 16
> +#define CLKMGR_PLLOUTDIV_C3CNT_OFFSET 24
> +
> +#define CLKMGR_PLLCX_EN_SET_MSK BIT(27)
> +#define CLKMGR_PLLCX_MUTE_SET_MSK BIT(28)
> +
> +#define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16)
> +#define CLKMGR_VCOCALIB_MSCNT_OFFSET 16
> +#define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0)
> +#define CLKMGR_VCOCALIB_MSCNT_CONST 100
> +#define CLKMGR_VCOCALIB_HSCNT_CONST 4
> +
> +#define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0)
> +
> +#define CLKMGR_LOSTLOCK_SET_MASK BIT(0)
> +
> +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
> +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26
> +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26)
> +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27
> +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK BIT(27)
> +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET 28
> +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK BIT(28)
> +
> +#define CLKMGR_ALT_EMACCTR_SRC_OFFSET 16
> +#define CLKMGR_ALT_EMACCTR_SRC_MASK GENMASK(18, 16)
> +#define CLKMGR_ALT_EMACCTR_CNT_OFFSET 0
> +#define CLKMGR_ALT_EMACCTR_CNT_MASK GENMASK(10, 0)
> +
> +#define CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK GENMASK(15, 0)
> +
> +#endif /* _CLK_DM_ */
> diff --git a/include/dt-bindings/clock/dm-clock.h b/include/dt-bindings/clock/dm-clock.h
> new file mode 100644
> index 0000000000..d624ac723c
> --- /dev/null
> +++ b/include/dt-bindings/clock/dm-clock.h
> @@ -0,0 +1,71 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020, Intel Corporation
> + */
> +
> +#ifndef __DM_CLOCK_H
> +#define __DM_CLOCK_H
> +
> +/* fixed rate clocks */
> +#define DM_OSC1 0
> +#define DM_CB_INTOSC_HS_DIV2_CLK 1
> +#define DM_CB_INTOSC_LS_CLK 2
> +#define DM_L4_SYS_FREE_CLK 3
> +#define DM_F2S_FREE_CLK 4
> +
> +/* PLL clocks */
> +#define DM_MAIN_PLL_CLK 5
> +#define DM_MAIN_PLL_C0_CLK 6
> +#define DM_MAIN_PLL_C1_CLK 7
> +#define DM_MAIN_PLL_C2_CLK 8
> +#define DM_MAIN_PLL_C3_CLK 9
> +#define DM_PERIPH_PLL_CLK 10
> +#define DM_PERIPH_PLL_C0_CLK 11
> +#define DM_PERIPH_PLL_C1_CLK 12
> +#define DM_PERIPH_PLL_C2_CLK 13
> +#define DM_PERIPH_PLL_C3_CLK 14
> +#define DM_MPU_FREE_CLK 15
> +#define DM_MPU_CCU_CLK 16
> +#define DM_BOOT_CLK 17
> +
> +/* fixed factor clocks */
> +#define DM_L3_MAIN_FREE_CLK 18
> +#define DM_NOC_FREE_CLK 19
> +#define DM_S2F_USR0_CLK 20
> +#define DM_NOC_CLK 21
> +#define DM_EMAC_A_FREE_CLK 22
> +#define DM_EMAC_B_FREE_CLK 23
> +#define DM_EMAC_PTP_FREE_CLK 24
> +#define DM_GPIO_DB_FREE_CLK 25
> +#define DM_SDMMC_FREE_CLK 26
> +#define DM_S2F_USER0_FREE_CLK 27
> +#define DM_S2F_USER1_FREE_CLK 28
> +#define DM_PSI_REF_FREE_CLK 29
> +
> +/* Gate clocks */
> +#define DM_MPU_CLK 30
> +#define DM_MPU_PERIPH_CLK 31
> +#define DM_L4_MAIN_CLK 32
> +#define DM_L4_MP_CLK 33
> +#define DM_L4_SP_CLK 34
> +#define DM_CS_AT_CLK 35
> +#define DM_CS_TRACE_CLK 36
> +#define DM_CS_PDBG_CLK 37
> +#define DM_CS_TIMER_CLK 38
> +#define DM_S2F_USER0_CLK 39
> +#define DM_EMAC0_CLK 40
> +#define DM_EMAC1_CLK 41
> +#define DM_EMAC2_CLK 42
> +#define DM_EMAC_PTP_CLK 43
> +#define DM_GPIO_DB_CLK 44
> +#define DM_NAND_CLK 45
> +#define DM_PSI_REF_CLK 46
> +#define DM_S2F_USER1_CLK 47
> +#define DM_SDMMC_CLK 48
> +#define DM_SPI_M_CLK 49
> +#define DM_USB_CLK 50
> +#define DM_NAND_X_CLK 51
> +#define DM_NAND_ECC_CLK 52
> +#define DM_NUM_CLKS 53
> +
> +#endif /* __DM_CLOCK_H */
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-09-28 17:14 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-18 12:17 [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Jit Loon Lim
2022-09-18 12:17 ` [PATCH 2/9] drivers: clk: dm: Add memory " Jit Loon Lim
2022-09-18 12:17 ` [PATCH 3/9] arm: socfpga: dm: Add clock manager " Jit Loon Lim
2022-09-18 12:17 ` [PATCH 4/9] ddr: altera: dm: Add SDRAM driver " Jit Loon Lim
2022-09-18 12:17 ` [PATCH 5/9] arm: socfpga: dm: Add SPL " Jit Loon Lim
2022-09-18 12:17 ` [PATCH 6/9] board: intel: dm: Add socdk board support " Jit Loon Lim
2022-09-18 12:17 ` [PATCH 7/9] arm: dts: dm: Add base dtsi and devkit dts " Jit Loon Lim
2022-09-18 12:17 ` [PATCH 8/9] configs: dm: Add Diamond Mesa CONFIGs Jit Loon Lim
2022-09-18 12:17 ` [PATCH 9/9] arm: socfpga: dm: Enable Intel Diamond Mesa bulid Jit Loon Lim
2022-09-28 17:14 ` [PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa Sean Anderson
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