* [PATCH v2] dt-bindings: interrupt-controller: migrate MIPS CPU interrupt controller text bindings to YAML
@ 2022-09-20 5:24 Sergio Paracuellos
2022-09-21 6:45 ` Krzysztof Kozlowski
0 siblings, 1 reply; 3+ messages in thread
From: Sergio Paracuellos @ 2022-09-20 5:24 UTC (permalink / raw)
To: devicetree; +Cc: tsbogend, robh+dt, krzysztof.kozlowski+dt, arinc.unal
MIPS CPU interrupt controller bindings used text format, so migrate them
to YAML.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
Changes in v2:
- Address review comment from Krzysztof:
- Rebase onto last kernel version.
- Add Thomas Bogendoerfer as maintainer since this is arch stuff.
- Change compatible to go first as property and required.
- Change sample node name to be generic. Use 'interrupt-controller'.
.../mti,cpu-interrupt-controller.yaml | 46 ++++++++++++++++++
.../devicetree/bindings/mips/cpu_irq.txt | 47 -------------------
2 files changed, 46 insertions(+), 47 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
delete mode 100644 Documentation/devicetree/bindings/mips/cpu_irq.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
new file mode 100644
index 000000000000..06dc65f0bbd2
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS CPU Interrupt Controller bindings
+
+description: >
+ On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
+ IRQs from a devicetree file and create a irq_domain for IRQ controller.
+
+ With the irq_domain in place we can describe how the 8 IRQs are wired to the
+ platforms internal interrupt controller cascade.
+
+maintainers:
+ - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+properties:
+ compatible:
+ const: mti,cpu-interrupt-controller
+
+ '#interrupt-cells':
+ const: 1
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+
+examples:
+ - |
+ interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
diff --git a/Documentation/devicetree/bindings/mips/cpu_irq.txt b/Documentation/devicetree/bindings/mips/cpu_irq.txt
deleted file mode 100644
index f080f06da6d8..000000000000
--- a/Documentation/devicetree/bindings/mips/cpu_irq.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-MIPS CPU interrupt controller
-
-On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
-IRQs from a devicetree file and create a irq_domain for IRQ controller.
-
-With the irq_domain in place we can describe how the 8 IRQs are wired to the
-platforms internal interrupt controller cascade.
-
-Below is an example of a platform describing the cascade inside the devicetree
-and the code used to load it inside arch_init_irq().
-
-Required properties:
-- compatible : Should be "mti,cpu-interrupt-controller"
-
-Example devicetree:
- cpu-irq: cpu-irq {
- #address-cells = <0>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
-
- compatible = "mti,cpu-interrupt-controller";
- };
-
- intc: intc@200 {
- compatible = "ralink,rt2880-intc";
- reg = <0x200 0x100>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
-
- interrupt-parent = <&cpu-irq>;
- interrupts = <2>;
- };
-
-
-Example platform irq.c:
-static struct of_device_id __initdata of_irq_ids[] = {
- { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
- { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
- {},
-};
-
-void __init arch_init_irq(void)
-{
- of_irq_init(of_irq_ids);
-}
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] dt-bindings: interrupt-controller: migrate MIPS CPU interrupt controller text bindings to YAML
2022-09-20 5:24 [PATCH v2] dt-bindings: interrupt-controller: migrate MIPS CPU interrupt controller text bindings to YAML Sergio Paracuellos
@ 2022-09-21 6:45 ` Krzysztof Kozlowski
2022-09-21 7:10 ` Sergio Paracuellos
0 siblings, 1 reply; 3+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-21 6:45 UTC (permalink / raw)
To: Sergio Paracuellos, devicetree
Cc: tsbogend, robh+dt, krzysztof.kozlowski+dt, arinc.unal
On 20/09/2022 07:24, Sergio Paracuellos wrote:
> MIPS CPU interrupt controller bindings used text format, so migrate them
> to YAML.
>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
> Changes in v2:
> - Address review comment from Krzysztof:
> - Rebase onto last kernel version.
> - Add Thomas Bogendoerfer as maintainer since this is arch stuff.
> - Change compatible to go first as property and required.
> - Change sample node name to be generic. Use 'interrupt-controller'.
Thank you for your patch. There is something to discuss/improve.
>
> .../mti,cpu-interrupt-controller.yaml | 46 ++++++++++++++++++
> .../devicetree/bindings/mips/cpu_irq.txt | 47 -------------------
> 2 files changed, 46 insertions(+), 47 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
> delete mode 100644 Documentation/devicetree/bindings/mips/cpu_irq.txt
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
> new file mode 100644
> index 000000000000..06dc65f0bbd2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MIPS CPU Interrupt Controller bindings
Drop bindings
> +
> +description: >
> + On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
> + IRQs from a devicetree file and create a irq_domain for IRQ controller.
> +
> + With the irq_domain in place we can describe how the 8 IRQs are wired to the
> + platforms internal interrupt controller cascade.
> +
> +maintainers:
> + - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> +
> +properties:
> + compatible:
> + const: mti,cpu-interrupt-controller
> +
> + '#interrupt-cells':
> + const: 1
> +
> + '#address-cells':
> + const: 0
> +
> + interrupt-controller: true
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - '#interrupt-cells'
> + - '#address-cells'
> + - interrupt-controller
> +
> +examples:
> + - |
> + interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
Put compatible first in list of properties. It's always first in DTS, by
convention.
> + };
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] dt-bindings: interrupt-controller: migrate MIPS CPU interrupt controller text bindings to YAML
2022-09-21 6:45 ` Krzysztof Kozlowski
@ 2022-09-21 7:10 ` Sergio Paracuellos
0 siblings, 0 replies; 3+ messages in thread
From: Sergio Paracuellos @ 2022-09-21 7:10 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Thomas Bogendoerfer, Rob Herring, Krzysztof Kozlowski,
Arınç ÜNAL
On Wed, Sep 21, 2022 at 8:45 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 20/09/2022 07:24, Sergio Paracuellos wrote:
> > MIPS CPU interrupt controller bindings used text format, so migrate them
> > to YAML.
> >
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > ---
> > Changes in v2:
> > - Address review comment from Krzysztof:
> > - Rebase onto last kernel version.
> > - Add Thomas Bogendoerfer as maintainer since this is arch stuff.
> > - Change compatible to go first as property and required.
> > - Change sample node name to be generic. Use 'interrupt-controller'.
>
> Thank you for your patch. There is something to discuss/improve.
>
> >
> > .../mti,cpu-interrupt-controller.yaml | 46 ++++++++++++++++++
> > .../devicetree/bindings/mips/cpu_irq.txt | 47 -------------------
> > 2 files changed, 46 insertions(+), 47 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
> > delete mode 100644 Documentation/devicetree/bindings/mips/cpu_irq.txt
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
> > new file mode 100644
> > index 000000000000..06dc65f0bbd2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
> > @@ -0,0 +1,46 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MIPS CPU Interrupt Controller bindings
>
> Drop bindings
Understood, wil drop.
>
> > +
> > +description: >
> > + On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
> > + IRQs from a devicetree file and create a irq_domain for IRQ controller.
> > +
> > + With the irq_domain in place we can describe how the 8 IRQs are wired to the
> > + platforms internal interrupt controller cascade.
> > +
> > +maintainers:
> > + - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > +
> > +properties:
> > + compatible:
> > + const: mti,cpu-interrupt-controller
> > +
> > + '#interrupt-cells':
> > + const: 1
> > +
> > + '#address-cells':
> > + const: 0
> > +
> > + interrupt-controller: true
> > +
> > +additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - '#interrupt-cells'
> > + - '#address-cells'
> > + - interrupt-controller
> > +
> > +examples:
> > + - |
> > + interrupt-controller {
> > + #address-cells = <0>;
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + compatible = "mti,cpu-interrupt-controller";
>
> Put compatible first in list of properties. It's always first in DTS, by
> convention.
Ok, I will put it first. Current dts files in arch/mips/boot/ using
this do not follow this convention at all so my copy-paste for adding
the sample here ended up in the same mistake :)
Thanks,
Sergio Paracuellos
>
> > + };
>
>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-09-20 5:24 [PATCH v2] dt-bindings: interrupt-controller: migrate MIPS CPU interrupt controller text bindings to YAML Sergio Paracuellos
2022-09-21 6:45 ` Krzysztof Kozlowski
2022-09-21 7:10 ` Sergio Paracuellos
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