* [PATCH 1/1] drm/i915/mtl: enable local stolen memory
@ 2022-09-20 7:19 ` Aravind Iddamsetty
0 siblings, 0 replies; 22+ messages in thread
From: Aravind Iddamsetty @ 2022-09-20 7:19 UTC (permalink / raw)
To: intel-gfx; +Cc: lucas.demarchi, dri-devel
As an integrated GPU, MTL does not have local memory and
HAS_LMEM() returns false. However the platform's stolen memory
is presented via BAR2 (i.e., the BAR we traditionally consider
to be the LMEM BAR) and should be managed by the driver the same
way that local memory is on dgpu platforms (which includes
setting the "lmem" bit on page table entries). We use the term
"local stolen memory" to refer to this model.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Original-author: CQ Tang
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 113 +++++++++++++++++----
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +
3 files changed, 100 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index acc561c0f0aa..bad5250fb764 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -77,6 +77,19 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
mutex_unlock(&i915->mm.stolen_lock);
}
+static bool is_dsm_invalid(struct drm_i915_private *i915, struct resource *dsm)
+{
+ if (!HAS_BAR2_SMEM_STOLEN(i915)) {
+ if (dsm->start == 0)
+ return true;
+ }
+
+ if (dsm->end <= dsm->start)
+ return true;
+
+ return false;
+}
+
static int i915_adjust_stolen(struct drm_i915_private *i915,
struct resource *dsm)
{
@@ -84,7 +97,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
struct intel_uncore *uncore = ggtt->vm.gt->uncore;
struct resource *r;
- if (dsm->start == 0 || dsm->end <= dsm->start)
+ if (is_dsm_invalid(i915, dsm))
return -EINVAL;
/*
@@ -136,7 +149,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
* overlaps with the non-stolen system memory range, since lmem is local
* to the gpu.
*/
- if (HAS_LMEM(i915))
+ if (HAS_LMEM(i915) || HAS_BAR2_SMEM_STOLEN(i915))
return 0;
/*
@@ -371,8 +384,6 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
- *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
-
switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
case GEN8_STOLEN_RESERVED_1M:
*size = 1024 * 1024;
@@ -390,6 +401,12 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
*size = 8 * 1024 * 1024;
MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
}
+
+ if ((GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) && !IS_DGFX(i915))
+ /* the base is initialized to stolen top so subtract size to get base */
+ *base -= *size;
+ else
+ *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
}
static int i915_gem_init_stolen(struct intel_memory_region *mem)
@@ -423,8 +440,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
if (i915_adjust_stolen(i915, &i915->dsm))
return 0;
- GEM_BUG_ON(i915->dsm.start == 0);
- GEM_BUG_ON(i915->dsm.end <= i915->dsm.start);
+ GEM_BUG_ON(is_dsm_invalid(i915, &i915->dsm));
stolen_top = i915->dsm.end + 1;
reserved_base = stolen_top;
@@ -796,6 +812,46 @@ static const struct intel_memory_region_ops i915_region_stolen_lmem_ops = {
.init_object = _i915_gem_object_stolen_init,
};
+static int get_mtl_gms_size(struct intel_uncore *uncore)
+{
+ u16 ggc, gms;
+
+ ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
+
+ /* check GGMS, should be fixed 0x3 (8MB) */
+ if ((ggc & 0xc0) != 0xc0)
+ return -EIO;
+
+ /* return valid GMS value, -EIO if invalid */
+ gms = ggc >> 8;
+ switch (gms) {
+ case 0x0 ... 0x10:
+ return gms * 32;
+ case 0x20:
+ return 1024;
+ case 0x30:
+ return 1536;
+ case 0x40:
+ return 2048;
+ case 0xf0 ... 0xfe:
+ return (gms - 0xf0 + 1) * 4;
+ default:
+ return -EIO;
+ }
+}
+
+static inline bool lmembar_is_igpu_stolen(struct drm_i915_private *i915)
+{
+ u32 regions = RUNTIME_INFO(i915)->memory_regions;
+
+ if (regions & REGION_LMEM)
+ return false;
+
+ drm_WARN_ON(&i915->drm, (regions & REGION_STOLEN_LMEM) == 0);
+
+ return true;
+}
+
struct intel_memory_region *
i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
u16 instance)
@@ -806,19 +862,16 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
struct intel_memory_region *mem;
resource_size_t io_start, io_size;
resource_size_t min_page_size;
+ int ret;
if (WARN_ON_ONCE(instance))
return ERR_PTR(-ENODEV);
- if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
+ if (!i915_pci_resource_valid(pdev, GFXMEM_BAR))
return ERR_PTR(-ENXIO);
- /* Use DSM base address instead for stolen memory */
- dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
- if (IS_DG1(uncore->i915)) {
- lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
- if (WARN_ON(lmem_size < dsm_base))
- return ERR_PTR(-ENODEV);
+ if (lmembar_is_igpu_stolen(i915) || IS_DG1(i915)) {
+ lmem_size = pci_resource_len(pdev, GFXMEM_BAR);
} else {
resource_size_t lmem_range;
@@ -827,13 +880,39 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
lmem_size *= SZ_1G;
}
- dsm_size = lmem_size - dsm_base;
- if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
+ if (HAS_BAR2_SMEM_STOLEN(i915)) {
+ /*
+ * MTL dsm size is in GGC register, not the bar size.
+ * also MTL uses offset to DSMBASE in ptes, so i915
+ * uses dsm_base = 0 to setup stolen region.
+ */
+ ret = get_mtl_gms_size(uncore);
+ if (ret < 0) {
+ drm_err(&i915->drm, "invalid MTL GGC register setting\n");
+ return ERR_PTR(ret);
+ }
+
+ dsm_base = 0;
+ dsm_size = (resource_size_t)(ret * SZ_1M);
+
+ GEM_BUG_ON(pci_resource_len(pdev, GFXMEM_BAR) != 256 * SZ_1M);
+ GEM_BUG_ON((dsm_size + 8 * SZ_1M) > lmem_size);
+ } else {
+ /* Use DSM base address instead for stolen memory */
+ dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
+ if (WARN_ON(lmem_size < dsm_base))
+ return ERR_PTR(-ENODEV);
+ dsm_size = lmem_size - dsm_base;
+ }
+
+ io_size = dsm_size;
+ if (pci_resource_len(pdev, GFXMEM_BAR) < dsm_size) {
io_start = 0;
io_size = 0;
+ } else if (HAS_BAR2_SMEM_STOLEN(i915)) {
+ io_start = pci_resource_start(pdev, GFXMEM_BAR) + 8 * SZ_1M;
} else {
- io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base;
- io_size = dsm_size;
+ io_start = pci_resource_start(pdev, GFXMEM_BAR) + dsm_base;
}
min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 30cf5c3369d9..b31fe0fb013f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -931,7 +931,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
unsigned int size;
u16 snb_gmch_ctl;
- if (!HAS_LMEM(i915)) {
+ if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) {
if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
return -ENXIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 134fc1621821..ef3120322077 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -973,6 +973,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
+#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
+ GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
@ 2022-09-20 7:19 ` Aravind Iddamsetty
0 siblings, 0 replies; 22+ messages in thread
From: Aravind Iddamsetty @ 2022-09-20 7:19 UTC (permalink / raw)
To: intel-gfx; +Cc: lucas.demarchi, dri-devel
As an integrated GPU, MTL does not have local memory and
HAS_LMEM() returns false. However the platform's stolen memory
is presented via BAR2 (i.e., the BAR we traditionally consider
to be the LMEM BAR) and should be managed by the driver the same
way that local memory is on dgpu platforms (which includes
setting the "lmem" bit on page table entries). We use the term
"local stolen memory" to refer to this model.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Original-author: CQ Tang
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 113 +++++++++++++++++----
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +
3 files changed, 100 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index acc561c0f0aa..bad5250fb764 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -77,6 +77,19 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
mutex_unlock(&i915->mm.stolen_lock);
}
+static bool is_dsm_invalid(struct drm_i915_private *i915, struct resource *dsm)
+{
+ if (!HAS_BAR2_SMEM_STOLEN(i915)) {
+ if (dsm->start == 0)
+ return true;
+ }
+
+ if (dsm->end <= dsm->start)
+ return true;
+
+ return false;
+}
+
static int i915_adjust_stolen(struct drm_i915_private *i915,
struct resource *dsm)
{
@@ -84,7 +97,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
struct intel_uncore *uncore = ggtt->vm.gt->uncore;
struct resource *r;
- if (dsm->start == 0 || dsm->end <= dsm->start)
+ if (is_dsm_invalid(i915, dsm))
return -EINVAL;
/*
@@ -136,7 +149,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
* overlaps with the non-stolen system memory range, since lmem is local
* to the gpu.
*/
- if (HAS_LMEM(i915))
+ if (HAS_LMEM(i915) || HAS_BAR2_SMEM_STOLEN(i915))
return 0;
/*
@@ -371,8 +384,6 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
- *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
-
switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
case GEN8_STOLEN_RESERVED_1M:
*size = 1024 * 1024;
@@ -390,6 +401,12 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
*size = 8 * 1024 * 1024;
MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
}
+
+ if ((GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) && !IS_DGFX(i915))
+ /* the base is initialized to stolen top so subtract size to get base */
+ *base -= *size;
+ else
+ *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
}
static int i915_gem_init_stolen(struct intel_memory_region *mem)
@@ -423,8 +440,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
if (i915_adjust_stolen(i915, &i915->dsm))
return 0;
- GEM_BUG_ON(i915->dsm.start == 0);
- GEM_BUG_ON(i915->dsm.end <= i915->dsm.start);
+ GEM_BUG_ON(is_dsm_invalid(i915, &i915->dsm));
stolen_top = i915->dsm.end + 1;
reserved_base = stolen_top;
@@ -796,6 +812,46 @@ static const struct intel_memory_region_ops i915_region_stolen_lmem_ops = {
.init_object = _i915_gem_object_stolen_init,
};
+static int get_mtl_gms_size(struct intel_uncore *uncore)
+{
+ u16 ggc, gms;
+
+ ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
+
+ /* check GGMS, should be fixed 0x3 (8MB) */
+ if ((ggc & 0xc0) != 0xc0)
+ return -EIO;
+
+ /* return valid GMS value, -EIO if invalid */
+ gms = ggc >> 8;
+ switch (gms) {
+ case 0x0 ... 0x10:
+ return gms * 32;
+ case 0x20:
+ return 1024;
+ case 0x30:
+ return 1536;
+ case 0x40:
+ return 2048;
+ case 0xf0 ... 0xfe:
+ return (gms - 0xf0 + 1) * 4;
+ default:
+ return -EIO;
+ }
+}
+
+static inline bool lmembar_is_igpu_stolen(struct drm_i915_private *i915)
+{
+ u32 regions = RUNTIME_INFO(i915)->memory_regions;
+
+ if (regions & REGION_LMEM)
+ return false;
+
+ drm_WARN_ON(&i915->drm, (regions & REGION_STOLEN_LMEM) == 0);
+
+ return true;
+}
+
struct intel_memory_region *
i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
u16 instance)
@@ -806,19 +862,16 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
struct intel_memory_region *mem;
resource_size_t io_start, io_size;
resource_size_t min_page_size;
+ int ret;
if (WARN_ON_ONCE(instance))
return ERR_PTR(-ENODEV);
- if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
+ if (!i915_pci_resource_valid(pdev, GFXMEM_BAR))
return ERR_PTR(-ENXIO);
- /* Use DSM base address instead for stolen memory */
- dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
- if (IS_DG1(uncore->i915)) {
- lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
- if (WARN_ON(lmem_size < dsm_base))
- return ERR_PTR(-ENODEV);
+ if (lmembar_is_igpu_stolen(i915) || IS_DG1(i915)) {
+ lmem_size = pci_resource_len(pdev, GFXMEM_BAR);
} else {
resource_size_t lmem_range;
@@ -827,13 +880,39 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
lmem_size *= SZ_1G;
}
- dsm_size = lmem_size - dsm_base;
- if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
+ if (HAS_BAR2_SMEM_STOLEN(i915)) {
+ /*
+ * MTL dsm size is in GGC register, not the bar size.
+ * also MTL uses offset to DSMBASE in ptes, so i915
+ * uses dsm_base = 0 to setup stolen region.
+ */
+ ret = get_mtl_gms_size(uncore);
+ if (ret < 0) {
+ drm_err(&i915->drm, "invalid MTL GGC register setting\n");
+ return ERR_PTR(ret);
+ }
+
+ dsm_base = 0;
+ dsm_size = (resource_size_t)(ret * SZ_1M);
+
+ GEM_BUG_ON(pci_resource_len(pdev, GFXMEM_BAR) != 256 * SZ_1M);
+ GEM_BUG_ON((dsm_size + 8 * SZ_1M) > lmem_size);
+ } else {
+ /* Use DSM base address instead for stolen memory */
+ dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
+ if (WARN_ON(lmem_size < dsm_base))
+ return ERR_PTR(-ENODEV);
+ dsm_size = lmem_size - dsm_base;
+ }
+
+ io_size = dsm_size;
+ if (pci_resource_len(pdev, GFXMEM_BAR) < dsm_size) {
io_start = 0;
io_size = 0;
+ } else if (HAS_BAR2_SMEM_STOLEN(i915)) {
+ io_start = pci_resource_start(pdev, GFXMEM_BAR) + 8 * SZ_1M;
} else {
- io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base;
- io_size = dsm_size;
+ io_start = pci_resource_start(pdev, GFXMEM_BAR) + dsm_base;
}
min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 30cf5c3369d9..b31fe0fb013f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -931,7 +931,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
unsigned int size;
u16 snb_gmch_ctl;
- if (!HAS_LMEM(i915)) {
+ if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) {
if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
return -ENXIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 134fc1621821..ef3120322077 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -973,6 +973,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
+#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
+ GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 7:19 ` [Intel-gfx] " Aravind Iddamsetty
(?)
@ 2022-09-20 7:33 ` Patchwork
-1 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-09-20 7:33 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/1] drm/i915/mtl: enable local stolen memory
URL : https://patchwork.freedesktop.org/series/108767/
State : warning
== Summary ==
Error: dim checkpatch failed
7dfaf4034615 drm/i915/mtl: enable local stolen memory
-:231: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#231: FILE: drivers/gpu/drm/i915/i915_drv.h:976:
+#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
+ GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
total: 0 errors, 0 warnings, 1 checks, 193 lines checked
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 7:19 ` [Intel-gfx] " Aravind Iddamsetty
(?)
(?)
@ 2022-09-20 7:34 ` Patchwork
-1 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-09-20 7:34 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/1] drm/i915/mtl: enable local stolen memory
URL : https://patchwork.freedesktop.org/series/108767/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 7:19 ` [Intel-gfx] " Aravind Iddamsetty
@ 2022-09-20 7:35 ` Jani Nikula
-1 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2022-09-20 7:35 UTC (permalink / raw)
To: Aravind Iddamsetty, intel-gfx; +Cc: lucas.demarchi, dri-devel
On Tue, 20 Sep 2022, Aravind Iddamsetty <aravind.iddamsetty@intel.com> wrote:
> As an integrated GPU, MTL does not have local memory and
> HAS_LMEM() returns false. However the platform's stolen memory
> is presented via BAR2 (i.e., the BAR we traditionally consider
> to be the LMEM BAR) and should be managed by the driver the same
> way that local memory is on dgpu platforms (which includes
> setting the "lmem" bit on page table entries). We use the term
> "local stolen memory" to refer to this model.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Signed-off-by: CQ Tang <cq.tang@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Original-author: CQ Tang
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 113 +++++++++++++++++----
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> 3 files changed, 100 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index acc561c0f0aa..bad5250fb764 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -77,6 +77,19 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
> mutex_unlock(&i915->mm.stolen_lock);
> }
>
> +static bool is_dsm_invalid(struct drm_i915_private *i915, struct resource *dsm)
Abstracting this as a separate function looks like a separate patch.
I generally recommend using positive naming, "is dsm valid", to avoid
any double negatives that might pop up, now or in the
future. !is_dsm_invalid() gets slower for human brains to parse.
BR,
Jani.
> +{
> + if (!HAS_BAR2_SMEM_STOLEN(i915)) {
> + if (dsm->start == 0)
> + return true;
> + }
> +
> + if (dsm->end <= dsm->start)
> + return true;
> +
> + return false;
> +}
> +
> static int i915_adjust_stolen(struct drm_i915_private *i915,
> struct resource *dsm)
> {
> @@ -84,7 +97,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
> struct intel_uncore *uncore = ggtt->vm.gt->uncore;
> struct resource *r;
>
> - if (dsm->start == 0 || dsm->end <= dsm->start)
> + if (is_dsm_invalid(i915, dsm))
> return -EINVAL;
>
> /*
> @@ -136,7 +149,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
> * overlaps with the non-stolen system memory range, since lmem is local
> * to the gpu.
> */
> - if (HAS_LMEM(i915))
> + if (HAS_LMEM(i915) || HAS_BAR2_SMEM_STOLEN(i915))
> return 0;
>
> /*
> @@ -371,8 +384,6 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
>
> drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
>
> - *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
> -
> switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
> case GEN8_STOLEN_RESERVED_1M:
> *size = 1024 * 1024;
> @@ -390,6 +401,12 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
> *size = 8 * 1024 * 1024;
> MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
> }
> +
> + if ((GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) && !IS_DGFX(i915))
> + /* the base is initialized to stolen top so subtract size to get base */
> + *base -= *size;
> + else
> + *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
> }
>
> static int i915_gem_init_stolen(struct intel_memory_region *mem)
> @@ -423,8 +440,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
> if (i915_adjust_stolen(i915, &i915->dsm))
> return 0;
>
> - GEM_BUG_ON(i915->dsm.start == 0);
> - GEM_BUG_ON(i915->dsm.end <= i915->dsm.start);
> + GEM_BUG_ON(is_dsm_invalid(i915, &i915->dsm));
>
> stolen_top = i915->dsm.end + 1;
> reserved_base = stolen_top;
> @@ -796,6 +812,46 @@ static const struct intel_memory_region_ops i915_region_stolen_lmem_ops = {
> .init_object = _i915_gem_object_stolen_init,
> };
>
> +static int get_mtl_gms_size(struct intel_uncore *uncore)
> +{
> + u16 ggc, gms;
> +
> + ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
> +
> + /* check GGMS, should be fixed 0x3 (8MB) */
> + if ((ggc & 0xc0) != 0xc0)
> + return -EIO;
> +
> + /* return valid GMS value, -EIO if invalid */
> + gms = ggc >> 8;
> + switch (gms) {
> + case 0x0 ... 0x10:
> + return gms * 32;
> + case 0x20:
> + return 1024;
> + case 0x30:
> + return 1536;
> + case 0x40:
> + return 2048;
> + case 0xf0 ... 0xfe:
> + return (gms - 0xf0 + 1) * 4;
> + default:
> + return -EIO;
> + }
> +}
> +
> +static inline bool lmembar_is_igpu_stolen(struct drm_i915_private *i915)
> +{
> + u32 regions = RUNTIME_INFO(i915)->memory_regions;
> +
> + if (regions & REGION_LMEM)
> + return false;
> +
> + drm_WARN_ON(&i915->drm, (regions & REGION_STOLEN_LMEM) == 0);
> +
> + return true;
> +}
> +
> struct intel_memory_region *
> i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
> u16 instance)
> @@ -806,19 +862,16 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
> struct intel_memory_region *mem;
> resource_size_t io_start, io_size;
> resource_size_t min_page_size;
> + int ret;
>
> if (WARN_ON_ONCE(instance))
> return ERR_PTR(-ENODEV);
>
> - if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
> + if (!i915_pci_resource_valid(pdev, GFXMEM_BAR))
> return ERR_PTR(-ENXIO);
>
> - /* Use DSM base address instead for stolen memory */
> - dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
> - if (IS_DG1(uncore->i915)) {
> - lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
> - if (WARN_ON(lmem_size < dsm_base))
> - return ERR_PTR(-ENODEV);
> + if (lmembar_is_igpu_stolen(i915) || IS_DG1(i915)) {
> + lmem_size = pci_resource_len(pdev, GFXMEM_BAR);
> } else {
> resource_size_t lmem_range;
>
> @@ -827,13 +880,39 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
> lmem_size *= SZ_1G;
> }
>
> - dsm_size = lmem_size - dsm_base;
> - if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
> + if (HAS_BAR2_SMEM_STOLEN(i915)) {
> + /*
> + * MTL dsm size is in GGC register, not the bar size.
> + * also MTL uses offset to DSMBASE in ptes, so i915
> + * uses dsm_base = 0 to setup stolen region.
> + */
> + ret = get_mtl_gms_size(uncore);
> + if (ret < 0) {
> + drm_err(&i915->drm, "invalid MTL GGC register setting\n");
> + return ERR_PTR(ret);
> + }
> +
> + dsm_base = 0;
> + dsm_size = (resource_size_t)(ret * SZ_1M);
> +
> + GEM_BUG_ON(pci_resource_len(pdev, GFXMEM_BAR) != 256 * SZ_1M);
> + GEM_BUG_ON((dsm_size + 8 * SZ_1M) > lmem_size);
> + } else {
> + /* Use DSM base address instead for stolen memory */
> + dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
> + if (WARN_ON(lmem_size < dsm_base))
> + return ERR_PTR(-ENODEV);
> + dsm_size = lmem_size - dsm_base;
> + }
> +
> + io_size = dsm_size;
> + if (pci_resource_len(pdev, GFXMEM_BAR) < dsm_size) {
> io_start = 0;
> io_size = 0;
> + } else if (HAS_BAR2_SMEM_STOLEN(i915)) {
> + io_start = pci_resource_start(pdev, GFXMEM_BAR) + 8 * SZ_1M;
> } else {
> - io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base;
> - io_size = dsm_size;
> + io_start = pci_resource_start(pdev, GFXMEM_BAR) + dsm_base;
> }
>
> min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 30cf5c3369d9..b31fe0fb013f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -931,7 +931,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> unsigned int size;
> u16 snb_gmch_ctl;
>
> - if (!HAS_LMEM(i915)) {
> + if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) {
> if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
> return -ENXIO;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 134fc1621821..ef3120322077 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -973,6 +973,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
>
> +#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
> + GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> +
> /* intel_device_info.c */
> static inline struct intel_device_info *
> mkwrite_device_info(struct drm_i915_private *dev_priv)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
@ 2022-09-20 7:35 ` Jani Nikula
0 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2022-09-20 7:35 UTC (permalink / raw)
To: Aravind Iddamsetty, intel-gfx; +Cc: lucas.demarchi, dri-devel
On Tue, 20 Sep 2022, Aravind Iddamsetty <aravind.iddamsetty@intel.com> wrote:
> As an integrated GPU, MTL does not have local memory and
> HAS_LMEM() returns false. However the platform's stolen memory
> is presented via BAR2 (i.e., the BAR we traditionally consider
> to be the LMEM BAR) and should be managed by the driver the same
> way that local memory is on dgpu platforms (which includes
> setting the "lmem" bit on page table entries). We use the term
> "local stolen memory" to refer to this model.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Signed-off-by: CQ Tang <cq.tang@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Original-author: CQ Tang
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 113 +++++++++++++++++----
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> 3 files changed, 100 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index acc561c0f0aa..bad5250fb764 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -77,6 +77,19 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
> mutex_unlock(&i915->mm.stolen_lock);
> }
>
> +static bool is_dsm_invalid(struct drm_i915_private *i915, struct resource *dsm)
Abstracting this as a separate function looks like a separate patch.
I generally recommend using positive naming, "is dsm valid", to avoid
any double negatives that might pop up, now or in the
future. !is_dsm_invalid() gets slower for human brains to parse.
BR,
Jani.
> +{
> + if (!HAS_BAR2_SMEM_STOLEN(i915)) {
> + if (dsm->start == 0)
> + return true;
> + }
> +
> + if (dsm->end <= dsm->start)
> + return true;
> +
> + return false;
> +}
> +
> static int i915_adjust_stolen(struct drm_i915_private *i915,
> struct resource *dsm)
> {
> @@ -84,7 +97,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
> struct intel_uncore *uncore = ggtt->vm.gt->uncore;
> struct resource *r;
>
> - if (dsm->start == 0 || dsm->end <= dsm->start)
> + if (is_dsm_invalid(i915, dsm))
> return -EINVAL;
>
> /*
> @@ -136,7 +149,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
> * overlaps with the non-stolen system memory range, since lmem is local
> * to the gpu.
> */
> - if (HAS_LMEM(i915))
> + if (HAS_LMEM(i915) || HAS_BAR2_SMEM_STOLEN(i915))
> return 0;
>
> /*
> @@ -371,8 +384,6 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
>
> drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
>
> - *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
> -
> switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
> case GEN8_STOLEN_RESERVED_1M:
> *size = 1024 * 1024;
> @@ -390,6 +401,12 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
> *size = 8 * 1024 * 1024;
> MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
> }
> +
> + if ((GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) && !IS_DGFX(i915))
> + /* the base is initialized to stolen top so subtract size to get base */
> + *base -= *size;
> + else
> + *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
> }
>
> static int i915_gem_init_stolen(struct intel_memory_region *mem)
> @@ -423,8 +440,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
> if (i915_adjust_stolen(i915, &i915->dsm))
> return 0;
>
> - GEM_BUG_ON(i915->dsm.start == 0);
> - GEM_BUG_ON(i915->dsm.end <= i915->dsm.start);
> + GEM_BUG_ON(is_dsm_invalid(i915, &i915->dsm));
>
> stolen_top = i915->dsm.end + 1;
> reserved_base = stolen_top;
> @@ -796,6 +812,46 @@ static const struct intel_memory_region_ops i915_region_stolen_lmem_ops = {
> .init_object = _i915_gem_object_stolen_init,
> };
>
> +static int get_mtl_gms_size(struct intel_uncore *uncore)
> +{
> + u16 ggc, gms;
> +
> + ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
> +
> + /* check GGMS, should be fixed 0x3 (8MB) */
> + if ((ggc & 0xc0) != 0xc0)
> + return -EIO;
> +
> + /* return valid GMS value, -EIO if invalid */
> + gms = ggc >> 8;
> + switch (gms) {
> + case 0x0 ... 0x10:
> + return gms * 32;
> + case 0x20:
> + return 1024;
> + case 0x30:
> + return 1536;
> + case 0x40:
> + return 2048;
> + case 0xf0 ... 0xfe:
> + return (gms - 0xf0 + 1) * 4;
> + default:
> + return -EIO;
> + }
> +}
> +
> +static inline bool lmembar_is_igpu_stolen(struct drm_i915_private *i915)
> +{
> + u32 regions = RUNTIME_INFO(i915)->memory_regions;
> +
> + if (regions & REGION_LMEM)
> + return false;
> +
> + drm_WARN_ON(&i915->drm, (regions & REGION_STOLEN_LMEM) == 0);
> +
> + return true;
> +}
> +
> struct intel_memory_region *
> i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
> u16 instance)
> @@ -806,19 +862,16 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
> struct intel_memory_region *mem;
> resource_size_t io_start, io_size;
> resource_size_t min_page_size;
> + int ret;
>
> if (WARN_ON_ONCE(instance))
> return ERR_PTR(-ENODEV);
>
> - if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
> + if (!i915_pci_resource_valid(pdev, GFXMEM_BAR))
> return ERR_PTR(-ENXIO);
>
> - /* Use DSM base address instead for stolen memory */
> - dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
> - if (IS_DG1(uncore->i915)) {
> - lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
> - if (WARN_ON(lmem_size < dsm_base))
> - return ERR_PTR(-ENODEV);
> + if (lmembar_is_igpu_stolen(i915) || IS_DG1(i915)) {
> + lmem_size = pci_resource_len(pdev, GFXMEM_BAR);
> } else {
> resource_size_t lmem_range;
>
> @@ -827,13 +880,39 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
> lmem_size *= SZ_1G;
> }
>
> - dsm_size = lmem_size - dsm_base;
> - if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
> + if (HAS_BAR2_SMEM_STOLEN(i915)) {
> + /*
> + * MTL dsm size is in GGC register, not the bar size.
> + * also MTL uses offset to DSMBASE in ptes, so i915
> + * uses dsm_base = 0 to setup stolen region.
> + */
> + ret = get_mtl_gms_size(uncore);
> + if (ret < 0) {
> + drm_err(&i915->drm, "invalid MTL GGC register setting\n");
> + return ERR_PTR(ret);
> + }
> +
> + dsm_base = 0;
> + dsm_size = (resource_size_t)(ret * SZ_1M);
> +
> + GEM_BUG_ON(pci_resource_len(pdev, GFXMEM_BAR) != 256 * SZ_1M);
> + GEM_BUG_ON((dsm_size + 8 * SZ_1M) > lmem_size);
> + } else {
> + /* Use DSM base address instead for stolen memory */
> + dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
> + if (WARN_ON(lmem_size < dsm_base))
> + return ERR_PTR(-ENODEV);
> + dsm_size = lmem_size - dsm_base;
> + }
> +
> + io_size = dsm_size;
> + if (pci_resource_len(pdev, GFXMEM_BAR) < dsm_size) {
> io_start = 0;
> io_size = 0;
> + } else if (HAS_BAR2_SMEM_STOLEN(i915)) {
> + io_start = pci_resource_start(pdev, GFXMEM_BAR) + 8 * SZ_1M;
> } else {
> - io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base;
> - io_size = dsm_size;
> + io_start = pci_resource_start(pdev, GFXMEM_BAR) + dsm_base;
> }
>
> min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 30cf5c3369d9..b31fe0fb013f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -931,7 +931,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> unsigned int size;
> u16 snb_gmch_ctl;
>
> - if (!HAS_LMEM(i915)) {
> + if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) {
> if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
> return -ENXIO;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 134fc1621821..ef3120322077 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -973,6 +973,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
>
> +#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
> + GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> +
> /* intel_device_info.c */
> static inline struct intel_device_info *
> mkwrite_device_info(struct drm_i915_private *dev_priv)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 7:19 ` [Intel-gfx] " Aravind Iddamsetty
` (3 preceding siblings ...)
(?)
@ 2022-09-20 7:56 ` Patchwork
-1 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-09-20 7:56 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 16150 bytes --]
== Series Details ==
Series: series starting with [1/1] drm/i915/mtl: enable local stolen memory
URL : https://patchwork.freedesktop.org/series/108767/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12158 -> Patchwork_108767v1
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_108767v1 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108767v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/index.html
Participating hosts (42 -> 43)
------------------------------
Additional (5): fi-cml-u2 fi-icl-u2 fi-cfl-guc fi-icl-y bat-dg2-11
Missing (4): fi-ctg-p8600 bat-jsl-3 fi-kbl-guc bat-dg1-5
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108767v1:
### IGT changes ###
#### Warnings ####
* igt@runner@aborted:
- fi-apl-guc: [FAIL][1] ([i915#6599]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-apl-guc/igt@runner@aborted.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-apl-guc/igt@runner@aborted.html
- fi-skl-guc: [FAIL][3] ([i915#6599]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-skl-guc/igt@runner@aborted.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-skl-guc/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_108767v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2: NOTRUN -> [SKIP][5] ([i915#1208]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cml-u2/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-y: NOTRUN -> [SKIP][6] ([i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-y/igt@gem_huc_copy@huc-copy.html
- fi-icl-u2: NOTRUN -> [SKIP][7] ([i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
- fi-cml-u2: NOTRUN -> [SKIP][8] ([i915#2190])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cml-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cml-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-u2/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-guc: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cfl-guc/igt@gem_lmem_swapping@verify-random.html
- fi-icl-y: NOTRUN -> [SKIP][12] ([i915#4613]) +3 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-y/igt@gem_lmem_swapping@verify-random.html
* igt@i915_module_load@load:
- fi-bdw-gvtdvm: [PASS][13] -> [DMESG-WARN][14] ([i915#6540])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-bdw-gvtdvm/igt@i915_module_load@load.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-bdw-gvtdvm/igt@i915_module_load@load.html
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [PASS][15] -> [DMESG-FAIL][16] ([i915#62])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live:
- fi-cfl-8109u: NOTRUN -> [INCOMPLETE][17] ([i915#6114])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cfl-8109u/igt@i915_selftest@live.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: NOTRUN -> [SKIP][19] ([fdo#109284] / [fdo#111827]) +8 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-edid-read:
- fi-cfl-guc: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +8 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cfl-guc/igt@kms_chamelium@dp-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][21] ([fdo#111827]) +8 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_chamelium@vga-hpd-fast:
- fi-icl-y: NOTRUN -> [SKIP][22] ([fdo#109284] / [fdo#111827]) +8 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-y/igt@kms_chamelium@vga-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-cml-u2: NOTRUN -> [SKIP][23] ([i915#4213])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cml-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
- fi-icl-y: NOTRUN -> [SKIP][24] ([i915#4103])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
- fi-icl-u2: NOTRUN -> [SKIP][25] ([i915#4103])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2: NOTRUN -> [WARN][26] ([i915#6008])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-u2/igt@kms_force_connector_basic@force-connector-state.html
- fi-bdw-gvtdvm: [PASS][27] -> [DMESG-WARN][28] ([i915#5922])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-bdw-gvtdvm/igt@kms_force_connector_basic@force-connector-state.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-bdw-gvtdvm/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2: NOTRUN -> [SKIP][29] ([fdo#109285])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cml-u2/igt@kms_force_connector_basic@force-load-detect.html
- fi-icl-y: NOTRUN -> [SKIP][30] ([fdo#109285])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-y/igt@kms_force_connector_basic@force-load-detect.html
- fi-icl-u2: NOTRUN -> [SKIP][31] ([fdo#109285])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [PASS][32] -> [DMESG-WARN][33] ([i915#62]) +12 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
- fi-cml-u2: NOTRUN -> [DMESG-WARN][34] ([i915#402])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_psr@sprite_plane_onoff:
- fi-icl-y: NOTRUN -> [SKIP][35] ([fdo#110189]) +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-y/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-y: NOTRUN -> [SKIP][36] ([i915#3555])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-y/igt@kms_setmode@basic-clone-single-crtc.html
- fi-icl-u2: NOTRUN -> [SKIP][37] ([i915#3555])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
- fi-cml-u2: NOTRUN -> [SKIP][38] ([i915#3555])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cml-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-cfl-guc: NOTRUN -> [SKIP][39] ([fdo#109271]) +10 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cfl-guc/igt@prime_vgem@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][40] ([fdo#109295] / [i915#3301])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-u2/igt@prime_vgem@basic-userptr.html
- fi-icl-y: NOTRUN -> [SKIP][41] ([fdo#109295] / [i915#3301])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-icl-y/igt@prime_vgem@basic-userptr.html
- fi-cml-u2: NOTRUN -> [SKIP][42] ([fdo#109295] / [i915#3301])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cml-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-cfl-8109u: NOTRUN -> [FAIL][43] ([i915#4312])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-cfl-8109u/igt@runner@aborted.html
- fi-bdw-gvtdvm: NOTRUN -> [FAIL][44] ([i915#4312])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-bdw-gvtdvm/igt@runner@aborted.html
#### Possible fixes ####
* igt@fbdev@write:
- {fi-tgl-mst}: [SKIP][45] ([i915#2582]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-tgl-mst/igt@fbdev@write.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-tgl-mst/igt@fbdev@write.html
* igt@gem_ctx_create@basic-files:
- {fi-tgl-mst}: [DMESG-WARN][47] -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-tgl-mst/igt@gem_ctx_create@basic-files.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-tgl-mst/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}: [DMESG-WARN][49] ([i915#2867]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][51] ([i915#4785]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [FAIL][53] ([i915#6298]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#5828]: https://gitlab.freedesktop.org/drm/intel/issues/5828
[i915#5922]: https://gitlab.freedesktop.org/drm/intel/issues/5922
[i915#6008]: https://gitlab.freedesktop.org/drm/intel/issues/6008
[i915#6114]: https://gitlab.freedesktop.org/drm/intel/issues/6114
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#6540]: https://gitlab.freedesktop.org/drm/intel/issues/6540
[i915#6596]: https://gitlab.freedesktop.org/drm/intel/issues/6596
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6724]: https://gitlab.freedesktop.org/drm/intel/issues/6724
[i915#6850]: https://gitlab.freedesktop.org/drm/intel/issues/6850
Build changes
-------------
* Linux: CI_DRM_12158 -> Patchwork_108767v1
CI-20190529: 20190529
CI_DRM_12158: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108767v1: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
9661b9b7576a drm/i915/mtl: enable local stolen memory
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/index.html
[-- Attachment #2: Type: text/html, Size: 17566 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 7:19 ` [Intel-gfx] " Aravind Iddamsetty
` (4 preceding siblings ...)
(?)
@ 2022-09-20 8:31 ` Lucas De Marchi
2022-09-20 20:05 ` Lucas De Marchi
-1 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2022-09-20 8:31 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: intel-gfx, dri-devel
On Tue, Sep 20, 2022 at 12:49:40PM +0530, Aravind Iddamsetty wrote:
>As an integrated GPU, MTL does not have local memory and
>HAS_LMEM() returns false. However the platform's stolen memory
>is presented via BAR2 (i.e., the BAR we traditionally consider
>to be the LMEM BAR) and should be managed by the driver the same
>way that local memory is on dgpu platforms (which includes
>setting the "lmem" bit on page table entries). We use the term
>"local stolen memory" to refer to this model.
>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>
>Signed-off-by: CQ Tang <cq.tang@intel.com>
>Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>Original-author: CQ Tang
>---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 113 +++++++++++++++++----
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> 3 files changed, 100 insertions(+), 18 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>index acc561c0f0aa..bad5250fb764 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>@@ -77,6 +77,19 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
> mutex_unlock(&i915->mm.stolen_lock);
> }
>
>+static bool is_dsm_invalid(struct drm_i915_private *i915, struct resource *dsm)
>+{
>+ if (!HAS_BAR2_SMEM_STOLEN(i915)) {
I called a similar function as is_dsm_valid() in
https://patchwork.freedesktop.org/series/108620/
sounds weird with "invalid" and the double negation on return early
style.
>+ if (dsm->start == 0)
>+ return true;
>+ }
>+
>+ if (dsm->end <= dsm->start)
>+ return true;
>+
>+ return false;
>+}
>+
> static int i915_adjust_stolen(struct drm_i915_private *i915,
> struct resource *dsm)
> {
>@@ -84,7 +97,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
> struct intel_uncore *uncore = ggtt->vm.gt->uncore;
> struct resource *r;
>
>- if (dsm->start == 0 || dsm->end <= dsm->start)
>+ if (is_dsm_invalid(i915, dsm))
> return -EINVAL;
>
> /*
>@@ -136,7 +149,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
> * overlaps with the non-stolen system memory range, since lmem is local
> * to the gpu.
> */
>- if (HAS_LMEM(i915))
>+ if (HAS_LMEM(i915) || HAS_BAR2_SMEM_STOLEN(i915))
comment above makes no sense when you add this. For this specific case
it's still system memory, reserved by the BIOS and that we access by
mapping the lmembar
> return 0;
>
> /*
>@@ -371,8 +384,6 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
>
> drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
>
>- *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
>-
> switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
> case GEN8_STOLEN_RESERVED_1M:
> *size = 1024 * 1024;
>@@ -390,6 +401,12 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
> *size = 8 * 1024 * 1024;
> MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
> }
>+
>+ if ((GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) && !IS_DGFX(i915))
>+ /* the base is initialized to stolen top so subtract size to get base */
>+ *base -= *size;
that doesn't necessarily holds true. According to the spec the wopcm
base is 1MB aligned so even if it is "at the top", it may not mean it is at the
very very top that we can just subtract the size.
>+ else
>+ *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
> }
>
> static int i915_gem_init_stolen(struct intel_memory_region *mem)
>@@ -423,8 +440,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
> if (i915_adjust_stolen(i915, &i915->dsm))
> return 0;
>
>- GEM_BUG_ON(i915->dsm.start == 0);
>- GEM_BUG_ON(i915->dsm.end <= i915->dsm.start);
>+ GEM_BUG_ON(is_dsm_invalid(i915, &i915->dsm));
>
> stolen_top = i915->dsm.end + 1;
> reserved_base = stolen_top;
>@@ -796,6 +812,46 @@ static const struct intel_memory_region_ops i915_region_stolen_lmem_ops = {
> .init_object = _i915_gem_object_stolen_init,
> };
>
>+static int get_mtl_gms_size(struct intel_uncore *uncore)
>+{
>+ u16 ggc, gms;
>+
>+ ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
??
>+
>+ /* check GGMS, should be fixed 0x3 (8MB) */
>+ if ((ggc & 0xc0) != 0xc0)
>+ return -EIO;
>+
>+ /* return valid GMS value, -EIO if invalid */
>+ gms = ggc >> 8;
>+ switch (gms) {
>+ case 0x0 ... 0x10:
>+ return gms * 32;
>+ case 0x20:
>+ return 1024;
>+ case 0x30:
>+ return 1536;
>+ case 0x40:
>+ return 2048;
>+ case 0xf0 ... 0xfe:
>+ return (gms - 0xf0 + 1) * 4;
>+ default:
>+ return -EIO;
>+ }
>+}
>+
>+static inline bool lmembar_is_igpu_stolen(struct drm_i915_private *i915)
doesn't deserve an inline. lmembar_is_igpu_stolen() doesn't make much
sense as the lmembar is never igpu stolen.... you probably mean
something else here
>+{
>+ u32 regions = RUNTIME_INFO(i915)->memory_regions;
>+
>+ if (regions & REGION_LMEM)
>+ return false;
>+
>+ drm_WARN_ON(&i915->drm, (regions & REGION_STOLEN_LMEM) == 0);
>+
>+ return true;
>+}
>+
> struct intel_memory_region *
> i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
> u16 instance)
>@@ -806,19 +862,16 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
> struct intel_memory_region *mem;
> resource_size_t io_start, io_size;
> resource_size_t min_page_size;
>+ int ret;
>
> if (WARN_ON_ONCE(instance))
> return ERR_PTR(-ENODEV);
>
>- if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
>+ if (!i915_pci_resource_valid(pdev, GFXMEM_BAR))
at least for MTL, Bspec 63830 still calls this lmembar. So the rename
for me is a net loss
> return ERR_PTR(-ENXIO);
>
>- /* Use DSM base address instead for stolen memory */
>- dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
>- if (IS_DG1(uncore->i915)) {
>- lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
>- if (WARN_ON(lmem_size < dsm_base))
>- return ERR_PTR(-ENODEV);
>+ if (lmembar_is_igpu_stolen(i915) || IS_DG1(i915)) {
>+ lmem_size = pci_resource_len(pdev, GFXMEM_BAR);
this looks confusing, but apparently correct. For DG1 the stolen is
on top of lmem. For MTL, it's on the end of lmembar (256M). This works
because on DG1 aperture == lmem size.
> } else {
> resource_size_t lmem_range;
>
>@@ -827,13 +880,39 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
> lmem_size *= SZ_1G;
> }
>
>- dsm_size = lmem_size - dsm_base;
>- if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
>+ if (HAS_BAR2_SMEM_STOLEN(i915)) {
>+ /*
>+ * MTL dsm size is in GGC register, not the bar size.
it's not exclusive to MTL. it has been there for ages and it was never
the BAR size like this comment says. Or at least it doesn't match the
else condition that is using the GEN12_DSMBASE register
>+ * also MTL uses offset to DSMBASE in ptes, so i915
>+ * uses dsm_base = 0 to setup stolen region.
>+ */
>+ ret = get_mtl_gms_size(uncore);
>+ if (ret < 0) {
>+ drm_err(&i915->drm, "invalid MTL GGC register setting\n");
>+ return ERR_PTR(ret);
>+ }
>+
>+ dsm_base = 0;
if we stop handling part of the values in the registers as relative to
the mapping and rather handle them as we read from the registers
(physical addresses), the size calculations should still match and we
shouldn't need all the if/else dance. If we pass the right io_start we
can then make them relative to the mapping by subtracting it, or if we
don't want GTT to be in the mapping we subtract it.
That makes me wonder if choosing the i915_gem_stolen_lmem_setup() for
all of this is even the right choice given we are actually talking about
system memory that is mapped through the lmembar.
>+ dsm_size = (resource_size_t)(ret * SZ_1M);
>+
>+ GEM_BUG_ON(pci_resource_len(pdev, GFXMEM_BAR) != 256 * SZ_1M);
>+ GEM_BUG_ON((dsm_size + 8 * SZ_1M) > lmem_size);
>+ } else {
>+ /* Use DSM base address instead for stolen memory */
>+ dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
>+ if (WARN_ON(lmem_size < dsm_base))
>+ return ERR_PTR(-ENODEV);
>+ dsm_size = lmem_size - dsm_base;
>+ }
>+
>+ io_size = dsm_size;
>+ if (pci_resource_len(pdev, GFXMEM_BAR) < dsm_size) {
> io_start = 0;
> io_size = 0;
>+ } else if (HAS_BAR2_SMEM_STOLEN(i915)) {
>+ io_start = pci_resource_start(pdev, GFXMEM_BAR) + 8 * SZ_1M;
should be the GGSM?
Lucas De Marchi
> } else {
>- io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base;
>- io_size = dsm_size;
>+ io_start = pci_resource_start(pdev, GFXMEM_BAR) + dsm_base;
> }
>
> min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
>diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>index 30cf5c3369d9..b31fe0fb013f 100644
>--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>@@ -931,7 +931,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> unsigned int size;
> u16 snb_gmch_ctl;
>
>- if (!HAS_LMEM(i915)) {
>+ if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) {
> if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
> return -ENXIO;
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 134fc1621821..ef3120322077 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -973,6 +973,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
>
>+#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
>+ GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>+
> /* intel_device_info.c */
> static inline struct intel_device_info *
> mkwrite_device_info(struct drm_i915_private *dev_priv)
>--
>2.25.1
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 7:19 ` [Intel-gfx] " Aravind Iddamsetty
` (5 preceding siblings ...)
(?)
@ 2022-09-20 11:52 ` Patchwork
-1 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-09-20 11:52 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 38765 bytes --]
== Series Details ==
Series: series starting with [1/1] drm/i915/mtl: enable local stolen memory
URL : https://patchwork.freedesktop.org/series/108767/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12158_full -> Patchwork_108767v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 11)
------------------------------
Additional (1): shard-rkl
Known issues
------------
Here are the changes found in Patchwork_108767v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [FAIL][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4392])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk1/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk1/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk1/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk3/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk3/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk3/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk5/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk7/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk8/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk8/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk8/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk9/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk9/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk9/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk5/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk6/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk6/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk6/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk7/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk7/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk7/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk8/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk8/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk8/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk9/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk9/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk9/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk1/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk2/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk2/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk2/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk1/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk1/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk1/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk5/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk5/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk3/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk3/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk3/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][51] -> [SKIP][52] ([i915#4525]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb1/igt@gem_exec_balancer@parallel.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb5/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][53] -> [FAIL][54] ([i915#2842])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-uc-set-default:
- shard-apl: [PASS][55] -> [DMESG-FAIL][56] ([i915#6864])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/igt@gem_exec_flush@basic-uc-set-default.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl7/igt@gem_exec_flush@basic-uc-set-default.html
* igt@gem_softpin@evict-single-offset:
- shard-tglb: [PASS][57] -> [FAIL][58] ([i915#4171])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb3/igt@gem_softpin@evict-single-offset.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-tglb2/igt@gem_softpin@evict-single-offset.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][59] ([i915#4991])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl3/igt@gem_userptr_blits@input-checking.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271]) +62 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl3/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][61] -> [DMESG-WARN][62] ([i915#5566] / [i915#716])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk5/igt@gen9_exec_parse@allowed-single.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk1/igt@gen9_exec_parse@allowed-single.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#3886]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl3/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color_chamelium@ctm-red-to-blue:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [fdo#111827]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl6/igt@kms_color_chamelium@ctm-red-to-blue.html
* igt@kms_cursor_crc@cursor-random-32x10:
- shard-glk: NOTRUN -> [SKIP][65] ([fdo#109271]) +7 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk8/igt@kms_cursor_crc@cursor-random-32x10.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [PASS][66] -> [FAIL][67] ([i915#2346])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][68] -> [FAIL][69] ([i915#79])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][70] -> [DMESG-WARN][71] ([i915#180]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][72] ([i915#3555]) +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][73] ([i915#2587] / [i915#2672]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][74] -> [SKIP][75] ([i915#5235]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl3/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: [PASS][77] -> [SKIP][78] ([fdo#109441]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb1/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglb: [PASS][79] -> [SKIP][80] ([i915#5519])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-tglb2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
- shard-iclb: [PASS][81] -> [SKIP][82] ([i915#5519])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#533])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl6/igt@kms_vblank@pipe-d-wait-idle.html
* igt@perf@polling-parameterized:
- shard-apl: [PASS][84] -> [FAIL][85] ([i915#5639])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/igt@perf@polling-parameterized.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl7/igt@perf@polling-parameterized.html
* igt@sysfs_clients@create:
- shard-glk: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#2994])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk8/igt@sysfs_clients@create.html
#### Possible fixes ####
* igt@drm_import_export@prime:
- shard-apl: [DMESG-WARN][87] ([i915#6864]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/igt@drm_import_export@prime.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl7/igt@drm_import_export@prime.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [FAIL][89] ([i915#6268]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb3/igt@gem_ctx_exec@basic-nohangcheck.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html
- {shard-tglu}: [FAIL][91] ([i915#6268]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglu-4/igt@gem_ctx_exec@basic-nohangcheck.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-tglu}: [FAIL][93] ([i915#2842]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglu-6/igt@gem_exec_fair@basic-none-share@rcs0.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-tglu-4/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][95] ([i915#2842]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [FAIL][97] ([i915#2842]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk9/igt@gem_exec_fair@basic-none@vcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk5/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_flush@basic-uc-set-default:
- shard-glk: [DMESG-FAIL][99] ([i915#6864]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/igt@gem_exec_flush@basic-uc-set-default.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk8/igt@gem_exec_flush@basic-uc-set-default.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [DMESG-WARN][101] ([i915#180]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/igt@gem_workarounds@suspend-resume.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl6/igt@gem_workarounds@suspend-resume.html
* igt@i915_pm_dc@dc5-psr:
- shard-iclb: [FAIL][103] ([i915#3989]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb8/igt@i915_pm_dc@dc5-psr.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb2/igt@i915_pm_dc@dc5-psr.html
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [DMESG-WARN][105] ([i915#5591]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb5/igt@i915_selftest@live@hangcheck.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-tglb3/igt@i915_selftest@live@hangcheck.html
* igt@kms_frontbuffer_tracking@fbc-badstride:
- shard-snb: [SKIP][107] ([fdo#109271]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-snb4/igt@kms_frontbuffer_tracking@fbc-badstride.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-snb6/igt@kms_frontbuffer_tracking@fbc-badstride.html
* igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1:
- shard-glk: [FAIL][109] ([i915#1888]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk2/igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [SKIP][111] ([fdo#109441]) -> [PASS][112] +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_vblank@pipe-b-accuracy-idle:
- shard-glk: [FAIL][113] ([i915#43]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@kms_vblank@pipe-b-accuracy-idle.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk9/igt@kms_vblank@pipe-b-accuracy-idle.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [FAIL][115] ([i915#6117]) -> [SKIP][116] ([i915#4525])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][117] ([i915#658]) -> [SKIP][118] ([i915#588])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-iclb: [FAIL][119] ([i915#2684]) -> [WARN][120] ([i915#2684])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][121] ([i915#658]) -> [SKIP][122] ([i915#2920]) +2 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb7/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][123] ([i915#2920]) -> [SKIP][124] ([i915#658])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: [SKIP][125] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][126] ([i915#5939])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb8/igt@kms_psr2_su@page_flip-p010.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html
* igt@runner@aborted:
- shard-apl: ([FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6884])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl2/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl1/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl7/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl3/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-apl8/igt@runner@aborted.html
- shard-tglb: ([FAIL][136], [FAIL][137]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][138], [FAIL][139]) ([i915#3002] / [i915#4312] / [i915#5257])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb8/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb1/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-tglb2/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-tglb5/igt@runner@aborted.html
- shard-glk: ([FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6884])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk8/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk9/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk2/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-glk1/igt@runner@aborted.html
- shard-skl: ([FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162], [FAIL][163], [FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171], [FAIL][172]) ([i915#6599]) -> ([FAIL][173], [FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177], [FAIL][178], [FAIL][179], [FAIL][180], [FAIL][181], [FAIL][182], [FAIL][183], [FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187], [FAIL][188], [FAIL][189], [FAIL][190], [FAIL][191], [FAIL][192], [FAIL][193], [FAIL][194], [FAIL][195], [FAIL][196], [FAIL][197]) ([i915#6884])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl9/igt@runner@aborted.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl3/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl5/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl10/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl2/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl9/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl7/igt@runner@aborted.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl1/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl3/igt@runner@aborted.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl1/igt@runner@aborted.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl4/igt@runner@aborted.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl7/igt@runner@aborted.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl6/igt@runner@aborted.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl3/igt@runner@aborted.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl5/igt@runner@aborted.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl6/igt@runner@aborted.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl2/igt@runner@aborted.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl4/igt@runner@aborted.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl7/igt@runner@aborted.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl9/igt@runner@aborted.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl1/igt@runner@aborted.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl10/igt@runner@aborted.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl6/igt@runner@aborted.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl10/igt@runner@aborted.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-skl4/igt@runner@aborted.html
- shard-iclb: ([FAIL][198], [FAIL][199]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][200], [FAIL][201]) ([i915#3002] / [i915#4312] / [i915#5257])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb7/igt@runner@aborted.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb5/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb4/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/shard-iclb8/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#6864]: https://gitlab.freedesktop.org/drm/intel/issues/6864
[i915#6884]: https://gitlab.freedesktop.org/drm/intel/issues/6884
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12158 -> Patchwork_108767v1
CI-20190529: 20190529
CI_DRM_12158: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108767v1: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108767v1/index.html
[-- Attachment #2: Type: text/html, Size: 38719 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 7:19 ` [Intel-gfx] " Aravind Iddamsetty
` (6 preceding siblings ...)
(?)
@ 2022-09-20 16:57 ` Andi Shyti
2022-09-20 20:01 ` Lucas De Marchi
2022-09-20 20:40 ` Matt Roper
-1 siblings, 2 replies; 22+ messages in thread
From: Andi Shyti @ 2022-09-20 16:57 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: intel-gfx, lucas.demarchi, dri-devel
Hi Aravind,
> +static int get_mtl_gms_size(struct intel_uncore *uncore)
> +{
> + u16 ggc, gms;
> +
> + ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
> +
> + /* check GGMS, should be fixed 0x3 (8MB) */
> + if ((ggc & 0xc0) != 0xc0)
> + return -EIO;
> +
> + /* return valid GMS value, -EIO if invalid */
> + gms = ggc >> 8;
> + switch (gms) {
> + case 0x0 ... 0x10:
> + return gms * 32;
> + case 0x20:
> + return 1024;
> + case 0x30:
> + return 1536;
> + case 0x40:
> + return 2048;
> + case 0xf0 ... 0xfe:
just a bit puzzled by the fact that case ranges are not standard
and are supported only by GCC, unless, of course, I miss
something. Do we still want to use them as they are widely used
around the kernel?
Andi
> + return (gms - 0xf0 + 1) * 4;
> + default:
> + return -EIO;
> + }
> +}
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 16:57 ` [Intel-gfx] [PATCH 1/1] " Andi Shyti
@ 2022-09-20 20:01 ` Lucas De Marchi
2022-09-20 20:40 ` Matt Roper
1 sibling, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2022-09-20 20:01 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx, dri-devel, Aravind Iddamsetty
On Tue, Sep 20, 2022 at 06:57:46PM +0200, Andi Shyti wrote:
>Hi Aravind,
>
>> +static int get_mtl_gms_size(struct intel_uncore *uncore)
>> +{
>> + u16 ggc, gms;
>> +
>> + ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
>> +
>> + /* check GGMS, should be fixed 0x3 (8MB) */
>> + if ((ggc & 0xc0) != 0xc0)
>> + return -EIO;
>> +
>> + /* return valid GMS value, -EIO if invalid */
>> + gms = ggc >> 8;
>> + switch (gms) {
>> + case 0x0 ... 0x10:
>> + return gms * 32;
>> + case 0x20:
>> + return 1024;
>> + case 0x30:
>> + return 1536;
>> + case 0x40:
>> + return 2048;
>> + case 0xf0 ... 0xfe:
>
>just a bit puzzled by the fact that case ranges are not standard
>and are supported only by GCC, unless, of course, I miss
clang also supports it and can build the kernel (or a great portion of
it).
Lucas De Marchi
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
@ 2022-09-20 20:01 ` Lucas De Marchi
0 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2022-09-20 20:01 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx, dri-devel
On Tue, Sep 20, 2022 at 06:57:46PM +0200, Andi Shyti wrote:
>Hi Aravind,
>
>> +static int get_mtl_gms_size(struct intel_uncore *uncore)
>> +{
>> + u16 ggc, gms;
>> +
>> + ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
>> +
>> + /* check GGMS, should be fixed 0x3 (8MB) */
>> + if ((ggc & 0xc0) != 0xc0)
>> + return -EIO;
>> +
>> + /* return valid GMS value, -EIO if invalid */
>> + gms = ggc >> 8;
>> + switch (gms) {
>> + case 0x0 ... 0x10:
>> + return gms * 32;
>> + case 0x20:
>> + return 1024;
>> + case 0x30:
>> + return 1536;
>> + case 0x40:
>> + return 2048;
>> + case 0xf0 ... 0xfe:
>
>just a bit puzzled by the fact that case ranges are not standard
>and are supported only by GCC, unless, of course, I miss
clang also supports it and can build the kernel (or a great portion of
it).
Lucas De Marchi
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 8:31 ` [Intel-gfx] [PATCH 1/1] " Lucas De Marchi
@ 2022-09-20 20:05 ` Lucas De Marchi
2022-09-21 6:30 ` Iddamsetty, Aravind
0 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2022-09-20 20:05 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: intel-gfx, dri-devel
On Tue, Sep 20, 2022 at 01:31:49AM -0700, Lucas De Marchi wrote:
>On Tue, Sep 20, 2022 at 12:49:40PM +0530, Aravind Iddamsetty wrote:
>>As an integrated GPU, MTL does not have local memory and
>>HAS_LMEM() returns false. However the platform's stolen memory
>>is presented via BAR2 (i.e., the BAR we traditionally consider
>>to be the LMEM BAR) and should be managed by the driver the same
>>way that local memory is on dgpu platforms (which includes
>>setting the "lmem" bit on page table entries). We use the term
>>"local stolen memory" to refer to this model.
>>
>>Cc: Matt Roper <matthew.d.roper@intel.com>
>>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>
>>Signed-off-by: CQ Tang <cq.tang@intel.com>
>>Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>>Original-author: CQ Tang
>>---
>>drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 113 +++++++++++++++++----
>>drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
>>drivers/gpu/drm/i915/i915_drv.h | 3 +
>>3 files changed, 100 insertions(+), 18 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>index acc561c0f0aa..bad5250fb764 100644
>>--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>@@ -77,6 +77,19 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
>> mutex_unlock(&i915->mm.stolen_lock);
>>}
>>
>>+static bool is_dsm_invalid(struct drm_i915_private *i915, struct resource *dsm)
>>+{
>>+ if (!HAS_BAR2_SMEM_STOLEN(i915)) {
>
>I called a similar function as is_dsm_valid() in
>https://patchwork.freedesktop.org/series/108620/
>
>sounds weird with "invalid" and the double negation on return early
>style.
>
>>+ if (dsm->start == 0)
>>+ return true;
>>+ }
>>+
>>+ if (dsm->end <= dsm->start)
>>+ return true;
>>+
>>+ return false;
>>+}
>>+
>>static int i915_adjust_stolen(struct drm_i915_private *i915,
>> struct resource *dsm)
>>{
>>@@ -84,7 +97,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
>> struct intel_uncore *uncore = ggtt->vm.gt->uncore;
>> struct resource *r;
>>
>>- if (dsm->start == 0 || dsm->end <= dsm->start)
>>+ if (is_dsm_invalid(i915, dsm))
>> return -EINVAL;
>>
>> /*
>>@@ -136,7 +149,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
>> * overlaps with the non-stolen system memory range, since lmem is local
>> * to the gpu.
>> */
>>- if (HAS_LMEM(i915))
>>+ if (HAS_LMEM(i915) || HAS_BAR2_SMEM_STOLEN(i915))
>
>comment above makes no sense when you add this. For this specific case
>it's still system memory, reserved by the BIOS and that we access by
>mapping the lmembar
>
>> return 0;
>>
>> /*
>>@@ -371,8 +384,6 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
>>
>> drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
>>
>>- *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
>>-
>> switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
>> case GEN8_STOLEN_RESERVED_1M:
>> *size = 1024 * 1024;
>>@@ -390,6 +401,12 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
>> *size = 8 * 1024 * 1024;
>> MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
>> }
>>+
>>+ if ((GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) && !IS_DGFX(i915))
>>+ /* the base is initialized to stolen top so subtract size to get base */
>>+ *base -= *size;
>
>that doesn't necessarily holds true. According to the spec the wopcm
>base is 1MB aligned so even if it is "at the top", it may not mean it is at the
>very very top that we can just subtract the size.
>
>
>>+ else
>>+ *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
>>}
>>
>>static int i915_gem_init_stolen(struct intel_memory_region *mem)
>>@@ -423,8 +440,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
>> if (i915_adjust_stolen(i915, &i915->dsm))
>> return 0;
>>
>>- GEM_BUG_ON(i915->dsm.start == 0);
>>- GEM_BUG_ON(i915->dsm.end <= i915->dsm.start);
>>+ GEM_BUG_ON(is_dsm_invalid(i915, &i915->dsm));
>>
>> stolen_top = i915->dsm.end + 1;
>> reserved_base = stolen_top;
>>@@ -796,6 +812,46 @@ static const struct intel_memory_region_ops i915_region_stolen_lmem_ops = {
>> .init_object = _i915_gem_object_stolen_init,
>>};
>>
>>+static int get_mtl_gms_size(struct intel_uncore *uncore)
>>+{
>>+ u16 ggc, gms;
>>+
>>+ ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
>
>??
>
>>+
>>+ /* check GGMS, should be fixed 0x3 (8MB) */
>>+ if ((ggc & 0xc0) != 0xc0)
>>+ return -EIO;
>>+
>>+ /* return valid GMS value, -EIO if invalid */
>>+ gms = ggc >> 8;
>>+ switch (gms) {
>>+ case 0x0 ... 0x10:
>>+ return gms * 32;
>>+ case 0x20:
>>+ return 1024;
>>+ case 0x30:
>>+ return 1536;
>>+ case 0x40:
>>+ return 2048;
>>+ case 0xf0 ... 0xfe:
>>+ return (gms - 0xf0 + 1) * 4;
>>+ default:
>>+ return -EIO;
>>+ }
>>+}
>>+
>>+static inline bool lmembar_is_igpu_stolen(struct drm_i915_private *i915)
>
>doesn't deserve an inline. lmembar_is_igpu_stolen() doesn't make much
>sense as the lmembar is never igpu stolen.... you probably mean
>something else here
>
>>+{
>>+ u32 regions = RUNTIME_INFO(i915)->memory_regions;
>>+
>>+ if (regions & REGION_LMEM)
>>+ return false;
>>+
>>+ drm_WARN_ON(&i915->drm, (regions & REGION_STOLEN_LMEM) == 0);
>>+
>>+ return true;
>>+}
>>+
>>struct intel_memory_region *
>>i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>> u16 instance)
>>@@ -806,19 +862,16 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>> struct intel_memory_region *mem;
>> resource_size_t io_start, io_size;
>> resource_size_t min_page_size;
>>+ int ret;
>>
>> if (WARN_ON_ONCE(instance))
>> return ERR_PTR(-ENODEV);
>>
>>- if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
>>+ if (!i915_pci_resource_valid(pdev, GFXMEM_BAR))
>
>at least for MTL, Bspec 63830 still calls this lmembar. So the rename
>for me is a net loss
>
>> return ERR_PTR(-ENXIO);
>>
>>- /* Use DSM base address instead for stolen memory */
>>- dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
>>- if (IS_DG1(uncore->i915)) {
>>- lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
>>- if (WARN_ON(lmem_size < dsm_base))
>>- return ERR_PTR(-ENODEV);
>>+ if (lmembar_is_igpu_stolen(i915) || IS_DG1(i915)) {
>>+ lmem_size = pci_resource_len(pdev, GFXMEM_BAR);
>
>this looks confusing, but apparently correct. For DG1 the stolen is
>on top of lmem. For MTL, it's on the end of lmembar (256M). This works
>because on DG1 aperture == lmem size.
>
>> } else {
>> resource_size_t lmem_range;
>>
>>@@ -827,13 +880,39 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>> lmem_size *= SZ_1G;
>> }
>>
>>- dsm_size = lmem_size - dsm_base;
>>- if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
>>+ if (HAS_BAR2_SMEM_STOLEN(i915)) {
>>+ /*
>>+ * MTL dsm size is in GGC register, not the bar size.
>
>it's not exclusive to MTL. it has been there for ages and it was never
>the BAR size like this comment says. Or at least it doesn't match the
>else condition that is using the GEN12_DSMBASE register
>
>>+ * also MTL uses offset to DSMBASE in ptes, so i915
>>+ * uses dsm_base = 0 to setup stolen region.
>>+ */
>>+ ret = get_mtl_gms_size(uncore);
>>+ if (ret < 0) {
>>+ drm_err(&i915->drm, "invalid MTL GGC register setting\n");
>>+ return ERR_PTR(ret);
>>+ }
>>+
>>+ dsm_base = 0;
>
>if we stop handling part of the values in the registers as relative to
>the mapping and rather handle them as we read from the registers
>(physical addresses), the size calculations should still match and we
>shouldn't need all the if/else dance. If we pass the right io_start we
>can then make them relative to the mapping by subtracting it, or if we
>don't want GTT to be in the mapping we subtract it.
>
>That makes me wonder if choosing the i915_gem_stolen_lmem_setup() for
>all of this is even the right choice given we are actually talking about
>system memory that is mapped through the lmembar.
another approach could be: handle the several coding style issues,
function names etc. Since this works for MTL, it's better than the
hypothetical solution that is not written and may not work well. I may
have missed something in my analysis. So I'd be fine to go with improved
version of this patch, and I can add to my todo list to try to clean
this up later.
Lucas De Marchi
>
>>+ dsm_size = (resource_size_t)(ret * SZ_1M);
>>+
>>+ GEM_BUG_ON(pci_resource_len(pdev, GFXMEM_BAR) != 256 * SZ_1M);
>>+ GEM_BUG_ON((dsm_size + 8 * SZ_1M) > lmem_size);
>>+ } else {
>>+ /* Use DSM base address instead for stolen memory */
>>+ dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
>>+ if (WARN_ON(lmem_size < dsm_base))
>>+ return ERR_PTR(-ENODEV);
>>+ dsm_size = lmem_size - dsm_base;
>>+ }
>>+
>>+ io_size = dsm_size;
>>+ if (pci_resource_len(pdev, GFXMEM_BAR) < dsm_size) {
>> io_start = 0;
>> io_size = 0;
>>+ } else if (HAS_BAR2_SMEM_STOLEN(i915)) {
>>+ io_start = pci_resource_start(pdev, GFXMEM_BAR) + 8 * SZ_1M;
>
>should be the GGSM?
>
>
>Lucas De Marchi
>
>> } else {
>>- io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base;
>>- io_size = dsm_size;
>>+ io_start = pci_resource_start(pdev, GFXMEM_BAR) + dsm_base;
>> }
>>
>> min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
>>diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>index 30cf5c3369d9..b31fe0fb013f 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>@@ -931,7 +931,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>> unsigned int size;
>> u16 snb_gmch_ctl;
>>
>>- if (!HAS_LMEM(i915)) {
>>+ if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) {
>> if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
>> return -ENXIO;
>>
>>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>index 134fc1621821..ef3120322077 100644
>>--- a/drivers/gpu/drm/i915/i915_drv.h
>>+++ b/drivers/gpu/drm/i915/i915_drv.h
>>@@ -973,6 +973,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>
>>#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
>>
>>+#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
>>+ GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>>+
>>/* intel_device_info.c */
>>static inline struct intel_device_info *
>>mkwrite_device_info(struct drm_i915_private *dev_priv)
>>--
>>2.25.1
>>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 16:57 ` [Intel-gfx] [PATCH 1/1] " Andi Shyti
@ 2022-09-20 20:40 ` Matt Roper
2022-09-20 20:40 ` Matt Roper
1 sibling, 0 replies; 22+ messages in thread
From: Matt Roper @ 2022-09-20 20:40 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx, lucas.demarchi, dri-devel, Aravind Iddamsetty
On Tue, Sep 20, 2022 at 06:57:46PM +0200, Andi Shyti wrote:
> Hi Aravind,
>
> > +static int get_mtl_gms_size(struct intel_uncore *uncore)
> > +{
> > + u16 ggc, gms;
> > +
> > + ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
> > +
> > + /* check GGMS, should be fixed 0x3 (8MB) */
> > + if ((ggc & 0xc0) != 0xc0)
> > + return -EIO;
> > +
> > + /* return valid GMS value, -EIO if invalid */
> > + gms = ggc >> 8;
> > + switch (gms) {
> > + case 0x0 ... 0x10:
> > + return gms * 32;
> > + case 0x20:
> > + return 1024;
> > + case 0x30:
> > + return 1536;
> > + case 0x40:
> > + return 2048;
> > + case 0xf0 ... 0xfe:
>
> just a bit puzzled by the fact that case ranges are not standard
> and are supported only by GCC, unless, of course, I miss
> something. Do we still want to use them as they are widely used
> around the kernel?
i915 already has 17 other uses of this notation and the DRM subsystem in
general has about 50 today. So it's not super common, but I think it
should be okay to use. I believe clang supports this language extension
as well and the coding style doc doesn't say anything one way or the
other.
Matt
>
> Andi
>
> > + return (gms - 0xf0 + 1) * 4;
> > + default:
> > + return -EIO;
> > + }
> > +}
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
@ 2022-09-20 20:40 ` Matt Roper
0 siblings, 0 replies; 22+ messages in thread
From: Matt Roper @ 2022-09-20 20:40 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx, lucas.demarchi, dri-devel
On Tue, Sep 20, 2022 at 06:57:46PM +0200, Andi Shyti wrote:
> Hi Aravind,
>
> > +static int get_mtl_gms_size(struct intel_uncore *uncore)
> > +{
> > + u16 ggc, gms;
> > +
> > + ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
> > +
> > + /* check GGMS, should be fixed 0x3 (8MB) */
> > + if ((ggc & 0xc0) != 0xc0)
> > + return -EIO;
> > +
> > + /* return valid GMS value, -EIO if invalid */
> > + gms = ggc >> 8;
> > + switch (gms) {
> > + case 0x0 ... 0x10:
> > + return gms * 32;
> > + case 0x20:
> > + return 1024;
> > + case 0x30:
> > + return 1536;
> > + case 0x40:
> > + return 2048;
> > + case 0xf0 ... 0xfe:
>
> just a bit puzzled by the fact that case ranges are not standard
> and are supported only by GCC, unless, of course, I miss
> something. Do we still want to use them as they are widely used
> around the kernel?
i915 already has 17 other uses of this notation and the DRM subsystem in
general has about 50 today. So it's not super common, but I think it
should be okay to use. I believe clang supports this language extension
as well and the coding style doc doesn't say anything one way or the
other.
Matt
>
> Andi
>
> > + return (gms - 0xf0 + 1) * 4;
> > + default:
> > + return -EIO;
> > + }
> > +}
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 20:40 ` Matt Roper
@ 2022-09-20 22:33 ` Andi Shyti
-1 siblings, 0 replies; 22+ messages in thread
From: Andi Shyti @ 2022-09-20 22:33 UTC (permalink / raw)
To: Matt Roper
Cc: dri-devel, intel-gfx, lucas.demarchi, Aravind Iddamsetty, Andi Shyti
Hi Matt, Lucas,
thanks for your feedback,
> > > + switch (gms) {
> > > + case 0x0 ... 0x10:
> > > + return gms * 32;
> > > + case 0x20:
> > > + return 1024;
> > > + case 0x30:
> > > + return 1536;
> > > + case 0x40:
> > > + return 2048;
> > > + case 0xf0 ... 0xfe:
> >
> > just a bit puzzled by the fact that case ranges are not standard
> > and are supported only by GCC, unless, of course, I miss
> > something. Do we still want to use them as they are widely used
> > around the kernel?
>
> i915 already has 17 other uses of this notation and the DRM subsystem in
> general has about 50 today. So it's not super common, but I think it
> should be okay to use. I believe clang supports this language extension
> as well and the coding style doc doesn't say anything one way or the
> other.
I thought clang supports it for C++ rather than C, but I'm not a
clang expert, so that I might be wrong.
The fact that it is widely used is never a convincing argument
and if gcc supports it, then it does it against the standard,
both C11 and C17 (this is what puzzles me everytime I see these C
tricks offered by gcc).
Anyway, I'm not against it (nor in favour) as the ellipsis is
becoming very commonly used. My comment, by the way, did not mean
to block the patch, I just wanted to check what other people
think about.
Thanks,
Andi
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
@ 2022-09-20 22:33 ` Andi Shyti
0 siblings, 0 replies; 22+ messages in thread
From: Andi Shyti @ 2022-09-20 22:33 UTC (permalink / raw)
To: Matt Roper; +Cc: dri-devel, intel-gfx, lucas.demarchi
Hi Matt, Lucas,
thanks for your feedback,
> > > + switch (gms) {
> > > + case 0x0 ... 0x10:
> > > + return gms * 32;
> > > + case 0x20:
> > > + return 1024;
> > > + case 0x30:
> > > + return 1536;
> > > + case 0x40:
> > > + return 2048;
> > > + case 0xf0 ... 0xfe:
> >
> > just a bit puzzled by the fact that case ranges are not standard
> > and are supported only by GCC, unless, of course, I miss
> > something. Do we still want to use them as they are widely used
> > around the kernel?
>
> i915 already has 17 other uses of this notation and the DRM subsystem in
> general has about 50 today. So it's not super common, but I think it
> should be okay to use. I believe clang supports this language extension
> as well and the coding style doc doesn't say anything one way or the
> other.
I thought clang supports it for C++ rather than C, but I'm not a
clang expert, so that I might be wrong.
The fact that it is widely used is never a convincing argument
and if gcc supports it, then it does it against the standard,
both C11 and C17 (this is what puzzles me everytime I see these C
tricks offered by gcc).
Anyway, I'm not against it (nor in favour) as the ellipsis is
becoming very commonly used. My comment, by the way, did not mean
to block the patch, I just wanted to check what other people
think about.
Thanks,
Andi
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 20:05 ` Lucas De Marchi
@ 2022-09-21 6:30 ` Iddamsetty, Aravind
2022-09-22 13:56 ` Lucas De Marchi
0 siblings, 1 reply; 22+ messages in thread
From: Iddamsetty, Aravind @ 2022-09-21 6:30 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
replying here for earlier comments too.
On 21-09-2022 01:35, Lucas De Marchi wrote:
> On Tue, Sep 20, 2022 at 01:31:49AM -0700, Lucas De Marchi wrote:
>> On Tue, Sep 20, 2022 at 12:49:40PM +0530, Aravind Iddamsetty wrote:
>>> As an integrated GPU, MTL does not have local memory and
>>> HAS_LMEM() returns false. However the platform's stolen memory
>>> is presented via BAR2 (i.e., the BAR we traditionally consider
>>> to be the LMEM BAR) and should be managed by the driver the same
>>> way that local memory is on dgpu platforms (which includes
>>> setting the "lmem" bit on page table entries). We use the term
>>> "local stolen memory" to refer to this model.
>>>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>>
>>> Signed-off-by: CQ Tang <cq.tang@intel.com>
>>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>>> Original-author: CQ Tang
>>> ---
>>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 113 +++++++++++++++++----
>>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
>>> drivers/gpu/drm/i915/i915_drv.h | 3 +
>>> 3 files changed, 100 insertions(+), 18 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>> index acc561c0f0aa..bad5250fb764 100644
>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>> @@ -77,6 +77,19 @@ void i915_gem_stolen_remove_node(struct
>>> drm_i915_private *i915,
>>> mutex_unlock(&i915->mm.stolen_lock);
>>> }
>>>
>>> +static bool is_dsm_invalid(struct drm_i915_private *i915, struct
>>> resource *dsm)
>>> +{
>>> + if (!HAS_BAR2_SMEM_STOLEN(i915)) {
>>
>> I called a similar function as is_dsm_valid() in
>> https://patchwork.freedesktop.org/series/108620/
>>
>> sounds weird with "invalid" and the double negation on return early
>> style.
sure, will change it hope i can use that from your patch.
>>
>>> + if (dsm->start == 0)
>>> + return true;
>>> + }
>>> +
>>> + if (dsm->end <= dsm->start)
>>> + return true;
>>> +
>>> + return false;
>>> +}
>>> +
>>> static int i915_adjust_stolen(struct drm_i915_private *i915,
>>> struct resource *dsm)
>>> {
>>> @@ -84,7 +97,7 @@ static int i915_adjust_stolen(struct
>>> drm_i915_private *i915,
>>> struct intel_uncore *uncore = ggtt->vm.gt->uncore;
>>> struct resource *r;
>>>
>>> - if (dsm->start == 0 || dsm->end <= dsm->start)
>>> + if (is_dsm_invalid(i915, dsm))
>>> return -EINVAL;
>>>
>>> /*
>>> @@ -136,7 +149,7 @@ static int i915_adjust_stolen(struct
>>> drm_i915_private *i915,
>>> * overlaps with the non-stolen system memory range, since lmem
>>> is local
>>> * to the gpu.
>>> */
>>> - if (HAS_LMEM(i915))
>>> + if (HAS_LMEM(i915) || HAS_BAR2_SMEM_STOLEN(i915))
>>
>> comment above makes no sense when you add this. For this specific case
>> it's still system memory, reserved by the BIOS and that we access by
>> mapping the lmembar
thanks for catching this.
>>
>>> return 0;
>>>
>>> /*
>>> @@ -371,8 +384,6 @@ static void icl_get_stolen_reserved(struct
>>> drm_i915_private *i915,
>>>
>>> drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
>>>
>>> - *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
>>> -
>>> switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
>>> case GEN8_STOLEN_RESERVED_1M:
>>> *size = 1024 * 1024;
>>> @@ -390,6 +401,12 @@ static void icl_get_stolen_reserved(struct
>>> drm_i915_private *i915,
>>> *size = 8 * 1024 * 1024;
>>> MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
>>> }
>>> +
>>> + if ((GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) && !IS_DGFX(i915))
>>> + /* the base is initialized to stolen top so subtract size to
>>> get base */
>>> + *base -= *size;
>>
>> that doesn't necessarily holds true. According to the spec the wopcm
>> base is 1MB aligned so even if it is "at the top", it may not mean it
>> is at the
>> very very top that we can just subtract the size.
well here the reserved_base is not to the top of the BAR, we got the
stolen size from GGC register so base is initialized to end of that
stolen size. hence we subtract the reserved size from it.
>>
>>
>>> + else
>>> + *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
>>> }
>>>
>>> static int i915_gem_init_stolen(struct intel_memory_region *mem)
>>> @@ -423,8 +440,7 @@ static int i915_gem_init_stolen(struct
>>> intel_memory_region *mem)
>>> if (i915_adjust_stolen(i915, &i915->dsm))
>>> return 0;
>>>
>>> - GEM_BUG_ON(i915->dsm.start == 0);
>>> - GEM_BUG_ON(i915->dsm.end <= i915->dsm.start);
>>> + GEM_BUG_ON(is_dsm_invalid(i915, &i915->dsm));
>>>
>>> stolen_top = i915->dsm.end + 1;
>>> reserved_base = stolen_top;
>>> @@ -796,6 +812,46 @@ static const struct intel_memory_region_ops
>>> i915_region_stolen_lmem_ops = {
>>> .init_object = _i915_gem_object_stolen_init,
>>> };
>>>
>>> +static int get_mtl_gms_size(struct intel_uncore *uncore)
>>> +{
>>> + u16 ggc, gms;
>>> +
>>> + ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
>>
>> ??
>>
>>> +
>>> + /* check GGMS, should be fixed 0x3 (8MB) */
>>> + if ((ggc & 0xc0) != 0xc0)
>>> + return -EIO;
>>> +
>>> + /* return valid GMS value, -EIO if invalid */
>>> + gms = ggc >> 8;
>>> + switch (gms) {
>>> + case 0x0 ... 0x10:
>>> + return gms * 32;
>>> + case 0x20:
>>> + return 1024;
>>> + case 0x30:
>>> + return 1536;
>>> + case 0x40:
>>> + return 2048;
>>> + case 0xf0 ... 0xfe:
>>> + return (gms - 0xf0 + 1) * 4;
>>> + default:
>>> + return -EIO;
>>> + }
>>> +}
>>> +
>>> +static inline bool lmembar_is_igpu_stolen(struct drm_i915_private
>>> *i915)
>>
>> doesn't deserve an inline. lmembar_is_igpu_stolen() doesn't make much
>> sense as the lmembar is never igpu stolen.... you probably mean
>> something else here
here the intent was to check the second BAR which is traditionally LMEM
is to be considered STOLEN, if the memory regions consists STOLEN_LMEM
and not LMEM. But I think i can rather replace this entire function and
just use HAS_LMEM check.
>>
>>> +{
>>> + u32 regions = RUNTIME_INFO(i915)->memory_regions;
>>> +
>>> + if (regions & REGION_LMEM)
>>> + return false;
>>> +
>>> + drm_WARN_ON(&i915->drm, (regions & REGION_STOLEN_LMEM) == 0);
>>> +
>>> + return true;
>>> +}
>>> +
>>> struct intel_memory_region *
>>> i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>>> u16 instance)
>>> @@ -806,19 +862,16 @@ i915_gem_stolen_lmem_setup(struct
>>> drm_i915_private *i915, u16 type,
>>> struct intel_memory_region *mem;
>>> resource_size_t io_start, io_size;
>>> resource_size_t min_page_size;
>>> + int ret;
>>>
>>> if (WARN_ON_ONCE(instance))
>>> return ERR_PTR(-ENODEV);
>>>
>>> - if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
>>> + if (!i915_pci_resource_valid(pdev, GFXMEM_BAR))
>>
>> at least for MTL, Bspec 63830 still calls this lmembar. So the rename
>> for me is a net loss
that is right, will revert this.
>>
>>> return ERR_PTR(-ENXIO);
>>>
>>> - /* Use DSM base address instead for stolen memory */
>>> - dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
>>> - if (IS_DG1(uncore->i915)) {
>>> - lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
>>> - if (WARN_ON(lmem_size < dsm_base))
>>> - return ERR_PTR(-ENODEV);
>>> + if (lmembar_is_igpu_stolen(i915) || IS_DG1(i915)) {
>>> + lmem_size = pci_resource_len(pdev, GFXMEM_BAR);
>>
>> this looks confusing, but apparently correct. For DG1 the stolen is
>> on top of lmem. For MTL, it's on the end of lmembar (256M). This works
>> because on DG1 aperture == lmem size.
>>
>>> } else {
>>> resource_size_t lmem_range;
>>>
>>> @@ -827,13 +880,39 @@ i915_gem_stolen_lmem_setup(struct
>>> drm_i915_private *i915, u16 type,
>>> lmem_size *= SZ_1G;
>>> }
>>>
>>> - dsm_size = lmem_size - dsm_base;
>>> - if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
>>> + if (HAS_BAR2_SMEM_STOLEN(i915)) {
>>> + /*
>>> + * MTL dsm size is in GGC register, not the bar size.
>>
>> it's not exclusive to MTL. it has been there for ages and it was never
>> the BAR size like this comment says. Or at least it doesn't match the
>> else condition that is using the GEN12_DSMBASE register
>>
>>> + * also MTL uses offset to DSMBASE in ptes, so i915
>>> + * uses dsm_base = 0 to setup stolen region.
>>> + */
>>> + ret = get_mtl_gms_size(uncore);
>>> + if (ret < 0) {
>>> + drm_err(&i915->drm, "invalid MTL GGC register setting\n");
>>> + return ERR_PTR(ret);
>>> + }
>>> +
>>> + dsm_base = 0;
>>
>> if we stop handling part of the values in the registers as relative to
>> the mapping and rather handle them as we read from the registers
>> (physical addresses), the size calculations should still match and we
>> shouldn't need all the if/else dance. If we pass the right io_start we
>> can then make them relative to the mapping by subtracting it, or if we
>> don't want GTT to be in the mapping we subtract it.
>>
>> That makes me wonder if choosing the i915_gem_stolen_lmem_setup() for
>> all of this is even the right choice given we are actually talking about
>> system memory that is mapped through the lmembar.
>
>
> another approach could be: handle the several coding style issues,
> function names etc. Since this works for MTL, it's better than the
> hypothetical solution that is not written and may not work well. I may
> have missed something in my analysis. So I'd be fine to go with improved
> version of this patch, and I can add to my todo list to try to clean
> this up later.
Thanks for that.
>
> Lucas De Marchi
>
>
>>
>>> + dsm_size = (resource_size_t)(ret * SZ_1M);
>>> +
>>> + GEM_BUG_ON(pci_resource_len(pdev, GFXMEM_BAR) != 256 * SZ_1M);
>>> + GEM_BUG_ON((dsm_size + 8 * SZ_1M) > lmem_size);
>>> + } else {
>>> + /* Use DSM base address instead for stolen memory */
>>> + dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
>>> + if (WARN_ON(lmem_size < dsm_base))
>>> + return ERR_PTR(-ENODEV);
>>> + dsm_size = lmem_size - dsm_base;
>>> + }
>>> +
>>> + io_size = dsm_size;
>>> + if (pci_resource_len(pdev, GFXMEM_BAR) < dsm_size) {
>>> io_start = 0;
>>> io_size = 0;
>>> + } else if (HAS_BAR2_SMEM_STOLEN(i915)) {
>>> + io_start = pci_resource_start(pdev, GFXMEM_BAR) + 8 * SZ_1M;
>>
>> should be the GGSM?
make sense can be derived from GGC registered.
Thanks,
Aravind.
>>
>>
>> Lucas De Marchi
>>
>>> } else {
>>> - io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base;
>>> - io_size = dsm_size;
>>> + io_start = pci_resource_start(pdev, GFXMEM_BAR) + dsm_base;
>>> }
>>>
>>> min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>> index 30cf5c3369d9..b31fe0fb013f 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>> @@ -931,7 +931,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>>> unsigned int size;
>>> u16 snb_gmch_ctl;
>>>
>>> - if (!HAS_LMEM(i915)) {
>>> + if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) {
>>> if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
>>> return -ENXIO;
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h
>>> index 134fc1621821..ef3120322077 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -973,6 +973,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>>
>>> #define HAS_ONE_EU_PER_FUSE_BIT(i915)
>>> (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
>>>
>>> +#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
>>> + GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>>> +
>>> /* intel_device_info.c */
>>> static inline struct intel_device_info *
>>> mkwrite_device_info(struct drm_i915_private *dev_priv)
>>> --
>>> 2.25.1
>>>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/1] drm/i915/mtl: enable local stolen memory
2022-09-20 7:35 ` [Intel-gfx] " Jani Nikula
@ 2022-09-21 6:32 ` Iddamsetty, Aravind
-1 siblings, 0 replies; 22+ messages in thread
From: Iddamsetty, Aravind @ 2022-09-21 6:32 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: lucas.demarchi, dri-devel
On 20-09-2022 13:05, Jani Nikula wrote:
> On Tue, 20 Sep 2022, Aravind Iddamsetty <aravind.iddamsetty@intel.com> wrote:
>> As an integrated GPU, MTL does not have local memory and
>> HAS_LMEM() returns false. However the platform's stolen memory
>> is presented via BAR2 (i.e., the BAR we traditionally consider
>> to be the LMEM BAR) and should be managed by the driver the same
>> way that local memory is on dgpu platforms (which includes
>> setting the "lmem" bit on page table entries). We use the term
>> "local stolen memory" to refer to this model.
>>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>
>> Signed-off-by: CQ Tang <cq.tang@intel.com>
>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>> Original-author: CQ Tang
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 113 +++++++++++++++++----
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
>> drivers/gpu/drm/i915/i915_drv.h | 3 +
>> 3 files changed, 100 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>> index acc561c0f0aa..bad5250fb764 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>> @@ -77,6 +77,19 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
>> mutex_unlock(&i915->mm.stolen_lock);
>> }
>>
>> +static bool is_dsm_invalid(struct drm_i915_private *i915, struct resource *dsm)
>
> Abstracting this as a separate function looks like a separate patch.
>
> I generally recommend using positive naming, "is dsm valid", to avoid
> any double negatives that might pop up, now or in the
> future. !is_dsm_invalid() gets slower for human brains to parse.
sure will change it.
Thanks,
Aravind.
>
> BR,
> Jani.
>
>
>> +{
>> + if (!HAS_BAR2_SMEM_STOLEN(i915)) {
>> + if (dsm->start == 0)
>> + return true;
>> + }
>> +
>> + if (dsm->end <= dsm->start)
>> + return true;
>> +
>> + return false;
>> +}
>> +
>> static int i915_adjust_stolen(struct drm_i915_private *i915,
>> struct resource *dsm)
>> {
>> @@ -84,7 +97,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
>> struct intel_uncore *uncore = ggtt->vm.gt->uncore;
>> struct resource *r;
>>
>> - if (dsm->start == 0 || dsm->end <= dsm->start)
>> + if (is_dsm_invalid(i915, dsm))
>> return -EINVAL;
>>
>> /*
>> @@ -136,7 +149,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
>> * overlaps with the non-stolen system memory range, since lmem is local
>> * to the gpu.
>> */
>> - if (HAS_LMEM(i915))
>> + if (HAS_LMEM(i915) || HAS_BAR2_SMEM_STOLEN(i915))
>> return 0;
>>
>> /*
>> @@ -371,8 +384,6 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
>>
>> drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
>>
>> - *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
>> -
>> switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
>> case GEN8_STOLEN_RESERVED_1M:
>> *size = 1024 * 1024;
>> @@ -390,6 +401,12 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
>> *size = 8 * 1024 * 1024;
>> MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
>> }
>> +
>> + if ((GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) && !IS_DGFX(i915))
>> + /* the base is initialized to stolen top so subtract size to get base */
>> + *base -= *size;
>> + else
>> + *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
>> }
>>
>> static int i915_gem_init_stolen(struct intel_memory_region *mem)
>> @@ -423,8 +440,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
>> if (i915_adjust_stolen(i915, &i915->dsm))
>> return 0;
>>
>> - GEM_BUG_ON(i915->dsm.start == 0);
>> - GEM_BUG_ON(i915->dsm.end <= i915->dsm.start);
>> + GEM_BUG_ON(is_dsm_invalid(i915, &i915->dsm));
>>
>> stolen_top = i915->dsm.end + 1;
>> reserved_base = stolen_top;
>> @@ -796,6 +812,46 @@ static const struct intel_memory_region_ops i915_region_stolen_lmem_ops = {
>> .init_object = _i915_gem_object_stolen_init,
>> };
>>
>> +static int get_mtl_gms_size(struct intel_uncore *uncore)
>> +{
>> + u16 ggc, gms;
>> +
>> + ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
>> +
>> + /* check GGMS, should be fixed 0x3 (8MB) */
>> + if ((ggc & 0xc0) != 0xc0)
>> + return -EIO;
>> +
>> + /* return valid GMS value, -EIO if invalid */
>> + gms = ggc >> 8;
>> + switch (gms) {
>> + case 0x0 ... 0x10:
>> + return gms * 32;
>> + case 0x20:
>> + return 1024;
>> + case 0x30:
>> + return 1536;
>> + case 0x40:
>> + return 2048;
>> + case 0xf0 ... 0xfe:
>> + return (gms - 0xf0 + 1) * 4;
>> + default:
>> + return -EIO;
>> + }
>> +}
>> +
>> +static inline bool lmembar_is_igpu_stolen(struct drm_i915_private *i915)
>> +{
>> + u32 regions = RUNTIME_INFO(i915)->memory_regions;
>> +
>> + if (regions & REGION_LMEM)
>> + return false;
>> +
>> + drm_WARN_ON(&i915->drm, (regions & REGION_STOLEN_LMEM) == 0);
>> +
>> + return true;
>> +}
>> +
>> struct intel_memory_region *
>> i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>> u16 instance)
>> @@ -806,19 +862,16 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>> struct intel_memory_region *mem;
>> resource_size_t io_start, io_size;
>> resource_size_t min_page_size;
>> + int ret;
>>
>> if (WARN_ON_ONCE(instance))
>> return ERR_PTR(-ENODEV);
>>
>> - if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
>> + if (!i915_pci_resource_valid(pdev, GFXMEM_BAR))
>> return ERR_PTR(-ENXIO);
>>
>> - /* Use DSM base address instead for stolen memory */
>> - dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
>> - if (IS_DG1(uncore->i915)) {
>> - lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
>> - if (WARN_ON(lmem_size < dsm_base))
>> - return ERR_PTR(-ENODEV);
>> + if (lmembar_is_igpu_stolen(i915) || IS_DG1(i915)) {
>> + lmem_size = pci_resource_len(pdev, GFXMEM_BAR);
>> } else {
>> resource_size_t lmem_range;
>>
>> @@ -827,13 +880,39 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>> lmem_size *= SZ_1G;
>> }
>>
>> - dsm_size = lmem_size - dsm_base;
>> - if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
>> + if (HAS_BAR2_SMEM_STOLEN(i915)) {
>> + /*
>> + * MTL dsm size is in GGC register, not the bar size.
>> + * also MTL uses offset to DSMBASE in ptes, so i915
>> + * uses dsm_base = 0 to setup stolen region.
>> + */
>> + ret = get_mtl_gms_size(uncore);
>> + if (ret < 0) {
>> + drm_err(&i915->drm, "invalid MTL GGC register setting\n");
>> + return ERR_PTR(ret);
>> + }
>> +
>> + dsm_base = 0;
>> + dsm_size = (resource_size_t)(ret * SZ_1M);
>> +
>> + GEM_BUG_ON(pci_resource_len(pdev, GFXMEM_BAR) != 256 * SZ_1M);
>> + GEM_BUG_ON((dsm_size + 8 * SZ_1M) > lmem_size);
>> + } else {
>> + /* Use DSM base address instead for stolen memory */
>> + dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
>> + if (WARN_ON(lmem_size < dsm_base))
>> + return ERR_PTR(-ENODEV);
>> + dsm_size = lmem_size - dsm_base;
>> + }
>> +
>> + io_size = dsm_size;
>> + if (pci_resource_len(pdev, GFXMEM_BAR) < dsm_size) {
>> io_start = 0;
>> io_size = 0;
>> + } else if (HAS_BAR2_SMEM_STOLEN(i915)) {
>> + io_start = pci_resource_start(pdev, GFXMEM_BAR) + 8 * SZ_1M;
>> } else {
>> - io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base;
>> - io_size = dsm_size;
>> + io_start = pci_resource_start(pdev, GFXMEM_BAR) + dsm_base;
>> }
>>
>> min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> index 30cf5c3369d9..b31fe0fb013f 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> @@ -931,7 +931,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>> unsigned int size;
>> u16 snb_gmch_ctl;
>>
>> - if (!HAS_LMEM(i915)) {
>> + if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) {
>> if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
>> return -ENXIO;
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 134fc1621821..ef3120322077 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -973,6 +973,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>
>> #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
>>
>> +#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
>> + GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>> +
>> /* intel_device_info.c */
>> static inline struct intel_device_info *
>> mkwrite_device_info(struct drm_i915_private *dev_priv)
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
@ 2022-09-21 6:32 ` Iddamsetty, Aravind
0 siblings, 0 replies; 22+ messages in thread
From: Iddamsetty, Aravind @ 2022-09-21 6:32 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: lucas.demarchi, dri-devel
On 20-09-2022 13:05, Jani Nikula wrote:
> On Tue, 20 Sep 2022, Aravind Iddamsetty <aravind.iddamsetty@intel.com> wrote:
>> As an integrated GPU, MTL does not have local memory and
>> HAS_LMEM() returns false. However the platform's stolen memory
>> is presented via BAR2 (i.e., the BAR we traditionally consider
>> to be the LMEM BAR) and should be managed by the driver the same
>> way that local memory is on dgpu platforms (which includes
>> setting the "lmem" bit on page table entries). We use the term
>> "local stolen memory" to refer to this model.
>>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>
>> Signed-off-by: CQ Tang <cq.tang@intel.com>
>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>> Original-author: CQ Tang
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 113 +++++++++++++++++----
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
>> drivers/gpu/drm/i915/i915_drv.h | 3 +
>> 3 files changed, 100 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>> index acc561c0f0aa..bad5250fb764 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>> @@ -77,6 +77,19 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
>> mutex_unlock(&i915->mm.stolen_lock);
>> }
>>
>> +static bool is_dsm_invalid(struct drm_i915_private *i915, struct resource *dsm)
>
> Abstracting this as a separate function looks like a separate patch.
>
> I generally recommend using positive naming, "is dsm valid", to avoid
> any double negatives that might pop up, now or in the
> future. !is_dsm_invalid() gets slower for human brains to parse.
sure will change it.
Thanks,
Aravind.
>
> BR,
> Jani.
>
>
>> +{
>> + if (!HAS_BAR2_SMEM_STOLEN(i915)) {
>> + if (dsm->start == 0)
>> + return true;
>> + }
>> +
>> + if (dsm->end <= dsm->start)
>> + return true;
>> +
>> + return false;
>> +}
>> +
>> static int i915_adjust_stolen(struct drm_i915_private *i915,
>> struct resource *dsm)
>> {
>> @@ -84,7 +97,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
>> struct intel_uncore *uncore = ggtt->vm.gt->uncore;
>> struct resource *r;
>>
>> - if (dsm->start == 0 || dsm->end <= dsm->start)
>> + if (is_dsm_invalid(i915, dsm))
>> return -EINVAL;
>>
>> /*
>> @@ -136,7 +149,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
>> * overlaps with the non-stolen system memory range, since lmem is local
>> * to the gpu.
>> */
>> - if (HAS_LMEM(i915))
>> + if (HAS_LMEM(i915) || HAS_BAR2_SMEM_STOLEN(i915))
>> return 0;
>>
>> /*
>> @@ -371,8 +384,6 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
>>
>> drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
>>
>> - *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
>> -
>> switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
>> case GEN8_STOLEN_RESERVED_1M:
>> *size = 1024 * 1024;
>> @@ -390,6 +401,12 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
>> *size = 8 * 1024 * 1024;
>> MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
>> }
>> +
>> + if ((GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) && !IS_DGFX(i915))
>> + /* the base is initialized to stolen top so subtract size to get base */
>> + *base -= *size;
>> + else
>> + *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
>> }
>>
>> static int i915_gem_init_stolen(struct intel_memory_region *mem)
>> @@ -423,8 +440,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
>> if (i915_adjust_stolen(i915, &i915->dsm))
>> return 0;
>>
>> - GEM_BUG_ON(i915->dsm.start == 0);
>> - GEM_BUG_ON(i915->dsm.end <= i915->dsm.start);
>> + GEM_BUG_ON(is_dsm_invalid(i915, &i915->dsm));
>>
>> stolen_top = i915->dsm.end + 1;
>> reserved_base = stolen_top;
>> @@ -796,6 +812,46 @@ static const struct intel_memory_region_ops i915_region_stolen_lmem_ops = {
>> .init_object = _i915_gem_object_stolen_init,
>> };
>>
>> +static int get_mtl_gms_size(struct intel_uncore *uncore)
>> +{
>> + u16 ggc, gms;
>> +
>> + ggc = intel_uncore_read16(uncore, _MMIO(0x108040));
>> +
>> + /* check GGMS, should be fixed 0x3 (8MB) */
>> + if ((ggc & 0xc0) != 0xc0)
>> + return -EIO;
>> +
>> + /* return valid GMS value, -EIO if invalid */
>> + gms = ggc >> 8;
>> + switch (gms) {
>> + case 0x0 ... 0x10:
>> + return gms * 32;
>> + case 0x20:
>> + return 1024;
>> + case 0x30:
>> + return 1536;
>> + case 0x40:
>> + return 2048;
>> + case 0xf0 ... 0xfe:
>> + return (gms - 0xf0 + 1) * 4;
>> + default:
>> + return -EIO;
>> + }
>> +}
>> +
>> +static inline bool lmembar_is_igpu_stolen(struct drm_i915_private *i915)
>> +{
>> + u32 regions = RUNTIME_INFO(i915)->memory_regions;
>> +
>> + if (regions & REGION_LMEM)
>> + return false;
>> +
>> + drm_WARN_ON(&i915->drm, (regions & REGION_STOLEN_LMEM) == 0);
>> +
>> + return true;
>> +}
>> +
>> struct intel_memory_region *
>> i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>> u16 instance)
>> @@ -806,19 +862,16 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>> struct intel_memory_region *mem;
>> resource_size_t io_start, io_size;
>> resource_size_t min_page_size;
>> + int ret;
>>
>> if (WARN_ON_ONCE(instance))
>> return ERR_PTR(-ENODEV);
>>
>> - if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
>> + if (!i915_pci_resource_valid(pdev, GFXMEM_BAR))
>> return ERR_PTR(-ENXIO);
>>
>> - /* Use DSM base address instead for stolen memory */
>> - dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
>> - if (IS_DG1(uncore->i915)) {
>> - lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
>> - if (WARN_ON(lmem_size < dsm_base))
>> - return ERR_PTR(-ENODEV);
>> + if (lmembar_is_igpu_stolen(i915) || IS_DG1(i915)) {
>> + lmem_size = pci_resource_len(pdev, GFXMEM_BAR);
>> } else {
>> resource_size_t lmem_range;
>>
>> @@ -827,13 +880,39 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>> lmem_size *= SZ_1G;
>> }
>>
>> - dsm_size = lmem_size - dsm_base;
>> - if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
>> + if (HAS_BAR2_SMEM_STOLEN(i915)) {
>> + /*
>> + * MTL dsm size is in GGC register, not the bar size.
>> + * also MTL uses offset to DSMBASE in ptes, so i915
>> + * uses dsm_base = 0 to setup stolen region.
>> + */
>> + ret = get_mtl_gms_size(uncore);
>> + if (ret < 0) {
>> + drm_err(&i915->drm, "invalid MTL GGC register setting\n");
>> + return ERR_PTR(ret);
>> + }
>> +
>> + dsm_base = 0;
>> + dsm_size = (resource_size_t)(ret * SZ_1M);
>> +
>> + GEM_BUG_ON(pci_resource_len(pdev, GFXMEM_BAR) != 256 * SZ_1M);
>> + GEM_BUG_ON((dsm_size + 8 * SZ_1M) > lmem_size);
>> + } else {
>> + /* Use DSM base address instead for stolen memory */
>> + dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
>> + if (WARN_ON(lmem_size < dsm_base))
>> + return ERR_PTR(-ENODEV);
>> + dsm_size = lmem_size - dsm_base;
>> + }
>> +
>> + io_size = dsm_size;
>> + if (pci_resource_len(pdev, GFXMEM_BAR) < dsm_size) {
>> io_start = 0;
>> io_size = 0;
>> + } else if (HAS_BAR2_SMEM_STOLEN(i915)) {
>> + io_start = pci_resource_start(pdev, GFXMEM_BAR) + 8 * SZ_1M;
>> } else {
>> - io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base;
>> - io_size = dsm_size;
>> + io_start = pci_resource_start(pdev, GFXMEM_BAR) + dsm_base;
>> }
>>
>> min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> index 30cf5c3369d9..b31fe0fb013f 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> @@ -931,7 +931,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>> unsigned int size;
>> u16 snb_gmch_ctl;
>>
>> - if (!HAS_LMEM(i915)) {
>> + if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) {
>> if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
>> return -ENXIO;
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 134fc1621821..ef3120322077 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -973,6 +973,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>
>> #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
>>
>> +#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
>> + GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>> +
>> /* intel_device_info.c */
>> static inline struct intel_device_info *
>> mkwrite_device_info(struct drm_i915_private *dev_priv)
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
2022-09-21 6:30 ` Iddamsetty, Aravind
@ 2022-09-22 13:56 ` Lucas De Marchi
2022-09-22 15:56 ` Iddamsetty, Aravind
0 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2022-09-22 13:56 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: intel-gfx, dri-devel
On Wed, Sep 21, 2022 at 12:00:38PM +0530, Iddamsetty, Aravind wrote:
>replying here for earlier comments too.
>
>On 21-09-2022 01:35, Lucas De Marchi wrote:
>> On Tue, Sep 20, 2022 at 01:31:49AM -0700, Lucas De Marchi wrote:
>>> On Tue, Sep 20, 2022 at 12:49:40PM +0530, Aravind Iddamsetty wrote:
>>>> As an integrated GPU, MTL does not have local memory and
>>>> HAS_LMEM() returns false. However the platform's stolen memory
>>>> is presented via BAR2 (i.e., the BAR we traditionally consider
>>>> to be the LMEM BAR) and should be managed by the driver the same
>>>> way that local memory is on dgpu platforms (which includes
>>>> setting the "lmem" bit on page table entries). We use the term
>>>> "local stolen memory" to refer to this model.
>>>>
>>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>>>
>>>> Signed-off-by: CQ Tang <cq.tang@intel.com>
>>>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>>>> Original-author: CQ Tang
>>>> ---
>>>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 113 +++++++++++++++++----
>>>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
>>>> drivers/gpu/drm/i915/i915_drv.h | 3 +
>>>> 3 files changed, 100 insertions(+), 18 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>>> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>>> index acc561c0f0aa..bad5250fb764 100644
>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>>> @@ -77,6 +77,19 @@ void i915_gem_stolen_remove_node(struct
>>>> drm_i915_private *i915,
>>>> mutex_unlock(&i915->mm.stolen_lock);
>>>> }
>>>>
>>>> +static bool is_dsm_invalid(struct drm_i915_private *i915, struct
>>>> resource *dsm)
>>>> +{
>>>> + if (!HAS_BAR2_SMEM_STOLEN(i915)) {
>>>
>>> I called a similar function as is_dsm_valid() in
>>> https://patchwork.freedesktop.org/series/108620/
>>>
>>> sounds weird with "invalid" and the double negation on return early
>>> style.
>
>sure, will change it hope i can use that from your patch.
that patch is now pushed, so now you can reuse it.
Lucas De Marchi
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: enable local stolen memory
2022-09-22 13:56 ` Lucas De Marchi
@ 2022-09-22 15:56 ` Iddamsetty, Aravind
0 siblings, 0 replies; 22+ messages in thread
From: Iddamsetty, Aravind @ 2022-09-22 15:56 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On 22-09-2022 19:26, Lucas De Marchi wrote:
> On Wed, Sep 21, 2022 at 12:00:38PM +0530, Iddamsetty, Aravind wrote:
>> replying here for earlier comments too.
>>
>> On 21-09-2022 01:35, Lucas De Marchi wrote:
>>> On Tue, Sep 20, 2022 at 01:31:49AM -0700, Lucas De Marchi wrote:
>>>> On Tue, Sep 20, 2022 at 12:49:40PM +0530, Aravind Iddamsetty wrote:
>>>>> As an integrated GPU, MTL does not have local memory and
>>>>> HAS_LMEM() returns false. However the platform's stolen memory
>>>>> is presented via BAR2 (i.e., the BAR we traditionally consider
>>>>> to be the LMEM BAR) and should be managed by the driver the same
>>>>> way that local memory is on dgpu platforms (which includes
>>>>> setting the "lmem" bit on page table entries). We use the term
>>>>> "local stolen memory" to refer to this model.
>>>>>
>>>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>>>>
>>>>> Signed-off-by: CQ Tang <cq.tang@intel.com>
>>>>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>>>>> Original-author: CQ Tang
>>>>> ---
>>>>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 113 +++++++++++++++++----
>>>>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
>>>>> drivers/gpu/drm/i915/i915_drv.h | 3 +
>>>>> 3 files changed, 100 insertions(+), 18 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>>>> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>>>> index acc561c0f0aa..bad5250fb764 100644
>>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>>>>> @@ -77,6 +77,19 @@ void i915_gem_stolen_remove_node(struct
>>>>> drm_i915_private *i915,
>>>>> mutex_unlock(&i915->mm.stolen_lock);
>>>>> }
>>>>>
>>>>> +static bool is_dsm_invalid(struct drm_i915_private *i915, struct
>>>>> resource *dsm)
>>>>> +{
>>>>> + if (!HAS_BAR2_SMEM_STOLEN(i915)) {
>>>>
>>>> I called a similar function as is_dsm_valid() in
>>>> https://patchwork.freedesktop.org/series/108620/
>>>>
>>>> sounds weird with "invalid" and the double negation on return early
>>>> style.
>>
>> sure, will change it hope i can use that from your patch.
>
> that patch is now pushed, so now you can reuse it.
Thanks for the info and help.
Aravind.
>
> Lucas De Marchi
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2022-09-22 15:56 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-20 7:19 [PATCH 1/1] drm/i915/mtl: enable local stolen memory Aravind Iddamsetty
2022-09-20 7:19 ` [Intel-gfx] " Aravind Iddamsetty
2022-09-20 7:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/1] " Patchwork
2022-09-20 7:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-20 7:35 ` [PATCH 1/1] " Jani Nikula
2022-09-20 7:35 ` [Intel-gfx] " Jani Nikula
2022-09-21 6:32 ` Iddamsetty, Aravind
2022-09-21 6:32 ` [Intel-gfx] " Iddamsetty, Aravind
2022-09-20 7:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/1] " Patchwork
2022-09-20 8:31 ` [Intel-gfx] [PATCH 1/1] " Lucas De Marchi
2022-09-20 20:05 ` Lucas De Marchi
2022-09-21 6:30 ` Iddamsetty, Aravind
2022-09-22 13:56 ` Lucas De Marchi
2022-09-22 15:56 ` Iddamsetty, Aravind
2022-09-20 11:52 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/1] " Patchwork
2022-09-20 16:57 ` [Intel-gfx] [PATCH 1/1] " Andi Shyti
2022-09-20 20:01 ` Lucas De Marchi
2022-09-20 20:01 ` Lucas De Marchi
2022-09-20 20:40 ` Matt Roper
2022-09-20 20:40 ` Matt Roper
2022-09-20 22:33 ` Andi Shyti
2022-09-20 22:33 ` Andi Shyti
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