From: Chunfeng Yun <chunfeng.yun@mediatek.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>, Vinod Koul <vkoul@kernel.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
Jitao Shi <jitao.shi@mediatek.com>,
Stanley Chu <stanley.chu@mediatek.com>
Subject: [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask
Date: Tue, 20 Sep 2022 17:00:33 +0800 [thread overview]
Message-ID: <20220920090038.15133-14-chunfeng.yun@mediatek.com> (raw)
In-Reply-To: <20220920090038.15133-1-chunfeng.yun@mediatek.com>
Use GENMASK() macro to generate bits mask
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 53 ++++++++++---------
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
index 7a847954594f..5c257d67d7be 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
@@ -9,9 +9,9 @@
#define MIPITX_DSI_CON 0x00
#define RG_DSI_LDOCORE_EN BIT(0)
#define RG_DSI_CKG_LDOOUT_EN BIT(1)
-#define RG_DSI_BCLK_SEL (3 << 2)
-#define RG_DSI_LD_IDX_SEL (7 << 4)
-#define RG_DSI_PHYCLK_SEL (2 << 8)
+#define RG_DSI_BCLK_SEL GENMASK(3, 2)
+#define RG_DSI_LD_IDX_SEL GENMASK(6, 4)
+#define RG_DSI_PHYCLK_SEL GENMASK(9, 8)
#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
#define RG_DSI_LPTX_CLMP_EN BIT(11)
@@ -27,41 +27,46 @@
#define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
#define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
-#define RG_DSI_LNTx_RT_CODE (0xf << 8)
+#define RG_DSI_LNTx_RT_CODE GENMASK(11, 8)
#define MIPITX_DSI_TOP_CON 0x40
#define RG_DSI_LNT_INTR_EN BIT(0)
#define RG_DSI_LNT_HS_BIAS_EN BIT(1)
#define RG_DSI_LNT_IMP_CAL_EN BIT(2)
#define RG_DSI_LNT_TESTMODE_EN BIT(3)
-#define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4)
-#define RG_DSI_LNT_AIO_SEL (7 << 8)
+#define RG_DSI_LNT_IMP_CAL_CODE GENMASK(7, 4)
+#define RG_DSI_LNT_AIO_SEL GENMASK(10, 8)
#define RG_DSI_PAD_TIE_LOW_EN BIT(11)
#define RG_DSI_DEBUG_INPUT_EN BIT(12)
-#define RG_DSI_PRESERVE (7 << 13)
+#define RG_DSI_PRESERVE GENMASK(15, 13)
#define MIPITX_DSI_BG_CON 0x44
#define RG_DSI_BG_CORE_EN BIT(0)
#define RG_DSI_BG_CKEN BIT(1)
-#define RG_DSI_BG_DIV (0x3 << 2)
+#define RG_DSI_BG_DIV GENMASK(3, 2)
#define RG_DSI_BG_FAST_CHARGE BIT(4)
-#define RG_DSI_VOUT_MSK (0x3ffff << 5)
-#define RG_DSI_V12_SEL (7 << 5)
-#define RG_DSI_V10_SEL (7 << 8)
-#define RG_DSI_V072_SEL (7 << 11)
-#define RG_DSI_V04_SEL (7 << 14)
-#define RG_DSI_V032_SEL (7 << 17)
-#define RG_DSI_V02_SEL (7 << 20)
-#define RG_DSI_BG_R1_TRIM (0xf << 24)
-#define RG_DSI_BG_R2_TRIM (0xf << 28)
+
+#define RG_DSI_V12_SEL GENMASK(7, 5)
+#define RG_DSI_V10_SEL GENMASK(10, 8)
+#define RG_DSI_V072_SEL GENMASK(13, 11)
+#define RG_DSI_V04_SEL GENMASK(16, 14)
+#define RG_DSI_V032_SEL GENMASK(19, 17)
+#define RG_DSI_V02_SEL GENMASK(22, 20)
+#define RG_DSI_VOUT_MSK \
+ (RG_DSI_V12_SEL | RG_DSI_V10_SEL | RG_DSI_V072_SEL | \
+ RG_DSI_V04_SEL | RG_DSI_V032_SEL | RG_DSI_V02_SEL)
+#define RG_DSI_BG_R1_TRIM GENMASK(27, 24)
+#define RG_DSI_BG_R2_TRIM GENMASK(31, 28)
#define MIPITX_DSI_PLL_CON0 0x50
#define RG_DSI_MPPLL_PLL_EN BIT(0)
-#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1)
-#define RG_DSI_MPPLL_PREDIV (3 << 1)
-#define RG_DSI_MPPLL_TXDIV0 (3 << 3)
-#define RG_DSI_MPPLL_TXDIV1 (3 << 5)
-#define RG_DSI_MPPLL_POSDIV (7 << 7)
+#define RG_DSI_MPPLL_PREDIV GENMASK(2, 1)
+#define RG_DSI_MPPLL_TXDIV0 GENMASK(4, 3)
+#define RG_DSI_MPPLL_TXDIV1 GENMASK(6, 5)
+#define RG_DSI_MPPLL_POSDIV GENMASK(9, 7)
+#define RG_DSI_MPPLL_DIV_MSK \
+ (RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | \
+ RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV)
#define RG_DSI_MPPLL_MONVC_EN BIT(10)
#define RG_DSI_MPPLL_MONREF_EN BIT(11)
#define RG_DSI_MPPLL_VOD_EN BIT(12)
@@ -70,12 +75,12 @@
#define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
#define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
-#define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16)
+#define RG_DSI_MPPLL_SDM_SSC_PRD GENMASK(31, 16)
#define MIPITX_DSI_PLL_CON2 0x58
#define MIPITX_DSI_PLL_TOP 0x64
-#define RG_DSI_MPPLL_PRESERVE (0xff << 8)
+#define RG_DSI_MPPLL_PRESERVE GENMASK(15, 8)
#define MIPITX_DSI_PLL_PWR 0x68
#define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Chunfeng Yun <chunfeng.yun@mediatek.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>, Vinod Koul <vkoul@kernel.org>
Cc: Jitao Shi <jitao.shi@mediatek.com>,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
Kishon Vijay Abraham I <kishon@ti.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-mediatek@lists.infradead.org,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Stanley Chu <stanley.chu@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask
Date: Tue, 20 Sep 2022 17:00:33 +0800 [thread overview]
Message-ID: <20220920090038.15133-14-chunfeng.yun@mediatek.com> (raw)
In-Reply-To: <20220920090038.15133-1-chunfeng.yun@mediatek.com>
Use GENMASK() macro to generate bits mask
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 53 ++++++++++---------
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
index 7a847954594f..5c257d67d7be 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
@@ -9,9 +9,9 @@
#define MIPITX_DSI_CON 0x00
#define RG_DSI_LDOCORE_EN BIT(0)
#define RG_DSI_CKG_LDOOUT_EN BIT(1)
-#define RG_DSI_BCLK_SEL (3 << 2)
-#define RG_DSI_LD_IDX_SEL (7 << 4)
-#define RG_DSI_PHYCLK_SEL (2 << 8)
+#define RG_DSI_BCLK_SEL GENMASK(3, 2)
+#define RG_DSI_LD_IDX_SEL GENMASK(6, 4)
+#define RG_DSI_PHYCLK_SEL GENMASK(9, 8)
#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
#define RG_DSI_LPTX_CLMP_EN BIT(11)
@@ -27,41 +27,46 @@
#define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
#define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
-#define RG_DSI_LNTx_RT_CODE (0xf << 8)
+#define RG_DSI_LNTx_RT_CODE GENMASK(11, 8)
#define MIPITX_DSI_TOP_CON 0x40
#define RG_DSI_LNT_INTR_EN BIT(0)
#define RG_DSI_LNT_HS_BIAS_EN BIT(1)
#define RG_DSI_LNT_IMP_CAL_EN BIT(2)
#define RG_DSI_LNT_TESTMODE_EN BIT(3)
-#define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4)
-#define RG_DSI_LNT_AIO_SEL (7 << 8)
+#define RG_DSI_LNT_IMP_CAL_CODE GENMASK(7, 4)
+#define RG_DSI_LNT_AIO_SEL GENMASK(10, 8)
#define RG_DSI_PAD_TIE_LOW_EN BIT(11)
#define RG_DSI_DEBUG_INPUT_EN BIT(12)
-#define RG_DSI_PRESERVE (7 << 13)
+#define RG_DSI_PRESERVE GENMASK(15, 13)
#define MIPITX_DSI_BG_CON 0x44
#define RG_DSI_BG_CORE_EN BIT(0)
#define RG_DSI_BG_CKEN BIT(1)
-#define RG_DSI_BG_DIV (0x3 << 2)
+#define RG_DSI_BG_DIV GENMASK(3, 2)
#define RG_DSI_BG_FAST_CHARGE BIT(4)
-#define RG_DSI_VOUT_MSK (0x3ffff << 5)
-#define RG_DSI_V12_SEL (7 << 5)
-#define RG_DSI_V10_SEL (7 << 8)
-#define RG_DSI_V072_SEL (7 << 11)
-#define RG_DSI_V04_SEL (7 << 14)
-#define RG_DSI_V032_SEL (7 << 17)
-#define RG_DSI_V02_SEL (7 << 20)
-#define RG_DSI_BG_R1_TRIM (0xf << 24)
-#define RG_DSI_BG_R2_TRIM (0xf << 28)
+
+#define RG_DSI_V12_SEL GENMASK(7, 5)
+#define RG_DSI_V10_SEL GENMASK(10, 8)
+#define RG_DSI_V072_SEL GENMASK(13, 11)
+#define RG_DSI_V04_SEL GENMASK(16, 14)
+#define RG_DSI_V032_SEL GENMASK(19, 17)
+#define RG_DSI_V02_SEL GENMASK(22, 20)
+#define RG_DSI_VOUT_MSK \
+ (RG_DSI_V12_SEL | RG_DSI_V10_SEL | RG_DSI_V072_SEL | \
+ RG_DSI_V04_SEL | RG_DSI_V032_SEL | RG_DSI_V02_SEL)
+#define RG_DSI_BG_R1_TRIM GENMASK(27, 24)
+#define RG_DSI_BG_R2_TRIM GENMASK(31, 28)
#define MIPITX_DSI_PLL_CON0 0x50
#define RG_DSI_MPPLL_PLL_EN BIT(0)
-#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1)
-#define RG_DSI_MPPLL_PREDIV (3 << 1)
-#define RG_DSI_MPPLL_TXDIV0 (3 << 3)
-#define RG_DSI_MPPLL_TXDIV1 (3 << 5)
-#define RG_DSI_MPPLL_POSDIV (7 << 7)
+#define RG_DSI_MPPLL_PREDIV GENMASK(2, 1)
+#define RG_DSI_MPPLL_TXDIV0 GENMASK(4, 3)
+#define RG_DSI_MPPLL_TXDIV1 GENMASK(6, 5)
+#define RG_DSI_MPPLL_POSDIV GENMASK(9, 7)
+#define RG_DSI_MPPLL_DIV_MSK \
+ (RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | \
+ RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV)
#define RG_DSI_MPPLL_MONVC_EN BIT(10)
#define RG_DSI_MPPLL_MONREF_EN BIT(11)
#define RG_DSI_MPPLL_VOD_EN BIT(12)
@@ -70,12 +75,12 @@
#define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
#define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
-#define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16)
+#define RG_DSI_MPPLL_SDM_SSC_PRD GENMASK(31, 16)
#define MIPITX_DSI_PLL_CON2 0x58
#define MIPITX_DSI_PLL_TOP 0x64
-#define RG_DSI_MPPLL_PRESERVE (0xff << 8)
+#define RG_DSI_MPPLL_PRESERVE GENMASK(15, 8)
#define MIPITX_DSI_PLL_PWR 0x68
#define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Chunfeng Yun <chunfeng.yun@mediatek.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>, Vinod Koul <vkoul@kernel.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
Jitao Shi <jitao.shi@mediatek.com>,
Stanley Chu <stanley.chu@mediatek.com>
Subject: [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask
Date: Tue, 20 Sep 2022 17:00:33 +0800 [thread overview]
Message-ID: <20220920090038.15133-14-chunfeng.yun@mediatek.com> (raw)
In-Reply-To: <20220920090038.15133-1-chunfeng.yun@mediatek.com>
Use GENMASK() macro to generate bits mask
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 53 ++++++++++---------
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
index 7a847954594f..5c257d67d7be 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
@@ -9,9 +9,9 @@
#define MIPITX_DSI_CON 0x00
#define RG_DSI_LDOCORE_EN BIT(0)
#define RG_DSI_CKG_LDOOUT_EN BIT(1)
-#define RG_DSI_BCLK_SEL (3 << 2)
-#define RG_DSI_LD_IDX_SEL (7 << 4)
-#define RG_DSI_PHYCLK_SEL (2 << 8)
+#define RG_DSI_BCLK_SEL GENMASK(3, 2)
+#define RG_DSI_LD_IDX_SEL GENMASK(6, 4)
+#define RG_DSI_PHYCLK_SEL GENMASK(9, 8)
#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
#define RG_DSI_LPTX_CLMP_EN BIT(11)
@@ -27,41 +27,46 @@
#define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
#define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
-#define RG_DSI_LNTx_RT_CODE (0xf << 8)
+#define RG_DSI_LNTx_RT_CODE GENMASK(11, 8)
#define MIPITX_DSI_TOP_CON 0x40
#define RG_DSI_LNT_INTR_EN BIT(0)
#define RG_DSI_LNT_HS_BIAS_EN BIT(1)
#define RG_DSI_LNT_IMP_CAL_EN BIT(2)
#define RG_DSI_LNT_TESTMODE_EN BIT(3)
-#define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4)
-#define RG_DSI_LNT_AIO_SEL (7 << 8)
+#define RG_DSI_LNT_IMP_CAL_CODE GENMASK(7, 4)
+#define RG_DSI_LNT_AIO_SEL GENMASK(10, 8)
#define RG_DSI_PAD_TIE_LOW_EN BIT(11)
#define RG_DSI_DEBUG_INPUT_EN BIT(12)
-#define RG_DSI_PRESERVE (7 << 13)
+#define RG_DSI_PRESERVE GENMASK(15, 13)
#define MIPITX_DSI_BG_CON 0x44
#define RG_DSI_BG_CORE_EN BIT(0)
#define RG_DSI_BG_CKEN BIT(1)
-#define RG_DSI_BG_DIV (0x3 << 2)
+#define RG_DSI_BG_DIV GENMASK(3, 2)
#define RG_DSI_BG_FAST_CHARGE BIT(4)
-#define RG_DSI_VOUT_MSK (0x3ffff << 5)
-#define RG_DSI_V12_SEL (7 << 5)
-#define RG_DSI_V10_SEL (7 << 8)
-#define RG_DSI_V072_SEL (7 << 11)
-#define RG_DSI_V04_SEL (7 << 14)
-#define RG_DSI_V032_SEL (7 << 17)
-#define RG_DSI_V02_SEL (7 << 20)
-#define RG_DSI_BG_R1_TRIM (0xf << 24)
-#define RG_DSI_BG_R2_TRIM (0xf << 28)
+
+#define RG_DSI_V12_SEL GENMASK(7, 5)
+#define RG_DSI_V10_SEL GENMASK(10, 8)
+#define RG_DSI_V072_SEL GENMASK(13, 11)
+#define RG_DSI_V04_SEL GENMASK(16, 14)
+#define RG_DSI_V032_SEL GENMASK(19, 17)
+#define RG_DSI_V02_SEL GENMASK(22, 20)
+#define RG_DSI_VOUT_MSK \
+ (RG_DSI_V12_SEL | RG_DSI_V10_SEL | RG_DSI_V072_SEL | \
+ RG_DSI_V04_SEL | RG_DSI_V032_SEL | RG_DSI_V02_SEL)
+#define RG_DSI_BG_R1_TRIM GENMASK(27, 24)
+#define RG_DSI_BG_R2_TRIM GENMASK(31, 28)
#define MIPITX_DSI_PLL_CON0 0x50
#define RG_DSI_MPPLL_PLL_EN BIT(0)
-#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1)
-#define RG_DSI_MPPLL_PREDIV (3 << 1)
-#define RG_DSI_MPPLL_TXDIV0 (3 << 3)
-#define RG_DSI_MPPLL_TXDIV1 (3 << 5)
-#define RG_DSI_MPPLL_POSDIV (7 << 7)
+#define RG_DSI_MPPLL_PREDIV GENMASK(2, 1)
+#define RG_DSI_MPPLL_TXDIV0 GENMASK(4, 3)
+#define RG_DSI_MPPLL_TXDIV1 GENMASK(6, 5)
+#define RG_DSI_MPPLL_POSDIV GENMASK(9, 7)
+#define RG_DSI_MPPLL_DIV_MSK \
+ (RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | \
+ RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV)
#define RG_DSI_MPPLL_MONVC_EN BIT(10)
#define RG_DSI_MPPLL_MONREF_EN BIT(11)
#define RG_DSI_MPPLL_VOD_EN BIT(12)
@@ -70,12 +75,12 @@
#define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
#define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
-#define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16)
+#define RG_DSI_MPPLL_SDM_SSC_PRD GENMASK(31, 16)
#define MIPITX_DSI_PLL_CON2 0x58
#define MIPITX_DSI_PLL_TOP 0x64
-#define RG_DSI_MPPLL_PRESERVE (0xff << 8)
+#define RG_DSI_MPPLL_PRESERVE GENMASK(15, 8)
#define MIPITX_DSI_PLL_PWR 0x68
#define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
--
2.18.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Chunfeng Yun <chunfeng.yun@mediatek.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>, Vinod Koul <vkoul@kernel.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
Jitao Shi <jitao.shi@mediatek.com>,
Stanley Chu <stanley.chu@mediatek.com>
Subject: [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask
Date: Tue, 20 Sep 2022 17:00:33 +0800 [thread overview]
Message-ID: <20220920090038.15133-14-chunfeng.yun@mediatek.com> (raw)
In-Reply-To: <20220920090038.15133-1-chunfeng.yun@mediatek.com>
Use GENMASK() macro to generate bits mask
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 53 ++++++++++---------
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
index 7a847954594f..5c257d67d7be 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
@@ -9,9 +9,9 @@
#define MIPITX_DSI_CON 0x00
#define RG_DSI_LDOCORE_EN BIT(0)
#define RG_DSI_CKG_LDOOUT_EN BIT(1)
-#define RG_DSI_BCLK_SEL (3 << 2)
-#define RG_DSI_LD_IDX_SEL (7 << 4)
-#define RG_DSI_PHYCLK_SEL (2 << 8)
+#define RG_DSI_BCLK_SEL GENMASK(3, 2)
+#define RG_DSI_LD_IDX_SEL GENMASK(6, 4)
+#define RG_DSI_PHYCLK_SEL GENMASK(9, 8)
#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
#define RG_DSI_LPTX_CLMP_EN BIT(11)
@@ -27,41 +27,46 @@
#define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
#define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
-#define RG_DSI_LNTx_RT_CODE (0xf << 8)
+#define RG_DSI_LNTx_RT_CODE GENMASK(11, 8)
#define MIPITX_DSI_TOP_CON 0x40
#define RG_DSI_LNT_INTR_EN BIT(0)
#define RG_DSI_LNT_HS_BIAS_EN BIT(1)
#define RG_DSI_LNT_IMP_CAL_EN BIT(2)
#define RG_DSI_LNT_TESTMODE_EN BIT(3)
-#define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4)
-#define RG_DSI_LNT_AIO_SEL (7 << 8)
+#define RG_DSI_LNT_IMP_CAL_CODE GENMASK(7, 4)
+#define RG_DSI_LNT_AIO_SEL GENMASK(10, 8)
#define RG_DSI_PAD_TIE_LOW_EN BIT(11)
#define RG_DSI_DEBUG_INPUT_EN BIT(12)
-#define RG_DSI_PRESERVE (7 << 13)
+#define RG_DSI_PRESERVE GENMASK(15, 13)
#define MIPITX_DSI_BG_CON 0x44
#define RG_DSI_BG_CORE_EN BIT(0)
#define RG_DSI_BG_CKEN BIT(1)
-#define RG_DSI_BG_DIV (0x3 << 2)
+#define RG_DSI_BG_DIV GENMASK(3, 2)
#define RG_DSI_BG_FAST_CHARGE BIT(4)
-#define RG_DSI_VOUT_MSK (0x3ffff << 5)
-#define RG_DSI_V12_SEL (7 << 5)
-#define RG_DSI_V10_SEL (7 << 8)
-#define RG_DSI_V072_SEL (7 << 11)
-#define RG_DSI_V04_SEL (7 << 14)
-#define RG_DSI_V032_SEL (7 << 17)
-#define RG_DSI_V02_SEL (7 << 20)
-#define RG_DSI_BG_R1_TRIM (0xf << 24)
-#define RG_DSI_BG_R2_TRIM (0xf << 28)
+
+#define RG_DSI_V12_SEL GENMASK(7, 5)
+#define RG_DSI_V10_SEL GENMASK(10, 8)
+#define RG_DSI_V072_SEL GENMASK(13, 11)
+#define RG_DSI_V04_SEL GENMASK(16, 14)
+#define RG_DSI_V032_SEL GENMASK(19, 17)
+#define RG_DSI_V02_SEL GENMASK(22, 20)
+#define RG_DSI_VOUT_MSK \
+ (RG_DSI_V12_SEL | RG_DSI_V10_SEL | RG_DSI_V072_SEL | \
+ RG_DSI_V04_SEL | RG_DSI_V032_SEL | RG_DSI_V02_SEL)
+#define RG_DSI_BG_R1_TRIM GENMASK(27, 24)
+#define RG_DSI_BG_R2_TRIM GENMASK(31, 28)
#define MIPITX_DSI_PLL_CON0 0x50
#define RG_DSI_MPPLL_PLL_EN BIT(0)
-#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1)
-#define RG_DSI_MPPLL_PREDIV (3 << 1)
-#define RG_DSI_MPPLL_TXDIV0 (3 << 3)
-#define RG_DSI_MPPLL_TXDIV1 (3 << 5)
-#define RG_DSI_MPPLL_POSDIV (7 << 7)
+#define RG_DSI_MPPLL_PREDIV GENMASK(2, 1)
+#define RG_DSI_MPPLL_TXDIV0 GENMASK(4, 3)
+#define RG_DSI_MPPLL_TXDIV1 GENMASK(6, 5)
+#define RG_DSI_MPPLL_POSDIV GENMASK(9, 7)
+#define RG_DSI_MPPLL_DIV_MSK \
+ (RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | \
+ RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV)
#define RG_DSI_MPPLL_MONVC_EN BIT(10)
#define RG_DSI_MPPLL_MONREF_EN BIT(11)
#define RG_DSI_MPPLL_VOD_EN BIT(12)
@@ -70,12 +75,12 @@
#define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
#define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
-#define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16)
+#define RG_DSI_MPPLL_SDM_SSC_PRD GENMASK(31, 16)
#define MIPITX_DSI_PLL_CON2 0x58
#define MIPITX_DSI_PLL_TOP 0x64
-#define RG_DSI_MPPLL_PRESERVE (0xff << 8)
+#define RG_DSI_MPPLL_PRESERVE GENMASK(15, 8)
#define MIPITX_DSI_PLL_PWR 0x68
#define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-09-20 9:02 UTC|newest]
Thread overview: 156+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` [PATCH 01/18] phy: mediatek: add a new helper to update bitfield Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-22 2:36 ` Chunfeng Yun
2022-09-22 2:36 ` Chunfeng Yun
2022-09-22 2:36 ` Chunfeng Yun
2022-09-22 2:36 ` Chunfeng Yun
2022-09-22 7:17 ` AngeloGioacchino Del Regno
2022-09-22 7:17 ` AngeloGioacchino Del Regno
2022-09-22 7:17 ` AngeloGioacchino Del Regno
2022-09-22 7:17 ` AngeloGioacchino Del Regno
2022-09-23 6:03 ` Chunfeng Yun
2022-09-23 6:03 ` Chunfeng Yun
2022-09-23 6:03 ` Chunfeng Yun
2022-09-23 6:03 ` Chunfeng Yun
2022-09-20 9:00 ` [PATCH 02/18] phy: mediatek: tphy: remove macros to prepare bitfield value Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` [PATCH 03/18] phy: mediatek: xsphy: remove macros used " Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` [PATCH 04/18] phy: mediatek: ufs: use common register access helpers Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 05/18] phy: mediatek: pcie: use new helper to update register bits Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 06/18] phy: mediatek: hdmi: mt2701: use GENMASK and BIT to generate mask and bits Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 07/18] phy: mediatek: hdmi: mt2701: use FIELD_PREP to prepare bits field Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 08/18] phy: mediatek: hdmi: mt2701: use common helper to access registers Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 09/18] phy: mediatek: hdmi: mt8173: use GENMASK to generate bits mask Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 10/18] phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 11/18] phy: mediatek: hdmi: mt8173: use common helper to access registers Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 12/18] phy: mediatek: hdmi: remove register access helpers Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` Chunfeng Yun [this message]
2022-09-20 9:00 ` [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 14/18] phy: mediatek: mipi: mt8173: use FIELD_PREP to prepare bits field Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 15/18] phy: mediatek: mipi: mt8173: use common helper to access registers Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 16/18] phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 17/18] phy: mediatek: mipi: mt8183: use common helper to access registers Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 18/18] phy: mediatek: mipi: remove register access helpers Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-24 6:28 ` [PATCH 00/18] unify register access and macros Vinod Koul
2022-09-24 6:28 ` Vinod Koul
2022-09-24 6:28 ` Vinod Koul
2022-09-24 6:28 ` Vinod Koul
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220920090038.15133-14-chunfeng.yun@mediatek.com \
--to=chunfeng.yun@mediatek.com \
--cc=chunkuang.hu@kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=jitao.shi@mediatek.com \
--cc=kishon@ti.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-phy@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=p.zabel@pengutronix.de \
--cc=stanley.chu@mediatek.com \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.