* [PATCH] intel_idle: Add AlderLake-N support
@ 2022-09-20 12:58 Zhang Rui
2022-09-21 18:35 ` Rafael J. Wysocki
0 siblings, 1 reply; 2+ messages in thread
From: Zhang Rui @ 2022-09-20 12:58 UTC (permalink / raw)
To: rjw; +Cc: linux-pm, vinay.kumar, baieswara.reddy.sagili, rui.zhang
Similar to ther other AlderLake platforms, the C1 and C1E states on
ADL-N are mutually exclusive. Only one of them can be enabled at a time.
C1E is preferred on ADL-N for better energy efficiency.
C6S is also supported on this platform. Its latency is far bigger than
C6, but really close to C8 (PC8), thus it is not exposed as a separate
state.
Suggested-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Suggested-by: Vinay Kumar <vinay.kumar@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
---
drivers/idle/intel_idle.c | 51 +++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 3e101719689a..8d56b06ddca4 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -928,6 +928,51 @@ static struct cpuidle_state adl_l_cstates[] __initdata = {
.enter = NULL }
};
+static struct cpuidle_state adl_n_cstates[] __initdata = {
+ {
+ .name = "C1",
+ .desc = "MWAIT 0x00",
+ .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE,
+ .exit_latency = 1,
+ .target_residency = 1,
+ .enter = &intel_idle,
+ .enter_s2idle = intel_idle_s2idle, },
+ {
+ .name = "C1E",
+ .desc = "MWAIT 0x01",
+ .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
+ .exit_latency = 2,
+ .target_residency = 4,
+ .enter = &intel_idle,
+ .enter_s2idle = intel_idle_s2idle, },
+ {
+ .name = "C6",
+ .desc = "MWAIT 0x20",
+ .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 195,
+ .target_residency = 585,
+ .enter = &intel_idle,
+ .enter_s2idle = intel_idle_s2idle, },
+ {
+ .name = "C8",
+ .desc = "MWAIT 0x40",
+ .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 260,
+ .target_residency = 1040,
+ .enter = &intel_idle,
+ .enter_s2idle = intel_idle_s2idle, },
+ {
+ .name = "C10",
+ .desc = "MWAIT 0x60",
+ .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 660,
+ .target_residency = 1980,
+ .enter = &intel_idle,
+ .enter_s2idle = intel_idle_s2idle, },
+ {
+ .enter = NULL }
+};
+
static struct cpuidle_state spr_cstates[] __initdata = {
{
.name = "C1",
@@ -1309,6 +1354,10 @@ static const struct idle_cpu idle_cpu_adl_l __initconst = {
.state_table = adl_l_cstates,
};
+static const struct idle_cpu idle_cpu_adl_n __initconst = {
+ .state_table = adl_n_cstates,
+};
+
static const struct idle_cpu idle_cpu_spr __initconst = {
.state_table = spr_cstates,
.disable_promotion_to_c1e = true,
@@ -1379,6 +1428,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &idle_cpu_icx),
X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &idle_cpu_adl),
X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &idle_cpu_adl_l),
+ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, &idle_cpu_adl_n),
X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &idle_cpu_spr),
X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
@@ -1816,6 +1866,7 @@ static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
break;
case INTEL_FAM6_ALDERLAKE:
case INTEL_FAM6_ALDERLAKE_L:
+ case INTEL_FAM6_ALDERLAKE_N:
adl_idle_state_table_update();
break;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] intel_idle: Add AlderLake-N support
2022-09-20 12:58 [PATCH] intel_idle: Add AlderLake-N support Zhang Rui
@ 2022-09-21 18:35 ` Rafael J. Wysocki
0 siblings, 0 replies; 2+ messages in thread
From: Rafael J. Wysocki @ 2022-09-21 18:35 UTC (permalink / raw)
To: Zhang Rui
Cc: Rafael J. Wysocki, Linux PM, vinay.kumar, baieswara.reddy.sagili
On Tue, Sep 20, 2022 at 2:56 PM Zhang Rui <rui.zhang@intel.com> wrote:
>
> Similar to ther other AlderLake platforms, the C1 and C1E states on
> ADL-N are mutually exclusive. Only one of them can be enabled at a time.
> C1E is preferred on ADL-N for better energy efficiency.
>
> C6S is also supported on this platform. Its latency is far bigger than
> C6, but really close to C8 (PC8), thus it is not exposed as a separate
> state.
>
> Suggested-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
> Suggested-by: Vinay Kumar <vinay.kumar@intel.com>
> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
> ---
> drivers/idle/intel_idle.c | 51 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
> index 3e101719689a..8d56b06ddca4 100644
> --- a/drivers/idle/intel_idle.c
> +++ b/drivers/idle/intel_idle.c
> @@ -928,6 +928,51 @@ static struct cpuidle_state adl_l_cstates[] __initdata = {
> .enter = NULL }
> };
>
> +static struct cpuidle_state adl_n_cstates[] __initdata = {
> + {
> + .name = "C1",
> + .desc = "MWAIT 0x00",
> + .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE,
> + .exit_latency = 1,
> + .target_residency = 1,
> + .enter = &intel_idle,
> + .enter_s2idle = intel_idle_s2idle, },
> + {
> + .name = "C1E",
> + .desc = "MWAIT 0x01",
> + .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
> + .exit_latency = 2,
> + .target_residency = 4,
> + .enter = &intel_idle,
> + .enter_s2idle = intel_idle_s2idle, },
> + {
> + .name = "C6",
> + .desc = "MWAIT 0x20",
> + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
> + .exit_latency = 195,
> + .target_residency = 585,
> + .enter = &intel_idle,
> + .enter_s2idle = intel_idle_s2idle, },
> + {
> + .name = "C8",
> + .desc = "MWAIT 0x40",
> + .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
> + .exit_latency = 260,
> + .target_residency = 1040,
> + .enter = &intel_idle,
> + .enter_s2idle = intel_idle_s2idle, },
> + {
> + .name = "C10",
> + .desc = "MWAIT 0x60",
> + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
> + .exit_latency = 660,
> + .target_residency = 1980,
> + .enter = &intel_idle,
> + .enter_s2idle = intel_idle_s2idle, },
> + {
> + .enter = NULL }
> +};
> +
> static struct cpuidle_state spr_cstates[] __initdata = {
> {
> .name = "C1",
> @@ -1309,6 +1354,10 @@ static const struct idle_cpu idle_cpu_adl_l __initconst = {
> .state_table = adl_l_cstates,
> };
>
> +static const struct idle_cpu idle_cpu_adl_n __initconst = {
> + .state_table = adl_n_cstates,
> +};
> +
> static const struct idle_cpu idle_cpu_spr __initconst = {
> .state_table = spr_cstates,
> .disable_promotion_to_c1e = true,
> @@ -1379,6 +1428,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
> X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &idle_cpu_icx),
> X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &idle_cpu_adl),
> X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &idle_cpu_adl_l),
> + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, &idle_cpu_adl_n),
> X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &idle_cpu_spr),
> X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
> X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
> @@ -1816,6 +1866,7 @@ static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
> break;
> case INTEL_FAM6_ALDERLAKE:
> case INTEL_FAM6_ALDERLAKE_L:
> + case INTEL_FAM6_ALDERLAKE_N:
> adl_idle_state_table_update();
> break;
> }
> --
Applied (with some minor changelog edits) as 6.1 material, thanks!
^ permalink raw reply [flat|nested] 2+ messages in thread
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2022-09-21 18:35 ` Rafael J. Wysocki
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