* [PATCH 1/3] drm/amdgpu: avoid gfx register accessing during gfxoff
@ 2022-09-21 4:56 Evan Quan
2022-09-21 4:56 ` [PATCH 2/3] drm/amd/pm: enable gfxoff feature for SMU 13.0.0 Evan Quan
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Evan Quan @ 2022-09-21 4:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan, hawking.zhang
Make sure gfxoff is disabled before gfx register accessing.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Change-Id: Ia032869080f51cdefc6e6bad4f04405193ab0fec
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index ce8c792cef1a..710074682279 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5245,6 +5245,8 @@ static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
{
u32 reg, data;
+ amdgpu_gfx_off_ctrl(adev, false);
+
reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
if (amdgpu_sriov_is_pp_one_vf(adev))
data = RREG32_NO_KIQ(reg);
@@ -5258,6 +5260,8 @@ static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
else
WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
+
+ amdgpu_gfx_off_ctrl(adev, true);
}
static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/3] drm/amd/pm: enable gfxoff feature for SMU 13.0.0
2022-09-21 4:56 [PATCH 1/3] drm/amdgpu: avoid gfx register accessing during gfxoff Evan Quan
@ 2022-09-21 4:56 ` Evan Quan
2022-09-21 4:56 ` [PATCH 3/3] drm/amd/pm: use adverse selection for dpm features unsupported by driver Evan Quan
2022-09-21 11:06 ` [PATCH 1/3] drm/amdgpu: avoid gfx register accessing during gfxoff Lazar, Lijo
2 siblings, 0 replies; 4+ messages in thread
From: Evan Quan @ 2022-09-21 4:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan, hawking.zhang
The feature is ready with latest 78.58.0 PMFW.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Change-Id: Ia8ec869be41b328eee9fd9544b3de604a085f9cc
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 096327513dd0..03b732bf8cd0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -239,6 +239,7 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
uint32_t *feature_mask, uint32_t num)
{
struct amdgpu_device *adev = smu->adev;
+ u32 smu_version;
if (num > 2)
return -EINVAL;
@@ -262,10 +263,11 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
-#if 0
- if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ /* PMFW 78.58 contains a critical fix for gfxoff feature */
+ smu_cmn_get_smc_version(smu, NULL, &smu_version);
+ if ((smu_version >= 0x004e3a00) &&
+ (adev->pm.pp_feature & PP_GFXOFF_MASK))
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
-#endif
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/3] drm/amd/pm: use adverse selection for dpm features unsupported by driver
2022-09-21 4:56 [PATCH 1/3] drm/amdgpu: avoid gfx register accessing during gfxoff Evan Quan
2022-09-21 4:56 ` [PATCH 2/3] drm/amd/pm: enable gfxoff feature for SMU 13.0.0 Evan Quan
@ 2022-09-21 4:56 ` Evan Quan
2022-09-21 11:06 ` [PATCH 1/3] drm/amdgpu: avoid gfx register accessing during gfxoff Lazar, Lijo
2 siblings, 0 replies; 4+ messages in thread
From: Evan Quan @ 2022-09-21 4:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan, hawking.zhang
It's vbios and pmfw instead of driver who decide whether some dpm features
is supported or not. Driver just de-selects those features which are not
permitted on user's request. Thus, we use adverse selects model.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Change-Id: I184ca0950e75d47ed20895f2643ddfa31417dc22
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 85 ++++++-------------
1 file changed, 24 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 03b732bf8cd0..1d454485e0d9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -244,79 +244,42 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
if (num > 2)
return -EINVAL;
- memset(feature_mask, 0, sizeof(uint32_t) * num);
+ memset(feature_mask, 0xff, sizeof(uint32_t) * num);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);
-
- if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
+ if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) {
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT);
}
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);
-
- if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
- (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
+ if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
+ !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
- if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
+ if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
/* PMFW 78.58 contains a critical fix for gfxoff feature */
smu_cmn_get_smc_version(smu, NULL, &smu_version);
- if ((smu_version >= 0x004e3a00) &&
- (adev->pm.pp_feature & PP_GFXOFF_MASK))
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
-
- if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
+ if ((smu_version < 0x004e3a00) ||
+ !(adev->pm.pp_feature & PP_GFXOFF_MASK))
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
+
+ if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
}
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
-
- if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
+ if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_DCFCLK_BIT);
-
- if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) {
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
+ if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
}
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_UCLK_BIT);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
-
- if (adev->pm.pp_feature & PP_ULV_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
+ if (!(adev->pm.pp_feature & PP_ULV_MASK))
+ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/3] drm/amdgpu: avoid gfx register accessing during gfxoff
2022-09-21 4:56 [PATCH 1/3] drm/amdgpu: avoid gfx register accessing during gfxoff Evan Quan
2022-09-21 4:56 ` [PATCH 2/3] drm/amd/pm: enable gfxoff feature for SMU 13.0.0 Evan Quan
2022-09-21 4:56 ` [PATCH 3/3] drm/amd/pm: use adverse selection for dpm features unsupported by driver Evan Quan
@ 2022-09-21 11:06 ` Lazar, Lijo
2 siblings, 0 replies; 4+ messages in thread
From: Lazar, Lijo @ 2022-09-21 11:06 UTC (permalink / raw)
To: Evan Quan, amd-gfx; +Cc: Alexander.Deucher, hawking.zhang
On 9/21/2022 10:26 AM, Evan Quan wrote:
> Make sure gfxoff is disabled before gfx register accessing.
>
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Series is -
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Thanks,
Lijo
> Change-Id: Ia032869080f51cdefc6e6bad4f04405193ab0fec
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index ce8c792cef1a..710074682279 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -5245,6 +5245,8 @@ static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
> {
> u32 reg, data;
>
> + amdgpu_gfx_off_ctrl(adev, false);
> +
> reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
> if (amdgpu_sriov_is_pp_one_vf(adev))
> data = RREG32_NO_KIQ(reg);
> @@ -5258,6 +5260,8 @@ static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
> WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
> else
> WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
> +
> + amdgpu_gfx_off_ctrl(adev, true);
> }
>
> static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-09-21 11:06 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2022-09-21 4:56 [PATCH 1/3] drm/amdgpu: avoid gfx register accessing during gfxoff Evan Quan
2022-09-21 4:56 ` [PATCH 2/3] drm/amd/pm: enable gfxoff feature for SMU 13.0.0 Evan Quan
2022-09-21 4:56 ` [PATCH 3/3] drm/amd/pm: use adverse selection for dpm features unsupported by driver Evan Quan
2022-09-21 11:06 ` [PATCH 1/3] drm/amdgpu: avoid gfx register accessing during gfxoff Lazar, Lijo
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