From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 4/4] drm/i915: WARN if PLL ref/unref got messed up
Date: Thu, 22 Sep 2022 00:15:25 +0300 [thread overview]
Message-ID: <20220921211525.10675-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220921211525.10675-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Spew a WARN if we try to ref/unref the same DPLL multiple
times for the same pipe.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c21818cb6fe2..2a6ef1398c84 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -384,6 +384,8 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
if (shared_dpll[id].pipe_mask == 0)
shared_dpll[id].hw_state = *pll_state;
+ drm_WARN_ON(&i915->drm, (shared_dpll[id].pipe_mask & BIT(crtc->pipe)) != 0);
+
shared_dpll[id].pipe_mask |= BIT(crtc->pipe);
drm_dbg(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
@@ -396,10 +398,13 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_shared_dpll_state *shared_dpll;
+ const enum intel_dpll_id id = pll->info->id;
shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
- shared_dpll[pll->info->id].pipe_mask &= ~BIT(crtc->pipe);
+ drm_WARN_ON(&i915->drm, (shared_dpll[id].pipe_mask & BIT(crtc->pipe)) == 0);
+
+ shared_dpll[id].pipe_mask &= ~BIT(crtc->pipe);
drm_dbg(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
--
2.35.1
next prev parent reply other threads:[~2022-09-21 21:15 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-21 21:15 [Intel-gfx] [PATCH 0/4] drm/i915: Fix TC port PLLs after readout Ville Syrjala
2022-09-21 21:15 ` [Intel-gfx] [PATCH 1/4] drm/i915: Force DPLL calculation for TC ports " Ville Syrjala
2022-09-22 11:56 ` Jani Nikula
2022-09-22 15:40 ` Ville Syrjälä
2022-09-22 19:12 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-09-26 17:00 ` Jani Nikula
2022-09-21 21:15 ` [Intel-gfx] [PATCH 2/4] drm/i915: Don't bail early from intel_dp_initial_fastset_check() Ville Syrjala
2022-09-22 19:13 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-09-21 21:15 ` [Intel-gfx] [PATCH 3/4] drm/i915: Pimp DPLL ref/unref debugs Ville Syrjala
2022-09-22 11:57 ` Jani Nikula
2022-09-22 15:42 ` Ville Syrjälä
2022-09-22 19:13 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-09-21 21:15 ` Ville Syrjala [this message]
2022-09-21 21:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix TC port PLLs after readout Patchwork
2022-09-21 22:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-22 0:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-09-22 23:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix TC port PLLs after readout (rev4) Patchwork
2022-09-22 23:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-23 6:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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