From: Chris Packham <judge.packham@gmail.com>
To: Stefan Roese <sr@denx.de>
Cc: Elad Nachman <enachman@marvell.com>,
Vadym Kochan <vadym.kochan@plvision.eu>,
Chris Packham <judge.packham@gmail.com>,
Joe Hershberger <joe.hershberger@ni.com>,
Ramon Fried <rfried.dev@gmail.com>,
u-boot@lists.denx.de
Subject: [PATCH v4 1/5] net: mvneta: Add support for AlleyCat5
Date: Thu, 22 Sep 2022 15:31:12 +1200 [thread overview]
Message-ID: <20220922033116.915635-2-judge.packham@gmail.com> (raw)
In-Reply-To: <20220922033116.915635-1-judge.packham@gmail.com>
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
---
(no changes since v3)
Changes in v3:
- Remove unnecessary changes to RX descriptor handling
- Use dev_get_dma_range() to parse dma-ranges property from parent
device.
drivers/net/Kconfig | 2 +-
drivers/net/mvneta.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 6bbbadc5ee..8df3dce6df 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -448,7 +448,7 @@ config MVGBE
config MVNETA
bool "Marvell Armada XP/385/3700 network interface support"
- depends on ARMADA_XP || ARMADA_38X || ARMADA_3700
+ depends on ARMADA_XP || ARMADA_38X || ARMADA_3700 || ALLEYCAT_5
select PHYLIB
select DM_MDIO
help
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index d2c42c4396..0fbfad11d4 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -91,6 +91,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define MVNETA_WIN_SIZE_MASK (0xffff0000)
#define MVNETA_BASE_ADDR_ENABLE 0x2290
#define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
+#define MVNETA_AC5_CNM_DDR_TARGET 0x2
+#define MVNETA_AC5_CNM_DDR_ATTR 0xb
#define MVNETA_PORT_ACCESS_PROTECT 0x2294
#define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
#define MVNETA_PORT_CONFIG 0x2400
@@ -282,6 +284,8 @@ struct mvneta_port {
struct gpio_desc phy_reset_gpio;
struct gpio_desc sfp_tx_disable_gpio;
#endif
+
+ uintptr_t dma_base; /* base address for DMA address decoding */
};
/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
@@ -1343,6 +1347,29 @@ static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
}
+static void mvneta_conf_ac5_cnm_xbar_windows(struct mvneta_port *pp)
+{
+ int i;
+
+ /* Clear all windows */
+ for (i = 0; i < 6; i++) {
+ mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
+ mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
+
+ if (i < 4)
+ mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
+ }
+
+ /*
+ * Setup window #0 base 0x0 to target XBAR port 2 (AMB2), attribute 0xb, size 4GB
+ * AMB2 address decoder remaps 0x0 to DDR 64 bit base address
+ */
+ mvreg_write(pp, MVNETA_WIN_BASE(0),
+ (MVNETA_AC5_CNM_DDR_ATTR << 8) | MVNETA_AC5_CNM_DDR_TARGET);
+ mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
+ mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, 0x3e);
+}
+
/* Power up the port */
static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
{
@@ -1525,7 +1552,7 @@ static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
* No cache invalidation needed here, since the rx_buffer's are
* located in a uncached memory region
*/
- *packetp = data;
+ *packetp = data + pp->dma_base;
/*
* Only mark one descriptor as free
@@ -1544,6 +1571,10 @@ static int mvneta_probe(struct udevice *dev)
struct ofnode_phandle_args sfp_args;
#endif
void *bd_space;
+ phys_addr_t cpu;
+ dma_addr_t bus;
+ u64 size;
+ int ret;
/*
* Allocate buffer area for descs and rx_buffers. This is only
@@ -1577,9 +1608,18 @@ static int mvneta_probe(struct udevice *dev)
/* Configure MBUS address windows */
if (device_is_compatible(dev, "marvell,armada-3700-neta"))
mvneta_bypass_mbus_windows(pp);
+ else if (device_is_compatible(dev, "marvell,armada-ac5-neta"))
+ mvneta_conf_ac5_cnm_xbar_windows(pp);
else
mvneta_conf_mbus_windows(pp);
+ /* fetch dma ranges property */
+ ret = dev_get_dma_range(dev, &cpu, &bus, &size);
+ if (!ret)
+ pp->dma_base = cpu;
+ else
+ pp->dma_base = 0;
+
#if CONFIG_IS_ENABLED(DM_GPIO)
if (!dev_read_phandle_with_args(dev, "sfp", NULL, 0, 0, &sfp_args) &&
ofnode_is_enabled(sfp_args.node))
@@ -1620,6 +1660,7 @@ static const struct eth_ops mvneta_ops = {
static const struct udevice_id mvneta_ids[] = {
{ .compatible = "marvell,armada-370-neta" },
+ { .compatible = "marvell,armada-ac5-neta" },
{ .compatible = "marvell,armada-xp-neta" },
{ .compatible = "marvell,armada-3700-neta" },
{ }
--
2.37.3
next prev parent reply other threads:[~2022-09-22 3:31 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-22 3:31 [PATCH v4 0/5] arm: mvebu: Support for 98DX25xx/98DX35xx (AlleyCat5) Chris Packham
2022-09-22 3:31 ` Chris Packham [this message]
2022-09-22 3:31 ` [PATCH v4 2/5] usb: ehci: ehci-marvell: Support for marvell,ac5-ehci Chris Packham
2022-09-22 5:18 ` Stefan Roese
2022-09-23 1:06 ` [PATCH v4 2/5] usb: ehci: ehci-marvell: Support for marvell, ac5-ehci Chris Packham
2022-09-22 3:31 ` [PATCH v4 3/5] pinctrl: mvebu: Add AlleyCat5 support Chris Packham
2022-09-22 3:31 ` [PATCH v4 4/5] arm: mvebu: Support for 98DX25xx/98DX35xx SoC Chris Packham
2022-09-22 3:31 ` [PATCH v4 5/5] arm: mvebu: Add RD-AC5X board Chris Packham
2022-09-22 5:10 ` Stefan Roese
2022-09-23 1:27 ` Chris Packham
2022-11-02 13:40 ` Stefan Roese
2022-11-02 13:49 ` Peter Robinson
2022-11-02 13:53 ` Stefan Roese
2022-11-02 20:29 ` Chris Packham
2022-11-03 1:01 ` Chris Packham
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