* [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling
@ 2022-09-22 7:59 Jouni Högander
2022-09-22 8:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev2) Patchwork
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Jouni Högander @ 2022-09-22 7:59 UTC (permalink / raw)
To: intel-gfx
Current PSR code is supposed to use TRANSCODER_EDP to force 0 shift for
bits in PSR_IMR/IIR registers:
/*
* gen12+ has registers relative to transcoder and one per transcoder
* using the same bit definition: handle it as TRANSCODER_EDP to force
* 0 shift in bit definition
*/
At the time of writing the code assumption "TRANSCODER_EDP == 0" was made.
This is not the case and all fields in PSR_IMR and PSR_IIR are shifted
incorrectly if DISPLAY_VER >= 12.
Fix this by using TRANSCODER_EDP definition instead of 0. Even thought
TRANSCODER_EDP doesn't exist in display_ver >= 12 doing it this way keeps
code clean and readable.
v2: Improve commit message (José)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9def8d9fade6..9ecf1a9a1120 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -129,7 +129,7 @@ static void psr_irq_control(struct intel_dp *intel_dp)
* 0 shift in bit definition
*/
if (DISPLAY_VER(dev_priv) >= 12) {
- trans_shift = 0;
+ trans_shift = TRANSCODER_EDP;
imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
} else {
trans_shift = intel_dp->psr.transcoder;
@@ -195,7 +195,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
i915_reg_t imr_reg;
if (DISPLAY_VER(dev_priv) >= 12) {
- trans_shift = 0;
+ trans_shift = TRANSCODER_EDP;
imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
} else {
trans_shift = intel_dp->psr.transcoder;
@@ -1197,7 +1197,7 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
if (DISPLAY_VER(dev_priv) >= 12) {
val = intel_de_read(dev_priv,
TRANS_PSR_IIR(intel_dp->psr.transcoder));
- val &= EDP_PSR_ERROR(0);
+ val &= EDP_PSR_ERROR(TRANSCODER_EDP);
} else {
val = intel_de_read(dev_priv, EDP_PSR_IIR);
val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev2)
2022-09-22 7:59 [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling Jouni Högander
@ 2022-09-22 8:49 ` Patchwork
2022-09-22 10:21 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-09-22 13:08 ` [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling Souza, Jose
2 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-09-22 8:49 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2741 bytes --]
== Series Details ==
Series: drm/i915/psr: Fix PSR_IMR/IIR field handling (rev2)
URL : https://patchwork.freedesktop.org/series/108811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12166 -> Patchwork_108811v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/index.html
Participating hosts (45 -> 42)
------------------------------
Missing (3): fi-rkl-11600 fi-bdw-samus fi-pnv-d510
Known issues
------------
Here are the changes found in Patchwork_108811v2 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-bxt-dsi: [DMESG-FAIL][1] ([i915#5334]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_suspend@basic-s3-without-i915:
- {bat-rpls-1}: [INCOMPLETE][3] -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-2:
- {bat-dg2-11}: [FAIL][5] ([i915#6818]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-2.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6818]: https://gitlab.freedesktop.org/drm/intel/issues/6818
Build changes
-------------
* Linux: CI_DRM_12166 -> Patchwork_108811v2
CI-20190529: 20190529
CI_DRM_12166: 3e89f6dc5d22dcc4f56bed3abade8107c95815b3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6659: 1becf700a737a7a98555a0cfbe8566355377afb2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108811v2: 3e89f6dc5d22dcc4f56bed3abade8107c95815b3 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
60e6336dd84c drm/i915/psr: Fix PSR_IMR/IIR field handling
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/index.html
[-- Attachment #2: Type: text/html, Size: 3348 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev2)
2022-09-22 7:59 [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling Jouni Högander
2022-09-22 8:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev2) Patchwork
@ 2022-09-22 10:21 ` Patchwork
2022-09-22 13:08 ` [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling Souza, Jose
2 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-09-22 10:21 UTC (permalink / raw)
To: Hogander, Jouni; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 40310 bytes --]
== Series Details ==
Series: drm/i915/psr: Fix PSR_IMR/IIR field handling (rev2)
URL : https://patchwork.freedesktop.org/series/108811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12166_full -> Patchwork_108811v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_108811v2_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-snb: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [FAIL][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4338])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb7/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb7/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb7/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb7/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb7/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb6/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb6/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb6/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb6/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb6/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb5/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb4/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb2/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb2/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb2/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb2/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-snb2/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb2/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb7/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb7/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb7/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb7/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb7/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb6/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb6/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb6/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb6/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb6/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb5/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb5/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb5/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb5/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb4/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb4/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb4/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb2/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb4/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb2/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-snb2/boot.html
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-3x:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#1839])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@feature_discovery@display-3x.html
* igt@gem_ccs@block-copy-inplace:
- shard-iclb: NOTRUN -> [SKIP][52] ([i915#5327])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@gem_ccs@block-copy-inplace.html
* igt@gem_create@create-massive:
- shard-iclb: NOTRUN -> [DMESG-WARN][53] ([i915#4991])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@gem_create@create-massive.html
* igt@gem_exec_balancer@parallel:
- shard-iclb: NOTRUN -> [SKIP][54] ([i915#4525])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][55] -> [SKIP][56] ([i915#4525]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_capture@capture-recoverable:
- shard-tglb: NOTRUN -> [SKIP][57] ([i915#6344])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_endless@dispatch@vcs1:
- shard-tglb: [PASS][58] -> [INCOMPLETE][59] ([i915#3778])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-tglb3/igt@gem_exec_endless@dispatch@vcs1.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@gem_exec_endless@dispatch@vcs1.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: [PASS][60] -> [FAIL][61] ([i915#2842])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: NOTRUN -> [FAIL][62] ([i915#2842]) +3 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_params@secure-non-master:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#112283])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@gem_exec_params@secure-non-master.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-iclb: NOTRUN -> [SKIP][64] ([i915#4613])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_pxp@create-protected-buffer:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#4270])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@gem_pxp@create-protected-buffer.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-iclb: NOTRUN -> [SKIP][66] ([i915#4270]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_render_copy@yf-tiled-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#768])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@gem_render_copy@yf-tiled-to-vebox-y-tiled.html
* igt@gem_softpin@evict-snoop:
- shard-iclb: NOTRUN -> [SKIP][68] ([fdo#109312])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@gem_softpin@evict-snoop.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-iclb: NOTRUN -> [SKIP][69] ([i915#3297]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@gem_userptr_blits@readonly-unsync.html
* igt@gen7_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][70] ([fdo#109289]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@gen7_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@allowed-single:
- shard-tglb: NOTRUN -> [SKIP][71] ([i915#2527] / [i915#2856])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-iclb: NOTRUN -> [SKIP][72] ([i915#2856]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-iclb: NOTRUN -> [SKIP][73] ([i915#1769] / [i915#3555])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][74] ([i915#5286]) +3 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#5286])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-glk: [PASS][76] -> [FAIL][77] ([i915#1888])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-glk8/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-glk9/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#110723])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][79] ([fdo#111615])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][80] ([i915#3689] / [i915#3886]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][81] ([fdo#109278]) +16 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][82] ([fdo#109278] / [i915#3886]) +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][83] ([i915#3689] / [i915#6095]) +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][84] ([fdo#111615] / [i915#3689])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-tglb: NOTRUN -> [SKIP][85] ([fdo#109284] / [fdo#111827]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_color_chamelium@degamma:
- shard-iclb: NOTRUN -> [SKIP][86] ([fdo#109284] / [fdo#111827]) +3 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@kms_color_chamelium@degamma.html
* igt@kms_content_protection@atomic:
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109300] / [fdo#111066])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_content_protection@atomic.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-iclb: NOTRUN -> [SKIP][88] ([i915#3359]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1:
- shard-apl: [PASS][89] -> [DMESG-WARN][90] ([i915#180]) +5 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-apl6/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-apl8/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-glk: [PASS][91] -> [DMESG-WARN][92] ([i915#118] / [i915#1888])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][93] ([fdo#109274]) +9 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-tglb: NOTRUN -> [SKIP][94] ([fdo#109274] / [fdo#111825] / [i915#3637]) +3 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][95] ([i915#6375])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][96] ([i915#2587] / [i915#2672])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][97] ([i915#2672]) +4 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][98] ([i915#2672] / [i915#3555]) +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109285])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt:
- shard-iclb: NOTRUN -> [SKIP][100] ([fdo#109280]) +12 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][101] ([fdo#109280] / [fdo#111825]) +4 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][102] ([i915#6497]) +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_plane_lowres@tiling-4:
- shard-tglb: NOTRUN -> [SKIP][103] ([fdo#112054] / [i915#5288])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_plane_lowres@tiling-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-edp-1:
- shard-tglb: NOTRUN -> [SKIP][104] ([i915#5235]) +3 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-edp-1.html
* igt@kms_prime@d3hot:
- shard-iclb: NOTRUN -> [SKIP][105] ([i915#6524])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-tglb: NOTRUN -> [SKIP][106] ([i915#2920])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: NOTRUN -> [SKIP][107] ([fdo#109441])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][108] -> [SKIP][109] ([fdo#109441]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_vrr@flip-basic:
- shard-iclb: NOTRUN -> [SKIP][110] ([i915#3555]) +2 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@kms_vrr@flip-basic.html
* igt@kms_writeback@writeback-fb-id:
- shard-iclb: NOTRUN -> [SKIP][111] ([i915#2437])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-c-source-rg:
- shard-iclb: NOTRUN -> [SKIP][112] ([i915#2530]) +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@nouveau_crc@pipe-c-source-rg.html
* igt@prime_nv_pcopy@test1_macro:
- shard-tglb: NOTRUN -> [SKIP][113] ([fdo#109291])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@prime_nv_pcopy@test1_macro.html
* igt@prime_nv_pcopy@test3_2:
- shard-iclb: NOTRUN -> [SKIP][114] ([fdo#109291]) +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@prime_nv_pcopy@test3_2.html
* igt@sysfs_clients@fair-0:
- shard-tglb: NOTRUN -> [SKIP][115] ([i915#2994])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@fair-7:
- shard-iclb: NOTRUN -> [SKIP][116] ([i915#2994])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb7/igt@sysfs_clients@fair-7.html
#### Possible fixes ####
* igt@drm_read@short-buffer-block:
- {shard-rkl}: [SKIP][117] ([i915#4098]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-5/igt@drm_read@short-buffer-block.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-6/igt@drm_read@short-buffer-block.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][119] ([i915#6268]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-tglu-6/igt@gem_ctx_exec@basic-nohangcheck.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglu-4/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-apl: [DMESG-WARN][121] ([i915#180]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-apl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-apl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_ctx_persistence@engines-hang@bcs0:
- {shard-rkl}: [SKIP][123] ([i915#6252]) -> [PASS][124] +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@bcs0.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-2/igt@gem_ctx_persistence@engines-hang@bcs0.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][125] ([i915#4525]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-iclb3/igt@gem_exec_balancer@parallel-balancer.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][127] ([i915#2842]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- {shard-rkl}: [FAIL][129] ([i915#2842]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-1/igt@gem_exec_fair@basic-none-solo@rcs0.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][131] ([i915#2842]) -> [PASS][132] +1 similar issue
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-gtt-wc-noreloc:
- {shard-rkl}: [SKIP][133] ([i915#3281]) -> [PASS][134] +10 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-1/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
* igt@gem_exec_schedule@semaphore-power:
- {shard-rkl}: [SKIP][135] ([fdo#110254]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-1/igt@gem_exec_schedule@semaphore-power.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-5/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_pread@self:
- {shard-rkl}: [SKIP][137] ([i915#3282]) -> [PASS][138] +3 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-1/igt@gem_pread@self.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-5/igt@gem_pread@self.html
* igt@gen9_exec_parse@batch-invalid-length:
- {shard-rkl}: [SKIP][139] ([i915#2527]) -> [PASS][140] +3 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-1/igt@gen9_exec_parse@batch-invalid-length.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-5/igt@gen9_exec_parse@batch-invalid-length.html
* igt@i915_pm_backlight@basic-brightness:
- {shard-rkl}: [SKIP][141] ([i915#3012]) -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-5/igt@i915_pm_backlight@basic-brightness.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_dc@dc5-psr:
- {shard-rkl}: [SKIP][143] ([i915#658]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-5/igt@i915_pm_dc@dc5-psr.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-6/igt@i915_pm_dc@dc5-psr.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][145] ([i915#4281]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html
- {shard-rkl}: [SKIP][147] ([i915#3361]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-5/igt@i915_pm_dc@dc9-dpms.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-tglu}: [FAIL][149] ([i915#3825]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-tglu-4/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglu-1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@system-suspend-devices:
- shard-tglb: [INCOMPLETE][151] -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-tglb8/igt@i915_pm_rpm@system-suspend-devices.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-tglb5/igt@i915_pm_rpm@system-suspend-devices.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][153] ([i915#2122]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-glk2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- {shard-rkl}: [SKIP][155] ([i915#1849] / [i915#4098]) -> [PASS][156] +14 similar issues
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- {shard-rkl}: [SKIP][157] ([i915#1849] / [i915#3546] / [i915#4098]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- {shard-rkl}: [SKIP][159] ([i915#1849] / [i915#3546] / [i915#4070] / [i915#4098]) -> [PASS][160] +1 similar issue
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_properties@crtc-properties-legacy:
- {shard-rkl}: [SKIP][161] ([i915#1849]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-5/igt@kms_properties@crtc-properties-legacy.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-6/igt@kms_properties@crtc-properties-legacy.html
* igt@kms_psr@cursor_blt:
- {shard-rkl}: [SKIP][163] ([i915#1072]) -> [PASS][164] +3 similar issues
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-5/igt@kms_psr@cursor_blt.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-6/igt@kms_psr@cursor_blt.html
* igt@kms_universal_plane@universal-plane-pipe-b-functional:
- {shard-rkl}: [SKIP][165] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-1/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
* igt@kms_vblank@pipe-b-ts-continuation-idle:
- {shard-rkl}: [SKIP][167] ([i915#1845] / [i915#4098]) -> [PASS][168] +22 similar issues
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-5/igt@kms_vblank@pipe-b-ts-continuation-idle.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-6/igt@kms_vblank@pipe-b-ts-continuation-idle.html
* igt@prime_vgem@basic-read:
- {shard-rkl}: [SKIP][169] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-rkl-1/igt@prime_vgem@basic-read.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-rkl-5/igt@prime_vgem@basic-read.html
#### Warnings ####
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][171] ([fdo#111068] / [i915#658]) -> [SKIP][172] ([i915#2920])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12166/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4338]: https://gitlab.freedesktop.org/drm/intel/issues/4338
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6375]: https://gitlab.freedesktop.org/drm/intel/issues/6375
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
Build changes
-------------
* Linux: CI_DRM_12166 -> Patchwork_108811v2
CI-20190529: 20190529
CI_DRM_12166: 3e89f6dc5d22dcc4f56bed3abade8107c95815b3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6659: 1becf700a737a7a98555a0cfbe8566355377afb2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108811v2: 3e89f6dc5d22dcc4f56bed3abade8107c95815b3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v2/index.html
[-- Attachment #2: Type: text/html, Size: 43907 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling
2022-09-22 7:59 [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling Jouni Högander
2022-09-22 8:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev2) Patchwork
2022-09-22 10:21 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-09-22 13:08 ` Souza, Jose
2022-09-23 6:11 ` Hogander, Jouni
2 siblings, 1 reply; 8+ messages in thread
From: Souza, Jose @ 2022-09-22 13:08 UTC (permalink / raw)
To: intel-gfx, Hogander, Jouni
On Thu, 2022-09-22 at 10:59 +0300, Jouni Högander wrote:
> Current PSR code is supposed to use TRANSCODER_EDP to force 0 shift for
> bits in PSR_IMR/IIR registers:
>
> /*
> * gen12+ has registers relative to transcoder and one per transcoder
> * using the same bit definition: handle it as TRANSCODER_EDP to force
> * 0 shift in bit definition
> */
>
> At the time of writing the code assumption "TRANSCODER_EDP == 0" was made.
> This is not the case and all fields in PSR_IMR and PSR_IIR are shifted
> incorrectly if DISPLAY_VER >= 12.
From where are you getting that TRANSCODER_EDP == 0?
enum pipe {
INVALID_PIPE = -1,
PIPE_A = 0,
PIPE_B,
PIPE_C,
PIPE_D,
_PIPE_EDP,
I915_MAX_PIPES = _PIPE_EDP
};
#define pipe_name(p) ((p) + 'A')
enum transcoder {
INVALID_TRANSCODER = -1,
/*
* The following transcoders have a 1:1 transcoder -> pipe mapping,
* keep their values fixed: the code assumes that TRANSCODER_A=0, the
* rest have consecutive values and match the enum values of the pipes
* they map to.
*/
TRANSCODER_A = PIPE_A,
TRANSCODER_B = PIPE_B,
TRANSCODER_C = PIPE_C,
TRANSCODER_D = PIPE_D,
/*
* The following transcoders can map to any pipe, their enum value
* doesn't need to stay fixed.
*/
TRANSCODER_EDP,
https://cgit.freedesktop.org/drm-tip/tree/drivers/gpu/drm/i915/display/intel_display.h#n87
>
> Fix this by using TRANSCODER_EDP definition instead of 0. Even thought
> TRANSCODER_EDP doesn't exist in display_ver >= 12 doing it this way keeps
> code clean and readable.
trans_shift = 0 is fine, we needed this because display12+ splited from a single register with all transcoder to one register per transcoder.
>
> v2: Improve commit message (José)
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9def8d9fade6..9ecf1a9a1120 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -129,7 +129,7 @@ static void psr_irq_control(struct intel_dp *intel_dp)
> * 0 shift in bit definition
> */
> if (DISPLAY_VER(dev_priv) >= 12) {
> - trans_shift = 0;
> + trans_shift = TRANSCODER_EDP;
> imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> } else {
> trans_shift = intel_dp->psr.transcoder;
> @@ -195,7 +195,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
> i915_reg_t imr_reg;
>
> if (DISPLAY_VER(dev_priv) >= 12) {
> - trans_shift = 0;
> + trans_shift = TRANSCODER_EDP;
> imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> } else {
> trans_shift = intel_dp->psr.transcoder;
> @@ -1197,7 +1197,7 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> if (DISPLAY_VER(dev_priv) >= 12) {
> val = intel_de_read(dev_priv,
> TRANS_PSR_IIR(intel_dp->psr.transcoder));
> - val &= EDP_PSR_ERROR(0);
> + val &= EDP_PSR_ERROR(TRANSCODER_EDP);
> } else {
> val = intel_de_read(dev_priv, EDP_PSR_IIR);
> val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling
2022-09-22 13:08 ` [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling Souza, Jose
@ 2022-09-23 6:11 ` Hogander, Jouni
2022-09-23 12:37 ` Souza, Jose
0 siblings, 1 reply; 8+ messages in thread
From: Hogander, Jouni @ 2022-09-23 6:11 UTC (permalink / raw)
To: intel-gfx, Souza, Jose
On Thu, 2022-09-22 at 13:08 +0000, Souza, Jose wrote:
> On Thu, 2022-09-22 at 10:59 +0300, Jouni Högander wrote:
> > Current PSR code is supposed to use TRANSCODER_EDP to force 0 shift
> > for
> > bits in PSR_IMR/IIR registers:
> >
> > /*
> > * gen12+ has registers relative to transcoder and one per
> > transcoder
> > * using the same bit definition: handle it as TRANSCODER_EDP to
> > force
> > * 0 shift in bit definition
> > */
> >
> > At the time of writing the code assumption "TRANSCODER_EDP == 0"
> > was made.
> > This is not the case and all fields in PSR_IMR and PSR_IIR are
> > shifted
> > incorrectly if DISPLAY_VER >= 12.
>
> From where are you getting that TRANSCODER_EDP == 0?
It's not. That is my point. If you look at this commit:
https://github.com/freedesktop/drm-tip/commit/8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf
adding this comment:
+ /*
+ * gen12+ has registers relative to transcoder and one per
transcoder
+ * using the same bit definition: handle it as TRANSCODER_EDP
to force
+ * 0 shift in bit definition
+ */
and the code added by this commit is doing
...
+ trans_shift = 0;
mask = EDP_PSR_ERROR(trans_shift);
...
+ mask = EDP_PSR_ERROR(trans_shift);
...
and if we look at EDP_PSR_ERROR definition:
...
#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) ==
TRANSCODER_EDP ? \
0 : ((trans) -
TRANSCODER_A + 1) * 8)
...
#define EDP_PSR_ERROR(trans) (0x4 <<
_EDP_PSR_TRANS_SHIFT(trans))
...
EDP_PSR_ERROR(0) is 0x400 which is wrong for e.g. TGL. Using
TRANSCODER_EDP as mentioned in the added comment:
EDP_PSR_ERROR(TRANSCODER_EDP) is 0x4 which is correct.
My patch is doing what is in the comment. There are other way to fix
this, but to my opinion original idea using TRANSCODER_EDP in commit
8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf to force 0 shift keeps the
code pretty clean.
>
> enum pipe {
> INVALID_PIPE = -1,
>
> PIPE_A = 0,
> PIPE_B,
> PIPE_C,
> PIPE_D,
> _PIPE_EDP,
>
> I915_MAX_PIPES = _PIPE_EDP
> };
>
> #define pipe_name(p) ((p) + 'A')
>
> enum transcoder {
> INVALID_TRANSCODER = -1,
> /*
> * The following transcoders have a 1:1 transcoder -> pipe
> mapping,
> * keep their values fixed: the code assumes that
> TRANSCODER_A=0, the
> * rest have consecutive values and match the enum values of
> the pipes
> * they map to.EDP_PSR_TRANS_
> */
> TRANSCODER_A = PIPE_A,
> TRANSCODER_B = PIPE_B,
> TRANSCODER_C = PIPE_C,
> TRANSCODER_D = PIPE_D,
>
> /*
> * The following transcoders can map to any pipe, their enum
> value
> * doesn't need to stay fixed.
> */
> TRANSCODER_EDP,
>
> https://cgit.freedesktop.org/drm-tip/tree/drivers/gpu/drm/i915/display/intel_display.h#n87
>
> >
> > Fix this by using TRANSCODER_EDP definition instead of 0. Even
> > thought
> > TRANSCODER_EDP doesn't exist in display_ver >= 12 doing it this way
> > keeps
> > code clean and readable.
>
> trans_shift = 0 is fine, we needed this because display12+ splited
> from a single register with all transcoder to one register per
> transcoder.
>
No, it's not. See the definition of _EDP_PSR_TRANS_SHIFT and
EDP_PSR_TRANS_*. Maybe renaming trans_shift to transcoder would prevent
misunderstanding here.
> >
> > v2: Improve commit message (José)
> >
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> >
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 9def8d9fade6..9ecf1a9a1120 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -129,7 +129,7 @@ static void psr_irq_control(struct intel_dp
> > *intel_dp)
> > * 0 shift in bit definition
> > */
> > if (DISPLAY_VER(dev_priv) >= 12) {
> > - trans_shift = 0;
> > + trans_shift = TRANSCODER_EDP;
> > imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> > } else {
> > trans_shift = intel_dp->psr.transcoder;
> > @@ -195,7 +195,7 @@ void intel_psr_irq_handler(struct intel_dp
> > *intel_dp, u32 psr_iir)
> > i915_reg_t imr_reg;
> >
> > if (DISPLAY_VER(dev_priv) >= 12) {
> > - trans_shift = 0;
> > + trans_shift = TRANSCODER_EDP;
> > imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> > } else {
> > trans_shift = intel_dp->psr.transcoder;
> > @@ -1197,7 +1197,7 @@ static bool psr_interrupt_error_check(struct
> > intel_dp *intel_dp)
> > if (DISPLAY_VER(dev_priv) >= 12) {
> > val = intel_de_read(dev_priv,
> > TRANS_PSR_IIR(intel_dp-
> > >psr.transcoder));
> > - val &= EDP_PSR_ERROR(0);
> > + val &= EDP_PSR_ERROR(TRANSCODER_EDP);
> > } else {
> > val = intel_de_read(dev_priv, EDP_PSR_IIR);
> > val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling
2022-09-23 6:11 ` Hogander, Jouni
@ 2022-09-23 12:37 ` Souza, Jose
2022-09-23 12:45 ` Hogander, Jouni
0 siblings, 1 reply; 8+ messages in thread
From: Souza, Jose @ 2022-09-23 12:37 UTC (permalink / raw)
To: intel-gfx, Hogander, Jouni
On Fri, 2022-09-23 at 06:11 +0000, Hogander, Jouni wrote:
> On Thu, 2022-09-22 at 13:08 +0000, Souza, Jose wrote:
> > On Thu, 2022-09-22 at 10:59 +0300, Jouni Högander wrote:
> > > Current PSR code is supposed to use TRANSCODER_EDP to force 0 shift
> > > for
> > > bits in PSR_IMR/IIR registers:
> > >
> > > /*
> > > * gen12+ has registers relative to transcoder and one per
> > > transcoder
> > > * using the same bit definition: handle it as TRANSCODER_EDP to
> > > force
> > > * 0 shift in bit definition
> > > */
> > >
> > > At the time of writing the code assumption "TRANSCODER_EDP == 0"
> > > was made.
> > > This is not the case and all fields in PSR_IMR and PSR_IIR are
> > > shifted
> > > incorrectly if DISPLAY_VER >= 12.
> >
> > From where are you getting that TRANSCODER_EDP == 0?
>
> It's not. That is my point. If you look at this commit:
>
> https://github.com/freedesktop/drm-tip/commit/8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf
>
> adding this comment:
>
> + /*
> + * gen12+ has registers relative to transcoder and one per
> transcoder
> + * using the same bit definition: handle it as TRANSCODER_EDP
> to force
> + * 0 shift in bit definition
> + */
>
> and the code added by this commit is doing
>
> ...
> + trans_shift = 0;
> mask = EDP_PSR_ERROR(trans_shift);
> ...
>
> + mask = EDP_PSR_ERROR(trans_shift);
> ...
>
> and if we look at EDP_PSR_ERROR definition:
>
> ...
> #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) ==
> TRANSCODER_EDP ? \
> 0 : ((trans) -
> TRANSCODER_A + 1) * 8)
> ...
> #define EDP_PSR_ERROR(trans) (0x4 <<
> _EDP_PSR_TRANS_SHIFT(trans))
> ...
>
> EDP_PSR_ERROR(0) is 0x400 which is wrong for e.g. TGL. Using
> TRANSCODER_EDP as mentioned in the added comment:
> EDP_PSR_ERROR(TRANSCODER_EDP) is 0x4 which is correct.
>
> My patch is doing what is in the comment. There are other way to fix
> this, but to my opinion original idea using TRANSCODER_EDP in commit
> 8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf to force 0 shift keeps the
> code pretty clean.
>
> >
> > enum pipe {
> > INVALID_PIPE = -1,
> >
> > PIPE_A = 0,
> > PIPE_B,
> > PIPE_C,
> > PIPE_D,
> > _PIPE_EDP,
> >
> > I915_MAX_PIPES = _PIPE_EDP
> > };
> >
> > #define pipe_name(p) ((p) + 'A')
> >
> > enum transcoder {
> > INVALID_TRANSCODER = -1,
> > /*
> > * The following transcoders have a 1:1 transcoder -> pipe
> > mapping,
> > * keep their values fixed: the code assumes that
> > TRANSCODER_A=0, the
> > * rest have consecutive values and match the enum values of
> > the pipes
> > * they map to.EDP_PSR_TRANS_
> > */
> > TRANSCODER_A = PIPE_A,
> > TRANSCODER_B = PIPE_B,
> > TRANSCODER_C = PIPE_C,
> > TRANSCODER_D = PIPE_D,
> >
> > /*
> > * The following transcoders can map to any pipe, their enum
> > value
> > * doesn't need to stay fixed.
> > */
> > TRANSCODER_EDP,
> >
> > https://cgit.freedesktop.org/drm-tip/tree/drivers/gpu/drm/i915/display/intel_display.h#n87
> >
> > >
> > > Fix this by using TRANSCODER_EDP definition instead of 0. Even
> > > thought
> > > TRANSCODER_EDP doesn't exist in display_ver >= 12 doing it this way
> > > keeps
> > > code clean and readable.
> >
> > trans_shift = 0 is fine, we needed this because display12+ splited
> > from a single register with all transcoder to one register per
> > transcoder.
> >
>
> No, it's not. See the definition of _EDP_PSR_TRANS_SHIFT and
> EDP_PSR_TRANS_*. Maybe renaming trans_shift to transcoder would prevent
> misunderstanding here.
Okay now I understood.
In my opinion the proper fix would be add TGL_X macros to be used in diplay12+ paths and drop the EDP transcoder concept that do not exist in TGL+.
Also please include a fixes tag pointing to 8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf so this gets backported.
>
> > >
> > > v2: Improve commit message (José)
> > >
> > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > >
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
> > > 1 file changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 9def8d9fade6..9ecf1a9a1120 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -129,7 +129,7 @@ static void psr_irq_control(struct intel_dp
> > > *intel_dp)
> > > * 0 shift in bit definition
> > > */
> > > if (DISPLAY_VER(dev_priv) >= 12) {
> > > - trans_shift = 0;
> > > + trans_shift = TRANSCODER_EDP;
> > > imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> > > } else {
> > > trans_shift = intel_dp->psr.transcoder;
> > > @@ -195,7 +195,7 @@ void intel_psr_irq_handler(struct intel_dp
> > > *intel_dp, u32 psr_iir)
> > > i915_reg_t imr_reg;
> > >
> > > if (DISPLAY_VER(dev_priv) >= 12) {
> > > - trans_shift = 0;
> > > + trans_shift = TRANSCODER_EDP;
> > > imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> > > } else {
> > > trans_shift = intel_dp->psr.transcoder;
> > > @@ -1197,7 +1197,7 @@ static bool psr_interrupt_error_check(struct
> > > intel_dp *intel_dp)
> > > if (DISPLAY_VER(dev_priv) >= 12) {
> > > val = intel_de_read(dev_priv,
> > > TRANS_PSR_IIR(intel_dp-
> > > > psr.transcoder));
> > > - val &= EDP_PSR_ERROR(0);
> > > + val &= EDP_PSR_ERROR(TRANSCODER_EDP);
> > > } else {
> > > val = intel_de_read(dev_priv, EDP_PSR_IIR);
> > > val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
> >
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling
2022-09-23 12:37 ` Souza, Jose
@ 2022-09-23 12:45 ` Hogander, Jouni
2022-09-23 12:56 ` Souza, Jose
0 siblings, 1 reply; 8+ messages in thread
From: Hogander, Jouni @ 2022-09-23 12:45 UTC (permalink / raw)
To: intel-gfx, Souza, Jose
On Fri, 2022-09-23 at 12:37 +0000, Souza, Jose wrote:
> On Fri, 2022-09-23 at 06:11 +0000, Hogander, Jouni wrote:
> > On Thu, 2022-09-22 at 13:08 +0000, Souza, Jose wrote:
> > > On Thu, 2022-09-22 at 10:59 +0300, Jouni Högander wrote:
> > > > Current PSR code is supposed to use TRANSCODER_EDP to force 0
> > > > shift
> > > > for
> > > > bits in PSR_IMR/IIR registers:
> > > >
> > > > /*
> > > > * gen12+ has registers relative to transcoder and one per
> > > > transcoder
> > > > * using the same bit definition: handle it as TRANSCODER_EDP
> > > > to
> > > > force
> > > > * 0 shift in bit definition
> > > > */
> > > >
> > > > At the time of writing the code assumption "TRANSCODER_EDP ==
> > > > 0"
> > > > was made.
> > > > This is not the case and all fields in PSR_IMR and PSR_IIR are
> > > > shifted
> > > > incorrectly if DISPLAY_VER >= 12.
> > >
> > > From where are you getting that TRANSCODER_EDP == 0?
> >
> > It's not. That is my point. If you look at this commit:
> >
> > https://github.com/freedesktop/drm-tip/commit/8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf
> >
> > adding this comment:
> >
> > + /*
> > + * gen12+ has registers relative to transcoder and one per
> > transcoder
> > + * using the same bit definition: handle it as
> > TRANSCODER_EDP
> > to force
> > + * 0 shift in bit definition
> > + */
> >
> > and the code added by this commit is doing
> >
> > ...
> > + trans_shift = 0;
> > mask = EDP_PSR_ERROR(trans_shift);
> > ...
> >
> > + mask = EDP_PSR_ERROR(trans_shift);
> > ...
> >
> > and if we look at EDP_PSR_ERROR definition:
> >
> > ...
> > #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) ==
> > TRANSCODER_EDP ? \
> > 0 : ((trans) -
> > TRANSCODER_A + 1) * 8)
> > ...
> > #define EDP_PSR_ERROR(trans) (0x4 <<
> > _EDP_PSR_TRANS_SHIFT(trans))
> > ...
> >
> > EDP_PSR_ERROR(0) is 0x400 which is wrong for e.g. TGL. Using
> > TRANSCODER_EDP as mentioned in the added comment:
> > EDP_PSR_ERROR(TRANSCODER_EDP) is 0x4 which is correct.
> >
> > My patch is doing what is in the comment. There are other way to
> > fix
> > this, but to my opinion original idea using TRANSCODER_EDP in
> > commit
> > 8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf to force 0 shift keeps the
> > code pretty clean.
> >
> > >
> > > enum pipe {
> > > INVALID_PIPE = -1,
> > >
> > > PIPE_A = 0,
> > > PIPE_B,
> > > PIPE_C,
> > > PIPE_D,
> > > _PIPE_EDP,
> > >
> > > I915_MAX_PIPES = _PIPE_EDP
> > > };
> > >
> > > #define pipe_name(p) ((p) + 'A')
> > >
> > > enum transcoder {
> > > INVALID_TRANSCODER = -1,
> > > /*
> > > * The following transcoders have a 1:1 transcoder ->
> > > pipe
> > > mapping,
> > > * keep their values fixed: the code assumes that
> > > TRANSCODER_A=0, the
> > > * rest have consecutive values and match the enum values
> > > of
> > > the pipes
> > > * they map to.EDP_PSR_TRANS_
> > > */
> > > TRANSCODER_A = PIPE_A,
> > > TRANSCODER_B = PIPE_B,
> > > TRANSCODER_C = PIPE_C,
> > > TRANSCODER_D = PIPE_D,
> > >
> > > /*
> > > * The following transcoders can map to any pipe, their
> > > enum
> > > value
> > > * doesn't need to stay fixed.
> > > */
> > > TRANSCODER_EDP,
> > >
> > > https://cgit.freedesktop.org/drm-tip/tree/drivers/gpu/drm/i915/display/intel_display.h#n87
> > >
> > > >
> > > > Fix this by using TRANSCODER_EDP definition instead of 0. Even
> > > > thought
> > > > TRANSCODER_EDP doesn't exist in display_ver >= 12 doing it this
> > > > way
> > > > keeps
> > > > code clean and readable.
> > >
> > > trans_shift = 0 is fine, we needed this because display12+
> > > splited
> > > from a single register with all transcoder to one register per
> > > transcoder.
> > >
> >
> > No, it's not. See the definition of _EDP_PSR_TRANS_SHIFT and
> > EDP_PSR_TRANS_*. Maybe renaming trans_shift to transcoder would
> > prevent
> > misunderstanding here.
>
> Okay now I understood.
> In my opinion the proper fix would be add TGL_X macros to be used in
> diplay12+ paths and drop the EDP transcoder concept that do not exist
> in TGL+.
Ok, I started to look at this originally and it gets a bit messy as
each bit in PSR_IMR/PSR_ISR needs separate handling. If we choose this
then I was thinking adding similar _bit_get functions as we have for
man_trk_ctl bits. What do you think?
I would still consider current approach as forcing 0 shifting using
EDP_PSR_TRANS_* keeps it pretty simple.
>
> Also please include a fixes tag pointing to
> 8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf so this gets backported.
>
> >
> > > >
> > > > v2: Improve commit message (José)
> > > >
> > > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > >
> > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
> > > > 1 file changed, 3 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 9def8d9fade6..9ecf1a9a1120 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -129,7 +129,7 @@ static void psr_irq_control(struct intel_dp
> > > > *intel_dp)
> > > > * 0 shift in bit definition
> > > > */
> > > > if (DISPLAY_VER(dev_priv) >= 12) {
> > > > - trans_shift = 0;
> > > > + trans_shift = TRANSCODER_EDP;
> > > > imr_reg = TRANS_PSR_IMR(intel_dp-
> > > > >psr.transcoder);
> > > > } else {
> > > > trans_shift = intel_dp->psr.transcoder;
> > > > @@ -195,7 +195,7 @@ void intel_psr_irq_handler(struct intel_dp
> > > > *intel_dp, u32 psr_iir)
> > > > i915_reg_t imr_reg;
> > > >
> > > > if (DISPLAY_VER(dev_priv) >= 12) {
> > > > - trans_shift = 0;
> > > > + trans_shift = TRANSCODER_EDP;
> > > > imr_reg = TRANS_PSR_IMR(intel_dp-
> > > > >psr.transcoder);
> > > > } else {
> > > > trans_shift = intel_dp->psr.transcoder;
> > > > @@ -1197,7 +1197,7 @@ static bool
> > > > psr_interrupt_error_check(struct
> > > > intel_dp *intel_dp)
> > > > if (DISPLAY_VER(dev_priv) >= 12) {
> > > > val = intel_de_read(dev_priv,
> > > > TRANS_PSR_IIR(intel_dp-
> > > > > psr.transcoder));
> > > > - val &= EDP_PSR_ERROR(0);
> > > > + val &= EDP_PSR_ERROR(TRANSCODER_EDP);
> > > > } else {
> > > > val = intel_de_read(dev_priv, EDP_PSR_IIR);
> > > > val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
> > >
> >
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling
2022-09-23 12:45 ` Hogander, Jouni
@ 2022-09-23 12:56 ` Souza, Jose
0 siblings, 0 replies; 8+ messages in thread
From: Souza, Jose @ 2022-09-23 12:56 UTC (permalink / raw)
To: intel-gfx, Hogander, Jouni
On Fri, 2022-09-23 at 12:45 +0000, Hogander, Jouni wrote:
> On Fri, 2022-09-23 at 12:37 +0000, Souza, Jose wrote:
> > On Fri, 2022-09-23 at 06:11 +0000, Hogander, Jouni wrote:
> > > On Thu, 2022-09-22 at 13:08 +0000, Souza, Jose wrote:
> > > > On Thu, 2022-09-22 at 10:59 +0300, Jouni Högander wrote:
> > > > > Current PSR code is supposed to use TRANSCODER_EDP to force 0
> > > > > shift
> > > > > for
> > > > > bits in PSR_IMR/IIR registers:
> > > > >
> > > > > /*
> > > > > * gen12+ has registers relative to transcoder and one per
> > > > > transcoder
> > > > > * using the same bit definition: handle it as TRANSCODER_EDP
> > > > > to
> > > > > force
> > > > > * 0 shift in bit definition
> > > > > */
> > > > >
> > > > > At the time of writing the code assumption "TRANSCODER_EDP ==
> > > > > 0"
> > > > > was made.
> > > > > This is not the case and all fields in PSR_IMR and PSR_IIR are
> > > > > shifted
> > > > > incorrectly if DISPLAY_VER >= 12.
> > > >
> > > > From where are you getting that TRANSCODER_EDP == 0?
> > >
> > > It's not. That is my point. If you look at this commit:
> > >
> > > https://github.com/freedesktop/drm-tip/commit/8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf
> > >
> > > adding this comment:
> > >
> > > + /*
> > > + * gen12+ has registers relative to transcoder and one per
> > > transcoder
> > > + * using the same bit definition: handle it as
> > > TRANSCODER_EDP
> > > to force
> > > + * 0 shift in bit definition
> > > + */
> > >
> > > and the code added by this commit is doing
> > >
> > > ...
> > > + trans_shift = 0;
> > > mask = EDP_PSR_ERROR(trans_shift);
> > > ...
> > >
> > > + mask = EDP_PSR_ERROR(trans_shift);
> > > ...
> > >
> > > and if we look at EDP_PSR_ERROR definition:
> > >
> > > ...
> > > #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) ==
> > > TRANSCODER_EDP ? \
> > > 0 : ((trans) -
> > > TRANSCODER_A + 1) * 8)
> > > ...
> > > #define EDP_PSR_ERROR(trans) (0x4 <<
> > > _EDP_PSR_TRANS_SHIFT(trans))
> > > ...
> > >
> > > EDP_PSR_ERROR(0) is 0x400 which is wrong for e.g. TGL. Using
> > > TRANSCODER_EDP as mentioned in the added comment:
> > > EDP_PSR_ERROR(TRANSCODER_EDP) is 0x4 which is correct.
> > >
> > > My patch is doing what is in the comment. There are other way to
> > > fix
> > > this, but to my opinion original idea using TRANSCODER_EDP in
> > > commit
> > > 8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf to force 0 shift keeps the
> > > code pretty clean.
> > >
> > > >
> > > > enum pipe {
> > > > INVALID_PIPE = -1,
> > > >
> > > > PIPE_A = 0,
> > > > PIPE_B,
> > > > PIPE_C,
> > > > PIPE_D,
> > > > _PIPE_EDP,
> > > >
> > > > I915_MAX_PIPES = _PIPE_EDP
> > > > };
> > > >
> > > > #define pipe_name(p) ((p) + 'A')
> > > >
> > > > enum transcoder {
> > > > INVALID_TRANSCODER = -1,
> > > > /*
> > > > * The following transcoders have a 1:1 transcoder ->
> > > > pipe
> > > > mapping,
> > > > * keep their values fixed: the code assumes that
> > > > TRANSCODER_A=0, the
> > > > * rest have consecutive values and match the enum values
> > > > of
> > > > the pipes
> > > > * they map to.EDP_PSR_TRANS_
> > > > */
> > > > TRANSCODER_A = PIPE_A,
> > > > TRANSCODER_B = PIPE_B,
> > > > TRANSCODER_C = PIPE_C,
> > > > TRANSCODER_D = PIPE_D,
> > > >
> > > > /*
> > > > * The following transcoders can map to any pipe, their
> > > > enum
> > > > value
> > > > * doesn't need to stay fixed.
> > > > */
> > > > TRANSCODER_EDP,
> > > >
> > > > https://cgit.freedesktop.org/drm-tip/tree/drivers/gpu/drm/i915/display/intel_display.h#n87
> > > >
> > > > >
> > > > > Fix this by using TRANSCODER_EDP definition instead of 0. Even
> > > > > thought
> > > > > TRANSCODER_EDP doesn't exist in display_ver >= 12 doing it this
> > > > > way
> > > > > keeps
> > > > > code clean and readable.
> > > >
> > > > trans_shift = 0 is fine, we needed this because display12+
> > > > splited
> > > > from a single register with all transcoder to one register per
> > > > transcoder.
> > > >
> > >
> > > No, it's not. See the definition of _EDP_PSR_TRANS_SHIFT and
> > > EDP_PSR_TRANS_*. Maybe renaming trans_shift to transcoder would
> > > prevent
> > > misunderstanding here.
> >
> > Okay now I understood.
> > In my opinion the proper fix would be add TGL_X macros to be used in
> > diplay12+ paths and drop the EDP transcoder concept that do not exist
> > in TGL+.
>
> Ok, I started to look at this originally and it gets a bit messy as
> each bit in PSR_IMR/PSR_ISR needs separate handling. If we choose this
> then I was thinking adding similar _bit_get functions as we have for
> man_trk_ctl bits. What do you think?
If the code gets simpler go ahead with functions to return the bits.
>
> I would still consider current approach as forcing 0 shifting using
> EDP_PSR_TRANS_* keeps it pretty simple.
But it is terrible for readability, took me a while to get what you wanted to fix.
>
> >
> > Also please include a fixes tag pointing to
> > 8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf so this gets backported.
> >
> > >
> > > > >
> > > > > v2: Improve commit message (José)
> > > > >
> > > > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > > >
> > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
> > > > > 1 file changed, 3 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index 9def8d9fade6..9ecf1a9a1120 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -129,7 +129,7 @@ static void psr_irq_control(struct intel_dp
> > > > > *intel_dp)
> > > > > * 0 shift in bit definition
> > > > > */
> > > > > if (DISPLAY_VER(dev_priv) >= 12) {
> > > > > - trans_shift = 0;
> > > > > + trans_shift = TRANSCODER_EDP;
> > > > > imr_reg = TRANS_PSR_IMR(intel_dp-
> > > > > > psr.transcoder);
> > > > > } else {
> > > > > trans_shift = intel_dp->psr.transcoder;
> > > > > @@ -195,7 +195,7 @@ void intel_psr_irq_handler(struct intel_dp
> > > > > *intel_dp, u32 psr_iir)
> > > > > i915_reg_t imr_reg;
> > > > >
> > > > > if (DISPLAY_VER(dev_priv) >= 12) {
> > > > > - trans_shift = 0;
> > > > > + trans_shift = TRANSCODER_EDP;
> > > > > imr_reg = TRANS_PSR_IMR(intel_dp-
> > > > > > psr.transcoder);
> > > > > } else {
> > > > > trans_shift = intel_dp->psr.transcoder;
> > > > > @@ -1197,7 +1197,7 @@ static bool
> > > > > psr_interrupt_error_check(struct
> > > > > intel_dp *intel_dp)
> > > > > if (DISPLAY_VER(dev_priv) >= 12) {
> > > > > val = intel_de_read(dev_priv,
> > > > > TRANS_PSR_IIR(intel_dp-
> > > > > > psr.transcoder));
> > > > > - val &= EDP_PSR_ERROR(0);
> > > > > + val &= EDP_PSR_ERROR(TRANSCODER_EDP);
> > > > > } else {
> > > > > val = intel_de_read(dev_priv, EDP_PSR_IIR);
> > > > > val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
> > > >
> > >
> >
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-09-23 12:56 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-22 7:59 [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling Jouni Högander
2022-09-22 8:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Fix PSR_IMR/IIR field handling (rev2) Patchwork
2022-09-22 10:21 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-09-22 13:08 ` [Intel-gfx] [PATCH v2] drm/i915/psr: Fix PSR_IMR/IIR field handling Souza, Jose
2022-09-23 6:11 ` Hogander, Jouni
2022-09-23 12:37 ` Souza, Jose
2022-09-23 12:45 ` Hogander, Jouni
2022-09-23 12:56 ` Souza, Jose
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