* [PATCH 0/2] Implement workaround for errata i2329
@ 2022-09-22 9:51 Ravi Gunasekaran
2022-09-22 9:51 ` [PATCH 1/2] net: ti: cpsw-mdio: Add " Ravi Gunasekaran
2022-09-22 9:51 ` [PATCH 2/2] net: ti: am65-cpsw-nuss: Enable MDIO manual mode Ravi Gunasekaran
0 siblings, 2 replies; 7+ messages in thread
From: Ravi Gunasekaran @ 2022-09-22 9:51 UTC (permalink / raw)
To: joe.hershberger, rfried.dev
Cc: vigneshr, kabel, sr, trini, vladimir.oltean, u-boot, r-gunasekaran
This patch series adds the MDIO workaround for the errata i2329.
On certain TI SoC's CPSW and ICSS peripherals, there is a possibility
that the MDIO interface returns corrupt data on MDIO reads or writes
incorrect data on MDIO writes. There is also a possibility for the
MDIO interface to become unavailable until the next peripheral reset.
The workaround is to configure the MDIO in manual mode and disable the
MDIO state machine and emulate the MDIO protocol by reading and writing
appropriate fields in MDIO_MANUAL_IF_REG register of the MDIO controller
to manipulate the MDIO clock and data pins.
Ravi Gunasekaran (2):
net: ti: cpsw-mdio: Add workaround for errata i2329
net: ti: am65-cpsw-nuss: Enable MDIO manual mode
drivers/net/ti/am65-cpsw-nuss.c | 24 ++-
drivers/net/ti/cpsw.c | 3 +-
drivers/net/ti/cpsw_mdio.c | 255 +++++++++++++++++++++++++++++++-
drivers/net/ti/cpsw_mdio.h | 2 +-
drivers/net/ti/keystone_net.c | 3 +-
5 files changed, 279 insertions(+), 8 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] net: ti: cpsw-mdio: Add workaround for errata i2329
2022-09-22 9:51 [PATCH 0/2] Implement workaround for errata i2329 Ravi Gunasekaran
@ 2022-09-22 9:51 ` Ravi Gunasekaran
2022-10-05 2:06 ` Ramon Fried
2022-10-07 15:48 ` Tom Rini
2022-09-22 9:51 ` [PATCH 2/2] net: ti: am65-cpsw-nuss: Enable MDIO manual mode Ravi Gunasekaran
1 sibling, 2 replies; 7+ messages in thread
From: Ravi Gunasekaran @ 2022-09-22 9:51 UTC (permalink / raw)
To: joe.hershberger, rfried.dev
Cc: vigneshr, kabel, sr, trini, vladimir.oltean, u-boot, r-gunasekaran
In certain TI SoCs, on the CPSW and ICSS peripherals, there is
a possibility that the MDIO interface returns corrupt data on
MDIO reads or writes incorrect data on MDIO writes. There is also
a possibility for the MDIO interface to become unavailable until
the next peripheral reset.
The workaround is to configure the MDIO in manual mode and disable the
MDIO state machine and emulate the MDIO protocol by reading and writing
appropriate fields in MDIO_MANUAL_IF_REG register of the MDIO controller
to manipulate the MDIO clock and data pins.
More details about the errata i2329 and the workaround is available in:
https://www.ti.com/lit/er/sprz487a/sprz487a.pdf
Add implementation to disable MDIO state machine, configure MDIO in manual
mode and provide software MDIO read and writes via MDIO bitbanging. Allow
the MDIO to be initialized based on the need for manual mode.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
---
drivers/net/ti/am65-cpsw-nuss.c | 3 +-
drivers/net/ti/cpsw.c | 3 +-
drivers/net/ti/cpsw_mdio.c | 255 +++++++++++++++++++++++++++++++-
drivers/net/ti/cpsw_mdio.h | 2 +-
drivers/net/ti/keystone_net.c | 3 +-
5 files changed, 258 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 9580fa37ea..29c0422961 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -552,7 +552,8 @@ static int am65_cpsw_mdio_init(struct udevice *dev)
cpsw_common->bus = cpsw_mdio_init(dev->name,
cpsw_common->mdio_base,
cpsw_common->bus_freq,
- clk_get_rate(&cpsw_common->fclk));
+ clk_get_rate(&cpsw_common->fclk),
+ false);
if (!cpsw_common->bus)
return -EFAULT;
diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 8988c21e66..41cba7930d 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -922,7 +922,8 @@ int _cpsw_register(struct cpsw_priv *priv)
idx = idx + 1;
}
- priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
+ priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0,
+ false);
if (!priv->bus)
return -EFAULT;
diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c
index f4cb86d10a..a5ba73b739 100644
--- a/drivers/net/ti/cpsw_mdio.c
+++ b/drivers/net/ti/cpsw_mdio.c
@@ -23,6 +23,11 @@ struct cpsw_mdio_regs {
#define CONTROL_FAULT_ENABLE BIT(18)
#define CONTROL_DIV_MASK GENMASK(15, 0)
+#define MDIO_MAN_MDCLK_O BIT(2)
+#define MDIO_MAN_OE BIT(1)
+#define MDIO_MAN_PIN BIT(0)
+#define MDIO_MANUALMODE BIT(31)
+
u32 alive;
u32 link;
u32 linkintraw;
@@ -32,7 +37,9 @@ struct cpsw_mdio_regs {
u32 userintmasked;
u32 userintmaskset;
u32 userintmaskclr;
- u32 __reserved_1[20];
+ u32 manualif;
+ u32 poll;
+ u32 __reserved_1[18];
struct {
u32 access;
@@ -51,6 +58,13 @@ struct cpsw_mdio_regs {
#define PHY_REG_MASK 0x1f
#define PHY_ID_MASK 0x1f
+#define MDIO_BITRANGE 0x8000
+#define C22_READ_PATTERN 0x6
+#define C22_WRITE_PATTERN 0x5
+#define C22_BITRANGE 0x8
+#define PHY_BITRANGE 0x10
+#define PHY_DATA_BITRANGE 0x8000
+
/*
* This timeout definition is a worst-case ultra defensive measure against
* unexpected controller lock ups. Ideally, we should never ever hit this
@@ -58,12 +72,239 @@ struct cpsw_mdio_regs {
*/
#define CPSW_MDIO_TIMEOUT 100 /* msecs */
+enum cpsw_mdio_manual {
+ MDIO_PIN = 0,
+ MDIO_OE,
+ MDIO_MDCLK,
+};
+
struct cpsw_mdio {
struct cpsw_mdio_regs *regs;
struct mii_dev *bus;
int div;
};
+static void cpsw_mdio_disable(struct cpsw_mdio *mdio)
+{
+ u32 reg;
+ /* Disable MDIO state machine */
+ reg = readl(&mdio->regs->control);
+ reg &= ~CONTROL_ENABLE;
+
+ writel(reg, &mdio->regs->control);
+}
+
+static void cpsw_mdio_enable_manual_mode(struct cpsw_mdio *mdio)
+{
+ u32 reg;
+
+ /* set manual mode */
+ reg = readl(&mdio->regs->poll);
+ reg |= MDIO_MANUALMODE;
+
+ writel(reg, &mdio->regs->poll);
+}
+
+static void cpsw_mdio_sw_set_bit(struct cpsw_mdio *mdio,
+ enum cpsw_mdio_manual bit)
+{
+ u32 reg;
+
+ reg = readl(&mdio->regs->manualif);
+
+ switch (bit) {
+ case MDIO_OE:
+ reg |= MDIO_MAN_OE;
+ writel(reg, &mdio->regs->manualif);
+ break;
+ case MDIO_PIN:
+ reg |= MDIO_MAN_PIN;
+ writel(reg, &mdio->regs->manualif);
+ break;
+ case MDIO_MDCLK:
+ reg |= MDIO_MAN_MDCLK_O;
+ writel(reg, &mdio->regs->manualif);
+ break;
+ default:
+ break;
+ };
+}
+
+static void cpsw_mdio_sw_clr_bit(struct cpsw_mdio *mdio,
+ enum cpsw_mdio_manual bit)
+{
+ u32 reg;
+
+ reg = readl(&mdio->regs->manualif);
+
+ switch (bit) {
+ case MDIO_OE:
+ reg &= ~MDIO_MAN_OE;
+ writel(reg, &mdio->regs->manualif);
+ break;
+ case MDIO_PIN:
+ reg &= ~MDIO_MAN_PIN;
+ writel(reg, &mdio->regs->manualif);
+ break;
+ case MDIO_MDCLK:
+ reg = readl(&mdio->regs->manualif);
+ reg &= ~MDIO_MAN_MDCLK_O;
+ writel(reg, &mdio->regs->manualif);
+ break;
+ default:
+ break;
+ };
+}
+
+static int cpsw_mdio_test_man_bit(struct cpsw_mdio *mdio,
+ enum cpsw_mdio_manual bit)
+{
+ u32 reg;
+
+ reg = readl(&mdio->regs->manualif);
+ return test_bit(bit, ®);
+}
+
+static void cpsw_mdio_toggle_man_bit(struct cpsw_mdio *mdio,
+ enum cpsw_mdio_manual bit)
+{
+ cpsw_mdio_sw_clr_bit(mdio, bit);
+ cpsw_mdio_sw_set_bit(mdio, bit);
+}
+
+static void cpsw_mdio_man_send_pattern(struct cpsw_mdio *mdio,
+ u32 bitrange, u32 val)
+{
+ u32 i;
+
+ for (i = bitrange; i; i = i >> 1) {
+ if (i & val)
+ cpsw_mdio_sw_set_bit(mdio, MDIO_PIN);
+ else
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_PIN);
+
+ cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
+ }
+}
+
+static void cpsw_mdio_sw_preamble(struct cpsw_mdio *mdio)
+{
+ u32 i;
+
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
+
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
+
+ for (i = 0; i < 32; i++) {
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
+ }
+}
+
+static int cpsw_mdio_sw_read(struct mii_dev *bus, int phy_id,
+ int dev_addr, int phy_reg)
+{
+ struct cpsw_mdio *mdio = bus->priv;
+ u32 reg, i;
+ u8 ack;
+
+ if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+ return -EINVAL;
+
+ cpsw_mdio_disable(mdio);
+ cpsw_mdio_enable_manual_mode(mdio);
+ cpsw_mdio_sw_preamble(mdio);
+
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_set_bit(mdio, MDIO_OE);
+
+ /* Issue clause 22 MII read function {0,1,1,0} */
+ cpsw_mdio_man_send_pattern(mdio, C22_BITRANGE, C22_READ_PATTERN);
+
+ /* Send the device number MSB first */
+ cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_id);
+
+ /* Send the register number MSB first */
+ cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_reg);
+
+ /* Send turn around cycles */
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
+
+ cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
+
+ ack = cpsw_mdio_test_man_bit(mdio, MDIO_PIN);
+ cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
+
+ reg = 0;
+ if (ack == 0) {
+ for (i = MDIO_BITRANGE; i; i = i >> 1) {
+ if (cpsw_mdio_test_man_bit(mdio, MDIO_PIN))
+ reg |= i;
+
+ cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
+ }
+ } else {
+ for (i = MDIO_BITRANGE; i; i = i >> 1)
+ cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
+
+ reg = 0xFFFF;
+ }
+
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
+
+ return reg;
+}
+
+static int cpsw_mdio_sw_write(struct mii_dev *bus, int phy_id,
+ int dev_addr, int phy_reg, u16 phy_data)
+{
+ struct cpsw_mdio *mdio = bus->priv;
+
+ if ((phy_reg & ~PHY_REG_MASK) || (phy_id & ~PHY_ID_MASK))
+ return -EINVAL;
+
+ cpsw_mdio_disable(mdio);
+ cpsw_mdio_enable_manual_mode(mdio);
+ cpsw_mdio_sw_preamble(mdio);
+
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_set_bit(mdio, MDIO_OE);
+
+ /* Issue clause 22 MII write function {0,1,0,1} */
+ cpsw_mdio_man_send_pattern(mdio, C22_BITRANGE, C22_WRITE_PATTERN);
+
+ /* Send the device number MSB first */
+ cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_id);
+
+ /* Send the register number MSB first */
+ cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_reg);
+
+ /* set turn-around cycles */
+ cpsw_mdio_sw_set_bit(mdio, MDIO_PIN);
+ cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_PIN);
+ cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
+
+ /* Send Register data MSB first */
+ cpsw_mdio_man_send_pattern(mdio, PHY_DATA_BITRANGE, phy_data);
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
+
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
+ cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
+
+ return 0;
+}
+
/* wait until hardware is ready for another user access */
static int cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio)
{
@@ -130,7 +371,7 @@ u32 cpsw_mdio_get_alive(struct mii_dev *bus)
}
struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
- u32 bus_freq, int fck_freq)
+ u32 bus_freq, int fck_freq, bool manual_mode)
{
struct cpsw_mdio *cpsw_mdio;
int ret;
@@ -172,8 +413,14 @@ struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
*/
mdelay(1);
- cpsw_mdio->bus->read = cpsw_mdio_read;
- cpsw_mdio->bus->write = cpsw_mdio_write;
+ if (manual_mode) {
+ cpsw_mdio->bus->read = cpsw_mdio_sw_read;
+ cpsw_mdio->bus->write = cpsw_mdio_sw_write;
+ } else {
+ cpsw_mdio->bus->read = cpsw_mdio_read;
+ cpsw_mdio->bus->write = cpsw_mdio_write;
+ }
+
cpsw_mdio->bus->priv = cpsw_mdio;
snprintf(cpsw_mdio->bus->name, sizeof(cpsw_mdio->bus->name), name);
diff --git a/drivers/net/ti/cpsw_mdio.h b/drivers/net/ti/cpsw_mdio.h
index dbf4a2dcac..9b98763656 100644
--- a/drivers/net/ti/cpsw_mdio.h
+++ b/drivers/net/ti/cpsw_mdio.h
@@ -11,7 +11,7 @@
struct cpsw_mdio;
struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
- u32 bus_freq, int fck_freq);
+ u32 bus_freq, int fck_freq, bool manual_mode);
void cpsw_mdio_free(struct mii_dev *bus);
u32 cpsw_mdio_get_alive(struct mii_dev *bus);
diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c
index fbec69f571..1bdbd599d7 100644
--- a/drivers/net/ti/keystone_net.c
+++ b/drivers/net/ti/keystone_net.c
@@ -571,7 +571,8 @@ static int ks2_eth_probe(struct udevice *dev)
mdio_bus = cpsw_mdio_init("ethernet-mdio",
priv->mdio_base,
EMAC_MDIO_CLOCK_FREQ,
- EMAC_MDIO_BUS_FREQ);
+ EMAC_MDIO_BUS_FREQ,
+ false);
if (!mdio_bus) {
pr_err("MDIO alloc failed\n");
return -ENOMEM;
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] net: ti: am65-cpsw-nuss: Enable MDIO manual mode
2022-09-22 9:51 [PATCH 0/2] Implement workaround for errata i2329 Ravi Gunasekaran
2022-09-22 9:51 ` [PATCH 1/2] net: ti: cpsw-mdio: Add " Ravi Gunasekaran
@ 2022-09-22 9:51 ` Ravi Gunasekaran
2022-10-05 2:07 ` Ramon Fried
2022-10-07 15:48 ` Tom Rini
1 sibling, 2 replies; 7+ messages in thread
From: Ravi Gunasekaran @ 2022-09-22 9:51 UTC (permalink / raw)
To: joe.hershberger, rfried.dev
Cc: vigneshr, kabel, sr, trini, vladimir.oltean, u-boot, r-gunasekaran
For the TI SoCs affected by errata i2329, enable MDIO manual
mode by default
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
---
drivers/net/ti/am65-cpsw-nuss.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 29c0422961..5ef04e3d83 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -21,6 +21,7 @@
#include <net.h>
#include <phy.h>
#include <power-domain.h>
+#include <soc.h>
#include <linux/bitops.h>
#include <linux/soc/ti/ti-udma.h>
@@ -127,6 +128,8 @@ struct am65_cpsw_priv {
bool has_phy;
ofnode phy_node;
u32 phy_addr;
+
+ bool mdio_manual_mode;
};
#ifdef PKTSIZE_ALIGN
@@ -541,6 +544,20 @@ static const struct eth_ops am65_cpsw_ops = {
.read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
};
+static const struct soc_attr k3_mdio_soc_data[] = {
+ { .family = "AM62X", .revision = "SR1.0" },
+ { .family = "AM64X", .revision = "SR1.0" },
+ { .family = "AM64X", .revision = "SR2.0" },
+ { .family = "AM65X", .revision = "SR1.0" },
+ { .family = "AM65X", .revision = "SR2.0" },
+ { .family = "J7200", .revision = "SR1.0" },
+ { .family = "J7200", .revision = "SR2.0" },
+ { .family = "J721E", .revision = "SR1.0" },
+ { .family = "J721E", .revision = "SR1.1" },
+ { .family = "J721S2", .revision = "SR1.0" },
+ { /* sentinel */ },
+};
+
static int am65_cpsw_mdio_init(struct udevice *dev)
{
struct am65_cpsw_priv *priv = dev_get_priv(dev);
@@ -553,7 +570,7 @@ static int am65_cpsw_mdio_init(struct udevice *dev)
cpsw_common->mdio_base,
cpsw_common->bus_freq,
clk_get_rate(&cpsw_common->fclk),
- false);
+ priv->mdio_manual_mode);
if (!cpsw_common->bus)
return -EFAULT;
@@ -658,6 +675,10 @@ static int am65_cpsw_port_probe(struct udevice *dev)
sprintf(portname, "%s%s", dev->parent->name, dev->name);
device_set_name(dev, portname);
+ priv->mdio_manual_mode = false;
+ if (soc_device_match(k3_mdio_soc_data))
+ priv->mdio_manual_mode = true;
+
ret = am65_cpsw_ofdata_parse_phy(dev);
if (ret)
goto out;
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] net: ti: cpsw-mdio: Add workaround for errata i2329
2022-09-22 9:51 ` [PATCH 1/2] net: ti: cpsw-mdio: Add " Ravi Gunasekaran
@ 2022-10-05 2:06 ` Ramon Fried
2022-10-07 15:48 ` Tom Rini
1 sibling, 0 replies; 7+ messages in thread
From: Ramon Fried @ 2022-10-05 2:06 UTC (permalink / raw)
To: Ravi Gunasekaran
Cc: joe.hershberger, vigneshr, kabel, sr, trini, vladimir.oltean, u-boot
On Thu, Sep 22, 2022 at 12:51 PM Ravi Gunasekaran <r-gunasekaran@ti.com> wrote:
>
> In certain TI SoCs, on the CPSW and ICSS peripherals, there is
> a possibility that the MDIO interface returns corrupt data on
> MDIO reads or writes incorrect data on MDIO writes. There is also
> a possibility for the MDIO interface to become unavailable until
> the next peripheral reset.
>
> The workaround is to configure the MDIO in manual mode and disable the
> MDIO state machine and emulate the MDIO protocol by reading and writing
> appropriate fields in MDIO_MANUAL_IF_REG register of the MDIO controller
> to manipulate the MDIO clock and data pins.
>
> More details about the errata i2329 and the workaround is available in:
> https://www.ti.com/lit/er/sprz487a/sprz487a.pdf
>
> Add implementation to disable MDIO state machine, configure MDIO in manual
> mode and provide software MDIO read and writes via MDIO bitbanging. Allow
> the MDIO to be initialized based on the need for manual mode.
>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> ---
> drivers/net/ti/am65-cpsw-nuss.c | 3 +-
> drivers/net/ti/cpsw.c | 3 +-
> drivers/net/ti/cpsw_mdio.c | 255 +++++++++++++++++++++++++++++++-
> drivers/net/ti/cpsw_mdio.h | 2 +-
> drivers/net/ti/keystone_net.c | 3 +-
> 5 files changed, 258 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
> index 9580fa37ea..29c0422961 100644
> --- a/drivers/net/ti/am65-cpsw-nuss.c
> +++ b/drivers/net/ti/am65-cpsw-nuss.c
> @@ -552,7 +552,8 @@ static int am65_cpsw_mdio_init(struct udevice *dev)
> cpsw_common->bus = cpsw_mdio_init(dev->name,
> cpsw_common->mdio_base,
> cpsw_common->bus_freq,
> - clk_get_rate(&cpsw_common->fclk));
> + clk_get_rate(&cpsw_common->fclk),
> + false);
> if (!cpsw_common->bus)
> return -EFAULT;
>
> diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
> index 8988c21e66..41cba7930d 100644
> --- a/drivers/net/ti/cpsw.c
> +++ b/drivers/net/ti/cpsw.c
> @@ -922,7 +922,8 @@ int _cpsw_register(struct cpsw_priv *priv)
> idx = idx + 1;
> }
>
> - priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
> + priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0,
> + false);
> if (!priv->bus)
> return -EFAULT;
>
> diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c
> index f4cb86d10a..a5ba73b739 100644
> --- a/drivers/net/ti/cpsw_mdio.c
> +++ b/drivers/net/ti/cpsw_mdio.c
> @@ -23,6 +23,11 @@ struct cpsw_mdio_regs {
> #define CONTROL_FAULT_ENABLE BIT(18)
> #define CONTROL_DIV_MASK GENMASK(15, 0)
>
> +#define MDIO_MAN_MDCLK_O BIT(2)
> +#define MDIO_MAN_OE BIT(1)
> +#define MDIO_MAN_PIN BIT(0)
> +#define MDIO_MANUALMODE BIT(31)
> +
> u32 alive;
> u32 link;
> u32 linkintraw;
> @@ -32,7 +37,9 @@ struct cpsw_mdio_regs {
> u32 userintmasked;
> u32 userintmaskset;
> u32 userintmaskclr;
> - u32 __reserved_1[20];
> + u32 manualif;
> + u32 poll;
> + u32 __reserved_1[18];
>
> struct {
> u32 access;
> @@ -51,6 +58,13 @@ struct cpsw_mdio_regs {
> #define PHY_REG_MASK 0x1f
> #define PHY_ID_MASK 0x1f
>
> +#define MDIO_BITRANGE 0x8000
> +#define C22_READ_PATTERN 0x6
> +#define C22_WRITE_PATTERN 0x5
> +#define C22_BITRANGE 0x8
> +#define PHY_BITRANGE 0x10
> +#define PHY_DATA_BITRANGE 0x8000
> +
> /*
> * This timeout definition is a worst-case ultra defensive measure against
> * unexpected controller lock ups. Ideally, we should never ever hit this
> @@ -58,12 +72,239 @@ struct cpsw_mdio_regs {
> */
> #define CPSW_MDIO_TIMEOUT 100 /* msecs */
>
> +enum cpsw_mdio_manual {
> + MDIO_PIN = 0,
> + MDIO_OE,
> + MDIO_MDCLK,
> +};
> +
> struct cpsw_mdio {
> struct cpsw_mdio_regs *regs;
> struct mii_dev *bus;
> int div;
> };
>
> +static void cpsw_mdio_disable(struct cpsw_mdio *mdio)
> +{
> + u32 reg;
> + /* Disable MDIO state machine */
> + reg = readl(&mdio->regs->control);
> + reg &= ~CONTROL_ENABLE;
> +
> + writel(reg, &mdio->regs->control);
> +}
> +
> +static void cpsw_mdio_enable_manual_mode(struct cpsw_mdio *mdio)
> +{
> + u32 reg;
> +
> + /* set manual mode */
> + reg = readl(&mdio->regs->poll);
> + reg |= MDIO_MANUALMODE;
> +
> + writel(reg, &mdio->regs->poll);
> +}
> +
> +static void cpsw_mdio_sw_set_bit(struct cpsw_mdio *mdio,
> + enum cpsw_mdio_manual bit)
> +{
> + u32 reg;
> +
> + reg = readl(&mdio->regs->manualif);
> +
> + switch (bit) {
> + case MDIO_OE:
> + reg |= MDIO_MAN_OE;
> + writel(reg, &mdio->regs->manualif);
> + break;
> + case MDIO_PIN:
> + reg |= MDIO_MAN_PIN;
> + writel(reg, &mdio->regs->manualif);
> + break;
> + case MDIO_MDCLK:
> + reg |= MDIO_MAN_MDCLK_O;
> + writel(reg, &mdio->regs->manualif);
> + break;
> + default:
> + break;
> + };
> +}
> +
> +static void cpsw_mdio_sw_clr_bit(struct cpsw_mdio *mdio,
> + enum cpsw_mdio_manual bit)
> +{
> + u32 reg;
> +
> + reg = readl(&mdio->regs->manualif);
> +
> + switch (bit) {
> + case MDIO_OE:
> + reg &= ~MDIO_MAN_OE;
> + writel(reg, &mdio->regs->manualif);
> + break;
> + case MDIO_PIN:
> + reg &= ~MDIO_MAN_PIN;
> + writel(reg, &mdio->regs->manualif);
> + break;
> + case MDIO_MDCLK:
> + reg = readl(&mdio->regs->manualif);
> + reg &= ~MDIO_MAN_MDCLK_O;
> + writel(reg, &mdio->regs->manualif);
> + break;
> + default:
> + break;
> + };
> +}
> +
> +static int cpsw_mdio_test_man_bit(struct cpsw_mdio *mdio,
> + enum cpsw_mdio_manual bit)
> +{
> + u32 reg;
> +
> + reg = readl(&mdio->regs->manualif);
> + return test_bit(bit, ®);
> +}
> +
> +static void cpsw_mdio_toggle_man_bit(struct cpsw_mdio *mdio,
> + enum cpsw_mdio_manual bit)
> +{
> + cpsw_mdio_sw_clr_bit(mdio, bit);
> + cpsw_mdio_sw_set_bit(mdio, bit);
> +}
> +
> +static void cpsw_mdio_man_send_pattern(struct cpsw_mdio *mdio,
> + u32 bitrange, u32 val)
> +{
> + u32 i;
> +
> + for (i = bitrange; i; i = i >> 1) {
> + if (i & val)
> + cpsw_mdio_sw_set_bit(mdio, MDIO_PIN);
> + else
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_PIN);
> +
> + cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
> + }
> +}
> +
> +static void cpsw_mdio_sw_preamble(struct cpsw_mdio *mdio)
> +{
> + u32 i;
> +
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
> +
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
> +
> + for (i = 0; i < 32; i++) {
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
> + }
> +}
> +
> +static int cpsw_mdio_sw_read(struct mii_dev *bus, int phy_id,
> + int dev_addr, int phy_reg)
> +{
> + struct cpsw_mdio *mdio = bus->priv;
> + u32 reg, i;
> + u8 ack;
> +
> + if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
> + return -EINVAL;
> +
> + cpsw_mdio_disable(mdio);
> + cpsw_mdio_enable_manual_mode(mdio);
> + cpsw_mdio_sw_preamble(mdio);
> +
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_set_bit(mdio, MDIO_OE);
> +
> + /* Issue clause 22 MII read function {0,1,1,0} */
> + cpsw_mdio_man_send_pattern(mdio, C22_BITRANGE, C22_READ_PATTERN);
> +
> + /* Send the device number MSB first */
> + cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_id);
> +
> + /* Send the register number MSB first */
> + cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_reg);
> +
> + /* Send turn around cycles */
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
> +
> + cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
> +
> + ack = cpsw_mdio_test_man_bit(mdio, MDIO_PIN);
> + cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
> +
> + reg = 0;
> + if (ack == 0) {
> + for (i = MDIO_BITRANGE; i; i = i >> 1) {
> + if (cpsw_mdio_test_man_bit(mdio, MDIO_PIN))
> + reg |= i;
> +
> + cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
> + }
> + } else {
> + for (i = MDIO_BITRANGE; i; i = i >> 1)
> + cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
> +
> + reg = 0xFFFF;
> + }
> +
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
> +
> + return reg;
> +}
> +
> +static int cpsw_mdio_sw_write(struct mii_dev *bus, int phy_id,
> + int dev_addr, int phy_reg, u16 phy_data)
> +{
> + struct cpsw_mdio *mdio = bus->priv;
> +
> + if ((phy_reg & ~PHY_REG_MASK) || (phy_id & ~PHY_ID_MASK))
> + return -EINVAL;
> +
> + cpsw_mdio_disable(mdio);
> + cpsw_mdio_enable_manual_mode(mdio);
> + cpsw_mdio_sw_preamble(mdio);
> +
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_set_bit(mdio, MDIO_OE);
> +
> + /* Issue clause 22 MII write function {0,1,0,1} */
> + cpsw_mdio_man_send_pattern(mdio, C22_BITRANGE, C22_WRITE_PATTERN);
> +
> + /* Send the device number MSB first */
> + cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_id);
> +
> + /* Send the register number MSB first */
> + cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_reg);
> +
> + /* set turn-around cycles */
> + cpsw_mdio_sw_set_bit(mdio, MDIO_PIN);
> + cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_PIN);
> + cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
> +
> + /* Send Register data MSB first */
> + cpsw_mdio_man_send_pattern(mdio, PHY_DATA_BITRANGE, phy_data);
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
> +
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
> + cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
> +
> + return 0;
> +}
> +
> /* wait until hardware is ready for another user access */
> static int cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio)
> {
> @@ -130,7 +371,7 @@ u32 cpsw_mdio_get_alive(struct mii_dev *bus)
> }
>
> struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
> - u32 bus_freq, int fck_freq)
> + u32 bus_freq, int fck_freq, bool manual_mode)
> {
> struct cpsw_mdio *cpsw_mdio;
> int ret;
> @@ -172,8 +413,14 @@ struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
> */
> mdelay(1);
>
> - cpsw_mdio->bus->read = cpsw_mdio_read;
> - cpsw_mdio->bus->write = cpsw_mdio_write;
> + if (manual_mode) {
> + cpsw_mdio->bus->read = cpsw_mdio_sw_read;
> + cpsw_mdio->bus->write = cpsw_mdio_sw_write;
> + } else {
> + cpsw_mdio->bus->read = cpsw_mdio_read;
> + cpsw_mdio->bus->write = cpsw_mdio_write;
> + }
> +
> cpsw_mdio->bus->priv = cpsw_mdio;
> snprintf(cpsw_mdio->bus->name, sizeof(cpsw_mdio->bus->name), name);
>
> diff --git a/drivers/net/ti/cpsw_mdio.h b/drivers/net/ti/cpsw_mdio.h
> index dbf4a2dcac..9b98763656 100644
> --- a/drivers/net/ti/cpsw_mdio.h
> +++ b/drivers/net/ti/cpsw_mdio.h
> @@ -11,7 +11,7 @@
> struct cpsw_mdio;
>
> struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
> - u32 bus_freq, int fck_freq);
> + u32 bus_freq, int fck_freq, bool manual_mode);
> void cpsw_mdio_free(struct mii_dev *bus);
> u32 cpsw_mdio_get_alive(struct mii_dev *bus);
>
> diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c
> index fbec69f571..1bdbd599d7 100644
> --- a/drivers/net/ti/keystone_net.c
> +++ b/drivers/net/ti/keystone_net.c
> @@ -571,7 +571,8 @@ static int ks2_eth_probe(struct udevice *dev)
> mdio_bus = cpsw_mdio_init("ethernet-mdio",
> priv->mdio_base,
> EMAC_MDIO_CLOCK_FREQ,
> - EMAC_MDIO_BUS_FREQ);
> + EMAC_MDIO_BUS_FREQ,
> + false);
> if (!mdio_bus) {
> pr_err("MDIO alloc failed\n");
> return -ENOMEM;
> --
> 2.17.1
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] net: ti: am65-cpsw-nuss: Enable MDIO manual mode
2022-09-22 9:51 ` [PATCH 2/2] net: ti: am65-cpsw-nuss: Enable MDIO manual mode Ravi Gunasekaran
@ 2022-10-05 2:07 ` Ramon Fried
2022-10-07 15:48 ` Tom Rini
1 sibling, 0 replies; 7+ messages in thread
From: Ramon Fried @ 2022-10-05 2:07 UTC (permalink / raw)
To: Ravi Gunasekaran
Cc: joe.hershberger, vigneshr, kabel, sr, trini, vladimir.oltean, u-boot
On Thu, Sep 22, 2022 at 12:51 PM Ravi Gunasekaran <r-gunasekaran@ti.com> wrote:
>
> For the TI SoCs affected by errata i2329, enable MDIO manual
> mode by default
>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> ---
> drivers/net/ti/am65-cpsw-nuss.c | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
> index 29c0422961..5ef04e3d83 100644
> --- a/drivers/net/ti/am65-cpsw-nuss.c
> +++ b/drivers/net/ti/am65-cpsw-nuss.c
> @@ -21,6 +21,7 @@
> #include <net.h>
> #include <phy.h>
> #include <power-domain.h>
> +#include <soc.h>
> #include <linux/bitops.h>
> #include <linux/soc/ti/ti-udma.h>
>
> @@ -127,6 +128,8 @@ struct am65_cpsw_priv {
> bool has_phy;
> ofnode phy_node;
> u32 phy_addr;
> +
> + bool mdio_manual_mode;
> };
>
> #ifdef PKTSIZE_ALIGN
> @@ -541,6 +544,20 @@ static const struct eth_ops am65_cpsw_ops = {
> .read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
> };
>
> +static const struct soc_attr k3_mdio_soc_data[] = {
> + { .family = "AM62X", .revision = "SR1.0" },
> + { .family = "AM64X", .revision = "SR1.0" },
> + { .family = "AM64X", .revision = "SR2.0" },
> + { .family = "AM65X", .revision = "SR1.0" },
> + { .family = "AM65X", .revision = "SR2.0" },
> + { .family = "J7200", .revision = "SR1.0" },
> + { .family = "J7200", .revision = "SR2.0" },
> + { .family = "J721E", .revision = "SR1.0" },
> + { .family = "J721E", .revision = "SR1.1" },
> + { .family = "J721S2", .revision = "SR1.0" },
> + { /* sentinel */ },
> +};
> +
> static int am65_cpsw_mdio_init(struct udevice *dev)
> {
> struct am65_cpsw_priv *priv = dev_get_priv(dev);
> @@ -553,7 +570,7 @@ static int am65_cpsw_mdio_init(struct udevice *dev)
> cpsw_common->mdio_base,
> cpsw_common->bus_freq,
> clk_get_rate(&cpsw_common->fclk),
> - false);
> + priv->mdio_manual_mode);
> if (!cpsw_common->bus)
> return -EFAULT;
>
> @@ -658,6 +675,10 @@ static int am65_cpsw_port_probe(struct udevice *dev)
> sprintf(portname, "%s%s", dev->parent->name, dev->name);
> device_set_name(dev, portname);
>
> + priv->mdio_manual_mode = false;
> + if (soc_device_match(k3_mdio_soc_data))
> + priv->mdio_manual_mode = true;
> +
> ret = am65_cpsw_ofdata_parse_phy(dev);
> if (ret)
> goto out;
> --
> 2.17.1
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] net: ti: cpsw-mdio: Add workaround for errata i2329
2022-09-22 9:51 ` [PATCH 1/2] net: ti: cpsw-mdio: Add " Ravi Gunasekaran
2022-10-05 2:06 ` Ramon Fried
@ 2022-10-07 15:48 ` Tom Rini
1 sibling, 0 replies; 7+ messages in thread
From: Tom Rini @ 2022-10-07 15:48 UTC (permalink / raw)
To: Ravi Gunasekaran
Cc: joe.hershberger, rfried.dev, vigneshr, kabel, sr,
vladimir.oltean, u-boot
[-- Attachment #1: Type: text/plain, Size: 1159 bytes --]
On Thu, Sep 22, 2022 at 03:21:23PM +0530, Ravi Gunasekaran wrote:
> In certain TI SoCs, on the CPSW and ICSS peripherals, there is
> a possibility that the MDIO interface returns corrupt data on
> MDIO reads or writes incorrect data on MDIO writes. There is also
> a possibility for the MDIO interface to become unavailable until
> the next peripheral reset.
>
> The workaround is to configure the MDIO in manual mode and disable the
> MDIO state machine and emulate the MDIO protocol by reading and writing
> appropriate fields in MDIO_MANUAL_IF_REG register of the MDIO controller
> to manipulate the MDIO clock and data pins.
>
> More details about the errata i2329 and the workaround is available in:
> https://www.ti.com/lit/er/sprz487a/sprz487a.pdf
>
> Add implementation to disable MDIO state machine, configure MDIO in manual
> mode and provide software MDIO read and writes via MDIO bitbanging. Allow
> the MDIO to be initialized based on the need for manual mode.
>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] net: ti: am65-cpsw-nuss: Enable MDIO manual mode
2022-09-22 9:51 ` [PATCH 2/2] net: ti: am65-cpsw-nuss: Enable MDIO manual mode Ravi Gunasekaran
2022-10-05 2:07 ` Ramon Fried
@ 2022-10-07 15:48 ` Tom Rini
1 sibling, 0 replies; 7+ messages in thread
From: Tom Rini @ 2022-10-07 15:48 UTC (permalink / raw)
To: Ravi Gunasekaran
Cc: joe.hershberger, rfried.dev, vigneshr, kabel, sr,
vladimir.oltean, u-boot
[-- Attachment #1: Type: text/plain, Size: 314 bytes --]
On Thu, Sep 22, 2022 at 03:21:24PM +0530, Ravi Gunasekaran wrote:
> For the TI SoCs affected by errata i2329, enable MDIO manual
> mode by default
>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-10-07 15:48 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-22 9:51 [PATCH 0/2] Implement workaround for errata i2329 Ravi Gunasekaran
2022-09-22 9:51 ` [PATCH 1/2] net: ti: cpsw-mdio: Add " Ravi Gunasekaran
2022-10-05 2:06 ` Ramon Fried
2022-10-07 15:48 ` Tom Rini
2022-09-22 9:51 ` [PATCH 2/2] net: ti: am65-cpsw-nuss: Enable MDIO manual mode Ravi Gunasekaran
2022-10-05 2:07 ` Ramon Fried
2022-10-07 15:48 ` Tom Rini
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