* [PULL 00/39] target-arm queue
@ 2022-09-22 16:34 Peter Maydell
2022-09-22 16:34 ` [PULL 01/39] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic Peter Maydell
` (39 more replies)
0 siblings, 40 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:34 UTC (permalink / raw)
To: qemu-devel
Hi; this pullreq contains mainly a chunk of RTH's refactoring
of the Arm pagetable walk code, plus a series from me fixing
configure checkpatch warnings, and some old patches to various
files all over the tree getting rid of dynamic stack allocation.
thanks
-- PMM
The following changes since commit 6338c30111d596d955e6bc933a82184a0b910c43:
Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k into staging (2022-09-21 13:12:36 -0400)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220922
for you to fetch changes up to b3b5472db0ab7a53499441c1fe1dedec05b1e285:
configure: Avoid use of 'local' as it is non-POSIX (2022-09-22 16:38:29 +0100)
----------------------------------------------------------------
target-arm queue:
* hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
* Fix alignment for Neon VLD4.32
* Refactoring of page-table-walk code
* hw/acpi: Add ospm_status hook implementation for acpi-ged
* hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
* chardev/baum: avoid variable-length arrays
* io/channel-websock: avoid variable-length arrays
* hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
* hw/ppc/pnv: Avoid dynamic stack allocation
* hw/intc/xics: Avoid dynamic stack allocation
* hw/i386/multiboot: Avoid dynamic stack allocation
* hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
* ui/curses: Avoid dynamic stack allocation
* tests/unit/test-vmstate: Avoid dynamic stack allocation
* configure: fix various shellcheck-spotted issues and nits
----------------------------------------------------------------
Anton Kochkov (1):
hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
Clément Chigot (1):
target/arm: Fix alignment for VLD4.32
Keqian Zhu (1):
hw/acpi: Add ospm_status hook implementation for acpi-ged
Lucas Dietrich (1):
hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
Peter Maydell (7):
configure: Remove unused python_version variable
configure: Remove unused meson_args variable
configure: Add missing quoting for some easy cases
configure: Add './' on front of glob of */config-devices.mak.d
configure: Remove use of backtick `...` syntax
configure: Check mkdir result directly, not via $?
configure: Avoid use of 'local' as it is non-POSIX
Philippe Mathieu-Daudé (11):
chardev/baum: Replace magic values by X_MAX / Y_MAX definitions
chardev/baum: Use definitions to avoid dynamic stack allocation
chardev/baum: Avoid dynamic stack allocation
io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1
hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
hw/ppc/pnv: Avoid dynamic stack allocation
hw/intc/xics: Avoid dynamic stack allocation
hw/i386/multiboot: Avoid dynamic stack allocation
hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
ui/curses: Avoid dynamic stack allocation
tests/unit/test-vmstate: Avoid dynamic stack allocation
Richard Henderson (17):
target/arm: Create GetPhysAddrResult
target/arm: Use GetPhysAddrResult in get_phys_addr_lpae
target/arm: Use GetPhysAddrResult in get_phys_addr_v6
target/arm: Use GetPhysAddrResult in get_phys_addr_v5
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8
target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup
target/arm: Remove is_subpage argument to pmsav8_mpu_lookup
target/arm: Add is_secure parameter to v8m_security_lookup
target/arm: Add secure parameter to pmsav8_mpu_lookup
target/arm: Add is_secure parameter to get_phys_addr_v5
target/arm: Add is_secure parameter to get_phys_addr_v6
target/arm: Add secure parameter to get_phys_addr_pmsav8
target/arm: Add is_secure parameter to pmsav7_use_background_region
target/arm: Add secure parameter to get_phys_addr_pmsav7
target/arm: Add is_secure parameter to get_phys_addr_pmsav5
configure | 82 +++++-----
target/arm/internals.h | 26 +--
chardev/baum.c | 22 ++-
hw/acpi/generic_event_device.c | 8 +
hw/i386/multiboot.c | 5 +-
hw/intc/xics.c | 2 +-
hw/net/can/xlnx-zynqmp-can.c | 32 ++--
hw/net/e1000e_core.c | 7 +-
hw/net/lan9118.c | 8 +
hw/ppc/pnv.c | 4 +-
hw/ppc/spapr.c | 8 +-
hw/ppc/spapr_pci_nvlink2.c | 2 +-
hw/usb/hcd-ohci.c | 7 +-
io/channel-websock.c | 2 +-
target/arm/helper.c | 27 ++-
target/arm/m_helper.c | 78 ++++-----
target/arm/ptw.c | 364 +++++++++++++++++++----------------------
target/arm/tlb_helper.c | 22 +--
target/arm/translate-neon.c | 6 +-
tests/unit/test-vmstate.c | 7 +-
ui/curses.c | 2 +-
21 files changed, 347 insertions(+), 374 deletions(-)
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PULL 01/39] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
@ 2022-09-22 16:34 ` Peter Maydell
2022-09-22 16:34 ` [PULL 02/39] target/arm: Fix alignment for VLD4.32 Peter Maydell
` (38 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:34 UTC (permalink / raw)
To: qemu-devel
From: Anton Kochkov <anton.kochkov@proton.me>
For consistency, function "update_rx_fifo()" should use the RX FIFO
register field names, not the TX FIFO ones, even if they refer to the
same bit positions in the register.
Signed-off-by: Anton Kochkov <anton.kochkov@proton.me>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220817141754.2105981-1-anton.kochkov@proton.me
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1123
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/can/xlnx-zynqmp-can.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
index 82ac48cee24..e93e6c5e194 100644
--- a/hw/net/can/xlnx-zynqmp-can.c
+++ b/hw/net/can/xlnx-zynqmp-can.c
@@ -696,30 +696,30 @@ static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame)
timestamp));
/* First 32 bit of the data. */
- fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT,
- R_TXFIFO_DATA1_DB3_LENGTH,
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA1_DB3_SHIFT,
+ R_RXFIFO_DATA1_DB3_LENGTH,
frame->data[0]) |
- deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT,
- R_TXFIFO_DATA1_DB2_LENGTH,
+ deposit32(0, R_RXFIFO_DATA1_DB2_SHIFT,
+ R_RXFIFO_DATA1_DB2_LENGTH,
frame->data[1]) |
- deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT,
- R_TXFIFO_DATA1_DB1_LENGTH,
+ deposit32(0, R_RXFIFO_DATA1_DB1_SHIFT,
+ R_RXFIFO_DATA1_DB1_LENGTH,
frame->data[2]) |
- deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT,
- R_TXFIFO_DATA1_DB0_LENGTH,
+ deposit32(0, R_RXFIFO_DATA1_DB0_SHIFT,
+ R_RXFIFO_DATA1_DB0_LENGTH,
frame->data[3]));
/* Last 32 bit of the data. */
- fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT,
- R_TXFIFO_DATA2_DB7_LENGTH,
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA2_DB7_SHIFT,
+ R_RXFIFO_DATA2_DB7_LENGTH,
frame->data[4]) |
- deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT,
- R_TXFIFO_DATA2_DB6_LENGTH,
+ deposit32(0, R_RXFIFO_DATA2_DB6_SHIFT,
+ R_RXFIFO_DATA2_DB6_LENGTH,
frame->data[5]) |
- deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT,
- R_TXFIFO_DATA2_DB5_LENGTH,
+ deposit32(0, R_RXFIFO_DATA2_DB5_SHIFT,
+ R_RXFIFO_DATA2_DB5_LENGTH,
frame->data[6]) |
- deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT,
- R_TXFIFO_DATA2_DB4_LENGTH,
+ deposit32(0, R_RXFIFO_DATA2_DB4_SHIFT,
+ R_RXFIFO_DATA2_DB4_LENGTH,
frame->data[7]));
ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 02/39] target/arm: Fix alignment for VLD4.32
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
2022-09-22 16:34 ` [PULL 01/39] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic Peter Maydell
@ 2022-09-22 16:34 ` Peter Maydell
2022-09-22 16:35 ` [PULL 03/39] target/arm: Create GetPhysAddrResult Peter Maydell
` (37 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:34 UTC (permalink / raw)
To: qemu-devel
From: Clément Chigot <chigot@adacore.com>
When requested, the alignment for VLD4.32 is 8 and not 16.
See ARM documentation about VLD4 encoding:
ebytes = 1 << UInt(size);
if size == '10' then
alignment = if a == '0' then 1 else 8;
else
alignment = if a == '0' then 1 else 4*ebytes;
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220914105058.2787404-1-chigot@adacore.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-neon.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index 321c17e2c7e..4016339d46f 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -584,7 +584,11 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
case 3:
return false;
case 4:
- align = pow2_align(size + 2);
+ if (size == 2) {
+ align = pow2_align(3);
+ } else {
+ align = pow2_align(size + 2);
+ }
break;
default:
g_assert_not_reached();
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 03/39] target/arm: Create GetPhysAddrResult
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
2022-09-22 16:34 ` [PULL 01/39] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic Peter Maydell
2022-09-22 16:34 ` [PULL 02/39] target/arm: Fix alignment for VLD4.32 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 04/39] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae Peter Maydell
` (36 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Combine 5 output pointer arguments from get_phys_addr
into a single struct. Adjust all callers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 13 ++++-
target/arm/helper.c | 27 ++++-----
target/arm/m_helper.c | 52 ++++++-----------
target/arm/ptw.c | 120 +++++++++++++++++++++-------------------
target/arm/tlb_helper.c | 22 +++-----
5 files changed, 109 insertions(+), 125 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index bf60cd5f845..e9743d3e220 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1142,11 +1142,18 @@ typedef struct ARMCacheAttrs {
bool is_s2_format:1;
} ARMCacheAttrs;
+/* Fields that are valid upon success. */
+typedef struct GetPhysAddrResult {
+ hwaddr phys;
+ target_ulong page_size;
+ int prot;
+ MemTxAttrs attrs;
+ ARMCacheAttrs cacheattrs;
+} GetPhysAddrResult;
+
bool get_phys_addr(CPUARMState *env, target_ulong address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
- target_ulong *page_size,
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
__attribute__((nonnull));
void arm_log_exception(CPUState *cs);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1a57d2e1d60..b5dac651e75 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3190,24 +3190,19 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
MMUAccessType access_type, ARMMMUIdx mmu_idx)
{
- hwaddr phys_addr;
- target_ulong page_size;
- int prot;
bool ret;
uint64_t par64;
bool format64 = false;
- MemTxAttrs attrs = {};
ARMMMUFaultInfo fi = {};
- ARMCacheAttrs cacheattrs = {};
+ GetPhysAddrResult res = {};
- ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
- &prot, &page_size, &fi, &cacheattrs);
+ ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi);
/*
* ATS operations only do S1 or S1+S2 translations, so we never
* have to deal with the ARMCacheAttrs format for S2 only.
*/
- assert(!cacheattrs.is_s2_format);
+ assert(!res.cacheattrs.is_s2_format);
if (ret) {
/*
@@ -3313,12 +3308,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
/* Create a 64-bit PAR */
par64 = (1 << 11); /* LPAE bit always set */
if (!ret) {
- par64 |= phys_addr & ~0xfffULL;
- if (!attrs.secure) {
+ par64 |= res.phys & ~0xfffULL;
+ if (!res.attrs.secure) {
par64 |= (1 << 9); /* NS */
}
- par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */
- par64 |= cacheattrs.shareability << 7; /* SH */
+ par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */
+ par64 |= res.cacheattrs.shareability << 7; /* SH */
} else {
uint32_t fsr = arm_fi_to_lfsc(&fi);
@@ -3338,13 +3333,13 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
*/
if (!ret) {
/* We do not set any attribute bits in the PAR */
- if (page_size == (1 << 24)
+ if (res.page_size == (1 << 24)
&& arm_feature(env, ARM_FEATURE_V7)) {
- par64 = (phys_addr & 0xff000000) | (1 << 1);
+ par64 = (res.phys & 0xff000000) | (1 << 1);
} else {
- par64 = phys_addr & 0xfffff000;
+ par64 = res.phys & 0xfffff000;
}
- if (!attrs.secure) {
+ if (!res.attrs.secure) {
par64 |= (1 << 9); /* NS */
}
} else {
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 308610f6b4e..84c6796b8d6 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -183,19 +183,14 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
{
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
- MemTxAttrs attrs = {};
MemTxResult txres;
- target_ulong page_size;
- hwaddr physaddr;
- int prot;
+ GetPhysAddrResult res = {};
ARMMMUFaultInfo fi = {};
- ARMCacheAttrs cacheattrs = {};
bool secure = mmu_idx & ARM_MMU_IDX_M_S;
int exc;
bool exc_secure;
- if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr,
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
+ if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &res, &fi)) {
/* MPU/SAU lookup failed */
if (fi.type == ARMFault_QEMU_SFault) {
if (mode == STACK_LAZYFP) {
@@ -228,8 +223,8 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
}
goto pend_fault;
}
- address_space_stl_le(arm_addressspace(cs, attrs), physaddr, value,
- attrs, &txres);
+ address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value,
+ res.attrs, &txres);
if (txres != MEMTX_OK) {
/* BusFault trying to write the data */
if (mode == STACK_LAZYFP) {
@@ -276,20 +271,15 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
{
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
- MemTxAttrs attrs = {};
MemTxResult txres;
- target_ulong page_size;
- hwaddr physaddr;
- int prot;
+ GetPhysAddrResult res = {};
ARMMMUFaultInfo fi = {};
- ARMCacheAttrs cacheattrs = {};
bool secure = mmu_idx & ARM_MMU_IDX_M_S;
int exc;
bool exc_secure;
uint32_t value;
- if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
+ if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) {
/* MPU/SAU lookup failed */
if (fi.type == ARMFault_QEMU_SFault) {
qemu_log_mask(CPU_LOG_INT,
@@ -308,8 +298,8 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
goto pend_fault;
}
- value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
- attrs, &txres);
+ value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
+ res.attrs, &txres);
if (txres != MEMTX_OK) {
/* BusFault trying to read the data */
qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n");
@@ -2008,13 +1998,9 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
V8M_SAttributes sattrs = {};
- MemTxAttrs attrs = {};
+ GetPhysAddrResult res = {};
ARMMMUFaultInfo fi = {};
- ARMCacheAttrs cacheattrs = {};
MemTxResult txres;
- target_ulong page_size;
- hwaddr physaddr;
- int prot;
v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
if (!sattrs.nsc || sattrs.ns) {
@@ -2028,16 +2014,15 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
"...really SecureFault with SFSR.INVEP\n");
return false;
}
- if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &physaddr,
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
+ if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &res, &fi)) {
/* the MPU lookup failed */
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
return false;
}
- *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr,
- attrs, &txres);
+ *insn = address_space_lduw_le(arm_addressspace(cs, res.attrs), res.phys,
+ res.attrs, &txres);
if (txres != MEMTX_OK) {
env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
@@ -2060,17 +2045,12 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
*/
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
- MemTxAttrs attrs = {};
MemTxResult txres;
- target_ulong page_size;
- hwaddr physaddr;
- int prot;
+ GetPhysAddrResult res = {};
ARMMMUFaultInfo fi = {};
- ARMCacheAttrs cacheattrs = {};
uint32_t value;
- if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
+ if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) {
/* MPU/SAU lookup failed */
if (fi.type == ARMFault_QEMU_SFault) {
qemu_log_mask(CPU_LOG_INT,
@@ -2088,8 +2068,8 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
}
return false;
}
- value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
- attrs, &txres);
+ value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
+ res.attrs, &txres);
if (txres != MEMTX_OK) {
/* BusFault trying to read the data */
qemu_log_mask(CPU_LOG_INT,
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 3261039d93a..8db2abac015 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2300,18 +2300,12 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
* @address: virtual address to get physical address for
* @access_type: 0 for read, 1 for write, 2 for execute
* @mmu_idx: MMU index indicating required translation regime
- * @phys_ptr: set to the physical address corresponding to the virtual address
- * @attrs: set to the memory transaction attributes to use
- * @prot: set to the permissions for the page containing phys_ptr
- * @page_size: set to the size of the page containing phys_ptr
+ * @result: set on translation success.
* @fi: set to fault info if the translation fails
- * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
*/
bool get_phys_addr(CPUARMState *env, target_ulong address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
- target_ulong *page_size,
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
@@ -2322,43 +2316,54 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
*/
if (arm_feature(env, ARM_FEATURE_EL2)) {
hwaddr ipa;
- int s2_prot;
+ int s1_prot;
int ret;
bool ipa_secure;
- ARMCacheAttrs cacheattrs2 = {};
+ ARMCacheAttrs cacheattrs1;
ARMMMUIdx s2_mmu_idx;
bool is_el0;
- ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa,
- attrs, prot, page_size, fi, cacheattrs);
+ ret = get_phys_addr(env, address, access_type, s1_mmu_idx,
+ result, fi);
/* If S1 fails or S2 is disabled, return early. */
if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
- *phys_ptr = ipa;
return ret;
}
- ipa_secure = attrs->secure;
+ ipa = result->phys;
+ ipa_secure = result->attrs.secure;
if (arm_is_secure_below_el3(env)) {
if (ipa_secure) {
- attrs->secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
+ result->attrs.secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
} else {
- attrs->secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
+ result->attrs.secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
}
} else {
assert(!ipa_secure);
}
- s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
+ s2_mmu_idx = (result->attrs.secure
+ ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
- /* S1 is done. Now do S2 translation. */
+ /*
+ * S1 is done, now do S2 translation.
+ * Save the stage1 results so that we may merge
+ * prot and cacheattrs later.
+ */
+ s1_prot = result->prot;
+ cacheattrs1 = result->cacheattrs;
+ memset(result, 0, sizeof(*result));
+
ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0,
- phys_ptr, attrs, &s2_prot,
- page_size, fi, &cacheattrs2);
+ &result->phys, &result->attrs,
+ &result->prot, &result->page_size,
+ fi, &result->cacheattrs);
fi->s2addr = ipa;
+
/* Combine the S1 and S2 perms. */
- *prot &= s2_prot;
+ result->prot &= s1_prot;
/* If S2 fails, return early. */
if (ret) {
@@ -2374,20 +2379,21 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
* Outer Write-Back Read-Allocate Write-Allocate.
* Do not overwrite Tagged within attrs.
*/
- if (cacheattrs->attrs != 0xf0) {
- cacheattrs->attrs = 0xff;
+ if (cacheattrs1.attrs != 0xf0) {
+ cacheattrs1.attrs = 0xff;
}
- cacheattrs->shareability = 0;
+ cacheattrs1.shareability = 0;
}
- *cacheattrs = combine_cacheattrs(env, *cacheattrs, cacheattrs2);
+ result->cacheattrs = combine_cacheattrs(env, cacheattrs1,
+ result->cacheattrs);
/* Check if IPA translates to secure or non-secure PA space. */
if (arm_is_secure_below_el3(env)) {
if (ipa_secure) {
- attrs->secure =
+ result->attrs.secure =
!(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW));
} else {
- attrs->secure =
+ result->attrs.secure =
!((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))
|| (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)));
}
@@ -2406,8 +2412,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
* cannot upgrade an non-secure translation regime's attributes
* to secure.
*/
- attrs->secure = regime_is_secure(env, mmu_idx);
- attrs->user = regime_is_user(env, mmu_idx);
+ result->attrs.secure = regime_is_secure(env, mmu_idx);
+ result->attrs.user = regime_is_user(env, mmu_idx);
/*
* Fast Context Switch Extension. This doesn't exist at all in v8.
@@ -2424,20 +2430,22 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
if (arm_feature(env, ARM_FEATURE_PMSA)) {
bool ret;
- *page_size = TARGET_PAGE_SIZE;
+ result->page_size = TARGET_PAGE_SIZE;
if (arm_feature(env, ARM_FEATURE_V8)) {
/* PMSAv8 */
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
- phys_ptr, attrs, prot, page_size, fi);
+ &result->phys, &result->attrs,
+ &result->prot, &result->page_size, fi);
} else if (arm_feature(env, ARM_FEATURE_V7)) {
/* PMSAv7 */
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
- phys_ptr, prot, page_size, fi);
+ &result->phys, &result->prot,
+ &result->page_size, fi);
} else {
/* Pre-v7 MPU */
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
- phys_ptr, prot, fi);
+ &result->phys, &result->prot, fi);
}
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
" mmu_idx %u -> %s (prot %c%c%c)\n",
@@ -2445,9 +2453,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
(access_type == MMU_DATA_STORE ? "writing" : "execute"),
(uint32_t)address, mmu_idx,
ret ? "Miss" : "Hit",
- *prot & PAGE_READ ? 'r' : '-',
- *prot & PAGE_WRITE ? 'w' : '-',
- *prot & PAGE_EXEC ? 'x' : '-');
+ result->prot & PAGE_READ ? 'r' : '-',
+ result->prot & PAGE_WRITE ? 'w' : '-',
+ result->prot & PAGE_EXEC ? 'x' : '-');
return ret;
}
@@ -2492,14 +2500,14 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
address = extract64(address, 0, 52);
}
}
- *phys_ptr = address;
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- *page_size = TARGET_PAGE_SIZE;
+ result->phys = address;
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ result->page_size = TARGET_PAGE_SIZE;
/* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
hcr = arm_hcr_el2_eff(env);
- cacheattrs->shareability = 0;
- cacheattrs->is_s2_format = false;
+ result->cacheattrs.shareability = 0;
+ result->cacheattrs.is_s2_format = false;
if (hcr & HCR_DC) {
if (hcr & HCR_DCT) {
memattr = 0xf0; /* Tagged, Normal, WB, RWA */
@@ -2512,24 +2520,27 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
} else {
memattr = 0x44; /* Normal, NC, No */
}
- cacheattrs->shareability = 2; /* outer sharable */
+ result->cacheattrs.shareability = 2; /* outer sharable */
} else {
memattr = 0x00; /* Device, nGnRnE */
}
- cacheattrs->attrs = memattr;
+ result->cacheattrs.attrs = memattr;
return 0;
}
if (regime_using_lpae_format(env, mmu_idx)) {
return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
- phys_ptr, attrs, prot, page_size,
- fi, cacheattrs);
+ &result->phys, &result->attrs,
+ &result->prot, &result->page_size,
+ fi, &result->cacheattrs);
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, address, access_type, mmu_idx,
- phys_ptr, attrs, prot, page_size, fi);
+ &result->phys, &result->attrs,
+ &result->prot, &result->page_size, fi);
} else {
return get_phys_addr_v5(env, address, access_type, mmu_idx,
- phys_ptr, prot, page_size, fi);
+ &result->phys, &result->prot,
+ &result->page_size, fi);
}
}
@@ -2538,21 +2549,16 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
- hwaddr phys_addr;
- target_ulong page_size;
- int prot;
- bool ret;
+ GetPhysAddrResult res = {};
ARMMMUFaultInfo fi = {};
ARMMMUIdx mmu_idx = arm_mmu_idx(env);
- ARMCacheAttrs cacheattrs = {};
+ bool ret;
- *attrs = (MemTxAttrs) {};
-
- ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr,
- attrs, &prot, &page_size, &fi, &cacheattrs);
+ ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi);
+ *attrs = res.attrs;
if (ret) {
return -1;
}
- return phys_addr;
+ return res.phys;
}
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 5a709eab56f..ad225b1cb20 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -209,11 +209,8 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
{
ARMCPU *cpu = ARM_CPU(cs);
ARMMMUFaultInfo fi = {};
- hwaddr phys_addr;
- target_ulong page_size;
- int prot, ret;
- MemTxAttrs attrs = {};
- ARMCacheAttrs cacheattrs = {};
+ GetPhysAddrResult res = {};
+ int ret;
/*
* Walk the page table and (if the mapping exists) add the page
@@ -223,25 +220,24 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
*/
ret = get_phys_addr(&cpu->env, address, access_type,
core_to_arm_mmu_idx(&cpu->env, mmu_idx),
- &phys_addr, &attrs, &prot, &page_size,
- &fi, &cacheattrs);
+ &res, &fi);
if (likely(!ret)) {
/*
* Map a single [sub]page. Regions smaller than our declared
* target page size are handled specially, so for those we
* pass in the exact addresses.
*/
- if (page_size >= TARGET_PAGE_SIZE) {
- phys_addr &= TARGET_PAGE_MASK;
+ if (res.page_size >= TARGET_PAGE_SIZE) {
+ res.phys &= TARGET_PAGE_MASK;
address &= TARGET_PAGE_MASK;
}
/* Notice and record tagged memory. */
- if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) {
- arm_tlb_mte_tagged(&attrs) = true;
+ if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs == 0xf0) {
+ arm_tlb_mte_tagged(&res.attrs) = true;
}
- tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
- prot, mmu_idx, page_size);
+ tlb_set_page_with_attrs(cs, address, res.phys, res.attrs,
+ res.prot, mmu_idx, res.page_size);
return true;
} else if (probe) {
return false;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 04/39] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2022-09-22 16:35 ` [PULL 03/39] target/arm: Create GetPhysAddrResult Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 05/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v6 Peter Maydell
` (35 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 69 ++++++++++++++++++------------------------------
1 file changed, 26 insertions(+), 43 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 8db2abac015..e8d3f88628e 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -16,10 +16,8 @@
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- bool s1_is_el0, hwaddr *phys_ptr,
- MemTxAttrs *txattrs, int *prot,
- target_ulong *page_size_ptr,
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
+ bool s1_is_el0, GetPhysAddrResult *result,
+ ARMMMUFaultInfo *fi)
__attribute__((nonnull));
/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
@@ -204,18 +202,13 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
{
if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
!regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
- target_ulong s2size;
- hwaddr s2pa;
- int s2prot;
- int ret;
ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2;
- ARMCacheAttrs cacheattrs = {};
- MemTxAttrs txattrs = {};
+ GetPhysAddrResult s2 = {};
+ int ret;
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
- &s2pa, &txattrs, &s2prot, &s2size, fi,
- &cacheattrs);
+ &s2, fi);
if (ret) {
assert(fi->type != ARMFault_None);
fi->s2addr = addr;
@@ -225,7 +218,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
return ~0;
}
if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
- ptw_attrs_are_device(env, cacheattrs)) {
+ ptw_attrs_are_device(env, s2.cacheattrs)) {
/*
* PTW set and S1 walk touched S2 Device memory:
* generate Permission fault.
@@ -249,7 +242,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
assert(!*is_secure);
}
- addr = s2pa;
+ addr = s2.phys;
}
return addr;
}
@@ -972,19 +965,13 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
* table walk), must be true if this is stage 2 of a stage 1+2
* walk for an EL0 access. If @mmu_idx is anything else,
* @s1_is_el0 is ignored.
- * @phys_ptr: set to the physical address corresponding to the virtual address
- * @attrs: set to the memory transaction attributes to use
- * @prot: set to the permissions for the page containing phys_ptr
- * @page_size_ptr: set to the size of the page containing phys_ptr
+ * @result: set on translation success,
* @fi: set to fault info if the translation fails
- * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
*/
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- bool s1_is_el0, hwaddr *phys_ptr,
- MemTxAttrs *txattrs, int *prot,
- target_ulong *page_size_ptr,
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
+ bool s1_is_el0, GetPhysAddrResult *result,
+ ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
/* Read an LPAE long-descriptor translation table. */
@@ -1302,16 +1289,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
ns = mmu_idx == ARMMMUIdx_Stage2;
xn = extract32(attrs, 11, 2);
- *prot = get_S2prot(env, ap, xn, s1_is_el0);
+ result->prot = get_S2prot(env, ap, xn, s1_is_el0);
} else {
ns = extract32(attrs, 3, 1);
xn = extract32(attrs, 12, 1);
pxn = extract32(attrs, 11, 1);
- *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
+ result->prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
}
fault_type = ARMFault_Permission;
- if (!(*prot & (1 << access_type))) {
+ if (!(result->prot & (1 << access_type))) {
goto do_fault;
}
@@ -1321,23 +1308,23 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
* the CPU doesn't support TZ or this is a non-secure translation
* regime, because the attribute will already be non-secure.
*/
- txattrs->secure = false;
+ result->attrs.secure = false;
}
/* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
- arm_tlb_bti_gp(txattrs) = true;
+ arm_tlb_bti_gp(&result->attrs) = true;
}
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
- cacheattrs->is_s2_format = true;
- cacheattrs->attrs = extract32(attrs, 0, 4);
+ result->cacheattrs.is_s2_format = true;
+ result->cacheattrs.attrs = extract32(attrs, 0, 4);
} else {
/* Index into MAIR registers for cache attributes */
uint8_t attrindx = extract32(attrs, 0, 3);
uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
assert(attrindx <= 7);
- cacheattrs->is_s2_format = false;
- cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
+ result->cacheattrs.is_s2_format = false;
+ result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
}
/*
@@ -1346,13 +1333,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
* that case comes from TCR_ELx, which we extracted earlier.
*/
if (param.ds) {
- cacheattrs->shareability = param.sh;
+ result->cacheattrs.shareability = param.sh;
} else {
- cacheattrs->shareability = extract32(attrs, 6, 2);
+ result->cacheattrs.shareability = extract32(attrs, 6, 2);
}
- *phys_ptr = descaddr;
- *page_size_ptr = page_size;
+ result->phys = descaddr;
+ result->page_size = page_size;
return false;
do_fault:
@@ -2356,10 +2343,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
cacheattrs1 = result->cacheattrs;
memset(result, 0, sizeof(*result));
- ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0,
- &result->phys, &result->attrs,
- &result->prot, &result->page_size,
- fi, &result->cacheattrs);
+ ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx,
+ is_el0, result, fi);
fi->s2addr = ipa;
/* Combine the S1 and S2 perms. */
@@ -2530,9 +2515,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
if (regime_using_lpae_format(env, mmu_idx)) {
return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
- &result->phys, &result->attrs,
- &result->prot, &result->page_size,
- fi, &result->cacheattrs);
+ result, fi);
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, address, access_type, mmu_idx,
&result->phys, &result->attrs,
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 05/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v6
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2022-09-22 16:35 ` [PULL 04/39] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 06/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v5 Peter Maydell
` (34 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 30 ++++++++++++++----------------
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index e8d3f88628e..600d9e6650d 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -536,8 +536,7 @@ do_fault:
static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
- target_ulong *page_size, ARMMMUFaultInfo *fi)
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
int level = 1;
@@ -597,11 +596,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
- *page_size = 0x1000000;
+ result->page_size = 0x1000000;
} else {
/* Section. */
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
- *page_size = 0x100000;
+ result->page_size = 0x100000;
}
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
xn = desc & (1 << 4);
@@ -627,12 +626,12 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
case 1: /* 64k page. */
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
xn = desc & (1 << 15);
- *page_size = 0x10000;
+ result->page_size = 0x10000;
break;
case 2: case 3: /* 4k page. */
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
xn = desc & 1;
- *page_size = 0x1000;
+ result->page_size = 0x1000;
break;
default:
/* Never happens, but compiler isn't smart enough to tell. */
@@ -640,7 +639,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
}
}
if (domain_prot == 3) {
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
} else {
if (pxn && !regime_is_user(env, mmu_idx)) {
xn = 1;
@@ -658,14 +657,14 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
fi->type = ARMFault_AccessFlag;
goto do_fault;
}
- *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
+ result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
} else {
- *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
+ result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
}
- if (*prot && !xn) {
- *prot |= PAGE_EXEC;
+ if (result->prot && !xn) {
+ result->prot |= PAGE_EXEC;
}
- if (!(*prot & (1 << access_type))) {
+ if (!(result->prot & (1 << access_type))) {
/* Access permission fault. */
fi->type = ARMFault_Permission;
goto do_fault;
@@ -676,9 +675,9 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
* the CPU doesn't support TZ or this is a non-secure translation
* regime, because the attribute will already be non-secure.
*/
- attrs->secure = false;
+ result->attrs.secure = false;
}
- *phys_ptr = phys_addr;
+ result->phys = phys_addr;
return false;
do_fault:
fi->domain = domain;
@@ -2518,8 +2517,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
result, fi);
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, address, access_type, mmu_idx,
- &result->phys, &result->attrs,
- &result->prot, &result->page_size, fi);
+ result, fi);
} else {
return get_phys_addr_v5(env, address, access_type, mmu_idx,
&result->phys, &result->prot,
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 06/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v5
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2022-09-22 16:35 ` [PULL 05/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v6 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 07/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5 Peter Maydell
` (33 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 25 +++++++++++--------------
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 600d9e6650d..4e2476278e1 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -414,9 +414,7 @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, int *prot,
- target_ulong *page_size,
- ARMMMUFaultInfo *fi)
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
int level = 1;
uint32_t table;
@@ -464,7 +462,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
/* 1Mb section. */
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
ap = (desc >> 10) & 3;
- *page_size = 1024 * 1024;
+ result->page_size = 1024 * 1024;
} else {
/* Lookup l2 entry. */
if (type == 1) {
@@ -486,12 +484,12 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
case 1: /* 64k page. */
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
- *page_size = 0x10000;
+ result->page_size = 0x10000;
break;
case 2: /* 4k page. */
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
- *page_size = 0x1000;
+ result->page_size = 0x1000;
break;
case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
if (type == 1) {
@@ -499,7 +497,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
if (arm_feature(env, ARM_FEATURE_XSCALE)
|| arm_feature(env, ARM_FEATURE_V6)) {
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
- *page_size = 0x1000;
+ result->page_size = 0x1000;
} else {
/*
* UNPREDICTABLE in ARMv5; we choose to take a
@@ -510,7 +508,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
}
} else {
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
- *page_size = 0x400;
+ result->page_size = 0x400;
}
ap = (desc >> 4) & 3;
break;
@@ -519,14 +517,14 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
g_assert_not_reached();
}
}
- *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
- *prot |= *prot ? PAGE_EXEC : 0;
- if (!(*prot & (1 << access_type))) {
+ result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
+ result->prot |= result->prot ? PAGE_EXEC : 0;
+ if (!(result->prot & (1 << access_type))) {
/* Access permission fault. */
fi->type = ARMFault_Permission;
goto do_fault;
}
- *phys_ptr = phys_addr;
+ result->phys = phys_addr;
return false;
do_fault:
fi->domain = domain;
@@ -2520,8 +2518,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
result, fi);
} else {
return get_phys_addr_v5(env, address, access_type, mmu_idx,
- &result->phys, &result->prot,
- &result->page_size, fi);
+ result, fi);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 07/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2022-09-22 16:35 ` [PULL 06/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v5 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 08/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7 Peter Maydell
` (32 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 4e2476278e1..70abcce81f9 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1351,7 +1351,7 @@ do_fault:
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, int *prot,
+ GetPhysAddrResult *result,
ARMMMUFaultInfo *fi)
{
int n;
@@ -1361,12 +1361,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
if (regime_translation_disabled(env, mmu_idx)) {
/* MPU disabled. */
- *phys_ptr = address;
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ result->phys = address;
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return false;
}
- *phys_ptr = address;
+ result->phys = address;
for (n = 7; n >= 0; n--) {
base = env->cp15.c6_region[n];
if ((base & 1) == 0) {
@@ -1402,16 +1402,16 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
fi->level = 1;
return true;
}
- *prot = PAGE_READ | PAGE_WRITE;
+ result->prot = PAGE_READ | PAGE_WRITE;
break;
case 2:
- *prot = PAGE_READ;
+ result->prot = PAGE_READ;
if (!is_user) {
- *prot |= PAGE_WRITE;
+ result->prot |= PAGE_WRITE;
}
break;
case 3:
- *prot = PAGE_READ | PAGE_WRITE;
+ result->prot = PAGE_READ | PAGE_WRITE;
break;
case 5:
if (is_user) {
@@ -1419,10 +1419,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
fi->level = 1;
return true;
}
- *prot = PAGE_READ;
+ result->prot = PAGE_READ;
break;
case 6:
- *prot = PAGE_READ;
+ result->prot = PAGE_READ;
break;
default:
/* Bad permission. */
@@ -1430,7 +1430,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
fi->level = 1;
return true;
}
- *prot |= PAGE_EXEC;
+ result->prot |= PAGE_EXEC;
return false;
}
@@ -2427,7 +2427,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
} else {
/* Pre-v7 MPU */
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
- &result->phys, &result->prot, fi);
+ result, fi);
}
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
" mmu_idx %u -> %s (prot %c%c%c)\n",
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 08/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2022-09-22 16:35 ` [PULL 07/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 09/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8 Peter Maydell
` (31 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 36 +++++++++++++++++-------------------
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 70abcce81f9..36b108907fc 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1513,17 +1513,16 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, int *prot,
- target_ulong *page_size,
+ GetPhysAddrResult *result,
ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
int n;
bool is_user = regime_is_user(env, mmu_idx);
- *phys_ptr = address;
- *page_size = TARGET_PAGE_SIZE;
- *prot = 0;
+ result->phys = address;
+ result->page_size = TARGET_PAGE_SIZE;
+ result->prot = 0;
if (regime_translation_disabled(env, mmu_idx) ||
m_is_ppb_region(env, address)) {
@@ -1535,7 +1534,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
* which always does a direct read using address_space_ldl(), rather
* than going via this function, so we don't need to check that here.
*/
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
} else { /* MPU enabled */
for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
/* region search */
@@ -1577,7 +1576,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
if (ranges_overlap(base, rmask,
address & TARGET_PAGE_MASK,
TARGET_PAGE_SIZE)) {
- *page_size = 1;
+ result->page_size = 1;
}
continue;
}
@@ -1615,7 +1614,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
continue;
}
if (rsize < TARGET_PAGE_BITS) {
- *page_size = 1 << rsize;
+ result->page_size = 1 << rsize;
}
break;
}
@@ -1626,7 +1625,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
fi->type = ARMFault_Background;
return true;
}
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
} else { /* a MPU hit! */
uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
@@ -1643,16 +1642,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
case 5:
break; /* no access */
case 3:
- *prot |= PAGE_WRITE;
+ result->prot |= PAGE_WRITE;
/* fall through */
case 2:
case 6:
- *prot |= PAGE_READ | PAGE_EXEC;
+ result->prot |= PAGE_READ | PAGE_EXEC;
break;
case 7:
/* for v7M, same as 6; for R profile a reserved value */
if (arm_feature(env, ARM_FEATURE_M)) {
- *prot |= PAGE_READ | PAGE_EXEC;
+ result->prot |= PAGE_READ | PAGE_EXEC;
break;
}
/* fall through */
@@ -1668,16 +1667,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
case 1:
case 2:
case 3:
- *prot |= PAGE_WRITE;
+ result->prot |= PAGE_WRITE;
/* fall through */
case 5:
case 6:
- *prot |= PAGE_READ | PAGE_EXEC;
+ result->prot |= PAGE_READ | PAGE_EXEC;
break;
case 7:
/* for v7M, same as 6; for R profile a reserved value */
if (arm_feature(env, ARM_FEATURE_M)) {
- *prot |= PAGE_READ | PAGE_EXEC;
+ result->prot |= PAGE_READ | PAGE_EXEC;
break;
}
/* fall through */
@@ -1690,14 +1689,14 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
/* execute never */
if (xn) {
- *prot &= ~PAGE_EXEC;
+ result->prot &= ~PAGE_EXEC;
}
}
}
fi->type = ARMFault_Permission;
fi->level = 1;
- return !(*prot & (1 << access_type));
+ return !(result->prot & (1 << access_type));
}
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
@@ -2422,8 +2421,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
} else if (arm_feature(env, ARM_FEATURE_V7)) {
/* PMSAv7 */
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
- &result->phys, &result->prot,
- &result->page_size, fi);
+ result, fi);
} else {
/* Pre-v7 MPU */
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 09/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2022-09-22 16:35 ` [PULL 08/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 10/39] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup Peter Maydell
` (30 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 36b108907fc..2286f6e12db 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1967,8 +1967,7 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
- int *prot, target_ulong *page_size,
+ GetPhysAddrResult *result,
ARMMMUFaultInfo *fi)
{
uint32_t secure = regime_is_secure(env, mmu_idx);
@@ -2003,9 +2002,9 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
} else {
fi->type = ARMFault_QEMU_SFault;
}
- *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
- *phys_ptr = address;
- *prot = 0;
+ result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
+ result->phys = address;
+ result->prot = 0;
return true;
}
} else {
@@ -2015,7 +2014,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
* might downgrade a secure access to nonsecure.
*/
if (sattrs.ns) {
- txattrs->secure = false;
+ result->attrs.secure = false;
} else if (!secure) {
/*
* NS access to S memory must fault.
@@ -2028,17 +2027,19 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
* for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
*/
fi->type = ARMFault_QEMU_SFault;
- *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
- *phys_ptr = address;
- *prot = 0;
+ result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
+ result->phys = address;
+ result->prot = 0;
return true;
}
}
}
- ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr,
- txattrs, prot, &mpu_is_subpage, fi, NULL);
- *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
+ ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
+ &result->phys, &result->attrs, &result->prot,
+ &mpu_is_subpage, fi, NULL);
+ result->page_size =
+ sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
return ret;
}
@@ -2416,8 +2417,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
if (arm_feature(env, ARM_FEATURE_V8)) {
/* PMSAv8 */
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
- &result->phys, &result->attrs,
- &result->prot, &result->page_size, fi);
+ result, fi);
} else if (arm_feature(env, ARM_FEATURE_V7)) {
/* PMSAv7 */
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 10/39] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2022-09-22 16:35 ` [PULL 09/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 11/39] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup Peter Maydell
` (29 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-10-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 11 +++++------
target/arm/m_helper.c | 16 +++++++---------
target/arm/ptw.c | 20 +++++++++-----------
3 files changed, 21 insertions(+), 26 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index e9743d3e220..103ae743a75 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1125,12 +1125,6 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
V8M_SAttributes *sattrs);
-bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
- int *prot, bool *is_subpage,
- ARMMMUFaultInfo *fi, uint32_t *mregion);
-
/* Cacheability and shareability attributes for a memory access */
typedef struct ARMCacheAttrs {
/*
@@ -1156,6 +1150,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
__attribute__((nonnull));
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
+ GetPhysAddrResult *result, bool *is_subpage,
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
+
void arm_log_exception(CPUState *cs);
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 84c6796b8d6..69d4a63fa6d 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -2770,15 +2770,10 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
V8M_SAttributes sattrs = {};
uint32_t tt_resp;
bool r, rw, nsr, nsrw, mrvalid;
- int prot;
- ARMMMUFaultInfo fi = {};
- MemTxAttrs attrs = {};
- hwaddr phys_addr;
ARMMMUIdx mmu_idx;
uint32_t mregion;
bool targetpriv;
bool targetsec = env->v7m.secure;
- bool is_subpage;
/*
* Work out what the security state and privilege level we're
@@ -2809,18 +2804,21 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
* inspecting the other MPU state.
*/
if (arm_current_el(env) != 0 || alt) {
+ GetPhysAddrResult res = {};
+ ARMMMUFaultInfo fi = {};
+ bool is_subpage;
+
/* We can ignore the return value as prot is always set */
pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
- &phys_addr, &attrs, &prot, &is_subpage,
- &fi, &mregion);
+ &res, &is_subpage, &fi, &mregion);
if (mregion == -1) {
mrvalid = false;
mregion = 0;
} else {
mrvalid = true;
}
- r = prot & PAGE_READ;
- rw = prot & PAGE_WRITE;
+ r = res.prot & PAGE_READ;
+ rw = res.prot & PAGE_WRITE;
} else {
r = false;
rw = false;
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 2286f6e12db..d6890048f13 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1701,8 +1701,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
- int *prot, bool *is_subpage,
+ GetPhysAddrResult *result, bool *is_subpage,
ARMMMUFaultInfo *fi, uint32_t *mregion)
{
/*
@@ -1724,8 +1723,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
*is_subpage = false;
- *phys_ptr = address;
- *prot = 0;
+ result->phys = address;
+ result->prot = 0;
if (mregion) {
*mregion = -1;
}
@@ -1807,7 +1806,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
if (matchregion == -1) {
/* hit using the background region */
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
} else {
uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
@@ -1822,9 +1821,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
xn = 1;
}
- *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
- if (*prot && !xn && !(pxn && !is_user)) {
- *prot |= PAGE_EXEC;
+ result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
+ if (result->prot && !xn && !(pxn && !is_user)) {
+ result->prot |= PAGE_EXEC;
}
/*
* We don't need to look the attribute up in the MAIR0/MAIR1
@@ -1837,7 +1836,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
fi->type = ARMFault_Permission;
fi->level = 1;
- return !(*prot & (1 << access_type));
+ return !(result->prot & (1 << access_type));
}
static bool v8m_is_sau_exempt(CPUARMState *env,
@@ -2036,8 +2035,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
}
ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
- &result->phys, &result->attrs, &result->prot,
- &mpu_is_subpage, fi, NULL);
+ result, &mpu_is_subpage, fi, NULL);
result->page_size =
sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
return ret;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 11/39] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2022-09-22 16:35 ` [PULL 10/39] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 12/39] target/arm: Add is_secure parameter to v8m_security_lookup Peter Maydell
` (28 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
This can be made redundant with result->page_size, by moving the basic
set of page_size from get_phys_addr_pmsav8. We still need to overwrite
page_size when v8m_security_lookup signals a subpage.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-11-richard.henderson@linaro.org
[PMM: Update a comment that used to refer to is_subpage]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 4 ++--
target/arm/m_helper.c | 3 +--
target/arm/ptw.c | 23 ++++++++++++-----------
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 103ae743a75..f8b22d3ab0b 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1152,8 +1152,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- GetPhysAddrResult *result, bool *is_subpage,
- ARMMMUFaultInfo *fi, uint32_t *mregion);
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
+ uint32_t *mregion);
void arm_log_exception(CPUState *cs);
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 69d4a63fa6d..01263990dc3 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -2806,11 +2806,10 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
if (arm_current_el(env) != 0 || alt) {
GetPhysAddrResult res = {};
ARMMMUFaultInfo fi = {};
- bool is_subpage;
/* We can ignore the return value as prot is always set */
pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
- &res, &is_subpage, &fi, &mregion);
+ &res, &fi, &mregion);
if (mregion == -1) {
mrvalid = false;
mregion = 0;
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index d6890048f13..bb3c709f8f5 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1701,8 +1701,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- GetPhysAddrResult *result, bool *is_subpage,
- ARMMMUFaultInfo *fi, uint32_t *mregion)
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
+ uint32_t *mregion)
{
/*
* Perform a PMSAv8 MPU lookup (without also doing the SAU check
@@ -1710,8 +1710,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
* mregion is (if not NULL) set to the region number which matched,
* or -1 if no region number is returned (MPU off, address did not
* hit a region, address hit in multiple regions).
- * We set is_subpage to true if the region hit doesn't cover the
- * entire TARGET_PAGE the address is within.
+ * If the region hit doesn't cover the entire TARGET_PAGE the address
+ * is within, then we set the result page_size to 1 to force the
+ * memory system to use a subpage.
*/
ARMCPU *cpu = env_archcpu(env);
bool is_user = regime_is_user(env, mmu_idx);
@@ -1722,7 +1723,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
uint32_t addr_page_base = address & TARGET_PAGE_MASK;
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
- *is_subpage = false;
+ result->page_size = TARGET_PAGE_SIZE;
result->phys = address;
result->prot = 0;
if (mregion) {
@@ -1774,13 +1775,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
ranges_overlap(base, limit - base + 1,
addr_page_base,
TARGET_PAGE_SIZE)) {
- *is_subpage = true;
+ result->page_size = 1;
}
continue;
}
if (base > addr_page_base || limit < addr_page_limit) {
- *is_subpage = true;
+ result->page_size = 1;
}
if (matchregion != -1) {
@@ -1972,7 +1973,6 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
uint32_t secure = regime_is_secure(env, mmu_idx);
V8M_SAttributes sattrs = {};
bool ret;
- bool mpu_is_subpage;
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
@@ -2035,9 +2035,10 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
}
ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
- result, &mpu_is_subpage, fi, NULL);
- result->page_size =
- sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
+ result, fi, NULL);
+ if (sattrs.subpage) {
+ result->page_size = 1;
+ }
return ret;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 12/39] target/arm: Add is_secure parameter to v8m_security_lookup
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2022-09-22 16:35 ` [PULL 11/39] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 13/39] target/arm: Add secure parameter to pmsav8_mpu_lookup Peter Maydell
` (27 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Remove the use of regime_is_secure from v8m_security_lookup,
passing the new parameter to the lookup instead.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 2 +-
target/arm/m_helper.c | 9 ++++++---
target/arm/ptw.c | 9 +++++----
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index f8b22d3ab0b..e97f5c3d47e 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1123,7 +1123,7 @@ typedef struct V8M_SAttributes {
void v8m_security_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- V8M_SAttributes *sattrs);
+ bool secure, V8M_SAttributes *sattrs);
/* Cacheability and shareability attributes for a memory access */
typedef struct ARMCacheAttrs {
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 01263990dc3..45fbf195590 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -689,7 +689,8 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
V8M_SAttributes sattrs = {};
- v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
+ v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
+ targets_secure, &sattrs);
if (sattrs.ns) {
attrs.secure = false;
} else if (!targets_secure) {
@@ -2002,7 +2003,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
ARMMMUFaultInfo fi = {};
MemTxResult txres;
- v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
+ v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx,
+ regime_is_secure(env, mmu_idx), &sattrs);
if (!sattrs.nsc || sattrs.ns) {
/*
* This must be the second half of the insn, and it straddles a
@@ -2826,7 +2828,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
}
if (env->v7m.secure) {
- v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
+ v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
+ targetsec, &sattrs);
nsr = sattrs.ns && r;
nsrw = sattrs.ns && rw;
} else {
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index bb3c709f8f5..74d2f63359f 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1857,8 +1857,8 @@ static bool v8m_is_sau_exempt(CPUARMState *env,
}
void v8m_security_lookup(CPUARMState *env, uint32_t address,
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
- V8M_SAttributes *sattrs)
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
+ bool is_secure, V8M_SAttributes *sattrs)
{
/*
* Look up the security attributes for this address. Compare the
@@ -1886,7 +1886,7 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
}
if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
- sattrs->ns = !regime_is_secure(env, mmu_idx);
+ sattrs->ns = !is_secure;
return;
}
@@ -1975,7 +1975,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
bool ret;
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
- v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
+ v8m_security_lookup(env, address, access_type, mmu_idx,
+ secure, &sattrs);
if (access_type == MMU_INST_FETCH) {
/*
* Instruction fetches always use the MMU bank and the
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 13/39] target/arm: Add secure parameter to pmsav8_mpu_lookup
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2022-09-22 16:35 ` [PULL 12/39] target/arm: Add is_secure parameter to v8m_security_lookup Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 14/39] target/arm: Add is_secure parameter to get_phys_addr_v5 Peter Maydell
` (26 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Remove the use of regime_is_secure from pmsav8_mpu_lookup,
passing the new parameter to the lookup instead.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-13-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 4 ++--
target/arm/m_helper.c | 2 +-
target/arm/ptw.c | 7 +++----
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index e97f5c3d47e..307a5965053 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1152,8 +1152,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
- uint32_t *mregion);
+ bool is_secure, GetPhysAddrResult *result,
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
void arm_log_exception(CPUState *cs);
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 45fbf195590..5ee4ee15b36 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -2810,7 +2810,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
ARMMMUFaultInfo fi = {};
/* We can ignore the return value as prot is always set */
- pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
+ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, targetsec,
&res, &fi, &mregion);
if (mregion == -1) {
mrvalid = false;
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 74d2f63359f..308a9cc3ac9 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1701,8 +1701,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
- uint32_t *mregion)
+ bool secure, GetPhysAddrResult *result,
+ ARMMMUFaultInfo *fi, uint32_t *mregion)
{
/*
* Perform a PMSAv8 MPU lookup (without also doing the SAU check
@@ -1716,7 +1716,6 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
*/
ARMCPU *cpu = env_archcpu(env);
bool is_user = regime_is_user(env, mmu_idx);
- uint32_t secure = regime_is_secure(env, mmu_idx);
int n;
int matchregion = -1;
bool hit = false;
@@ -2035,7 +2034,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
}
}
- ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
+ ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure,
result, fi, NULL);
if (sattrs.subpage) {
result->page_size = 1;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 14/39] target/arm: Add is_secure parameter to get_phys_addr_v5
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2022-09-22 16:35 ` [PULL 13/39] target/arm: Add secure parameter to pmsav8_mpu_lookup Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 15/39] target/arm: Add is_secure parameter to get_phys_addr_v6 Peter Maydell
` (25 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Remove the use of regime_is_secure from get_phys_addr_v5,
passing the new parameter to the lookup instead.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: Folded in definition of local is_secure in get_phys_addr(),
since I dropped the earlier patch that would have provided it]
Message-id: 20220822152741.1617527-14-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 308a9cc3ac9..96639da504e 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -414,7 +414,8 @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+ bool is_secure, GetPhysAddrResult *result,
+ ARMMMUFaultInfo *fi)
{
int level = 1;
uint32_t table;
@@ -433,8 +434,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
fi->type = ARMFault_Translation;
goto do_fault;
}
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
- mmu_idx, fi);
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
if (fi->type != ARMFault_None) {
goto do_fault;
}
@@ -472,8 +472,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
/* Fine pagetable. */
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
}
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
- mmu_idx, fi);
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
if (fi->type != ARMFault_None) {
goto do_fault;
}
@@ -2291,6 +2290,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
+ bool is_secure = regime_is_secure(env, mmu_idx);
if (mmu_idx != s1_mmu_idx) {
/*
@@ -2393,7 +2393,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
* cannot upgrade an non-secure translation regime's attributes
* to secure.
*/
- result->attrs.secure = regime_is_secure(env, mmu_idx);
+ result->attrs.secure = is_secure;
result->attrs.user = regime_is_user(env, mmu_idx);
/*
@@ -2515,7 +2515,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
result, fi);
} else {
return get_phys_addr_v5(env, address, access_type, mmu_idx,
- result, fi);
+ is_secure, result, fi);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 15/39] target/arm: Add is_secure parameter to get_phys_addr_v6
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2022-09-22 16:35 ` [PULL 14/39] target/arm: Add is_secure parameter to get_phys_addr_v5 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 16/39] target/arm: Add secure parameter to get_phys_addr_pmsav8 Peter Maydell
` (24 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Remove the use of regime_is_secure from get_phys_addr_v6,
passing the new parameter to the lookup instead.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-15-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 96639da504e..8f0810a1968 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -533,7 +533,8 @@ do_fault:
static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+ bool is_secure, GetPhysAddrResult *result,
+ ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
int level = 1;
@@ -556,8 +557,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
fi->type = ARMFault_Translation;
goto do_fault;
}
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
- mmu_idx, fi);
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
if (fi->type != ARMFault_None) {
goto do_fault;
}
@@ -610,8 +610,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
ns = extract32(desc, 3, 1);
/* Lookup l2 entry. */
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
- mmu_idx, fi);
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
if (fi->type != ARMFault_None) {
goto do_fault;
}
@@ -2512,7 +2511,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
result, fi);
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, address, access_type, mmu_idx,
- result, fi);
+ is_secure, result, fi);
} else {
return get_phys_addr_v5(env, address, access_type, mmu_idx,
is_secure, result, fi);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 16/39] target/arm: Add secure parameter to get_phys_addr_pmsav8
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2022-09-22 16:35 ` [PULL 15/39] target/arm: Add is_secure parameter to get_phys_addr_v6 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 17/39] target/arm: Add is_secure parameter to pmsav7_use_background_region Peter Maydell
` (23 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Remove the use of regime_is_secure from get_phys_addr_pmsav8.
Since we already had a local variable named secure, use that.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-16-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 8f0810a1968..6a73f16e092 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1964,10 +1964,9 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- GetPhysAddrResult *result,
+ bool secure, GetPhysAddrResult *result,
ARMMMUFaultInfo *fi)
{
- uint32_t secure = regime_is_secure(env, mmu_idx);
V8M_SAttributes sattrs = {};
bool ret;
@@ -2415,7 +2414,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
if (arm_feature(env, ARM_FEATURE_V8)) {
/* PMSAv8 */
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
- result, fi);
+ is_secure, result, fi);
} else if (arm_feature(env, ARM_FEATURE_V7)) {
/* PMSAv7 */
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 17/39] target/arm: Add is_secure parameter to pmsav7_use_background_region
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2022-09-22 16:35 ` [PULL 16/39] target/arm: Add secure parameter to get_phys_addr_pmsav8 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 18/39] target/arm: Add secure parameter to get_phys_addr_pmsav7 Peter Maydell
` (22 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Remove the use of regime_is_secure from pmsav7_use_background_region,
using the new parameter instead.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-17-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 6a73f16e092..9e1f60d10b4 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1489,7 +1489,7 @@ static bool m_is_system_region(CPUARMState *env, uint32_t address)
}
static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
- bool is_user)
+ bool is_secure, bool is_user)
{
/*
* Return true if we should use the default memory map as a
@@ -1502,8 +1502,7 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
}
if (arm_feature(env, ARM_FEATURE_M)) {
- return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
- & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
+ return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
} else {
return regime_sctlr(env, mmu_idx) & SCTLR_BR;
}
@@ -1516,6 +1515,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
{
ARMCPU *cpu = env_archcpu(env);
int n;
+ bool secure = regime_is_secure(env, mmu_idx);
bool is_user = regime_is_user(env, mmu_idx);
result->phys = address;
@@ -1618,7 +1618,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
}
if (n == -1) { /* no hits */
- if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
+ if (!pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) {
/* background fault */
fi->type = ARMFault_Background;
return true;
@@ -1739,7 +1739,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
} else if (m_is_ppb_region(env, address)) {
hit = true;
} else {
- if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
+ if (pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) {
hit = true;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 18/39] target/arm: Add secure parameter to get_phys_addr_pmsav7
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2022-09-22 16:35 ` [PULL 17/39] target/arm: Add is_secure parameter to pmsav7_use_background_region Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 19/39] target/arm: Add is_secure parameter to get_phys_addr_pmsav5 Peter Maydell
` (21 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Remove the use of regime_is_secure from get_phys_addr_pmsav7,
using the new parameter instead.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-19-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 9e1f60d10b4..1e81eefa47a 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1510,12 +1510,11 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- GetPhysAddrResult *result,
+ bool secure, GetPhysAddrResult *result,
ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
int n;
- bool secure = regime_is_secure(env, mmu_idx);
bool is_user = regime_is_user(env, mmu_idx);
result->phys = address;
@@ -2418,7 +2417,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
} else if (arm_feature(env, ARM_FEATURE_V7)) {
/* PMSAv7 */
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
- result, fi);
+ is_secure, result, fi);
} else {
/* Pre-v7 MPU */
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 19/39] target/arm: Add is_secure parameter to get_phys_addr_pmsav5
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2022-09-22 16:35 ` [PULL 18/39] target/arm: Add secure parameter to get_phys_addr_pmsav7 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 20/39] hw/acpi: Add ospm_status hook implementation for acpi-ged Peter Maydell
` (20 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Remove the use of regime_is_secure from get_phys_addr_pmsav5.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-21-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 1e81eefa47a..2ddfc028abb 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1349,7 +1349,7 @@ do_fault:
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- GetPhysAddrResult *result,
+ bool is_secure, GetPhysAddrResult *result,
ARMMMUFaultInfo *fi)
{
int n;
@@ -2421,7 +2421,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
} else {
/* Pre-v7 MPU */
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
- result, fi);
+ is_secure, result, fi);
}
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
" mmu_idx %u -> %s (prot %c%c%c)\n",
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 20/39] hw/acpi: Add ospm_status hook implementation for acpi-ged
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (18 preceding siblings ...)
2022-09-22 16:35 ` [PULL 19/39] target/arm: Add is_secure parameter to get_phys_addr_pmsav5 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 21/39] hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level Peter Maydell
` (19 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Keqian Zhu <zhukeqian1@huawei.com>
Setup an ARM virtual machine of machine virt and execute qmp "query-acpi-ospm-status"
causes segmentation fault with following dumpstack:
#1 0x0000aaaaab64235c in qmp_query_acpi_ospm_status (errp=errp@entry=0xfffffffff030) at ../monitor/qmp-cmds.c:312
#2 0x0000aaaaabfc4e20 in qmp_marshal_query_acpi_ospm_status (args=<optimized out>, ret=0xffffea4ffe90, errp=0xffffea4ffe88) at qapi/qapi-commands-acpi.c:63
#3 0x0000aaaaabff8ba0 in do_qmp_dispatch_bh (opaque=0xffffea4ffe98) at ../qapi/qmp-dispatch.c:128
#4 0x0000aaaaac02e594 in aio_bh_call (bh=0xffffe0004d80) at ../util/async.c:150
#5 aio_bh_poll (ctx=ctx@entry=0xaaaaad0f6040) at ../util/async.c:178
#6 0x0000aaaaac00bd40 in aio_dispatch (ctx=ctx@entry=0xaaaaad0f6040) at ../util/aio-posix.c:421
#7 0x0000aaaaac02e010 in aio_ctx_dispatch (source=0xaaaaad0f6040, callback=<optimized out>, user_data=<optimized out>) at ../util/async.c:320
#8 0x0000fffff76f6884 in g_main_context_dispatch () at /usr/lib64/libglib-2.0.so.0
#9 0x0000aaaaac0452d4 in glib_pollfds_poll () at ../util/main-loop.c:297
#10 os_host_main_loop_wait (timeout=0) at ../util/main-loop.c:320
#11 main_loop_wait (nonblocking=nonblocking@entry=0) at ../util/main-loop.c:596
#12 0x0000aaaaab5c9e50 in qemu_main_loop () at ../softmmu/runstate.c:734
#13 0x0000aaaaab185370 in qemu_main (argc=argc@entry=47, argv=argv@entry=0xfffffffff518, envp=envp@entry=0x0) at ../softmmu/main.c:38
#14 0x0000aaaaab16f99c in main (argc=47, argv=0xfffffffff518) at ../softmmu/main.c:47
Fixes: ebb62075021a ("hw/acpi: Add ACPI Generic Event Device Support")
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220816094957.31700-1-zhukeqian1@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/acpi/generic_event_device.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
index e28457a7d10..a3d31631fe0 100644
--- a/hw/acpi/generic_event_device.c
+++ b/hw/acpi/generic_event_device.c
@@ -267,6 +267,13 @@ static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
}
}
+static void acpi_ged_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
+{
+ AcpiGedState *s = ACPI_GED(adev);
+
+ acpi_memory_ospm_status(&s->memhp_state, list);
+}
+
static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
{
AcpiGedState *s = ACPI_GED(adev);
@@ -409,6 +416,7 @@ static void acpi_ged_class_init(ObjectClass *class, void *data)
hc->unplug_request = acpi_ged_unplug_request_cb;
hc->unplug = acpi_ged_unplug_cb;
+ adevc->ospm_status = acpi_ged_ospm_status;
adevc->send_event = acpi_ged_send_event;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 21/39] hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (19 preceding siblings ...)
2022-09-22 16:35 ` [PULL 20/39] hw/acpi: Add ospm_status hook implementation for acpi-ged Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 22/39] chardev/baum: Replace magic values by X_MAX / Y_MAX definitions Peter Maydell
` (18 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Lucas Dietrich <ld.adecy@gmail.com>
The LAN9118 allows the guest to specify a level for both the TX and
RX FIFOs at which an interrupt will be generated. We implement the
RSFL_INT interrupt for the RX FIFO but are missing the handling of
the equivalent TSFL_INT for the TX FIFO. Add the missing test to set
the interrupt if the TX FIFO has exceeded the guest-specified level.
This flag is required for Micrium lan911x ethernet driver to work.
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
[PMM: Tweaked commit message and comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/lan9118.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
index 456ae38107b..f1cba559672 100644
--- a/hw/net/lan9118.c
+++ b/hw/net/lan9118.c
@@ -696,6 +696,14 @@ static void do_tx_packet(lan9118_state *s)
n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
s->tx_status_fifo[n] = status;
s->tx_status_fifo_used++;
+
+ /*
+ * Generate TSFL interrupt if TX FIFO level exceeds the level
+ * specified in the FIFO_INT TX Status Level field.
+ */
+ if (s->tx_status_fifo_used > ((s->fifo_int >> 16) & 0xff)) {
+ s->int_sts |= TSFL_INT;
+ }
if (s->tx_status_fifo_used == 512) {
s->int_sts |= TSFF_INT;
/* TODO: Stop transmission. */
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 22/39] chardev/baum: Replace magic values by X_MAX / Y_MAX definitions
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (20 preceding siblings ...)
2022-09-22 16:35 ` [PULL 21/39] hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 23/39] chardev/baum: Use definitions to avoid dynamic stack allocation Peter Maydell
` (17 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Replace '84' magic value by the X_MAX definition, and '1' by Y_MAX.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220819153931.3147384-2-peter.maydell@linaro.org
---
chardev/baum.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/chardev/baum.c b/chardev/baum.c
index 79d618e3504..6d538808a0f 100644
--- a/chardev/baum.c
+++ b/chardev/baum.c
@@ -87,6 +87,9 @@
#define BUF_SIZE 256
+#define X_MAX 84
+#define Y_MAX 1
+
struct BaumChardev {
Chardev parent;
@@ -244,11 +247,11 @@ static int baum_deferred_init(BaumChardev *baum)
brlapi_perror("baum: brlapi__getDisplaySize");
return 0;
}
- if (baum->y > 1) {
- baum->y = 1;
+ if (baum->y > Y_MAX) {
+ baum->y = Y_MAX;
}
- if (baum->x > 84) {
- baum->x = 84;
+ if (baum->x > X_MAX) {
+ baum->x = X_MAX;
}
con = qemu_console_lookup_by_index(0);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 23/39] chardev/baum: Use definitions to avoid dynamic stack allocation
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (21 preceding siblings ...)
2022-09-22 16:35 ` [PULL 22/39] chardev/baum: Replace magic values by X_MAX / Y_MAX definitions Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 24/39] chardev/baum: Avoid " Peter Maydell
` (16 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
We know 'x * y' will be at most 'X_MAX * Y_MAX' (which is not
a big value, it is actually 84). Instead of having the compiler
use variable-length array, declare an array able to hold the
maximum 'x * y'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220819153931.3147384-3-peter.maydell@linaro.org
---
chardev/baum.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/chardev/baum.c b/chardev/baum.c
index 6d538808a0f..6a210ffd815 100644
--- a/chardev/baum.c
+++ b/chardev/baum.c
@@ -383,9 +383,9 @@ static int baum_eat_packet(BaumChardev *baum, const uint8_t *buf, int len)
switch (req) {
case BAUM_REQ_DisplayData:
{
- uint8_t cells[baum->x * baum->y], c;
- uint8_t text[baum->x * baum->y];
- uint8_t zero[baum->x * baum->y];
+ uint8_t cells[X_MAX * Y_MAX], c;
+ uint8_t text[X_MAX * Y_MAX];
+ uint8_t zero[X_MAX * Y_MAX];
int cursor = BRLAPI_CURSOR_OFF;
int i;
@@ -408,7 +408,7 @@ static int baum_eat_packet(BaumChardev *baum, const uint8_t *buf, int len)
}
timer_del(baum->cellCount_timer);
- memset(zero, 0, sizeof(zero));
+ memset(zero, 0, baum->x * baum->y);
brlapi_writeArguments_t wa = {
.displayNumber = BRLAPI_DISPLAY_DEFAULT,
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 24/39] chardev/baum: Avoid dynamic stack allocation
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (22 preceding siblings ...)
2022-09-22 16:35 ` [PULL 23/39] chardev/baum: Use definitions to avoid dynamic stack allocation Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 25/39] io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1 Peter Maydell
` (15 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Use autofree heap allocation instead of variable-length
array on the stack.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220819153931.3147384-4-peter.maydell@linaro.org
---
chardev/baum.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/chardev/baum.c b/chardev/baum.c
index 6a210ffd815..0a0d12661a4 100644
--- a/chardev/baum.c
+++ b/chardev/baum.c
@@ -299,7 +299,8 @@ static void baum_chr_accept_input(struct Chardev *chr)
static void baum_write_packet(BaumChardev *baum, const uint8_t *buf, int len)
{
Chardev *chr = CHARDEV(baum);
- uint8_t io_buf[1 + 2 * len], *cur = io_buf;
+ g_autofree uint8_t *io_buf = g_malloc(1 + 2 * len);
+ uint8_t *cur = io_buf;
int room;
*cur++ = ESC;
while (len--)
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 25/39] io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (23 preceding siblings ...)
2022-09-22 16:35 ` [PULL 24/39] chardev/baum: Avoid " Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 26/39] hw/net/e1000e_core: Use definition to avoid dynamic stack allocation Peter Maydell
` (14 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
The combined_key[... QIO_CHANNEL_WEBSOCK_GUID_LEN ...] array in
qio_channel_websock_handshake_send_res_ok() expands to a call
to strlen(QIO_CHANNEL_WEBSOCK_GUID), and the compiler doesn't
realize the string is const, so consider combined_key[] being
a variable-length array.
To remove the variable-length array, we provide it a hint to
the compiler by using sizeof() - 1 instead of strlen().
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220819153931.3147384-5-peter.maydell@linaro.org
---
io/channel-websock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/io/channel-websock.c b/io/channel-websock.c
index 9619906ac36..fb4932ade70 100644
--- a/io/channel-websock.c
+++ b/io/channel-websock.c
@@ -32,7 +32,7 @@
#define QIO_CHANNEL_WEBSOCK_CLIENT_KEY_LEN 24
#define QIO_CHANNEL_WEBSOCK_GUID "258EAFA5-E914-47DA-95CA-C5AB0DC85B11"
-#define QIO_CHANNEL_WEBSOCK_GUID_LEN strlen(QIO_CHANNEL_WEBSOCK_GUID)
+#define QIO_CHANNEL_WEBSOCK_GUID_LEN (sizeof(QIO_CHANNEL_WEBSOCK_GUID) - 1)
#define QIO_CHANNEL_WEBSOCK_HEADER_PROTOCOL "sec-websocket-protocol"
#define QIO_CHANNEL_WEBSOCK_HEADER_VERSION "sec-websocket-version"
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 26/39] hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (24 preceding siblings ...)
2022-09-22 16:35 ` [PULL 25/39] io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1 Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 27/39] hw/ppc/pnv: Avoid " Peter Maydell
` (13 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
The compiler isn't clever enough to figure 'min_buf_size'
is a constant, so help it by using a definitions instead.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220819153931.3147384-6-peter.maydell@linaro.org
---
hw/net/e1000e_core.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
index 208e3e0d798..82aa61fedcd 100644
--- a/hw/net/e1000e_core.c
+++ b/hw/net/e1000e_core.c
@@ -1622,15 +1622,16 @@ e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
}
}
+/* Min. octets in an ethernet frame sans FCS */
+#define MIN_BUF_SIZE 60
+
ssize_t
e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
{
static const int maximum_ethernet_hdr_len = (14 + 4);
- /* Min. octets in an ethernet frame sans FCS */
- static const int min_buf_size = 60;
uint32_t n = 0;
- uint8_t min_buf[min_buf_size];
+ uint8_t min_buf[MIN_BUF_SIZE];
struct iovec min_iov;
uint8_t *filter_buf;
size_t size, orig_size;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 27/39] hw/ppc/pnv: Avoid dynamic stack allocation
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (25 preceding siblings ...)
2022-09-22 16:35 ` [PULL 26/39] hw/net/e1000e_core: Use definition to avoid dynamic stack allocation Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 28/39] hw/intc/xics: " Peter Maydell
` (12 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Use autofree heap allocation instead of variable-length
array on the stack.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-id: 20220819153931.3147384-7-peter.maydell@linaro.org
---
hw/ppc/pnv.c | 4 ++--
hw/ppc/spapr.c | 8 ++++----
hw/ppc/spapr_pci_nvlink2.c | 2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 354aa289d18..78e00afb9b9 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -138,7 +138,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
int smt_threads = CPU_CORE(pc)->nr_threads;
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
- uint32_t servers_prop[smt_threads];
+ g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
int i;
uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
0xffffffff, 0xffffffff};
@@ -241,7 +241,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
servers_prop[i] = cpu_to_be32(pc->pir + i);
}
_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
- servers_prop, sizeof(servers_prop))));
+ servers_prop, sizeof(*servers_prop) * smt_threads)));
}
static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index cc1adc23faf..8bbaf4f8a4e 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -177,8 +177,8 @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
int smt_threads)
{
int i, ret = 0;
- uint32_t servers_prop[smt_threads];
- uint32_t gservers_prop[smt_threads * 2];
+ g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
+ g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2);
int index = spapr_get_vcpu_id(cpu);
if (cpu->compat_pvr) {
@@ -196,12 +196,12 @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
gservers_prop[i*2 + 1] = 0;
}
ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
- servers_prop, sizeof(servers_prop));
+ servers_prop, sizeof(*servers_prop) * smt_threads);
if (ret < 0) {
return ret;
}
ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
- gservers_prop, sizeof(gservers_prop));
+ gservers_prop, sizeof(*gservers_prop) * smt_threads * 2);
return ret;
}
diff --git a/hw/ppc/spapr_pci_nvlink2.c b/hw/ppc/spapr_pci_nvlink2.c
index 63b476c8f72..2a8a11be1d6 100644
--- a/hw/ppc/spapr_pci_nvlink2.c
+++ b/hw/ppc/spapr_pci_nvlink2.c
@@ -397,7 +397,7 @@ void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
continue;
}
if (dev == nvslot->gpdev) {
- uint32_t npus[nvslot->linknum];
+ g_autofree uint32_t *npus = g_new(uint32_t, nvslot->linknum);
for (j = 0; j < nvslot->linknum; ++j) {
PCIDevice *npdev = nvslot->links[j].npdev;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 28/39] hw/intc/xics: Avoid dynamic stack allocation
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (26 preceding siblings ...)
2022-09-22 16:35 ` [PULL 27/39] hw/ppc/pnv: Avoid " Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 29/39] hw/i386/multiboot: " Peter Maydell
` (11 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Use autofree heap allocation instead of variable-length
array on the stack.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220819153931.3147384-8-peter.maydell@linaro.org
---
hw/intc/xics.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 5b0b4d96242..dcd021af668 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -567,8 +567,8 @@ static void ics_reset_irq(ICSIRQState *irq)
static void ics_reset(DeviceState *dev)
{
ICSState *ics = ICS(dev);
+ g_autofree uint8_t *flags = g_malloc(ics->nr_irqs);
int i;
- uint8_t flags[ics->nr_irqs];
for (i = 0; i < ics->nr_irqs; i++) {
flags[i] = ics->irqs[i].flags;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 29/39] hw/i386/multiboot: Avoid dynamic stack allocation
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (27 preceding siblings ...)
2022-09-22 16:35 ` [PULL 28/39] hw/intc/xics: " Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 30/39] hw/usb/hcd-ohci: Use definition to avoid " Peter Maydell
` (10 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Use autofree heap allocation instead of variable-length array on
the stack. Replace the snprintf() call by g_strdup_printf().
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220819153931.3147384-9-peter.maydell@linaro.org
---
hw/i386/multiboot.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c
index 0a10089f14b..963e29362e4 100644
--- a/hw/i386/multiboot.c
+++ b/hw/i386/multiboot.c
@@ -163,6 +163,7 @@ int load_multiboot(X86MachineState *x86ms,
uint8_t *mb_bootinfo_data;
uint32_t cmdline_len;
GList *mods = NULL;
+ g_autofree char *kcmdline = NULL;
/* Ok, let's see if it is a multiboot image.
The header is 12x32bit long, so the latest entry may be 8192 - 48. */
@@ -362,9 +363,7 @@ int load_multiboot(X86MachineState *x86ms,
}
/* Commandline support */
- char kcmdline[strlen(kernel_filename) + strlen(kernel_cmdline) + 2];
- snprintf(kcmdline, sizeof(kcmdline), "%s %s",
- kernel_filename, kernel_cmdline);
+ kcmdline = g_strdup_printf("%s %s", kernel_filename, kernel_cmdline);
stl_p(bootinfo + MBI_CMDLINE, mb_add_cmdline(&mbs, kcmdline));
stl_p(bootinfo + MBI_BOOTLOADER, mb_add_bootloader(&mbs, bootloader_name));
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 30/39] hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (28 preceding siblings ...)
2022-09-22 16:35 ` [PULL 29/39] hw/i386/multiboot: " Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 31/39] ui/curses: Avoid " Peter Maydell
` (9 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
The compiler isn't clever enough to figure 'width' is a constant,
so help it by using a definitions instead.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220819153931.3147384-10-peter.maydell@linaro.org
---
hw/usb/hcd-ohci.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index 895b29fb865..5585fd32ccf 100644
--- a/hw/usb/hcd-ohci.c
+++ b/hw/usb/hcd-ohci.c
@@ -805,13 +805,14 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
return 1;
}
+#define HEX_CHAR_PER_LINE 16
+
static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
{
bool print16;
bool printall;
- const int width = 16;
int i;
- char tmp[3 * width + 1];
+ char tmp[3 * HEX_CHAR_PER_LINE + 1];
char *p = tmp;
print16 = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT);
@@ -822,7 +823,7 @@ static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
}
for (i = 0; ; i++) {
- if (i && (!(i % width) || (i == len))) {
+ if (i && (!(i % HEX_CHAR_PER_LINE) || (i == len))) {
if (!printall) {
trace_usb_ohci_td_pkt_short(msg, tmp);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 31/39] ui/curses: Avoid dynamic stack allocation
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (29 preceding siblings ...)
2022-09-22 16:35 ` [PULL 30/39] hw/usb/hcd-ohci: Use definition to avoid " Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 32/39] tests/unit/test-vmstate: " Peter Maydell
` (8 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Use autofree heap allocation instead of variable-length
array on the stack.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220819153931.3147384-11-peter.maydell@linaro.org
---
ui/curses.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ui/curses.c b/ui/curses.c
index 861d63244c7..de962faa7cd 100644
--- a/ui/curses.c
+++ b/ui/curses.c
@@ -69,7 +69,7 @@ static void curses_update(DisplayChangeListener *dcl,
int x, int y, int w, int h)
{
console_ch_t *line;
- cchar_t curses_line[width];
+ g_autofree cchar_t *curses_line = g_new(cchar_t, width);
wchar_t wch[CCHARW_MAX];
attr_t attrs;
short colors;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 32/39] tests/unit/test-vmstate: Avoid dynamic stack allocation
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (30 preceding siblings ...)
2022-09-22 16:35 ` [PULL 31/39] ui/curses: Avoid " Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 33/39] configure: Remove unused python_version variable Peter Maydell
` (7 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Use autofree heap allocation instead of variable-length
array on the stack.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220819153931.3147384-12-peter.maydell@linaro.org
---
tests/unit/test-vmstate.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/tests/unit/test-vmstate.c b/tests/unit/test-vmstate.c
index 72077b57800..541bb4f63e3 100644
--- a/tests/unit/test-vmstate.c
+++ b/tests/unit/test-vmstate.c
@@ -87,17 +87,16 @@ static void save_buffer(const uint8_t *buf, size_t buf_size)
static void compare_vmstate(const uint8_t *wire, size_t size)
{
QEMUFile *f = open_test_file(false);
- uint8_t result[size];
+ g_autofree uint8_t *result = g_malloc(size);
/* read back as binary */
- g_assert_cmpint(qemu_get_buffer(f, result, sizeof(result)), ==,
- sizeof(result));
+ g_assert_cmpint(qemu_get_buffer(f, result, size), ==, size);
g_assert(!qemu_file_get_error(f));
/* Compare that what is on the file is the same that what we
expected to be there */
- SUCCESS(memcmp(result, wire, sizeof(result)));
+ SUCCESS(memcmp(result, wire, size));
/* Must reach EOF */
qemu_get_byte(f);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 33/39] configure: Remove unused python_version variable
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (31 preceding siblings ...)
2022-09-22 16:35 ` [PULL 32/39] tests/unit/test-vmstate: " Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 34/39] configure: Remove unused meson_args variable Peter Maydell
` (6 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
Shellcheck correctly reports that we set python_version and never use
it. This is a leftover from commit f9332757898a7: we used to use
python_version purely to as part of the summary information printed
at the end of a configure run, and that commit changed to printing
the information from meson (which looks up the python version
itself). Remove the unused variable.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220825150703.4074125-2-peter.maydell@linaro.org
---
configure | 3 ---
1 file changed, 3 deletions(-)
diff --git a/configure b/configure
index 0bbf9d28af7..b5ace4cb49e 100755
--- a/configure
+++ b/configure
@@ -1112,9 +1112,6 @@ if ! $python -c 'import sys; sys.exit(sys.version_info < (3,6))'; then
"Use --python=/path/to/python to specify a supported Python."
fi
-# Preserve python version since some functionality is dependent on it
-python_version=$($python -c 'import sys; print("%d.%d.%d" % (sys.version_info[0], sys.version_info[1], sys.version_info[2]))' 2>/dev/null)
-
# Suppress writing compiled files
python="$python -B"
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 34/39] configure: Remove unused meson_args variable
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (32 preceding siblings ...)
2022-09-22 16:35 ` [PULL 33/39] configure: Remove unused python_version variable Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 35/39] configure: Add missing quoting for some easy cases Peter Maydell
` (5 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
The meson_args variable was added in commit 3b4da13293482134b, but
was not used in that commit and isn't used today. Delete the
unnecessary assignment.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220825150703.4074125-3-peter.maydell@linaro.org
---
configure | 1 -
1 file changed, 1 deletion(-)
diff --git a/configure b/configure
index b5ace4cb49e..e42d43d6a50 100755
--- a/configure
+++ b/configure
@@ -311,7 +311,6 @@ pie=""
coroutine=""
plugins="$default_feature"
meson=""
-meson_args=""
ninja=""
bindir="bin"
skip_meson=no
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 35/39] configure: Add missing quoting for some easy cases
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (33 preceding siblings ...)
2022-09-22 16:35 ` [PULL 34/39] configure: Remove unused meson_args variable Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 36/39] configure: Add './' on front of glob of */config-devices.mak.d Peter Maydell
` (4 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
This commit adds quotes in some places which:
* are spotted by shellcheck
* are obviously incorrect
* are easy to fix just by adding the quotes
It doesn't attempt fix all of the places shellcheck finds errors,
or even all the ones which are easy to fix. It's just a random
sampling which is hopefully easy to review and which cuts
down the size of the problem for next time somebody wants to
try to look at shellcheck errors.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220825150703.4074125-4-peter.maydell@linaro.org
---
configure | 64 +++++++++++++++++++++++++++----------------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/configure b/configure
index e42d43d6a50..86cc6259181 100755
--- a/configure
+++ b/configure
@@ -57,7 +57,7 @@ GNUmakefile: ;
EOF
cd build
- exec $source_path/configure "$@"
+ exec "$source_path/configure" "$@"
fi
# Temporary directory used for files created while
@@ -691,7 +691,7 @@ meson_option_build_array() {
printf ']\n'
}
-. $source_path/scripts/meson-buildoptions.sh
+. "$source_path/scripts/meson-buildoptions.sh"
meson_options=
meson_option_add() {
@@ -711,7 +711,7 @@ for opt do
case "$opt" in
--help|-h) show_help=yes
;;
- --version|-V) exec cat $source_path/VERSION
+ --version|-V) exec cat "$source_path/VERSION"
;;
--prefix=*) prefix="$optarg"
;;
@@ -985,7 +985,7 @@ default_target_list=""
mak_wilds=""
if [ "$linux_user" != no ]; then
- if [ "$targetos" = linux ] && [ -d $source_path/linux-user/include/host/$cpu ]; then
+ if [ "$targetos" = linux ] && [ -d "$source_path/linux-user/include/host/$cpu" ]; then
linux_user=yes
elif [ "$linux_user" = yes ]; then
error_exit "linux-user not supported on this architecture"
@@ -995,7 +995,7 @@ if [ "$bsd_user" != no ]; then
if [ "$bsd_user" = "" ]; then
test $targetos = freebsd && bsd_user=yes
fi
- if [ "$bsd_user" = yes ] && ! [ -d $source_path/bsd-user/$targetos ]; then
+ if [ "$bsd_user" = yes ] && ! [ -d "$source_path/bsd-user/$targetos" ]; then
error_exit "bsd-user not supported on this host OS"
fi
fi
@@ -1117,7 +1117,7 @@ python="$python -B"
if test -z "$meson"; then
if test "$explicit_python" = no && has meson && version_ge "$(meson --version)" 0.59.3; then
meson=meson
- elif test $git_submodules_action != 'ignore' ; then
+ elif test "$git_submodules_action" != 'ignore' ; then
meson=git
elif test -e "${source_path}/meson/meson.py" ; then
meson=internal
@@ -1834,7 +1834,7 @@ esac
container="no"
if test $use_containers = "yes"; then
if has "docker" || has "podman"; then
- container=$($python $source_path/tests/docker/docker.py probe)
+ container=$($python "$source_path"/tests/docker/docker.py probe)
fi
fi
@@ -2284,7 +2284,7 @@ if test "$QEMU_GA_DISTRO" = ""; then
QEMU_GA_DISTRO=Linux
fi
if test "$QEMU_GA_VERSION" = ""; then
- QEMU_GA_VERSION=$(cat $source_path/VERSION)
+ QEMU_GA_VERSION=$(cat "$source_path"/VERSION)
fi
@@ -2533,7 +2533,7 @@ fi
for target in $target_list; do
target_dir="$target"
target_name=$(echo $target | cut -d '-' -f 1)$EXESUF
- mkdir -p $target_dir
+ mkdir -p "$target_dir"
case $target in
*-user) symlink "../qemu-$target_name" "$target_dir/qemu-$target_name" ;;
*) symlink "../qemu-system-$target_name" "$target_dir/qemu-system-$target_name" ;;
@@ -2568,14 +2568,14 @@ for target in $target_list; do
config_target_mak=tests/tcg/config-$target.mak
echo "# Automatically generated by configure - do not modify" > $config_target_mak
- echo "TARGET_NAME=$arch" >> $config_target_mak
+ echo "TARGET_NAME=$arch" >> "$config_target_mak"
case $target in
xtensa*-linux-user)
# the toolchain is not complete with headers, only build softmmu tests
continue
;;
*-softmmu)
- test -f $source_path/tests/tcg/$arch/Makefile.softmmu-target || continue
+ test -f "$source_path/tests/tcg/$arch/Makefile.softmmu-target" || continue
qemu="qemu-system-$arch"
;;
*-linux-user|*-bsd-user)
@@ -2590,73 +2590,73 @@ for target in $target_list; do
# compilers is a requirememt for adding a new test that needs a
# compiler feature.
- echo "BUILD_STATIC=$build_static" >> $config_target_mak
- write_target_makefile >> $config_target_mak
+ echo "BUILD_STATIC=$build_static" >> "$config_target_mak"
+ write_target_makefile >> "$config_target_mak"
case $target in
aarch64-*)
if do_compiler "$target_cc" $target_cflags \
-march=armv8.1-a+sve -o $TMPE $TMPC; then
- echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak
+ echo "CROSS_CC_HAS_SVE=y" >> "$config_target_mak"
fi
if do_compiler "$target_cc" $target_cflags \
-march=armv8.1-a+sve2 -o $TMPE $TMPC; then
- echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak
+ echo "CROSS_CC_HAS_SVE2=y" >> "$config_target_mak"
fi
if do_compiler "$target_cc" $target_cflags \
-march=armv8.3-a -o $TMPE $TMPC; then
- echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
+ echo "CROSS_CC_HAS_ARMV8_3=y" >> "$config_target_mak"
fi
if do_compiler "$target_cc" $target_cflags \
-mbranch-protection=standard -o $TMPE $TMPC; then
- echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
+ echo "CROSS_CC_HAS_ARMV8_BTI=y" >> "$config_target_mak"
fi
if do_compiler "$target_cc" $target_cflags \
-march=armv8.5-a+memtag -o $TMPE $TMPC; then
- echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak
+ echo "CROSS_CC_HAS_ARMV8_MTE=y" >> "$config_target_mak"
fi
;;
ppc*)
if do_compiler "$target_cc" $target_cflags \
-mpower8-vector -o $TMPE $TMPC; then
- echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> $config_target_mak
+ echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> "$config_target_mak"
fi
if do_compiler "$target_cc" $target_cflags \
-mpower10 -o $TMPE $TMPC; then
- echo "CROSS_CC_HAS_POWER10=y" >> $config_target_mak
+ echo "CROSS_CC_HAS_POWER10=y" >> "$config_target_mak"
fi
;;
i386-linux-user)
if do_compiler "$target_cc" $target_cflags \
-Werror -fno-pie -o $TMPE $TMPC; then
- echo "CROSS_CC_HAS_I386_NOPIE=y" >> $config_target_mak
+ echo "CROSS_CC_HAS_I386_NOPIE=y" >> "$config_target_mak"
fi
;;
esac
elif test -n "$container_image"; then
echo "build-tcg-tests-$target: docker-image-$container_image" >> $makefile
- echo "BUILD_STATIC=y" >> $config_target_mak
- write_container_target_makefile >> $config_target_mak
+ echo "BUILD_STATIC=y" >> "$config_target_mak"
+ write_container_target_makefile >> "$config_target_mak"
case $target in
aarch64-*)
- echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak
- echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak
- echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
- echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
- echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak
+ echo "CROSS_CC_HAS_SVE=y" >> "$config_target_mak"
+ echo "CROSS_CC_HAS_SVE2=y" >> "$config_target_mak"
+ echo "CROSS_CC_HAS_ARMV8_3=y" >> "$config_target_mak"
+ echo "CROSS_CC_HAS_ARMV8_BTI=y" >> "$config_target_mak"
+ echo "CROSS_CC_HAS_ARMV8_MTE=y" >> "$config_target_mak"
;;
ppc*)
- echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> $config_target_mak
- echo "CROSS_CC_HAS_POWER10=y" >> $config_target_mak
+ echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> "$config_target_mak"
+ echo "CROSS_CC_HAS_POWER10=y" >> "$config_target_mak"
;;
i386-linux-user)
- echo "CROSS_CC_HAS_I386_NOPIE=y" >> $config_target_mak
+ echo "CROSS_CC_HAS_I386_NOPIE=y" >> "$config_target_mak"
;;
esac
got_cross_cc=yes
fi
if test $got_cross_cc = yes; then
mkdir -p tests/tcg/$target
- echo "QEMU=$PWD/$qemu" >> $config_target_mak
+ echo "QEMU=$PWD/$qemu" >> "$config_target_mak"
echo "run-tcg-tests-$target: $qemu\$(EXESUF)" >> $makefile
tcg_tests_targets="$tcg_tests_targets $target"
fi
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 36/39] configure: Add './' on front of glob of */config-devices.mak.d
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (34 preceding siblings ...)
2022-09-22 16:35 ` [PULL 35/39] configure: Add missing quoting for some easy cases Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 37/39] configure: Remove use of backtick `...` syntax Peter Maydell
` (3 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
Shellcheck warns that in
rm -f */config-devices.mak.d
the glob might expand to something with a '-' in it, which would
then be misinterpreted as an option to rm. Fix this by adding './'.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220825150703.4074125-5-peter.maydell@linaro.org
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index 86cc6259181..482497e9743 100755
--- a/configure
+++ b/configure
@@ -1093,7 +1093,7 @@ exit 0
fi
# Remove old dependency files to make sure that they get properly regenerated
-rm -f */config-devices.mak.d
+rm -f ./*/config-devices.mak.d
if test -z "$python"
then
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 37/39] configure: Remove use of backtick `...` syntax
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (35 preceding siblings ...)
2022-09-22 16:35 ` [PULL 36/39] configure: Add './' on front of glob of */config-devices.mak.d Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 38/39] configure: Check mkdir result directly, not via $? Peter Maydell
` (2 subsequent siblings)
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
There's only one place in configure where we use `...` to execute a
command and capture the result. Switch to $() to match the rest of
the script. This silences a shellcheck warning.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220825150703.4074125-6-peter.maydell@linaro.org
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index 482497e9743..8b48e72a135 100755
--- a/configure
+++ b/configure
@@ -2311,7 +2311,7 @@ LINKS="$LINKS python"
LINKS="$LINKS contrib/plugins/Makefile "
for f in $LINKS ; do
if [ -e "$source_path/$f" ]; then
- mkdir -p `dirname ./$f`
+ mkdir -p "$(dirname ./"$f")"
symlink "$source_path/$f" "$f"
fi
done
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 38/39] configure: Check mkdir result directly, not via $?
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (36 preceding siblings ...)
2022-09-22 16:35 ` [PULL 37/39] configure: Remove use of backtick `...` syntax Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-22 16:35 ` [PULL 39/39] configure: Avoid use of 'local' as it is non-POSIX Peter Maydell
2022-09-26 19:22 ` [PULL 00/39] target-arm queue Stefan Hajnoczi
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
Shellcheck warns that we have one place where we run a command and
then check if it failed using $?; this is better written to simply
check the command in the 'if' statement directly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220825150703.4074125-7-peter.maydell@linaro.org
---
configure | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/configure b/configure
index 8b48e72a135..b39561b2ed7 100755
--- a/configure
+++ b/configure
@@ -67,8 +67,7 @@ fi
# it when configure exits.)
TMPDIR1="config-temp"
rm -rf "${TMPDIR1}"
-mkdir -p "${TMPDIR1}"
-if [ $? -ne 0 ]; then
+if ! mkdir -p "${TMPDIR1}"; then
echo "ERROR: failed to create temporary directory"
exit 1
fi
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 39/39] configure: Avoid use of 'local' as it is non-POSIX
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (37 preceding siblings ...)
2022-09-22 16:35 ` [PULL 38/39] configure: Check mkdir result directly, not via $? Peter Maydell
@ 2022-09-22 16:35 ` Peter Maydell
2022-09-26 19:22 ` [PULL 00/39] target-arm queue Stefan Hajnoczi
39 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-09-22 16:35 UTC (permalink / raw)
To: qemu-devel
We use the non-POSIX 'local' keyword in just two places in configure;
rewrite to avoid it.
In do_compiler(), just drop the 'local' keyword. The variable
'compiler' is only used elsewhere in the do_compiler_werror()
function, which already uses the variable as a normal non-local one.
In probe_target_compiler(), $try and $t are both local; make them
normal variables and use a more obviously distinct variable name
for $t.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220825150703.4074125-8-peter.maydell@linaro.org
---
configure | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/configure b/configure
index b39561b2ed7..cc4ecd6008b 100755
--- a/configure
+++ b/configure
@@ -110,7 +110,7 @@ error_exit() {
do_compiler() {
# Run the compiler, capturing its output to the log. First argument
# is compiler binary to execute.
- local compiler="$1"
+ compiler="$1"
shift
if test -n "$BASH_VERSION"; then eval '
echo >>config.log "
@@ -2065,7 +2065,6 @@ probe_target_compiler() {
: ${container_cross_strip:=${container_cross_prefix}strip}
done
- local t try
try=cross
case "$target_arch:$cpu" in
aarch64_be:aarch64 | \
@@ -2078,8 +2077,8 @@ probe_target_compiler() {
try='native cross' ;;
esac
eval "target_cflags=\${cross_cc_cflags_$target_arch}"
- for t in $try; do
- case $t in
+ for thistry in $try; do
+ case $thistry in
native)
target_cc=$cc
target_ccas=$ccas
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PULL 00/39] target-arm queue
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
` (38 preceding siblings ...)
2022-09-22 16:35 ` [PULL 39/39] configure: Avoid use of 'local' as it is non-POSIX Peter Maydell
@ 2022-09-26 19:22 ` Stefan Hajnoczi
39 siblings, 0 replies; 48+ messages in thread
From: Stefan Hajnoczi @ 2022-09-26 19:22 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 115 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PULL 00/39] target-arm queue
2022-02-08 11:39 Peter Maydell
@ 2022-02-08 15:03 ` Peter Maydell
0 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2022-02-08 15:03 UTC (permalink / raw)
To: qemu-devel
On Tue, 8 Feb 2022 at 11:39, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit 55ef0b702bc2c90c3c4ed97f97676d8f139e5ca1:
>
> Merge remote-tracking branch 'remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request' into staging (2022-02-07 10:48:25 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220208
>
> for you to fetch changes up to 4fd1ebb10593087d45d2f56f7f3d13447d24802c:
>
> hw/sensor: Add lsm303dlhc magnetometer device (2022-02-08 10:56:29 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Fix handling of SVE ZCR_LEN when using VHE
> * xlnx-zynqmp: 'Or' the QSPI / QSPI DMA IRQs
> * Don't ever enable PSCI when booting guest in EL3
> * Adhere to SMCCC 1.3 section 5.2
> * highbank: Fix issues with booting SMP
> * midway: Fix issues booting at all
> * boot: Drop existing dtb /psci node rather than retaining it
> * versal-virt: Always call arm_load_kernel()
> * force flag recalculation when messing with DAIF
> * hw/timer/armv7m_systick: Update clock source before enabling timer
> * hw/arm/smmuv3: Fix device reset
> * hw/intc/arm_gicv3_its: refactorings and minor bug fixes
> * hw/sensor: Add lsm303dlhc magnetometer device
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PULL 00/39] target-arm queue
@ 2022-02-08 11:39 Peter Maydell
2022-02-08 15:03 ` Peter Maydell
0 siblings, 1 reply; 48+ messages in thread
From: Peter Maydell @ 2022-02-08 11:39 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 55ef0b702bc2c90c3c4ed97f97676d8f139e5ca1:
Merge remote-tracking branch 'remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request' into staging (2022-02-07 10:48:25 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220208
for you to fetch changes up to 4fd1ebb10593087d45d2f56f7f3d13447d24802c:
hw/sensor: Add lsm303dlhc magnetometer device (2022-02-08 10:56:29 +0000)
----------------------------------------------------------------
target-arm queue:
* Fix handling of SVE ZCR_LEN when using VHE
* xlnx-zynqmp: 'Or' the QSPI / QSPI DMA IRQs
* Don't ever enable PSCI when booting guest in EL3
* Adhere to SMCCC 1.3 section 5.2
* highbank: Fix issues with booting SMP
* midway: Fix issues booting at all
* boot: Drop existing dtb /psci node rather than retaining it
* versal-virt: Always call arm_load_kernel()
* force flag recalculation when messing with DAIF
* hw/timer/armv7m_systick: Update clock source before enabling timer
* hw/arm/smmuv3: Fix device reset
* hw/intc/arm_gicv3_its: refactorings and minor bug fixes
* hw/sensor: Add lsm303dlhc magnetometer device
----------------------------------------------------------------
Alex Bennée (1):
arm: force flag recalculation when messing with DAIF
Edgar E. Iglesias (1):
hw/arm: versal-virt: Always call arm_load_kernel()
Eric Auger (1):
hw/arm/smmuv3: Fix device reset
Francisco Iglesias (1):
hw/arm/xlnx-zynqmp: 'Or' the QSPI / QSPI DMA IRQs
Kevin Townsend (1):
hw/sensor: Add lsm303dlhc magnetometer device
Peter Maydell (29):
target/arm: make psci-conduit settable after realize
cpu.c: Make start-powered-off settable after realize
hw/arm/boot: Support setting psci-conduit based on guest EL
hw/arm: imx: Don't enable PSCI conduit when booting guest in EL3
hw/arm: allwinner: Don't enable PSCI conduit when booting guest in EL3
hw/arm/xlnx-zcu102: Don't enable PSCI conduit when booting guest in EL3
hw/arm/versal: Let boot.c handle PSCI enablement
hw/arm/virt: Let boot.c handle PSCI enablement
hw/arm: highbank: For EL3 guests, don't enable PSCI, start all cores
arm: tcg: Adhere to SMCCC 1.3 section 5.2
hw/arm/highbank: Drop use of secure_board_setup
hw/arm/boot: Prevent setting both psci_conduit and secure_board_setup
hw/arm/boot: Don't write secondary boot stub if using PSCI
hw/arm/highbank: Drop unused secondary boot stub code
hw/arm/boot: Drop nb_cpus field from arm_boot_info
hw/arm/boot: Drop existing dtb /psci node rather than retaining it
hw/intc/arm_gicv3_its: Use address_space_map() to access command queue packets
hw/intc/arm_gicv3_its: Keep DTEs as a struct, not a raw uint64_t
hw/intc/arm_gicv3_its: Pass DTEntry to update_dte()
hw/intc/arm_gicv3_its: Keep CTEs as a struct, not a raw uint64_t
hw/intc/arm_gicv3_its: Pass CTEntry to update_cte()
hw/intc/arm_gicv3_its: Fix address calculation in get_ite() and update_ite()
hw/intc/arm_gicv3_its: Avoid nested ifs in get_ite()
hw/intc/arm_gicv3_its: Pass ITE values back from get_ite() via a struct
hw/intc/arm_gicv3_its: Make update_ite() use ITEntry
hw/intc/arm_gicv3_its: Drop TableDesc and CmdQDesc valid fields
hw/intc/arm_gicv3_its: In MAPC with V=0, don't check rdbase field
hw/intc/arm_gicv3_its: Don't allow intid 1023 in MAPI/MAPTI
hw/intc/arm_gicv3_its: Split error checks
Richard Henderson (4):
target/arm: Fix sve_zcr_len_for_el for VHE mode running
target/arm: Tidy sve_exception_el for CPACR_EL1 access
target/arm: Fix {fp, sve}_exception_el for VHE mode running
target/arm: Use CPTR_TFP with CPTR_EL3 in fp_exception_el
Richard Petri (1):
hw/timer/armv7m_systick: Update clock source before enabling timer
hw/intc/gicv3_internal.h | 23 +-
include/hw/arm/boot.h | 14 +-
include/hw/arm/xlnx-versal.h | 1 -
include/hw/arm/xlnx-zynqmp.h | 2 +
include/hw/intc/arm_gicv3_its_common.h | 2 -
cpu.c | 22 +-
hw/arm/allwinner-h3.c | 9 +-
hw/arm/aspeed.c | 1 -
hw/arm/boot.c | 107 ++++-
hw/arm/exynos4_boards.c | 1 -
hw/arm/fsl-imx6ul.c | 2 -
hw/arm/fsl-imx7.c | 8 +-
hw/arm/highbank.c | 72 +---
hw/arm/imx25_pdk.c | 3 +-
hw/arm/kzm.c | 1 -
hw/arm/mcimx6ul-evk.c | 2 +-
hw/arm/mcimx7d-sabre.c | 2 +-
hw/arm/npcm7xx.c | 3 -
hw/arm/orangepi.c | 5 +-
hw/arm/raspi.c | 1 -
hw/arm/realview.c | 1 -
hw/arm/sabrelite.c | 1 -
hw/arm/sbsa-ref.c | 1 -
hw/arm/smmuv3.c | 6 +
hw/arm/vexpress.c | 1 -
hw/arm/virt.c | 13 +-
hw/arm/xilinx_zynq.c | 1 -
hw/arm/xlnx-versal-virt.c | 17 +-
hw/arm/xlnx-versal.c | 5 +-
hw/arm/xlnx-zcu102.c | 1 +
hw/arm/xlnx-zynqmp.c | 25 +-
hw/intc/arm_gicv3_its.c | 696 +++++++++++++++------------------
hw/sensor/lsm303dlhc_mag.c | 556 ++++++++++++++++++++++++++
hw/timer/armv7m_systick.c | 8 +-
target/arm/cpu.c | 6 +-
target/arm/helper-a64.c | 2 +
target/arm/helper.c | 118 ++++--
target/arm/psci.c | 35 +-
tests/qtest/lsm303dlhc-mag-test.c | 148 +++++++
hw/sensor/Kconfig | 4 +
hw/sensor/meson.build | 1 +
tests/qtest/meson.build | 1 +
42 files changed, 1308 insertions(+), 620 deletions(-)
create mode 100644 hw/sensor/lsm303dlhc_mag.c
create mode 100644 tests/qtest/lsm303dlhc-mag-test.c
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PULL 00/39] target-arm queue
@ 2021-03-12 13:51 Peter Maydell
0 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2021-03-12 13:51 UTC (permalink / raw)
To: qemu-devel
Last pullreq before 6.0 softfreeze: a few minor feature patches,
some bugfixes, some cleanups.
-- PMM
The following changes since commit 6f34661b6c97a37a5efc27d31c037ddeda4547e2:
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging (2021-03-11 18:55:27 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210312-1
for you to fetch changes up to 41f09f2e9f09e4dd386d84174a6dcb5136af17ca:
hw/display/pxa2xx: Inline template header (2021-03-12 13:26:08 +0000)
----------------------------------------------------------------
target-arm queue:
* versal: Support XRAMs and XRAM controller
* smmu: Various minor bug fixes
* SVE emulation: fix bugs handling odd vector lengths
* allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
* tests/acceptance: fix orangepi-pc acceptance tests
* hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
* hw/arm/virt: KVM: The IPA lower bound is 32
* npcm7xx: support MFT module
* pl110, pxa2xx_lcd: tidy up template headers
----------------------------------------------------------------
Andrew Jones (2):
accel: kvm: Fix kvm_type invocation
hw/arm/virt: KVM: The IPA lower bound is 32
Edgar E. Iglesias (2):
hw/misc: versal: Add a model of the XRAM controller
hw/arm: versal: Add support for the XRAMs
Eric Auger (7):
intel_iommu: Fix mask may be uninitialized in vtd_context_device_invalidate
dma: Introduce dma_aligned_pow2_mask()
virtio-iommu: Handle non power of 2 range invalidations
hw/arm/smmu-common: Fix smmu_iotlb_inv_iova when asid is not set
hw/arm/smmuv3: Enforce invalidation on a power of two range
hw/arm/smmuv3: Fix SMMU_CMD_CFGI_STE_RANGE handling
hw/arm/smmuv3: Uniformize sid traces
Hao Wu (5):
hw/misc: Add GPIOs for duty in NPCM7xx PWM
hw/misc: Add NPCM7XX MFT Module
hw/arm: Add MFT device to NPCM7xx Soc
hw/arm: Connect PWM fans in NPCM7XX boards
tests/qtest: Test PWM fan RPM using MFT in PWM test
Niek Linnenbank (5):
hw/net/allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
tests/acceptance/boot_linux_console: remove Armbian 19.11.3 bionic test for orangepi-pc machine
tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08
tests/acceptance: update sunxi kernel from armbian to 5.10.16
tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests
Peter Maydell (9):
hw/display/pl110: Remove dead code for non-32-bpp surfaces
hw/display/pl110: Pull included-once parts of template header into pl110.c
hw/display/pl110: Remove use of BITS from pl110_template.h
hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces
hw/display/pxa2xx_lcd: Remove dest_width state field
hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h
hw/display/pxa2xx: Apply brace-related coding style fixes to template header
hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header
hw/display/pxa2xx: Inline template header
Philippe Mathieu-Daudé (1):
hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
Richard Henderson (8):
target/arm: Fix sve_uzp_p vs odd vector lengths
target/arm: Fix sve_zip_p vs odd vector lengths
target/arm: Fix sve_punpk_p vs odd vector lengths
target/arm: Update find_last_active for PREDDESC
target/arm: Update BRKA, BRKB, BRKN for PREDDESC
target/arm: Update CNTP for PREDDESC
target/arm: Update WHILE for PREDDESC
target/arm: Update sve reduction vs simd_desc
docs/system/arm/nuvoton.rst | 2 +-
docs/system/arm/xlnx-versal-virt.rst | 1 +
hw/arm/smmu-internal.h | 5 +
hw/display/pl110_template.h | 120 +-------
hw/display/pxa2xx_template.h | 447 ---------------------------
include/hw/arm/npcm7xx.h | 13 +-
include/hw/arm/xlnx-versal.h | 13 +
include/hw/boards.h | 1 +
include/hw/misc/npcm7xx_mft.h | 70 +++++
include/hw/misc/npcm7xx_pwm.h | 4 +-
include/hw/misc/xlnx-versal-xramc.h | 97 ++++++
include/sysemu/dma.h | 12 +
target/arm/kvm_arm.h | 6 +-
accel/kvm/kvm-all.c | 2 +
hw/arm/npcm7xx.c | 45 ++-
hw/arm/npcm7xx_boards.c | 99 ++++++
hw/arm/smmu-common.c | 32 +-
hw/arm/smmuv3.c | 58 ++--
hw/arm/virt.c | 23 +-
hw/arm/xlnx-versal.c | 36 +++
hw/display/pl110.c | 123 +++++---
hw/display/pxa2xx_lcd.c | 520 ++++++++++++++++++++++++++-----
hw/i386/intel_iommu.c | 32 +-
hw/misc/npcm7xx_mft.c | 540 +++++++++++++++++++++++++++++++++
hw/misc/npcm7xx_pwm.c | 4 +
hw/misc/xlnx-versal-xramc.c | 253 +++++++++++++++
hw/net/allwinner-sun8i-emac.c | 62 ++--
hw/timer/sse-timer.c | 1 +
hw/virtio/virtio-iommu.c | 19 +-
softmmu/dma-helpers.c | 26 ++
target/arm/kvm.c | 4 +-
target/arm/sve_helper.c | 107 ++++---
target/arm/translate-sve.c | 26 +-
tests/qtest/npcm7xx_pwm-test.c | 205 ++++++++++++-
hw/arm/trace-events | 24 +-
hw/misc/meson.build | 2 +
hw/misc/trace-events | 8 +
tests/acceptance/boot_linux_console.py | 120 +++-----
tests/acceptance/replay_kernel.py | 10 +-
39 files changed, 2235 insertions(+), 937 deletions(-)
delete mode 100644 hw/display/pxa2xx_template.h
create mode 100644 include/hw/misc/npcm7xx_mft.h
create mode 100644 include/hw/misc/xlnx-versal-xramc.h
create mode 100644 hw/misc/npcm7xx_mft.c
create mode 100644 hw/misc/xlnx-versal-xramc.c
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PULL 00/39] target-arm queue
2020-05-04 12:32 Peter Maydell
2020-05-04 13:34 ` Peter Maydell
2020-05-05 8:19 ` no-reply
@ 2020-05-05 8:20 ` no-reply
2 siblings, 0 replies; 48+ messages in thread
From: no-reply @ 2020-05-05 8:20 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel
Patchew URL: https://patchew.org/QEMU/20200504123309.3808-1-peter.maydell@linaro.org/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#! /bin/bash
export ARCH=x86_64
make docker-image-fedora V=1 NETWORK=1
time make docker-test-mingw@fedora J=14 NETWORK=1
=== TEST SCRIPT END ===
The full log is available at
http://patchew.org/logs/20200504123309.3808-1-peter.maydell@linaro.org/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PULL 00/39] target-arm queue
2020-05-04 12:32 Peter Maydell
2020-05-04 13:34 ` Peter Maydell
@ 2020-05-05 8:19 ` no-reply
2020-05-05 8:20 ` no-reply
2 siblings, 0 replies; 48+ messages in thread
From: no-reply @ 2020-05-05 8:19 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel
Patchew URL: https://patchew.org/QEMU/20200504123309.3808-1-peter.maydell@linaro.org/
Hi,
This series failed build test on FreeBSD host. Please find the details below.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointing to a commit that has the patches applied on top of "base"
# branch
if qemu-system-x86_64 --help >/dev/null 2>&1; then
QEMU=qemu-system-x86_64
elif /usr/libexec/qemu-kvm --help >/dev/null 2>&1; then
QEMU=/usr/libexec/qemu-kvm
else
exit 1
fi
make vm-build-freebsd J=21 QEMU=$QEMU
exit 0
=== TEST SCRIPT END ===
The full log is available at
http://patchew.org/logs/20200504123309.3808-1-peter.maydell@linaro.org/testing.FreeBSD/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PULL 00/39] target-arm queue
2020-05-04 12:32 Peter Maydell
@ 2020-05-04 13:34 ` Peter Maydell
2020-05-05 8:19 ` no-reply
2020-05-05 8:20 ` no-reply
2 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2020-05-04 13:34 UTC (permalink / raw)
To: QEMU Developers
On Mon, 4 May 2020 at 13:33, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Most of this is the Neon decodetree patches, followed by Edgar's versal cleanups.
>
> thanks
> -- PMM
>
>
> The following changes since commit 2ef486e76d64436be90f7359a3071fb2a56ce835:
>
> Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging (2020-05-03 14:12:56 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200504
>
> for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211:
>
> target/arm: Move gen_ function typedefs to translate.h (2020-05-04 12:59:26 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Start of conversion of Neon insns to decodetree
> * versal board: support SD and RTC
> * Implement ARMv8.2-TTS2UXN
> * Make VQDMULL undefined when U=1
> * Some minor code cleanups
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PULL 00/39] target-arm queue
@ 2020-05-04 12:32 Peter Maydell
2020-05-04 13:34 ` Peter Maydell
` (2 more replies)
0 siblings, 3 replies; 48+ messages in thread
From: Peter Maydell @ 2020-05-04 12:32 UTC (permalink / raw)
To: qemu-devel
Most of this is the Neon decodetree patches, followed by Edgar's versal cleanups.
thanks
-- PMM
The following changes since commit 2ef486e76d64436be90f7359a3071fb2a56ce835:
Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging (2020-05-03 14:12:56 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200504
for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211:
target/arm: Move gen_ function typedefs to translate.h (2020-05-04 12:59:26 +0100)
----------------------------------------------------------------
target-arm queue:
* Start of conversion of Neon insns to decodetree
* versal board: support SD and RTC
* Implement ARMv8.2-TTS2UXN
* Make VQDMULL undefined when U=1
* Some minor code cleanups
----------------------------------------------------------------
Edgar E. Iglesias (11):
hw/arm: versal: Remove inclusion of arm_gicv3_common.h
hw/arm: versal: Move misplaced comment
hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal
hw/arm: versal: Embed the UARTs into the SoC type
hw/arm: versal: Embed the GEMs into the SoC type
hw/arm: versal: Embed the ADMAs into the SoC type
hw/arm: versal: Embed the APUs into the SoC type
hw/arm: versal: Add support for SD
hw/arm: versal: Add support for the RTC
hw/arm: versal-virt: Add support for SD
hw/arm: versal-virt: Add support for the RTC
Fredrik Strupe (1):
target/arm: Make VQDMULL undefined when U=1
Peter Maydell (25):
target/arm: Don't use a TLB for ARMMMUIdx_Stage2
target/arm: Use enum constant in get_phys_addr_lpae() call
target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()
target/arm: Implement ARMv8.2-TTS2UXN
target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0
target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check
target/arm: Don't allow Thumb Neon insns without FEATURE_NEON
target/arm: Add stubs for AArch32 Neon decodetree
target/arm: Convert VCMLA (vector) to decodetree
target/arm: Convert VCADD (vector) to decodetree
target/arm: Convert V[US]DOT (vector) to decodetree
target/arm: Convert VFM[AS]L (vector) to decodetree
target/arm: Convert VCMLA (scalar) to decodetree
target/arm: Convert V[US]DOT (scalar) to decodetree
target/arm: Convert VFM[AS]L (scalar) to decodetree
target/arm: Convert Neon load/store multiple structures to decodetree
target/arm: Convert Neon 'load single structure to all lanes' to decodetree
target/arm: Convert Neon 'load/store single structure' to decodetree
target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
target/arm: Convert Neon 3-reg-same logic ops to decodetree
target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
target/arm: Convert Neon 3-reg-same comparisons to decodetree
target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree
target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree
target/arm: Move gen_ function typedefs to translate.h
Philippe Mathieu-Daudé (2):
hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string
target/arm: Use uint64_t for midr field in CPU state struct
include/hw/arm/xlnx-versal.h | 31 +-
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 38 ++-
target/arm/translate-a64.h | 9 -
target/arm/translate.h | 26 ++
target/arm/neon-dp.decode | 86 +++++
target/arm/neon-ls.decode | 52 +++
target/arm/neon-shared.decode | 66 ++++
hw/arm/mps2-tz.c | 2 +-
hw/arm/xlnx-versal-virt.c | 74 ++++-
hw/arm/xlnx-versal.c | 115 +++++--
target/arm/cpu.c | 3 +-
target/arm/cpu64.c | 8 +-
target/arm/helper.c | 183 ++++------
target/arm/translate-a64.c | 17 -
target/arm/translate-neon.inc.c | 714 +++++++++++++++++++++++++++++++++++++++
target/arm/translate-vfp.inc.c | 6 -
target/arm/translate.c | 716 +++-------------------------------------
target/arm/Makefile.objs | 18 +
19 files changed, 1302 insertions(+), 864 deletions(-)
create mode 100644 target/arm/neon-dp.decode
create mode 100644 target/arm/neon-ls.decode
create mode 100644 target/arm/neon-shared.decode
create mode 100644 target/arm/translate-neon.inc.c
^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2022-09-26 19:24 UTC | newest]
Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-22 16:34 [PULL 00/39] target-arm queue Peter Maydell
2022-09-22 16:34 ` [PULL 01/39] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic Peter Maydell
2022-09-22 16:34 ` [PULL 02/39] target/arm: Fix alignment for VLD4.32 Peter Maydell
2022-09-22 16:35 ` [PULL 03/39] target/arm: Create GetPhysAddrResult Peter Maydell
2022-09-22 16:35 ` [PULL 04/39] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae Peter Maydell
2022-09-22 16:35 ` [PULL 05/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v6 Peter Maydell
2022-09-22 16:35 ` [PULL 06/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v5 Peter Maydell
2022-09-22 16:35 ` [PULL 07/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5 Peter Maydell
2022-09-22 16:35 ` [PULL 08/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7 Peter Maydell
2022-09-22 16:35 ` [PULL 09/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8 Peter Maydell
2022-09-22 16:35 ` [PULL 10/39] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup Peter Maydell
2022-09-22 16:35 ` [PULL 11/39] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup Peter Maydell
2022-09-22 16:35 ` [PULL 12/39] target/arm: Add is_secure parameter to v8m_security_lookup Peter Maydell
2022-09-22 16:35 ` [PULL 13/39] target/arm: Add secure parameter to pmsav8_mpu_lookup Peter Maydell
2022-09-22 16:35 ` [PULL 14/39] target/arm: Add is_secure parameter to get_phys_addr_v5 Peter Maydell
2022-09-22 16:35 ` [PULL 15/39] target/arm: Add is_secure parameter to get_phys_addr_v6 Peter Maydell
2022-09-22 16:35 ` [PULL 16/39] target/arm: Add secure parameter to get_phys_addr_pmsav8 Peter Maydell
2022-09-22 16:35 ` [PULL 17/39] target/arm: Add is_secure parameter to pmsav7_use_background_region Peter Maydell
2022-09-22 16:35 ` [PULL 18/39] target/arm: Add secure parameter to get_phys_addr_pmsav7 Peter Maydell
2022-09-22 16:35 ` [PULL 19/39] target/arm: Add is_secure parameter to get_phys_addr_pmsav5 Peter Maydell
2022-09-22 16:35 ` [PULL 20/39] hw/acpi: Add ospm_status hook implementation for acpi-ged Peter Maydell
2022-09-22 16:35 ` [PULL 21/39] hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level Peter Maydell
2022-09-22 16:35 ` [PULL 22/39] chardev/baum: Replace magic values by X_MAX / Y_MAX definitions Peter Maydell
2022-09-22 16:35 ` [PULL 23/39] chardev/baum: Use definitions to avoid dynamic stack allocation Peter Maydell
2022-09-22 16:35 ` [PULL 24/39] chardev/baum: Avoid " Peter Maydell
2022-09-22 16:35 ` [PULL 25/39] io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1 Peter Maydell
2022-09-22 16:35 ` [PULL 26/39] hw/net/e1000e_core: Use definition to avoid dynamic stack allocation Peter Maydell
2022-09-22 16:35 ` [PULL 27/39] hw/ppc/pnv: Avoid " Peter Maydell
2022-09-22 16:35 ` [PULL 28/39] hw/intc/xics: " Peter Maydell
2022-09-22 16:35 ` [PULL 29/39] hw/i386/multiboot: " Peter Maydell
2022-09-22 16:35 ` [PULL 30/39] hw/usb/hcd-ohci: Use definition to avoid " Peter Maydell
2022-09-22 16:35 ` [PULL 31/39] ui/curses: Avoid " Peter Maydell
2022-09-22 16:35 ` [PULL 32/39] tests/unit/test-vmstate: " Peter Maydell
2022-09-22 16:35 ` [PULL 33/39] configure: Remove unused python_version variable Peter Maydell
2022-09-22 16:35 ` [PULL 34/39] configure: Remove unused meson_args variable Peter Maydell
2022-09-22 16:35 ` [PULL 35/39] configure: Add missing quoting for some easy cases Peter Maydell
2022-09-22 16:35 ` [PULL 36/39] configure: Add './' on front of glob of */config-devices.mak.d Peter Maydell
2022-09-22 16:35 ` [PULL 37/39] configure: Remove use of backtick `...` syntax Peter Maydell
2022-09-22 16:35 ` [PULL 38/39] configure: Check mkdir result directly, not via $? Peter Maydell
2022-09-22 16:35 ` [PULL 39/39] configure: Avoid use of 'local' as it is non-POSIX Peter Maydell
2022-09-26 19:22 ` [PULL 00/39] target-arm queue Stefan Hajnoczi
-- strict thread matches above, loose matches on Subject: below --
2022-02-08 11:39 Peter Maydell
2022-02-08 15:03 ` Peter Maydell
2021-03-12 13:51 Peter Maydell
2020-05-04 12:32 Peter Maydell
2020-05-04 13:34 ` Peter Maydell
2020-05-05 8:19 ` no-reply
2020-05-05 8:20 ` no-reply
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