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From: Vidya Sagar <vidyas@nvidia.com>
To: <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>,
	<bhelgaas@google.com>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>, <kishon@ti.com>, <vkoul@kernel.org>,
	<mani@kernel.org>, <Sergey.Semin@baikalelectronics.ru>,
	<ffclaire1224@gmail.com>
Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
	<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
	<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH V2 8/9] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration
Date: Mon, 26 Sep 2022 17:20:37 +0530	[thread overview]
Message-ID: <20220926115038.24727-9-vidyas@nvidia.com> (raw)
In-Reply-To: <20220926115038.24727-1-vidyas@nvidia.com>

Set ENABLE_L2_EXIT_RATE_CHANGE to request UPHY PLL rate change to Gen1
during initialization. This helps in the below surprise down cases,
  - Surprise down happens at Gen3/Gen4 link speed
  - Surprise down happens and external REFCLK is cut off which causes
UPHY PLL rate to deviate to an invalid rate

ENABLE_L2_EXIT_RATE_CHANGE needs to be set to bring the UPHY PLL rate
back to Gen1 during controller initialization for the link up.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reported-by: kernel test robot <lkp@intel.com>
---
V2:
* Addressed review comment from test bot and Vinod

 drivers/phy/tegra/phy-tegra194-p2u.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c
index 1415ca71de38..633e6b747275 100644
--- a/drivers/phy/tegra/phy-tegra194-p2u.c
+++ b/drivers/phy/tegra/phy-tegra194-p2u.c
@@ -15,6 +15,7 @@
 #include <linux/phy/phy.h>
 
 #define P2U_CONTROL_CMN			0x74
+#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE		BIT(13)
 #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN			BIT(20)
 
 #define P2U_PERIODIC_EQ_CTRL_GEN3	0xc0
@@ -85,8 +86,21 @@ static int tegra_p2u_power_on(struct phy *x)
 	return 0;
 }
 
+static int tegra_p2u_calibrate(struct phy *x)
+{
+	struct tegra_p2u *phy = phy_get_drvdata(x);
+	u32 val;
+
+	val = p2u_readl(phy, P2U_CONTROL_CMN);
+	val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE;
+	p2u_writel(phy, val, P2U_CONTROL_CMN);
+
+	return 0;
+}
+
 static const struct phy_ops ops = {
 	.power_on = tegra_p2u_power_on,
+	.calibrate = tegra_p2u_calibrate,
 	.owner = THIS_MODULE,
 };
 
-- 
2.17.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>,
	<bhelgaas@google.com>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>, <kishon@ti.com>, <vkoul@kernel.org>,
	<mani@kernel.org>, <Sergey.Semin@baikalelectronics.ru>,
	<ffclaire1224@gmail.com>
Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
	<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
	<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH V2 8/9] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration
Date: Mon, 26 Sep 2022 17:20:37 +0530	[thread overview]
Message-ID: <20220926115038.24727-9-vidyas@nvidia.com> (raw)
In-Reply-To: <20220926115038.24727-1-vidyas@nvidia.com>

Set ENABLE_L2_EXIT_RATE_CHANGE to request UPHY PLL rate change to Gen1
during initialization. This helps in the below surprise down cases,
  - Surprise down happens at Gen3/Gen4 link speed
  - Surprise down happens and external REFCLK is cut off which causes
UPHY PLL rate to deviate to an invalid rate

ENABLE_L2_EXIT_RATE_CHANGE needs to be set to bring the UPHY PLL rate
back to Gen1 during controller initialization for the link up.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reported-by: kernel test robot <lkp@intel.com>
---
V2:
* Addressed review comment from test bot and Vinod

 drivers/phy/tegra/phy-tegra194-p2u.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c
index 1415ca71de38..633e6b747275 100644
--- a/drivers/phy/tegra/phy-tegra194-p2u.c
+++ b/drivers/phy/tegra/phy-tegra194-p2u.c
@@ -15,6 +15,7 @@
 #include <linux/phy/phy.h>
 
 #define P2U_CONTROL_CMN			0x74
+#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE		BIT(13)
 #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN			BIT(20)
 
 #define P2U_PERIODIC_EQ_CTRL_GEN3	0xc0
@@ -85,8 +86,21 @@ static int tegra_p2u_power_on(struct phy *x)
 	return 0;
 }
 
+static int tegra_p2u_calibrate(struct phy *x)
+{
+	struct tegra_p2u *phy = phy_get_drvdata(x);
+	u32 val;
+
+	val = p2u_readl(phy, P2U_CONTROL_CMN);
+	val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE;
+	p2u_writel(phy, val, P2U_CONTROL_CMN);
+
+	return 0;
+}
+
 static const struct phy_ops ops = {
 	.power_on = tegra_p2u_power_on,
+	.calibrate = tegra_p2u_calibrate,
 	.owner = THIS_MODULE,
 };
 
-- 
2.17.1


  parent reply	other threads:[~2022-09-26 11:52 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-26 11:50 [PATCH V2 0/9] Enhancements to pcie-tegra194 driver Vidya Sagar
2022-09-26 11:50 ` Vidya Sagar
2022-09-26 11:50 ` [PATCH V2 1/9] PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select" Vidya Sagar
2022-09-26 11:50   ` Vidya Sagar
2022-09-26 11:50 ` [PATCH V2 2/9] PCI: tegra194: Drive CLKREQ signal low explicitly Vidya Sagar
2022-09-26 11:50   ` Vidya Sagar
2022-09-26 11:50 ` [PATCH V2 3/9] PCI: tegra194: Fix polling delay for L2 state Vidya Sagar
2022-09-26 11:50   ` Vidya Sagar
2022-09-26 11:50 ` [PATCH V2 4/9] PCI: tegra194: Handle errors in BPMP response Vidya Sagar
2022-09-26 11:50   ` Vidya Sagar
2022-09-26 11:50 ` [PATCH V2 5/9] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP Vidya Sagar
2022-09-26 11:50   ` Vidya Sagar
2022-09-26 11:50 ` [PATCH V2 6/9] PCI: tegra194: Refactor LTSSM state polling on surprise down Vidya Sagar
2022-09-26 11:50   ` Vidya Sagar
2022-09-26 18:16   ` Bjorn Helgaas
2022-09-26 18:16     ` Bjorn Helgaas
2022-09-26 11:50 ` [PATCH V2 7/9] PCI: tegra194: Disable direct speed change for EP Vidya Sagar
2022-09-26 11:50   ` Vidya Sagar
2022-09-26 11:50 ` Vidya Sagar [this message]
2022-09-26 11:50   ` [PATCH V2 8/9] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration Vidya Sagar
2022-09-26 18:18   ` Bjorn Helgaas
2022-09-26 18:18     ` Bjorn Helgaas
2022-09-26 11:50 ` [PATCH V2 9/9] PCI: tegra194: Calibrate P2U for endpoint mode Vidya Sagar
2022-09-26 11:50   ` Vidya Sagar

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