* [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" @ 2022-09-26 14:09 Dinh Nguyen 2022-09-26 14:09 ` [PATCHv3 2/3] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Dinh Nguyen ` (3 more replies) 0 siblings, 4 replies; 8+ messages in thread From: Dinh Nguyen @ 2022-09-26 14:09 UTC (permalink / raw) To: jh80.chung Cc: dinguyen, ulf.hansson, robh+dt, krzysztof.kozlowski+dt, linux-mmc, linux-kernel, devicetree Document the optional "altr,sysmgr-syscon" binding that is used to access the System Manager register that controls the SDMMC clock phase. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: document that the "altr,sysmgr-syscon" binding is only applicable to "altr,socfpga-dw-mshc" v2: document "altr,sysmgr-syscon" in the MMC section --- .../bindings/mmc/synopsys-dw-mshc.yaml | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml index ae6d6fca79e2..fc7ea20f1d8c 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Mobile Storage Host Controller Binding -allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" - maintainers: - Ulf Hansson <ulf.hansson@linaro.org> @@ -38,6 +35,31 @@ properties: - const: biu - const: ciu + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + description: + Contains the phandle to System Manager block that contains + the SDMMC clock-phase control register. The first value is the pointer + to the sysmgr and the 2nd value is the register offset for the SDMMC + clock phase register. + +allOf: + - $ref: "synopsys-dw-mshc-common.yaml#" + + - if: + properties: + compatible: + contains: + const: + - altr,socfpga-dw-mshc + then: + required: + - altr,sysmgr-syscon + required: - compatible - reg -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCHv3 2/3] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node 2022-09-26 14:09 [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Dinh Nguyen @ 2022-09-26 14:09 ` Dinh Nguyen 2022-09-26 14:09 ` [PATCHv3 3/3] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Dinh Nguyen ` (2 subsequent siblings) 3 siblings, 0 replies; 8+ messages in thread From: Dinh Nguyen @ 2022-09-26 14:09 UTC (permalink / raw) To: jh80.chung Cc: dinguyen, ulf.hansson, robh+dt, krzysztof.kozlowski+dt, linux-mmc, linux-kernel, devicetree The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: removed unnecessary property in "altr,sysmgr-syscon" --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 + arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 + arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 14c220d87807..ff2906672deb 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -309,6 +309,7 @@ mmc: mmc@ff808000 { <&clkmgr STRATIX10_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 48424e459f12..19e7284b4cd5 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -105,6 +105,7 @@ &mmc { cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 7bbec8aafa62..3f694d6fc338 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -313,6 +313,7 @@ mmc: mmc@ff808000 { <&clkmgr AGILEX_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 26cd3c121757..07c3f8876613 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -83,6 +83,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 62c66e52b656..08c088571270 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -74,6 +74,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCHv3 3/3] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase 2022-09-26 14:09 [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Dinh Nguyen 2022-09-26 14:09 ` [PATCHv3 2/3] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Dinh Nguyen @ 2022-09-26 14:09 ` Dinh Nguyen 2022-09-26 15:35 ` [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Krzysztof Kozlowski 2022-09-27 14:39 ` Rob Herring 3 siblings, 0 replies; 8+ messages in thread From: Dinh Nguyen @ 2022-09-26 14:09 UTC (permalink / raw) To: jh80.chung Cc: dinguyen, ulf.hansson, robh+dt, krzysztof.kozlowski+dt, linux-mmc, linux-kernel, devicetree The clock-phase settings for the SDMMC controller in the SoCFPGA Strarix10/Agilex/N5X platforms reside in a register in the System Manager. Add a method to access that register through the syscon interface. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: add space before &socfpga_drv_data v2: simplify clk-phase calculations --- drivers/mmc/host/dw_mmc-pltfm.c | 41 ++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index 9901208be797..0f07fa6d0150 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -17,10 +17,16 @@ #include <linux/mmc/host.h> #include <linux/mmc/mmc.h> #include <linux/of.h> +#include <linux/mfd/altera-sysmgr.h> +#include <linux/regmap.h> #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#define SOCFPGA_DW_MMC_CLK_PHASE_STEP 45 +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0)) + int dw_mci_pltfm_register(struct platform_device *pdev, const struct dw_mci_drv_data *drv_data) { @@ -62,9 +68,42 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = { }; EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); +static int dw_mci_socfpga_priv_init(struct dw_mci *host) +{ + struct device_node *np = host->dev->of_node; + struct regmap *sys_mgr_base_addr; + u32 clk_phase[2] = {0}, reg_offset; + int i, rc, hs_timing; + + rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0); + if (rc) { + sys_mgr_base_addr = + altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); + if (IS_ERR(sys_mgr_base_addr)) { + pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__); + return 1; + } + } else + return 1; + + of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); + + for (i = 0; i < ARRAY_SIZE(clk_phase); i++) + clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP; + + hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); + regmap_write(sys_mgr_base_addr, reg_offset, hs_timing); + + return 0; +} + +static const struct dw_mci_drv_data socfpga_drv_data = { + .init = dw_mci_socfpga_priv_init, +}; + static const struct of_device_id dw_mci_pltfm_match[] = { { .compatible = "snps,dw-mshc", }, - { .compatible = "altr,socfpga-dw-mshc", }, + { .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data, }, { .compatible = "img,pistachio-dw-mshc", }, {}, }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" 2022-09-26 14:09 [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Dinh Nguyen 2022-09-26 14:09 ` [PATCHv3 2/3] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Dinh Nguyen 2022-09-26 14:09 ` [PATCHv3 3/3] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Dinh Nguyen @ 2022-09-26 15:35 ` Krzysztof Kozlowski 2022-09-26 16:49 ` Dinh Nguyen 2022-09-27 14:39 ` Rob Herring 3 siblings, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2022-09-26 15:35 UTC (permalink / raw) To: Dinh Nguyen, jh80.chung Cc: ulf.hansson, robh+dt, krzysztof.kozlowski+dt, linux-mmc, linux-kernel, devicetree On 26/09/2022 16:09, Dinh Nguyen wrote: > +allOf: > + - $ref: "synopsys-dw-mshc-common.yaml#" > + > + - if: > + properties: > + compatible: > + contains: > + const: > + - altr,socfpga-dw-mshc > + then: > + required: > + - altr,sysmgr-syscon else: properties: altr,sysmgr-syscon: false and then you will probably see the warnings leading to error in syntax (const is not an array)... Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" 2022-09-26 15:35 ` [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Krzysztof Kozlowski @ 2022-09-26 16:49 ` Dinh Nguyen 2022-09-27 22:05 ` Rob Herring 0 siblings, 1 reply; 8+ messages in thread From: Dinh Nguyen @ 2022-09-26 16:49 UTC (permalink / raw) To: Krzysztof Kozlowski, jh80.chung Cc: ulf.hansson, robh+dt, krzysztof.kozlowski+dt, linux-mmc, linux-kernel, devicetree On 9/26/22 10:35, Krzysztof Kozlowski wrote: > On 26/09/2022 16:09, Dinh Nguyen wrote: >> +allOf: >> + - $ref: "synopsys-dw-mshc-common.yaml#" >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: >> + - altr,socfpga-dw-mshc >> + then: >> + required: >> + - altr,sysmgr-syscon > > else: > properties: > altr,sysmgr-syscon: false > and then you will probably see the warnings leading to error in syntax > (const is not an array)... > Hmm, okay. I ran dt_binding_check and did not see the warning. I'll check it again. Dinh ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" 2022-09-26 16:49 ` Dinh Nguyen @ 2022-09-27 22:05 ` Rob Herring 0 siblings, 0 replies; 8+ messages in thread From: Rob Herring @ 2022-09-27 22:05 UTC (permalink / raw) To: Dinh Nguyen Cc: Krzysztof Kozlowski, jh80.chung, ulf.hansson, krzysztof.kozlowski+dt, linux-mmc, linux-kernel, devicetree On Mon, Sep 26, 2022 at 11:49 AM Dinh Nguyen <dinguyen@kernel.org> wrote: > > > > On 9/26/22 10:35, Krzysztof Kozlowski wrote: > > On 26/09/2022 16:09, Dinh Nguyen wrote: > >> +allOf: > >> + - $ref: "synopsys-dw-mshc-common.yaml#" > >> + > >> + - if: > >> + properties: > >> + compatible: > >> + contains: > >> + const: > >> + - altr,socfpga-dw-mshc > >> + then: > >> + required: > >> + - altr,sysmgr-syscon > > > > else: > > properties: > > altr,sysmgr-syscon: false > > and then you will probably see the warnings leading to error in syntax > > (const is not an array)... > > > > Hmm, okay. I ran dt_binding_check and did not see the warning. I'll > check it again. Indeed, it does not warn. An array is allowed here as you could have a constant array value. Expect a warning soon though, as I'm working on adding one. Rob ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" 2022-09-26 14:09 [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Dinh Nguyen ` (2 preceding siblings ...) 2022-09-26 15:35 ` [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Krzysztof Kozlowski @ 2022-09-27 14:39 ` Rob Herring 2022-09-28 2:54 ` Dinh Nguyen 3 siblings, 1 reply; 8+ messages in thread From: Rob Herring @ 2022-09-27 14:39 UTC (permalink / raw) To: Dinh Nguyen Cc: krzysztof.kozlowski+dt, devicetree, linux-kernel, ulf.hansson, jh80.chung, linux-mmc, robh+dt On Mon, 26 Sep 2022 09:09:30 -0500, Dinh Nguyen wrote: > Document the optional "altr,sysmgr-syscon" binding that is used to > access the System Manager register that controls the SDMMC clock > phase. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- > v3: document that the "altr,sysmgr-syscon" binding is only applicable to > "altr,socfpga-dw-mshc" > v2: document "altr,sysmgr-syscon" in the MMC section > --- > .../bindings/mmc/synopsys-dw-mshc.yaml | 28 +++++++++++++++++-- > 1 file changed, 25 insertions(+), 3 deletions(-) > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/ dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match '^mmc(@.*)?$' arch/arm/boot/dts/socfpga_arria5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb arch/arm/boot/dts/socfpga_vt.dtb dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'cd-gpios', 'fifo-depth', 'resets', 'vmmc-supply', 'vqmmc-supply' were unexpected) arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets', 'vmmc-supply', 'vqmmc-supply' were unexpected) arch/arm/boot/dts/socfpga_arria5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb arch/arm/boot/dts/socfpga_vt.dtb dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$' arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb mmc@ff808000: Unevaluated properties are not allowed ('altr,dw-mshc-ciu-div', 'altr,dw-mshc-sdr-timing', 'iommus' were unexpected) arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dtb mmc@ff808000: Unevaluated properties are not allowed ('iommus' was unexpected) arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dtb arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dtb arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dtb arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dtb mmcsd@40004000: $nodename:0: 'mmcsd@40004000' does not match '^mmc(@.*)?$' arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: clock-names:0: 'biu' was expected arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: clock-names:1: 'ciu' was expected arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: Unevaluated properties are not allowed ('bus-width', 'clock-names', 'resets', 'vmmc-supply' were unexpected) arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: Unevaluated properties are not allowed ('clock-names', 'resets' were unexpected) arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" 2022-09-27 14:39 ` Rob Herring @ 2022-09-28 2:54 ` Dinh Nguyen 0 siblings, 0 replies; 8+ messages in thread From: Dinh Nguyen @ 2022-09-28 2:54 UTC (permalink / raw) To: Rob Herring Cc: krzysztof.kozlowski+dt, devicetree, linux-kernel, ulf.hansson, jh80.chung, linux-mmc, robh+dt Hi Rob, On 9/27/22 09:39, Rob Herring wrote: > On Mon, 26 Sep 2022 09:09:30 -0500, Dinh Nguyen wrote: >> Document the optional "altr,sysmgr-syscon" binding that is used to >> access the System Manager register that controls the SDMMC clock >> phase. >> >> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: document >> that the "altr,sysmgr-syscon" binding is only applicable to >> "altr,socfpga-dw-mshc" v2: document "altr,sysmgr-syscon" in the MMC >> section --- .../bindings/mmc/synopsys-dw-mshc.yaml | 28 >> +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 >> deletions(-) >> > > Running 'make dtbs_check' with the schema in this patch gives the > following warnings. Consider if they are expected or the schema is > incorrect. These may not be new warnings. > > Note that it is not yet a requirement to have 0 warnings for > dtbs_check. This will change in the future. > > Full log is available here: https://patchwork.ozlabs.org/patch/ > > > dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match > '^mmc(@.*)?$' arch/arm/boot/dts/socfpga_arria5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb > arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb > arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb > arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb > arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb > arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb > arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb > arch/arm/boot/dts/socfpga_vt.dtb > > dwmmc0@ff704000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', > 'cap-mmc-highspeed', 'cap-sd-highspeed', 'cd-gpios', 'fifo-depth', > 'resets', 'vmmc-supply', 'vqmmc-supply' were unexpected) > arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb > > dwmmc0@ff704000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', > 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets', > 'vmmc-supply', 'vqmmc-supply' were unexpected) > arch/arm/boot/dts/socfpga_arria5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb > arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb > arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb > > dwmmc0@ff704000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', > 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were > unexpected) arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb > arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb > arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb > arch/arm/boot/dts/socfpga_vt.dtb > > dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match > '^mmc(@.*)?$' arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb > arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb > arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb > arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb > > dwmmc0@ff808000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', > 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were > unexpected) arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb > > dwmmc0@ff808000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', > 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected) > arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb > > dwmmc0@ff808000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'fifo-depth', 'resets' were > unexpected) arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb > arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb > > mmc@ff808000: Unevaluated properties are not allowed > ('altr,dw-mshc-ciu-div', 'altr,dw-mshc-sdr-timing', 'iommus' were > unexpected) arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dtb > > mmc@ff808000: Unevaluated properties are not allowed ('iommus' was > unexpected) arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb > arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dtb > arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dtb > arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb > arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dtb > arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dtb > > mmcsd@40004000: $nodename:0: 'mmcsd@40004000' does not match > '^mmc(@.*)?$' arch/arm/boot/dts/lpc4337-ciaa.dtb > arch/arm/boot/dts/lpc4350-hitex-eval.dtb > arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb > arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb > > mmcsd@40004000: clock-names:0: 'biu' was expected > arch/arm/boot/dts/lpc4337-ciaa.dtb > arch/arm/boot/dts/lpc4350-hitex-eval.dtb > arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb > arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb > > mmcsd@40004000: clock-names:1: 'ciu' was expected > arch/arm/boot/dts/lpc4337-ciaa.dtb > arch/arm/boot/dts/lpc4350-hitex-eval.dtb > arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb > arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb > > mmcsd@40004000: Unevaluated properties are not allowed ('bus-width', > 'clock-names', 'resets', 'vmmc-supply' were unexpected) > arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb > arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb > > mmcsd@40004000: Unevaluated properties are not allowed > ('clock-names', 'resets' were unexpected) > arch/arm/boot/dts/lpc4337-ciaa.dtb > arch/arm/boot/dts/lpc4350-hitex-eval.dtb > Hmm, I see these warnings on the standard v6.0-rc1 and linux-next(next-20220923), but with this patch applied I don't see any warnings regarding MMC. DTC arch/arm/boot/dts/socfpga_arria5_socdk.dtb DTC arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb DTC arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb DTC arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb CHECK arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb CHECK arch/arm/boot/dts/socfpga_arria5_socdk.dtb CHECK arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb CHECK arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: pmu@ff111000: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: /home/dinguyen/linux_dev/linux/Documentation/devicetree/bindings/arm/pmu.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: soc: amba: {'compatible': ['simple-bus'], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': True, 'pdma@ffda1000': {'compatible': ['arm,pl330', 'arm,primecell'], 'reg': [[4292481024, 4096]], 'interrupts': [[0, 83, 4], [0, 84, 4], [0, 85, 4], [0, 86, 4], [0, 87, 4], [0, 88, 4], [0, 89, 4], [0, 90, 4], [0, 91, 4]], '#dma-cells': [[1]], 'clocks': [[5]], 'clock-names': ['apb_pclk'], 'resets': [[6, 48], [6, 53]], 'reset-names': ['dma', 'dma-ocp'], 'phandle': [[34]]}} should not be valid under {'type': 'object'} From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: soc: base_fpga_region: {'#address-cells': [[1]], '#size-cells': [[1]], 'compatible': ['fpga-region'], 'fpga-mgr': [[7]]} should not be valid under {'type': 'object'} From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: soc: stmmac-axi-config: {'snps,wr_osr_lmt': [[15]], 'snps,rd_osr_lmt': [[15]], 'snps,blen': [[0, 0, 0, 0, 16, 0, 0]], 'phandle': [[30]]} should not be valid under {'type': 'object'} From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: soc: eccmgr: {'compatible': ['altr,socfpga-a10-ecc-manager'], 'altr,sysmgr-syscon': [[28]], '#address-cells': [[1]], '#size-cells': [[1]], 'interrupts': [[0, 2, 4], [0, 0, 4]], 'interrupt-controller': True, '#interrupt-cells': [[2]], 'ranges': True, 'sdramedac': {'compatible': ['altr,sdram-edac-a10'], 'altr,sdr-syscon': [[39]], 'interrupts': [[17, 4], [49, 4]]}, 'l2-ecc@ffd06010': {'compatible': ['altr,socfpga-a10-l2-ecc'], 'reg': [[4291846160, 4]], 'interrupts': [[0, 4], [32, 4]]}, 'ocram-ecc@ff8c3000': {'compatible': ['altr,socfpga-a10-ocram-ecc'], 'reg': [[4287377408, 1024]], 'interrupts': [[1, 4], [33, 4]]}, 'emac0-rx-ecc@ff8c0800': {'compatible': ['altr,socfpga-eth-mac-ecc'], 'reg': [[4287367168, 1024]], 'altr,ecc-parent': [[40]], 'interrupts': [[4, 4], [36, 4]]}, 'emac0-tx-ecc@ff8c0c00': {'compatible': ['altr,socfpga-eth-mac-ecc'], 'reg': [[4287368192, 1024]], 'altr,ecc-parent': [[40]], 'interrupts': [[5, 4], [37, 4]]}, 'sdmmca-ecc@ff8c2c00': {'compatible': ['altr,socfpga-sdmmc-ecc'], 'reg': [[4287376384, 1024]], 'altr,ecc-parent': [[41]], 'interrupts': [[15, 4], [47, 4], [16, 4], [48, 4]]}, 'dma-ecc@ff8c8000': {'compatible': ['altr,socfpga-dma-ecc'], 'reg': [[4287397888, 1024]], 'altr,ecc-parent': [[34]], 'interrupts': [[10, 4], [42, 4]]}, 'usb0-ecc@ff8c8800': {'compatible': ['altr,socfpga-usb-ecc'], 'reg': [[4287399936, 1024]], 'altr,ecc-parent': [[42]], 'interrupts': [[2, 4], [34, 4]]}} should not be valid under {'type': 'object'} From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: soc: usbphy: {'#phy-cells': [[0]], 'compatible': ['usb-nop-xceiv'], 'status': ['okay'], 'phandle': [[47]]} should not be valid under {'type': 'object'} From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: amba: $nodename:0: 'amba' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: pdma@ffda1000: $nodename:0: 'pdma@ffda1000' does not match '^dma-controller(@.*)?$' From schema: /home/dinguyen/linux_dev/linux/Documentation/devicetree/bindings/dma/arm,pl330.yaml Dinh ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-09-28 2:54 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-09-26 14:09 [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Dinh Nguyen 2022-09-26 14:09 ` [PATCHv3 2/3] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Dinh Nguyen 2022-09-26 14:09 ` [PATCHv3 3/3] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Dinh Nguyen 2022-09-26 15:35 ` [PATCHv3 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Krzysztof Kozlowski 2022-09-26 16:49 ` Dinh Nguyen 2022-09-27 22:05 ` Rob Herring 2022-09-27 14:39 ` Rob Herring 2022-09-28 2:54 ` Dinh Nguyen
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