[PATCH v6 0/3] Initial Meteorlake Support

[PATCH v6 0/3] Initial Meteorlake Support

[Radhakrishna Sripada]

The PCI Id's and platform definition are posted earlier.
Handful of early enablement patches including support for
display power wells, VBT and AUX Channel mapping, PCH and
gmbus support, dbus, mbus, sagv and memory bandwidth support
got merged.

This series adds the support for a new way to read Graphics,
Media and Display versions, the way to read stepping info and
engine context layouts.

This is based out of the earlier series posted at [1]. Several
of the patches from the earlier series got merged. This version is
rebased on top of the earlier patches that got merged.

[1] https://patchwork.freedesktop.org/series/106786/



José Roberto de Souza (1):
  drm/i915: Parse and set stepping for platforms with GMD

Matt Roper (2):
  drm/i915: Read graphics/media/display arch version from hw
  drm/i915/mtl: Define engine context layouts

 drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 +
 drivers/gpu/drm/i915/gt/intel_lrc.c      | 84 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_driver.c       |  3 +-
 drivers/gpu/drm/i915/i915_drv.h          |  2 +
 drivers/gpu/drm/i915/i915_pci.c          |  1 +
 drivers/gpu/drm/i915/i915_reg.h          |  7 ++
 drivers/gpu/drm/i915/intel_device_info.c | 67 ++++++++++++++++++-
 drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
 drivers/gpu/drm/i915/intel_step.c        | 25 +++++++
 drivers/gpu/drm/i915/intel_step.h        | 24 ++++++-
 10 files changed, 221 insertions(+), 6 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH v6 0/3] Initial Meteorlake Support

[Radhakrishna Sripada]

The PCI Id's and platform definition are posted earlier.
Handful of early enablement patches including support for
display power wells, VBT and AUX Channel mapping, PCH and
gmbus support, dbus, mbus, sagv and memory bandwidth support
got merged.

This series adds the support for a new way to read Graphics,
Media and Display versions, the way to read stepping info and
engine context layouts.

This is based out of the earlier series posted at [1]. Several
of the patches from the earlier series got merged. This version is
rebased on top of the earlier patches that got merged.

[1] https://patchwork.freedesktop.org/series/106786/



José Roberto de Souza (1):
  drm/i915: Parse and set stepping for platforms with GMD

Matt Roper (2):
  drm/i915: Read graphics/media/display arch version from hw
  drm/i915/mtl: Define engine context layouts

 drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 +
 drivers/gpu/drm/i915/gt/intel_lrc.c      | 84 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_driver.c       |  3 +-
 drivers/gpu/drm/i915/i915_drv.h          |  2 +
 drivers/gpu/drm/i915/i915_pci.c          |  1 +
 drivers/gpu/drm/i915/i915_reg.h          |  7 ++
 drivers/gpu/drm/i915/intel_device_info.c | 67 ++++++++++++++++++-
 drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
 drivers/gpu/drm/i915/intel_step.c        | 25 +++++++
 drivers/gpu/drm/i915/intel_step.h        | 24 ++++++-
 10 files changed, 221 insertions(+), 6 deletions(-)

-- 
2.34.1

[PATCH v6 1/3] drm/i915: Read graphics/media/display arch version from hw

[Radhakrishna Sripada]

From: Matt Roper <matthew.d.roper@intel.com>

Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be read
directly from a register in the MMIO space.  New hardware programming
styles, features, and workarounds should be conditional solely on the
architecture version, and should no longer be derived from the PCI
device ID, revision ID, or platform-specific feature flags.

Bspec: 63361, 64111

v2:
  - Move the IP version readout to intel_device_info.c
  - Convert the macro into a function

v3:
  - Move subplatform init to runtime early init
  - Cache runtime ver, release info to compare with hardware values.
  - Use IP_VER for snaity check(MattR)

v4:
  - Minor doccumentation changes.
  - Normalize HAS_GMD_ID macro value.(JaniN)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 +
 drivers/gpu/drm/i915/i915_driver.c       |  3 +-
 drivers/gpu/drm/i915/i915_drv.h          |  2 +
 drivers/gpu/drm/i915/i915_pci.c          |  1 +
 drivers/gpu/drm/i915/i915_reg.h          |  7 +++
 drivers/gpu/drm/i915/intel_device_info.c | 67 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_device_info.h | 12 ++++-
 7 files changed, 91 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 2275ee47da95..2d2044f2ed9d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -39,6 +39,8 @@
 #define FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0xd84)
 #define FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0xd88)
 
+#define GMD_ID_GRAPHICS				_MMIO(0xd8c)
+
 #define MCFG_MCR_SELECTOR			_MMIO(0xfd0)
 #define SF_MCR_SELECTOR				_MMIO(0xfd8)
 #define GEN8_MCR_SELECTOR			_MMIO(0xfdc)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index c459eb362c47..e86798eaecb6 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -337,7 +337,8 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 	if (i915_inject_probe_failure(dev_priv))
 		return -ENODEV;
 
-	intel_device_info_subplatform_init(dev_priv);
+	intel_device_info_runtime_init_early(dev_priv);
+
 	intel_step_init(dev_priv);
 
 	intel_uncore_mmio_debug_init_early(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9f9372931fd2..7034ea848d65 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -940,6 +940,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
 
+#define HAS_GMD_ID(i915)	(INTEL_INFO(i915)->has_gmd_id)
+
 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
 
 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 77e7df21f539..cace897e1db1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1143,6 +1143,7 @@ static const struct intel_device_info mtl_info = {
 	.display.has_modular_fia = 1,
 	.extra_gt_list = xelpmp_extra_gt,
 	.has_flat_ccs = 0,
+	.has_gmd_id = 1,
 	.has_snoop = 1,
 	.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a9bd829fc7e..acfcd155c8d0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5839,6 +5839,11 @@
 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)
 
+#define GMD_ID_DISPLAY				_MMIO(0x510a0)
+#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
+#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
+#define   GMD_ID_STEP				REG_GENMASK(5, 0)
+
 /*GEN11 chicken */
 #define _PIPEA_CHICKEN				0x70038
 #define _PIPEB_CHICKEN				0x71038
@@ -8356,4 +8361,6 @@ enum skl_power_gate {
 #define   MTL_TRAS_MASK			REG_GENMASK(16, 8)
 #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
 
+#define MTL_MEDIA_GSI_BASE		0x380000
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 1434dc33cf49..3464de801b67 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -29,6 +29,7 @@
 
 #include "display/intel_cdclk.h"
 #include "display/intel_de.h"
+#include "gt/intel_gt_regs.h"
 #include "intel_device_info.h"
 #include "i915_drv.h"
 #include "i915_utils.h"
@@ -231,7 +232,7 @@ static bool find_devid(u16 id, const u16 *p, unsigned int num)
 	return false;
 }
 
-void intel_device_info_subplatform_init(struct drm_i915_private *i915)
+static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 {
 	const struct intel_device_info *info = INTEL_INFO(i915);
 	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
@@ -288,6 +289,70 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
 }
 
+static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct ip_version *ip)
+{
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	void __iomem *addr;
+	u32 val;
+	u8 ver = ip->ver;
+	u8 rel = ip->rel;
+
+	addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
+	if (drm_WARN_ON(&i915->drm, !addr))
+		return;
+
+	val = ioread32(addr);
+	pci_iounmap(pdev, addr);
+
+	ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
+	ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
+	ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
+
+	/* Sanity check against expected versions from device info */
+	if (IP_VER(ip->ver, ip->rel) < IP_VER(ver, rel))
+		drm_dbg(&i915->drm,
+			"Hardware reports GMD IP version %u.%u but minimum expected is %u.%u\n",
+			ip->ver, ip->rel, ver, rel);
+}
+
+/*
+ * Setup the graphics version for the current device.  This must be done before
+ * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
+ * function should be called very early in the driver initialization sequence.
+ *
+ * Regular MMIO access is not yet setup at the point this function is called so
+ * we peek at the appropriate MMIO offset directly.  The GMD_ID register is
+ * part of an 'always on' power well by design, so we don't need to worry about
+ * forcewake while reading it.
+ */
+static void intel_ipver_early_init(struct drm_i915_private *i915)
+{
+	struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
+
+	if (!HAS_GMD_ID(i915))
+		return;
+
+	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
+		    &runtime->graphics.ip);
+	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
+		    &runtime->display.ip);
+	ip_ver_read(i915, MTL_MEDIA_GSI_BASE + i915_mmio_reg_offset(GMD_ID_GRAPHICS),
+		    &runtime->media.ip);
+}
+
+/**
+ * intel_device_info_runtime_init_early - initialize early runtime info
+ * @i915: the i915 device
+ *
+ * Determine early intel_device_info fields at runtime. This function needs
+ * to be called before the MMIO has been setup.
+ */
+void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
+{
+	intel_ipver_early_init(i915);
+	intel_device_info_subplatform_init(i915);
+}
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @dev_priv: the i915 device
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 09b18910d3ab..e3aa88d33d63 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
 	func(has_4tile); \
 	func(has_flat_ccs); \
 	func(has_global_mocs); \
+	func(has_gmd_id); \
 	func(has_gt_uc); \
 	func(has_heci_pxp); \
 	func(has_heci_gscfi); \
@@ -198,9 +199,18 @@ enum intel_ppgtt_type {
 struct ip_version {
 	u8 ver;
 	u8 rel;
+	u8 step;
 };
 
 struct intel_runtime_info {
+	/*
+	 * On modern platforms, the architecture major.minor version numbers
+	 * and stepping are read directly from the hardware rather than derived
+	 * from the PCI device and revision ID's.
+	 *
+	 * Note that the hardware gives us a single "graphics" number that
+	 * should represent render, compute, and copy behavior.
+	 */
 	struct {
 		struct ip_version ip;
 	} graphics;
@@ -309,7 +319,7 @@ struct intel_driver_caps {
 
 const char *intel_platform_name(enum intel_platform platform);
 
-void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
+void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);
 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
 
 void intel_device_info_print(const struct intel_device_info *info,
-- 
2.34.1

[Intel-gfx] [PATCH v6 1/3] drm/i915: Read graphics/media/display arch version from hw

[Radhakrishna Sripada]

From: Matt Roper <matthew.d.roper@intel.com>

Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be read
directly from a register in the MMIO space.  New hardware programming
styles, features, and workarounds should be conditional solely on the
architecture version, and should no longer be derived from the PCI
device ID, revision ID, or platform-specific feature flags.

Bspec: 63361, 64111

v2:
  - Move the IP version readout to intel_device_info.c
  - Convert the macro into a function

v3:
  - Move subplatform init to runtime early init
  - Cache runtime ver, release info to compare with hardware values.
  - Use IP_VER for snaity check(MattR)

v4:
  - Minor doccumentation changes.
  - Normalize HAS_GMD_ID macro value.(JaniN)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 +
 drivers/gpu/drm/i915/i915_driver.c       |  3 +-
 drivers/gpu/drm/i915/i915_drv.h          |  2 +
 drivers/gpu/drm/i915/i915_pci.c          |  1 +
 drivers/gpu/drm/i915/i915_reg.h          |  7 +++
 drivers/gpu/drm/i915/intel_device_info.c | 67 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_device_info.h | 12 ++++-
 7 files changed, 91 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 2275ee47da95..2d2044f2ed9d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -39,6 +39,8 @@
 #define FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0xd84)
 #define FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0xd88)
 
+#define GMD_ID_GRAPHICS				_MMIO(0xd8c)
+
 #define MCFG_MCR_SELECTOR			_MMIO(0xfd0)
 #define SF_MCR_SELECTOR				_MMIO(0xfd8)
 #define GEN8_MCR_SELECTOR			_MMIO(0xfdc)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index c459eb362c47..e86798eaecb6 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -337,7 +337,8 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 	if (i915_inject_probe_failure(dev_priv))
 		return -ENODEV;
 
-	intel_device_info_subplatform_init(dev_priv);
+	intel_device_info_runtime_init_early(dev_priv);
+
 	intel_step_init(dev_priv);
 
 	intel_uncore_mmio_debug_init_early(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9f9372931fd2..7034ea848d65 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -940,6 +940,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
 
+#define HAS_GMD_ID(i915)	(INTEL_INFO(i915)->has_gmd_id)
+
 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
 
 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 77e7df21f539..cace897e1db1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1143,6 +1143,7 @@ static const struct intel_device_info mtl_info = {
 	.display.has_modular_fia = 1,
 	.extra_gt_list = xelpmp_extra_gt,
 	.has_flat_ccs = 0,
+	.has_gmd_id = 1,
 	.has_snoop = 1,
 	.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a9bd829fc7e..acfcd155c8d0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5839,6 +5839,11 @@
 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)
 
+#define GMD_ID_DISPLAY				_MMIO(0x510a0)
+#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
+#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
+#define   GMD_ID_STEP				REG_GENMASK(5, 0)
+
 /*GEN11 chicken */
 #define _PIPEA_CHICKEN				0x70038
 #define _PIPEB_CHICKEN				0x71038
@@ -8356,4 +8361,6 @@ enum skl_power_gate {
 #define   MTL_TRAS_MASK			REG_GENMASK(16, 8)
 #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
 
+#define MTL_MEDIA_GSI_BASE		0x380000
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 1434dc33cf49..3464de801b67 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -29,6 +29,7 @@
 
 #include "display/intel_cdclk.h"
 #include "display/intel_de.h"
+#include "gt/intel_gt_regs.h"
 #include "intel_device_info.h"
 #include "i915_drv.h"
 #include "i915_utils.h"
@@ -231,7 +232,7 @@ static bool find_devid(u16 id, const u16 *p, unsigned int num)
 	return false;
 }
 
-void intel_device_info_subplatform_init(struct drm_i915_private *i915)
+static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 {
 	const struct intel_device_info *info = INTEL_INFO(i915);
 	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
@@ -288,6 +289,70 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
 }
 
+static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct ip_version *ip)
+{
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	void __iomem *addr;
+	u32 val;
+	u8 ver = ip->ver;
+	u8 rel = ip->rel;
+
+	addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
+	if (drm_WARN_ON(&i915->drm, !addr))
+		return;
+
+	val = ioread32(addr);
+	pci_iounmap(pdev, addr);
+
+	ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
+	ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
+	ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
+
+	/* Sanity check against expected versions from device info */
+	if (IP_VER(ip->ver, ip->rel) < IP_VER(ver, rel))
+		drm_dbg(&i915->drm,
+			"Hardware reports GMD IP version %u.%u but minimum expected is %u.%u\n",
+			ip->ver, ip->rel, ver, rel);
+}
+
+/*
+ * Setup the graphics version for the current device.  This must be done before
+ * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
+ * function should be called very early in the driver initialization sequence.
+ *
+ * Regular MMIO access is not yet setup at the point this function is called so
+ * we peek at the appropriate MMIO offset directly.  The GMD_ID register is
+ * part of an 'always on' power well by design, so we don't need to worry about
+ * forcewake while reading it.
+ */
+static void intel_ipver_early_init(struct drm_i915_private *i915)
+{
+	struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
+
+	if (!HAS_GMD_ID(i915))
+		return;
+
+	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
+		    &runtime->graphics.ip);
+	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
+		    &runtime->display.ip);
+	ip_ver_read(i915, MTL_MEDIA_GSI_BASE + i915_mmio_reg_offset(GMD_ID_GRAPHICS),
+		    &runtime->media.ip);
+}
+
+/**
+ * intel_device_info_runtime_init_early - initialize early runtime info
+ * @i915: the i915 device
+ *
+ * Determine early intel_device_info fields at runtime. This function needs
+ * to be called before the MMIO has been setup.
+ */
+void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
+{
+	intel_ipver_early_init(i915);
+	intel_device_info_subplatform_init(i915);
+}
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @dev_priv: the i915 device
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 09b18910d3ab..e3aa88d33d63 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
 	func(has_4tile); \
 	func(has_flat_ccs); \
 	func(has_global_mocs); \
+	func(has_gmd_id); \
 	func(has_gt_uc); \
 	func(has_heci_pxp); \
 	func(has_heci_gscfi); \
@@ -198,9 +199,18 @@ enum intel_ppgtt_type {
 struct ip_version {
 	u8 ver;
 	u8 rel;
+	u8 step;
 };
 
 struct intel_runtime_info {
+	/*
+	 * On modern platforms, the architecture major.minor version numbers
+	 * and stepping are read directly from the hardware rather than derived
+	 * from the PCI device and revision ID's.
+	 *
+	 * Note that the hardware gives us a single "graphics" number that
+	 * should represent render, compute, and copy behavior.
+	 */
 	struct {
 		struct ip_version ip;
 	} graphics;
@@ -309,7 +319,7 @@ struct intel_driver_caps {
 
 const char *intel_platform_name(enum intel_platform platform);
 
-void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
+void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);
 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
 
 void intel_device_info_print(const struct intel_device_info *info,
-- 
2.34.1

Re: [Intel-gfx] [PATCH v6 1/3] drm/i915: Read graphics/media/display arch version from hw

[Lucas De Marchi]

On Thu, Sep 15, 2022 at 06:46:46PM -0700, Radhakrishna Sripada wrote:
>From: Matt Roper <matthew.d.roper@intel.com>
>
>Going forward, the hardware teams no longer consider new platforms to
>have a "generation" in the way we've defined it for past platforms.
>Instead, each IP block (graphics, media, display) will have their own
>architecture major.minor versions and stepping ID's which should be read
>directly from a register in the MMIO space.  New hardware programming
>styles, features, and workarounds should be conditional solely on the
>architecture version, and should no longer be derived from the PCI
>device ID, revision ID, or platform-specific feature flags.

I'd just remove "New hardware programming ..." until the end, because:

1) Binding to the device will always happen by using the PCI ID.
2) I don't see us moving away from grouping them per-platform.
3) Flags may still be convenient to convey paths to take in the software
regardless of what the hardware provides.

Basically there is a new way to read the individual IP versions: we
didn't have that before and we were just hardcoding the info per
platform. And the new scheme for reading the stepping replaces what we
were reading before from PCI config space.


>
>Bspec: 63361, 64111
>
>v2:
>  - Move the IP version readout to intel_device_info.c
>  - Convert the macro into a function
>
>v3:
>  - Move subplatform init to runtime early init
>  - Cache runtime ver, release info to compare with hardware values.
>  - Use IP_VER for snaity check(MattR)
>
>v4:
>  - Minor doccumentation changes.
>  - Normalize HAS_GMD_ID macro value.(JaniN)
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 +
> drivers/gpu/drm/i915/i915_driver.c       |  3 +-
> drivers/gpu/drm/i915/i915_drv.h          |  2 +
> drivers/gpu/drm/i915/i915_pci.c          |  1 +
> drivers/gpu/drm/i915/i915_reg.h          |  7 +++
> drivers/gpu/drm/i915/intel_device_info.c | 67 +++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_device_info.h | 12 ++++-
> 7 files changed, 91 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>index 2275ee47da95..2d2044f2ed9d 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>@@ -39,6 +39,8 @@
> #define FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0xd84)
> #define FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0xd88)
>
>+#define GMD_ID_GRAPHICS				_MMIO(0xd8c)
>+
> #define MCFG_MCR_SELECTOR			_MMIO(0xfd0)
> #define SF_MCR_SELECTOR				_MMIO(0xfd8)
> #define GEN8_MCR_SELECTOR			_MMIO(0xfdc)
>diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
>index c459eb362c47..e86798eaecb6 100644
>--- a/drivers/gpu/drm/i915/i915_driver.c
>+++ b/drivers/gpu/drm/i915/i915_driver.c
>@@ -337,7 +337,8 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> 	if (i915_inject_probe_failure(dev_priv))
> 		return -ENODEV;
>
>-	intel_device_info_subplatform_init(dev_priv);
>+	intel_device_info_runtime_init_early(dev_priv);
>+
> 	intel_step_init(dev_priv);
>
> 	intel_uncore_mmio_debug_init_early(dev_priv);
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 9f9372931fd2..7034ea848d65 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -940,6 +940,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
>
>+#define HAS_GMD_ID(i915)	(INTEL_INFO(i915)->has_gmd_id)
>+
> #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
>
> #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index 77e7df21f539..cace897e1db1 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -1143,6 +1143,7 @@ static const struct intel_device_info mtl_info = {
> 	.display.has_modular_fia = 1,
> 	.extra_gt_list = xelpmp_extra_gt,
> 	.has_flat_ccs = 0,
>+	.has_gmd_id = 1,

heh... this basically proves what I just said above ;)

> 	.has_snoop = 1,
> 	.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 1a9bd829fc7e..acfcd155c8d0 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -5839,6 +5839,11 @@
> #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
> #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)
>
>+#define GMD_ID_DISPLAY				_MMIO(0x510a0)
>+#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
>+#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
>+#define   GMD_ID_STEP				REG_GENMASK(5, 0)
>+
> /*GEN11 chicken */
> #define _PIPEA_CHICKEN				0x70038
> #define _PIPEB_CHICKEN				0x71038
>@@ -8356,4 +8361,6 @@ enum skl_power_gate {
> #define   MTL_TRAS_MASK			REG_GENMASK(16, 8)
> #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
>
>+#define MTL_MEDIA_GSI_BASE		0x380000
>+
> #endif /* _I915_REG_H_ */
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>index 1434dc33cf49..3464de801b67 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -29,6 +29,7 @@
>
> #include "display/intel_cdclk.h"
> #include "display/intel_de.h"
>+#include "gt/intel_gt_regs.h"
> #include "intel_device_info.h"
> #include "i915_drv.h"
> #include "i915_utils.h"
>@@ -231,7 +232,7 @@ static bool find_devid(u16 id, const u16 *p, unsigned int num)
> 	return false;
> }
>
>-void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>+static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> {
> 	const struct intel_device_info *info = INTEL_INFO(i915);
> 	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
>@@ -288,6 +289,70 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> 	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
> }
>
>+static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct ip_version *ip)
>+{
>+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>+	void __iomem *addr;
>+	u32 val;
>+	u8 ver = ip->ver;
>+	u8 rel = ip->rel;

s/ver/expected_ver/
s/rel/expected_rel/

>+
>+	addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
>+	if (drm_WARN_ON(&i915->drm, !addr))
>+		return;
>+
>+	val = ioread32(addr);
>+	pci_iounmap(pdev, addr);
>+
>+	ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
>+	ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
>+	ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
>+
>+	/* Sanity check against expected versions from device info */
>+	if (IP_VER(ip->ver, ip->rel) < IP_VER(ver, rel))
>+		drm_dbg(&i915->drm,
>+			"Hardware reports GMD IP version %u.%u but minimum expected is %u.%u\n",
>+			ip->ver, ip->rel, ver, rel);

slightly more useful if it says what register this is about so we know
if it's graphics, media or display

		drm_dbg(&i915->drm,
			"Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n",
			ip->ver, ip->rel, offset, val, expected_ver, expected_rel);

>+}
>+
>+/*
>+ * Setup the graphics version for the current device.  This must be done before
>+ * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
>+ * function should be called very early in the driver initialization sequence.
>+ *
>+ * Regular MMIO access is not yet setup at the point this function is called so
>+ * we peek at the appropriate MMIO offset directly.  The GMD_ID register is
>+ * part of an 'always on' power well by design, so we don't need to worry about
>+ * forcewake while reading it.
>+ */
>+static void intel_ipver_early_init(struct drm_i915_private *i915)
>+{
>+	struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
>+
>+	if (!HAS_GMD_ID(i915))
>+		return;
>+
>+	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
>+		    &runtime->graphics.ip);
>+	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
>+		    &runtime->display.ip);
>+	ip_ver_read(i915, MTL_MEDIA_GSI_BASE + i915_mmio_reg_offset(GMD_ID_GRAPHICS),

this belongs to a GMD_ID_MEDIA macro?

#define GMD_ID_MEDIA	(MTL_MEDIA_GSI_BASE + 0xd8c)

>+		    &runtime->media.ip);
>+}
>+
>+/**
>+ * intel_device_info_runtime_init_early - initialize early runtime info
>+ * @i915: the i915 device
>+ *
>+ * Determine early intel_device_info fields at runtime. This function needs
>+ * to be called before the MMIO has been setup.
>+ */
>+void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
>+{
>+	intel_ipver_early_init(i915);
>+	intel_device_info_subplatform_init(i915);
>+}
>+
> /**
>  * intel_device_info_runtime_init - initialize runtime info
>  * @dev_priv: the i915 device
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>index 09b18910d3ab..e3aa88d33d63 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
> 	func(has_4tile); \
> 	func(has_flat_ccs); \
> 	func(has_global_mocs); \
>+	func(has_gmd_id); \
> 	func(has_gt_uc); \
> 	func(has_heci_pxp); \
> 	func(has_heci_gscfi); \
>@@ -198,9 +199,18 @@ enum intel_ppgtt_type {
> struct ip_version {
> 	u8 ver;
> 	u8 rel;
>+	u8 step;
> };
>
> struct intel_runtime_info {
>+	/*
>+	 * On modern platforms, the architecture major.minor version numbers
>+	 * and stepping are read directly from the hardware rather than derived
>+	 * from the PCI device and revision ID's.
>+	 *
>+	 * Note that the hardware gives us a single "graphics" number that
>+	 * should represent render, compute, and copy behavior.
>+	 */

humn... "modern" doesn't read nice a few months/years from now. This is
already in the intel_runtime_info so it's expected that it's not
hardcoded somewhere in the ro data

I'd just make this paragrapho read like:

	/*
	 * Single "graphics" IP version that represents
	 * render, compute, and copy behavior.
	 */


A few nits above, but this is in general good to me. Feel free
to add  Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

> 	struct {
> 		struct ip_version ip;
> 	} graphics;
>@@ -309,7 +319,7 @@ struct intel_driver_caps {
>
> const char *intel_platform_name(enum intel_platform platform);
>
>-void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
>+void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);
> void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
>
> void intel_device_info_print(const struct intel_device_info *info,
>-- 
>2.34.1
>

[PATCH v6 2/3] drm/i915: Parse and set stepping for platforms with GMD

[Radhakrishna Sripada]

From: José Roberto de Souza <jose.souza@intel.com>

Expand the current stepping convention to accommodate the GMD
stepping info. Typically GMD step maps to letter stepping
by "A + step %4" and number to "A + step /4" i.e, GMD step
0 maps to STEP_A0, 1 to _A1, 2 to _A2, 3 to _A3, 4 to STEP_B0...

Future platforms might break this formulae and may require a table
mapping to decode GMD step compatible with the convention.

v2:
 - Pass the updated ip version structure
v3:
 - Skip using GMD to step table(MattR)

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_step.c | 25 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_step.h | 24 +++++++++++++++++++++++-
 2 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 42b3133d8387..91e7c51991b0 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -135,6 +135,19 @@ static const struct intel_step_info adlp_n_revids[] = {
 	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
 };
 
+static u8 gmd_to_intel_step(struct drm_i915_private *i915,
+			    struct ip_version *gmd)
+{
+	u8 step = gmd->step + STEP_A0;
+
+	if (step >= STEP_FUTURE) {
+		drm_dbg(&i915->drm, "Using future steppings\n");
+		return STEP_FUTURE;
+	}
+
+	return step;
+}
+
 static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
 
 void intel_step_init(struct drm_i915_private *i915)
@@ -144,6 +157,18 @@ void intel_step_init(struct drm_i915_private *i915)
 	int revid = INTEL_REVID(i915);
 	struct intel_step_info step = {};
 
+	if (HAS_GMD_ID(i915)) {
+		step.graphics_step = gmd_to_intel_step(i915,
+						       &RUNTIME_INFO(i915)->graphics.ip);
+		step.media_step = gmd_to_intel_step(i915,
+						    &RUNTIME_INFO(i915)->media.ip);
+		step.display_step = gmd_to_intel_step(i915,
+						      &RUNTIME_INFO(i915)->display.ip);
+		RUNTIME_INFO(i915)->step = step;
+
+		return;
+	}
+
 	if (IS_PONTEVECCHIO(i915)) {
 		pvc_step_init(i915, revid);
 		return;
diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h
index a6b12bfa9744..57b9928ddca6 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -23,21 +23,43 @@ struct intel_step_info {
 	func(A0)			\
 	func(A1)			\
 	func(A2)			\
+	func(A3)			\
 	func(B0)			\
 	func(B1)			\
 	func(B2)			\
 	func(B3)			\
 	func(C0)			\
 	func(C1)			\
+	func(C2)			\
+	func(C3)			\
 	func(D0)			\
 	func(D1)			\
+	func(D2)			\
+	func(D3)			\
 	func(E0)			\
+	func(E1)			\
+	func(E2)			\
+	func(E3)			\
 	func(F0)			\
+	func(F1)			\
+	func(F2)			\
+	func(F3)			\
 	func(G0)			\
+	func(G1)			\
+	func(G2)			\
+	func(G3)			\
 	func(H0)			\
+	func(H1)			\
+	func(H2)			\
+	func(H3)			\
 	func(I0)			\
 	func(I1)			\
-	func(J0)
+	func(I2)			\
+	func(I3)			\
+	func(J0)			\
+	func(J1)			\
+	func(J2)			\
+	func(J3)
 
 /*
  * Symbolic steppings that do not match the hardware. These are valid both as gt
-- 
2.34.1

[Intel-gfx] [PATCH v6 2/3] drm/i915: Parse and set stepping for platforms with GMD

[Radhakrishna Sripada]

From: José Roberto de Souza <jose.souza@intel.com>

Expand the current stepping convention to accommodate the GMD
stepping info. Typically GMD step maps to letter stepping
by "A + step %4" and number to "A + step /4" i.e, GMD step
0 maps to STEP_A0, 1 to _A1, 2 to _A2, 3 to _A3, 4 to STEP_B0...

Future platforms might break this formulae and may require a table
mapping to decode GMD step compatible with the convention.

v2:
 - Pass the updated ip version structure
v3:
 - Skip using GMD to step table(MattR)

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_step.c | 25 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_step.h | 24 +++++++++++++++++++++++-
 2 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 42b3133d8387..91e7c51991b0 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -135,6 +135,19 @@ static const struct intel_step_info adlp_n_revids[] = {
 	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
 };
 
+static u8 gmd_to_intel_step(struct drm_i915_private *i915,
+			    struct ip_version *gmd)
+{
+	u8 step = gmd->step + STEP_A0;
+
+	if (step >= STEP_FUTURE) {
+		drm_dbg(&i915->drm, "Using future steppings\n");
+		return STEP_FUTURE;
+	}
+
+	return step;
+}
+
 static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
 
 void intel_step_init(struct drm_i915_private *i915)
@@ -144,6 +157,18 @@ void intel_step_init(struct drm_i915_private *i915)
 	int revid = INTEL_REVID(i915);
 	struct intel_step_info step = {};
 
+	if (HAS_GMD_ID(i915)) {
+		step.graphics_step = gmd_to_intel_step(i915,
+						       &RUNTIME_INFO(i915)->graphics.ip);
+		step.media_step = gmd_to_intel_step(i915,
+						    &RUNTIME_INFO(i915)->media.ip);
+		step.display_step = gmd_to_intel_step(i915,
+						      &RUNTIME_INFO(i915)->display.ip);
+		RUNTIME_INFO(i915)->step = step;
+
+		return;
+	}
+
 	if (IS_PONTEVECCHIO(i915)) {
 		pvc_step_init(i915, revid);
 		return;
diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h
index a6b12bfa9744..57b9928ddca6 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -23,21 +23,43 @@ struct intel_step_info {
 	func(A0)			\
 	func(A1)			\
 	func(A2)			\
+	func(A3)			\
 	func(B0)			\
 	func(B1)			\
 	func(B2)			\
 	func(B3)			\
 	func(C0)			\
 	func(C1)			\
+	func(C2)			\
+	func(C3)			\
 	func(D0)			\
 	func(D1)			\
+	func(D2)			\
+	func(D3)			\
 	func(E0)			\
+	func(E1)			\
+	func(E2)			\
+	func(E3)			\
 	func(F0)			\
+	func(F1)			\
+	func(F2)			\
+	func(F3)			\
 	func(G0)			\
+	func(G1)			\
+	func(G2)			\
+	func(G3)			\
 	func(H0)			\
+	func(H1)			\
+	func(H2)			\
+	func(H3)			\
 	func(I0)			\
 	func(I1)			\
-	func(J0)
+	func(I2)			\
+	func(I3)			\
+	func(J0)			\
+	func(J1)			\
+	func(J2)			\
+	func(J3)
 
 /*
  * Symbolic steppings that do not match the hardware. These are valid both as gt
-- 
2.34.1

Re: [PATCH v6 2/3] drm/i915: Parse and set stepping for platforms with GMD

[Lucas De Marchi]

On Thu, Sep 15, 2022 at 06:46:47PM -0700, Radhakrishna Sripada wrote:
>From: José Roberto de Souza <jose.souza@intel.com>
>
>Expand the current stepping convention to accommodate the GMD
>stepping info. Typically GMD step maps to letter stepping
>by "A + step %4" and number to "A + step /4" i.e, GMD step
>0 maps to STEP_A0, 1 to _A1, 2 to _A2, 3 to _A3, 4 to STEP_B0...
>
>Future platforms might break this formulae and may require a table
>mapping to decode GMD step compatible with the convention.
>
>v2:
> - Pass the updated ip version structure
>v3:
> - Skip using GMD to step table(MattR)
>
>Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>---
> drivers/gpu/drm/i915/intel_step.c | 25 +++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_step.h | 24 +++++++++++++++++++++++-
> 2 files changed, 48 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
>index 42b3133d8387..91e7c51991b0 100644
>--- a/drivers/gpu/drm/i915/intel_step.c
>+++ b/drivers/gpu/drm/i915/intel_step.c
>@@ -135,6 +135,19 @@ static const struct intel_step_info adlp_n_revids[] = {
> 	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
> };
>
>+static u8 gmd_to_intel_step(struct drm_i915_private *i915,
>+			    struct ip_version *gmd)
>+{
>+	u8 step = gmd->step + STEP_A0;
>+
>+	if (step >= STEP_FUTURE) {
>+		drm_dbg(&i915->drm, "Using future steppings\n");
>+		return STEP_FUTURE;
>+	}
>+
>+	return step;
>+}
>+
> static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
>
> void intel_step_init(struct drm_i915_private *i915)
>@@ -144,6 +157,18 @@ void intel_step_init(struct drm_i915_private *i915)
> 	int revid = INTEL_REVID(i915);
> 	struct intel_step_info step = {};
>
>+	if (HAS_GMD_ID(i915)) {
>+		step.graphics_step = gmd_to_intel_step(i915,
>+						       &RUNTIME_INFO(i915)->graphics.ip);
>+		step.media_step = gmd_to_intel_step(i915,
>+						    &RUNTIME_INFO(i915)->media.ip);
>+		step.display_step = gmd_to_intel_step(i915,
>+						      &RUNTIME_INFO(i915)->display.ip);
>+		RUNTIME_INFO(i915)->step = step;
>+
>+		return;
>+	}
>+
> 	if (IS_PONTEVECCHIO(i915)) {
> 		pvc_step_init(i915, revid);
> 		return;
>diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h
>index a6b12bfa9744..57b9928ddca6 100644
>--- a/drivers/gpu/drm/i915/intel_step.h
>+++ b/drivers/gpu/drm/i915/intel_step.h
>@@ -23,21 +23,43 @@ struct intel_step_info {

missing comment in this struct that it's expected to have 4 number steps
per letter. I don't want someone to add a stepping B4 in future without
realizing that will render gmd_to_intel_step()  invalid


with that added: Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

Re: [Intel-gfx] [PATCH v6 2/3] drm/i915: Parse and set stepping for platforms with GMD

[Lucas De Marchi]

On Thu, Sep 15, 2022 at 06:46:47PM -0700, Radhakrishna Sripada wrote:
>From: José Roberto de Souza <jose.souza@intel.com>
>
>Expand the current stepping convention to accommodate the GMD
>stepping info. Typically GMD step maps to letter stepping
>by "A + step %4" and number to "A + step /4" i.e, GMD step
>0 maps to STEP_A0, 1 to _A1, 2 to _A2, 3 to _A3, 4 to STEP_B0...
>
>Future platforms might break this formulae and may require a table
>mapping to decode GMD step compatible with the convention.
>
>v2:
> - Pass the updated ip version structure
>v3:
> - Skip using GMD to step table(MattR)
>
>Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>---
> drivers/gpu/drm/i915/intel_step.c | 25 +++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_step.h | 24 +++++++++++++++++++++++-
> 2 files changed, 48 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
>index 42b3133d8387..91e7c51991b0 100644
>--- a/drivers/gpu/drm/i915/intel_step.c
>+++ b/drivers/gpu/drm/i915/intel_step.c
>@@ -135,6 +135,19 @@ static const struct intel_step_info adlp_n_revids[] = {
> 	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
> };
>
>+static u8 gmd_to_intel_step(struct drm_i915_private *i915,
>+			    struct ip_version *gmd)
>+{
>+	u8 step = gmd->step + STEP_A0;
>+
>+	if (step >= STEP_FUTURE) {
>+		drm_dbg(&i915->drm, "Using future steppings\n");
>+		return STEP_FUTURE;
>+	}
>+
>+	return step;
>+}
>+
> static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
>
> void intel_step_init(struct drm_i915_private *i915)
>@@ -144,6 +157,18 @@ void intel_step_init(struct drm_i915_private *i915)
> 	int revid = INTEL_REVID(i915);
> 	struct intel_step_info step = {};
>
>+	if (HAS_GMD_ID(i915)) {
>+		step.graphics_step = gmd_to_intel_step(i915,
>+						       &RUNTIME_INFO(i915)->graphics.ip);
>+		step.media_step = gmd_to_intel_step(i915,
>+						    &RUNTIME_INFO(i915)->media.ip);
>+		step.display_step = gmd_to_intel_step(i915,
>+						      &RUNTIME_INFO(i915)->display.ip);
>+		RUNTIME_INFO(i915)->step = step;
>+
>+		return;
>+	}
>+
> 	if (IS_PONTEVECCHIO(i915)) {
> 		pvc_step_init(i915, revid);
> 		return;
>diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h
>index a6b12bfa9744..57b9928ddca6 100644
>--- a/drivers/gpu/drm/i915/intel_step.h
>+++ b/drivers/gpu/drm/i915/intel_step.h
>@@ -23,21 +23,43 @@ struct intel_step_info {

missing comment in this struct that it's expected to have 4 number steps
per letter. I don't want someone to add a stepping B4 in future without
realizing that will render gmd_to_intel_step()  invalid


with that added: Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

[PATCH v6 3/3] drm/i915/mtl: Define engine context layouts

[Radhakrishna Sripada]

From: Matt Roper <matthew.d.roper@intel.com>

The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Add missing nop in xcs offsets(Bala)
v3:
 - Fix the spacing for nop in xcs offset(MattR)
v4:
 - Fix rcs register offset(MattR)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
 1 file changed, 82 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3955292483a6..c7937d8d120a 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+	NOP(1),
+	LRI(13, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	NOP(4),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	END
+};
+
 static const u8 gen8_rcs_offsets[] = {
 	NOP(1),
 	LRI(14, POSTED),
@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+	NOP(1),
+	LRI(15, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	REG(0x120),
+	REG(0x124),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	NOP(2),
+	LRI(2, POSTED),
+	REG16(0x5a8),
+	REG16(0x5ac),
+
+	NOP(6),
+	LRI(1, 0),
+	REG(0x0c8),
+
+	END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		   !intel_engine_has_relative_mmio(engine));
 
 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_rcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_rcs_offsets;
 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
 			return xehp_rcs_offsets;
@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		else
 			return gen8_rcs_offsets;
 	} else {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_xcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_xcs_offsets;
 		else if (GRAPHICS_VER(engine->i915) >= 12)
 			return gen12_xcs_offsets;
-- 
2.34.1

[Intel-gfx] [PATCH v6 3/3] drm/i915/mtl: Define engine context layouts

[Radhakrishna Sripada]

From: Matt Roper <matthew.d.roper@intel.com>

The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Add missing nop in xcs offsets(Bala)
v3:
 - Fix the spacing for nop in xcs offset(MattR)
v4:
 - Fix rcs register offset(MattR)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
 1 file changed, 82 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3955292483a6..c7937d8d120a 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+	NOP(1),
+	LRI(13, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	NOP(4),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	END
+};
+
 static const u8 gen8_rcs_offsets[] = {
 	NOP(1),
 	LRI(14, POSTED),
@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+	NOP(1),
+	LRI(15, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	REG(0x120),
+	REG(0x124),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	NOP(2),
+	LRI(2, POSTED),
+	REG16(0x5a8),
+	REG16(0x5ac),
+
+	NOP(6),
+	LRI(1, 0),
+	REG(0x0c8),
+
+	END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		   !intel_engine_has_relative_mmio(engine));
 
 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_rcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_rcs_offsets;
 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
 			return xehp_rcs_offsets;
@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		else
 			return gen8_rcs_offsets;
 	} else {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_xcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_xcs_offsets;
 		else if (GRAPHICS_VER(engine->i915) >= 12)
 			return gen12_xcs_offsets;
-- 
2.34.1

Re: [PATCH v6 3/3] drm/i915/mtl: Define engine context layouts

[Lucas De Marchi]

On Thu, Sep 15, 2022 at 06:46:48PM -0700, Radhakrishna Sripada wrote:
>From: Matt Roper <matthew.d.roper@intel.com>
>
>The part of the media and blitter engine contexts that we care about for
>setting up an initial state are the same on MTL as they were on DG2
>(and PVC), so we need to update the driver conditions to re-use the DG2
>context table.

this paragraph doesn't match what you are doing in the patch. Which one
is correct?  From "v2" below it looks like the original intention was to
just reuse and now they are changed.

>
>For render/compute engines, the part of the context images are nearly
>the same, although the layout had a very slight change --- one POSH
>register was removed and the placement of some LRI/noops adjusted
>slightly to compensate.
>
>v2:
> - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> - Add missing nop in xcs offsets(Bala)
>v3:
> - Fix the spacing for nop in xcs offset(MattR)
>v4:
> - Fix rcs register offset(MattR)
>
>Bspec: 46261, 46260, 45585
>Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
> 1 file changed, 82 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>index 3955292483a6..c7937d8d120a 100644
>--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
> 	END
> };
>
>+static const u8 mtl_xcs_offsets[] = {
>+	NOP(1),
>+	LRI(13, POSTED),
>+	REG16(0x244),
>+	REG(0x034),
>+	REG(0x030),
>+	REG(0x038),
>+	REG(0x03c),
>+	REG(0x168),
>+	REG(0x140),
>+	REG(0x110),
>+	REG(0x1c0),
>+	REG(0x1c4),
>+	REG(0x1c8),
>+	REG(0x180),
>+	REG16(0x2b4),

are we missing 0x120 here?

>+	NOP(4),

NOP(2), but it seems this is here to
overcome the missing 0x120?

>+
>+	NOP(1),
>+	LRI(9, POSTED),
>+	REG16(0x3a8),
>+	REG16(0x28c),
>+	REG16(0x288),
>+	REG16(0x284),
>+	REG16(0x280),
>+	REG16(0x27c),
>+	REG16(0x278),
>+	REG16(0x274),
>+	REG16(0x270),
>+
>+	END
>+};
>+
> static const u8 gen8_rcs_offsets[] = {
> 	NOP(1),
> 	LRI(14, POSTED),
>@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
> 	END
> };
>
>+static const u8 mtl_rcs_offsets[] = {
>+	NOP(1),
>+	LRI(15, POSTED),
>+	REG16(0x244),
>+	REG(0x034),
>+	REG(0x030),
>+	REG(0x038),
>+	REG(0x03c),
>+	REG(0x168),
>+	REG(0x140),
>+	REG(0x110),
>+	REG(0x1c0),
>+	REG(0x1c4),
>+	REG(0x1c8),
>+	REG(0x180),
>+	REG16(0x2b4),
>+	REG(0x120),
>+	REG(0x124),
>+
>+	NOP(1),
>+	LRI(9, POSTED),

humn... set_offsets() is forcing MI_LRI_LRM_CS_MMIO
for ver >= 11, although here bspec shows this MI_LOAD_REGISTER_IMM
doesn't have it set.

+Mika, +Chris


Lucas De Marchi

>+	REG16(0x3a8),
>+	REG16(0x28c),
>+	REG16(0x288),
>+	REG16(0x284),
>+	REG16(0x280),
>+	REG16(0x27c),
>+	REG16(0x278),
>+	REG16(0x274),
>+	REG16(0x270),
>+
>+	NOP(2),
>+	LRI(2, POSTED),
>+	REG16(0x5a8),
>+	REG16(0x5ac),
>+
>+	NOP(6),
>+	LRI(1, 0),
>+	REG(0x0c8),
>+
>+	END
>+};
>+
> #undef END
> #undef REG16
> #undef REG
>@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> 		   !intel_engine_has_relative_mmio(engine));
>
> 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
>-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
>+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
>+			return mtl_rcs_offsets;
>+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> 			return dg2_rcs_offsets;
> 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> 			return xehp_rcs_offsets;
>@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> 		else
> 			return gen8_rcs_offsets;
> 	} else {
>-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
>+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
>+			return mtl_xcs_offsets;
>+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> 			return dg2_xcs_offsets;
> 		else if (GRAPHICS_VER(engine->i915) >= 12)
> 			return gen12_xcs_offsets;
>-- 
>2.34.1
>

Re: [Intel-gfx] [PATCH v6 3/3] drm/i915/mtl: Define engine context layouts

[Lucas De Marchi]

On Thu, Sep 15, 2022 at 06:46:48PM -0700, Radhakrishna Sripada wrote:
>From: Matt Roper <matthew.d.roper@intel.com>
>
>The part of the media and blitter engine contexts that we care about for
>setting up an initial state are the same on MTL as they were on DG2
>(and PVC), so we need to update the driver conditions to re-use the DG2
>context table.

this paragraph doesn't match what you are doing in the patch. Which one
is correct?  From "v2" below it looks like the original intention was to
just reuse and now they are changed.

>
>For render/compute engines, the part of the context images are nearly
>the same, although the layout had a very slight change --- one POSH
>register was removed and the placement of some LRI/noops adjusted
>slightly to compensate.
>
>v2:
> - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> - Add missing nop in xcs offsets(Bala)
>v3:
> - Fix the spacing for nop in xcs offset(MattR)
>v4:
> - Fix rcs register offset(MattR)
>
>Bspec: 46261, 46260, 45585
>Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
> 1 file changed, 82 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>index 3955292483a6..c7937d8d120a 100644
>--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
> 	END
> };
>
>+static const u8 mtl_xcs_offsets[] = {
>+	NOP(1),
>+	LRI(13, POSTED),
>+	REG16(0x244),
>+	REG(0x034),
>+	REG(0x030),
>+	REG(0x038),
>+	REG(0x03c),
>+	REG(0x168),
>+	REG(0x140),
>+	REG(0x110),
>+	REG(0x1c0),
>+	REG(0x1c4),
>+	REG(0x1c8),
>+	REG(0x180),
>+	REG16(0x2b4),

are we missing 0x120 here?

>+	NOP(4),

NOP(2), but it seems this is here to
overcome the missing 0x120?

>+
>+	NOP(1),
>+	LRI(9, POSTED),
>+	REG16(0x3a8),
>+	REG16(0x28c),
>+	REG16(0x288),
>+	REG16(0x284),
>+	REG16(0x280),
>+	REG16(0x27c),
>+	REG16(0x278),
>+	REG16(0x274),
>+	REG16(0x270),
>+
>+	END
>+};
>+
> static const u8 gen8_rcs_offsets[] = {
> 	NOP(1),
> 	LRI(14, POSTED),
>@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
> 	END
> };
>
>+static const u8 mtl_rcs_offsets[] = {
>+	NOP(1),
>+	LRI(15, POSTED),
>+	REG16(0x244),
>+	REG(0x034),
>+	REG(0x030),
>+	REG(0x038),
>+	REG(0x03c),
>+	REG(0x168),
>+	REG(0x140),
>+	REG(0x110),
>+	REG(0x1c0),
>+	REG(0x1c4),
>+	REG(0x1c8),
>+	REG(0x180),
>+	REG16(0x2b4),
>+	REG(0x120),
>+	REG(0x124),
>+
>+	NOP(1),
>+	LRI(9, POSTED),

humn... set_offsets() is forcing MI_LRI_LRM_CS_MMIO
for ver >= 11, although here bspec shows this MI_LOAD_REGISTER_IMM
doesn't have it set.

+Mika, +Chris


Lucas De Marchi

>+	REG16(0x3a8),
>+	REG16(0x28c),
>+	REG16(0x288),
>+	REG16(0x284),
>+	REG16(0x280),
>+	REG16(0x27c),
>+	REG16(0x278),
>+	REG16(0x274),
>+	REG16(0x270),
>+
>+	NOP(2),
>+	LRI(2, POSTED),
>+	REG16(0x5a8),
>+	REG16(0x5ac),
>+
>+	NOP(6),
>+	LRI(1, 0),
>+	REG(0x0c8),
>+
>+	END
>+};
>+
> #undef END
> #undef REG16
> #undef REG
>@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> 		   !intel_engine_has_relative_mmio(engine));
>
> 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
>-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
>+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
>+			return mtl_rcs_offsets;
>+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> 			return dg2_rcs_offsets;
> 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> 			return xehp_rcs_offsets;
>@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> 		else
> 			return gen8_rcs_offsets;
> 	} else {
>-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
>+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
>+			return mtl_xcs_offsets;
>+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> 			return dg2_xcs_offsets;
> 		else if (GRAPHICS_VER(engine->i915) >= 12)
> 			return gen12_xcs_offsets;
>-- 
>2.34.1
>

Re: [PATCH v6 3/3] drm/i915/mtl: Define engine context layouts

[Matt Roper]

On Fri, Sep 23, 2022 at 03:48:51PM -0700, Lucas De Marchi wrote:
> On Thu, Sep 15, 2022 at 06:46:48PM -0700, Radhakrishna Sripada wrote:
> > From: Matt Roper <matthew.d.roper@intel.com>
> > 
> > The part of the media and blitter engine contexts that we care about for
> > setting up an initial state are the same on MTL as they were on DG2
> > (and PVC), so we need to update the driver conditions to re-use the DG2
> > context table.
> 
> this paragraph doesn't match what you are doing in the patch. Which one
> is correct?  From "v2" below it looks like the original intention was to
> just reuse and now they are changed.
> 
> > 
> > For render/compute engines, the part of the context images are nearly
> > the same, although the layout had a very slight change --- one POSH
> > register was removed and the placement of some LRI/noops adjusted
> > slightly to compensate.
> > 
> > v2:
> > - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> > - Add missing nop in xcs offsets(Bala)
> > v3:
> > - Fix the spacing for nop in xcs offset(MattR)
> > v4:
> > - Fix rcs register offset(MattR)
> > 
> > Bspec: 46261, 46260, 45585
> > Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
> > 1 file changed, 82 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index 3955292483a6..c7937d8d120a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
> > 	END
> > };
> > 
> > +static const u8 mtl_xcs_offsets[] = {
> > +	NOP(1),
> > +	LRI(13, POSTED),
> > +	REG16(0x244),
> > +	REG(0x034),
> > +	REG(0x030),
> > +	REG(0x038),
> > +	REG(0x03c),
> > +	REG(0x168),
> > +	REG(0x140),
> > +	REG(0x110),
> > +	REG(0x1c0),
> > +	REG(0x1c4),
> > +	REG(0x1c8),
> > +	REG(0x180),
> > +	REG16(0x2b4),
> 
> are we missing 0x120 here?
> 
> > +	NOP(4),
> 
> NOP(2), but it seems this is here to
> overcome the missing 0x120?

If 0x120 were included, it's a 64-bit register so it would fill both of
the NOP slots (i.e., it would be listed as 0x120 and 0x124 in the code
here).

The bspec tagging/filtering doesn't seem to be working quite right here.
The project column of bspec 45585 indicates it should only be included
here on PVC (and all other platforms should have a 4-dword NOP instead).
But the filter option doesn't actually drop out the row of the table as
you'd expect.  Also inspecting the tags directly leaves some ambiguity
about whether the final platform list is correct or not.

I suspect it doesn't actually really matter whether we include that
register here or not; the overall "shape" of the context image is
correct either way.  The hardware should be able to do its initial
context switch with load suppressed regardless.  After that the next
time a context switch happens the full context will get written out to
memory in the correct form.  And 0x120 isn't a register we're actively
doing anything with in the driver that would require special care.

If need be, we could always look at a post-context switch context in
memory on actual hardware and see whether it includes 0x120 in this spot
or not.

> 
> > +
> > +	NOP(1),
> > +	LRI(9, POSTED),
> > +	REG16(0x3a8),
> > +	REG16(0x28c),
> > +	REG16(0x288),
> > +	REG16(0x284),
> > +	REG16(0x280),
> > +	REG16(0x27c),
> > +	REG16(0x278),
> > +	REG16(0x274),
> > +	REG16(0x270),
> > +
> > +	END
> > +};
> > +
> > static const u8 gen8_rcs_offsets[] = {
> > 	NOP(1),
> > 	LRI(14, POSTED),
> > @@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
> > 	END
> > };
> > 
> > +static const u8 mtl_rcs_offsets[] = {
> > +	NOP(1),
> > +	LRI(15, POSTED),
> > +	REG16(0x244),
> > +	REG(0x034),
> > +	REG(0x030),
> > +	REG(0x038),
> > +	REG(0x03c),
> > +	REG(0x168),
> > +	REG(0x140),
> > +	REG(0x110),
> > +	REG(0x1c0),
> > +	REG(0x1c4),
> > +	REG(0x1c8),
> > +	REG(0x180),
> > +	REG16(0x2b4),
> > +	REG(0x120),
> > +	REG(0x124),
> > +
> > +	NOP(1),
> > +	LRI(9, POSTED),
> 
> humn... set_offsets() is forcing MI_LRI_LRM_CS_MMIO
> for ver >= 11, although here bspec shows this MI_LOAD_REGISTER_IMM
> doesn't have it set.

Since all of the offsets here are engine-relative offsets, that sounds
like a spec bug.  Otherwise you'd be loading into absolute register
offsets 0x3a8, 0x28c, etc. rather than the proper registers.  It's
probably a copy/paste from the render engine's page where they document
everything with the absolute 0x2XXX offsets.


Matt

> 
> +Mika, +Chris
> 
> 
> Lucas De Marchi
> 
> > +	REG16(0x3a8),
> > +	REG16(0x28c),
> > +	REG16(0x288),
> > +	REG16(0x284),
> > +	REG16(0x280),
> > +	REG16(0x27c),
> > +	REG16(0x278),
> > +	REG16(0x274),
> > +	REG16(0x270),
> > +
> > +	NOP(2),
> > +	LRI(2, POSTED),
> > +	REG16(0x5a8),
> > +	REG16(0x5ac),
> > +
> > +	NOP(6),
> > +	LRI(1, 0),
> > +	REG(0x0c8),
> > +
> > +	END
> > +};
> > +
> > #undef END
> > #undef REG16
> > #undef REG
> > @@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> > 		   !intel_engine_has_relative_mmio(engine));
> > 
> > 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
> > -		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> > +		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> > +			return mtl_rcs_offsets;
> > +		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> > 			return dg2_rcs_offsets;
> > 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> > 			return xehp_rcs_offsets;
> > @@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> > 		else
> > 			return gen8_rcs_offsets;
> > 	} else {
> > -		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> > +		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> > +			return mtl_xcs_offsets;
> > +		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> > 			return dg2_xcs_offsets;
> > 		else if (GRAPHICS_VER(engine->i915) >= 12)
> > 			return gen12_xcs_offsets;
> > -- 
> > 2.34.1
> > 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v6 3/3] drm/i915/mtl: Define engine context layouts

[Matt Roper]

On Fri, Sep 23, 2022 at 03:48:51PM -0700, Lucas De Marchi wrote:
> On Thu, Sep 15, 2022 at 06:46:48PM -0700, Radhakrishna Sripada wrote:
> > From: Matt Roper <matthew.d.roper@intel.com>
> > 
> > The part of the media and blitter engine contexts that we care about for
> > setting up an initial state are the same on MTL as they were on DG2
> > (and PVC), so we need to update the driver conditions to re-use the DG2
> > context table.
> 
> this paragraph doesn't match what you are doing in the patch. Which one
> is correct?  From "v2" below it looks like the original intention was to
> just reuse and now they are changed.
> 
> > 
> > For render/compute engines, the part of the context images are nearly
> > the same, although the layout had a very slight change --- one POSH
> > register was removed and the placement of some LRI/noops adjusted
> > slightly to compensate.
> > 
> > v2:
> > - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> > - Add missing nop in xcs offsets(Bala)
> > v3:
> > - Fix the spacing for nop in xcs offset(MattR)
> > v4:
> > - Fix rcs register offset(MattR)
> > 
> > Bspec: 46261, 46260, 45585
> > Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
> > 1 file changed, 82 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index 3955292483a6..c7937d8d120a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
> > 	END
> > };
> > 
> > +static const u8 mtl_xcs_offsets[] = {
> > +	NOP(1),
> > +	LRI(13, POSTED),
> > +	REG16(0x244),
> > +	REG(0x034),
> > +	REG(0x030),
> > +	REG(0x038),
> > +	REG(0x03c),
> > +	REG(0x168),
> > +	REG(0x140),
> > +	REG(0x110),
> > +	REG(0x1c0),
> > +	REG(0x1c4),
> > +	REG(0x1c8),
> > +	REG(0x180),
> > +	REG16(0x2b4),
> 
> are we missing 0x120 here?
> 
> > +	NOP(4),
> 
> NOP(2), but it seems this is here to
> overcome the missing 0x120?

If 0x120 were included, it's a 64-bit register so it would fill both of
the NOP slots (i.e., it would be listed as 0x120 and 0x124 in the code
here).

The bspec tagging/filtering doesn't seem to be working quite right here.
The project column of bspec 45585 indicates it should only be included
here on PVC (and all other platforms should have a 4-dword NOP instead).
But the filter option doesn't actually drop out the row of the table as
you'd expect.  Also inspecting the tags directly leaves some ambiguity
about whether the final platform list is correct or not.

I suspect it doesn't actually really matter whether we include that
register here or not; the overall "shape" of the context image is
correct either way.  The hardware should be able to do its initial
context switch with load suppressed regardless.  After that the next
time a context switch happens the full context will get written out to
memory in the correct form.  And 0x120 isn't a register we're actively
doing anything with in the driver that would require special care.

If need be, we could always look at a post-context switch context in
memory on actual hardware and see whether it includes 0x120 in this spot
or not.

> 
> > +
> > +	NOP(1),
> > +	LRI(9, POSTED),
> > +	REG16(0x3a8),
> > +	REG16(0x28c),
> > +	REG16(0x288),
> > +	REG16(0x284),
> > +	REG16(0x280),
> > +	REG16(0x27c),
> > +	REG16(0x278),
> > +	REG16(0x274),
> > +	REG16(0x270),
> > +
> > +	END
> > +};
> > +
> > static const u8 gen8_rcs_offsets[] = {
> > 	NOP(1),
> > 	LRI(14, POSTED),
> > @@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
> > 	END
> > };
> > 
> > +static const u8 mtl_rcs_offsets[] = {
> > +	NOP(1),
> > +	LRI(15, POSTED),
> > +	REG16(0x244),
> > +	REG(0x034),
> > +	REG(0x030),
> > +	REG(0x038),
> > +	REG(0x03c),
> > +	REG(0x168),
> > +	REG(0x140),
> > +	REG(0x110),
> > +	REG(0x1c0),
> > +	REG(0x1c4),
> > +	REG(0x1c8),
> > +	REG(0x180),
> > +	REG16(0x2b4),
> > +	REG(0x120),
> > +	REG(0x124),
> > +
> > +	NOP(1),
> > +	LRI(9, POSTED),
> 
> humn... set_offsets() is forcing MI_LRI_LRM_CS_MMIO
> for ver >= 11, although here bspec shows this MI_LOAD_REGISTER_IMM
> doesn't have it set.

Since all of the offsets here are engine-relative offsets, that sounds
like a spec bug.  Otherwise you'd be loading into absolute register
offsets 0x3a8, 0x28c, etc. rather than the proper registers.  It's
probably a copy/paste from the render engine's page where they document
everything with the absolute 0x2XXX offsets.


Matt

> 
> +Mika, +Chris
> 
> 
> Lucas De Marchi
> 
> > +	REG16(0x3a8),
> > +	REG16(0x28c),
> > +	REG16(0x288),
> > +	REG16(0x284),
> > +	REG16(0x280),
> > +	REG16(0x27c),
> > +	REG16(0x278),
> > +	REG16(0x274),
> > +	REG16(0x270),
> > +
> > +	NOP(2),
> > +	LRI(2, POSTED),
> > +	REG16(0x5a8),
> > +	REG16(0x5ac),
> > +
> > +	NOP(6),
> > +	LRI(1, 0),
> > +	REG(0x0c8),
> > +
> > +	END
> > +};
> > +
> > #undef END
> > #undef REG16
> > #undef REG
> > @@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> > 		   !intel_engine_has_relative_mmio(engine));
> > 
> > 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
> > -		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> > +		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> > +			return mtl_rcs_offsets;
> > +		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> > 			return dg2_rcs_offsets;
> > 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> > 			return xehp_rcs_offsets;
> > @@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> > 		else
> > 			return gen8_rcs_offsets;
> > 	} else {
> > -		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> > +		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> > +			return mtl_xcs_offsets;
> > +		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> > 			return dg2_xcs_offsets;
> > 		else if (GRAPHICS_VER(engine->i915) >= 12)
> > 			return gen12_xcs_offsets;
> > -- 
> > 2.34.1
> > 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

[PATCH v4.1] drm/i915/mtl: Define engine context layouts

[Radhakrishna Sripada]

From: Matt Roper <matthew.d.roper@intel.com>

The part of the media and blitter engine contexts that we care about for
setting up an initial state on MTL are nearly similar to DG2 (and PVC).
The difference being PRT_BB_STATE being replaced with NOP.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Add missing nop in xcs offsets(Bala)
v3:
 - Fix the spacing for nop in xcs offset(MattR)
v4:
 - Fix rcs register offset(MattR)
v4.1:
 - Fix commit message(Lucas)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Licas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
 1 file changed, 82 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 82d899f170fb..e84ef3859934 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+	NOP(1),
+	LRI(13, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	NOP(4),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	END
+};
+
 static const u8 gen8_rcs_offsets[] = {
 	NOP(1),
 	LRI(14, POSTED),
@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+	NOP(1),
+	LRI(15, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	REG(0x120),
+	REG(0x124),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	NOP(2),
+	LRI(2, POSTED),
+	REG16(0x5a8),
+	REG16(0x5ac),
+
+	NOP(6),
+	LRI(1, 0),
+	REG(0x0c8),
+
+	END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		   !intel_engine_has_relative_mmio(engine));
 
 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_rcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_rcs_offsets;
 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
 			return xehp_rcs_offsets;
@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		else
 			return gen8_rcs_offsets;
 	} else {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_xcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_xcs_offsets;
 		else if (GRAPHICS_VER(engine->i915) >= 12)
 			return gen12_xcs_offsets;
-- 
2.34.1

[Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts

[Radhakrishna Sripada]

From: Matt Roper <matthew.d.roper@intel.com>

The part of the media and blitter engine contexts that we care about for
setting up an initial state on MTL are nearly similar to DG2 (and PVC).
The difference being PRT_BB_STATE being replaced with NOP.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Add missing nop in xcs offsets(Bala)
v3:
 - Fix the spacing for nop in xcs offset(MattR)
v4:
 - Fix rcs register offset(MattR)
v4.1:
 - Fix commit message(Lucas)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Licas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
 1 file changed, 82 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 82d899f170fb..e84ef3859934 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+	NOP(1),
+	LRI(13, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	NOP(4),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	END
+};
+
 static const u8 gen8_rcs_offsets[] = {
 	NOP(1),
 	LRI(14, POSTED),
@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+	NOP(1),
+	LRI(15, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	REG(0x120),
+	REG(0x124),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	NOP(2),
+	LRI(2, POSTED),
+	REG16(0x5a8),
+	REG16(0x5ac),
+
+	NOP(6),
+	LRI(1, 0),
+	REG(0x0c8),
+
+	END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		   !intel_engine_has_relative_mmio(engine));
 
 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_rcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_rcs_offsets;
 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
 			return xehp_rcs_offsets;
@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		else
 			return gen8_rcs_offsets;
 	} else {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_xcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_xcs_offsets;
 		else if (GRAPHICS_VER(engine->i915) >= 12)
 			return gen12_xcs_offsets;
-- 
2.34.1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Initial Meteorlake Support (rev10)

[Patchwork]

== Series Details ==

Series: Initial Meteorlake Support (rev10)
URL   : https://patchwork.freedesktop.org/series/106786/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Initial Meteorlake Support (rev10)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 10377 bytes --]

== Series Details ==

Series: Initial Meteorlake Support (rev10)
URL   : https://patchwork.freedesktop.org/series/106786/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12144 -> Patchwork_106786v10
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/index.html

Participating hosts (35 -> 40)
------------------------------

  Additional (7): fi-bxt-dsi bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adln-1 bat-rpls-1 
  Missing    (2): fi-ctg-p8600 fi-hsw-4200u 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_106786v10:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_suspend@basic-s0@smem:
    - {fi-tgl-mst}:       [DMESG-WARN][1] ([i915#1982] / [i915#5122]) -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/fi-tgl-mst/igt@gem_exec_suspend@basic-s0@smem.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-tgl-mst/igt@gem_exec_suspend@basic-s0@smem.html

  
New tests
---------

  New tests have been introduced between CI_DRM_12144 and Patchwork_106786v10:

### New IGT tests (1) ###

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-7:
    - Statuses : 1 pass(s)
    - Exec time: [3.64] s

  

Known issues
------------

  Here are the changes found in Patchwork_106786v10 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-bxt-dsi/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-icl-u2:          NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-icl-u2/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-bxt-dsi/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_tiled_blits@basic:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][6] ([fdo#109271]) +12 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-bxt-dsi/igt@gem_tiled_blits@basic.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-g3258:       [PASS][7] -> [INCOMPLETE][8] ([i915#3303] / [i915#4785])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@requests:
    - fi-pnv-d510:        [PASS][9] -> [DMESG-FAIL][10] ([i915#4528])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/fi-pnv-d510/igt@i915_selftest@live@requests.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-pnv-d510/igt@i915_selftest@live@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-ivb-3770:        NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-ivb-3770/igt@kms_chamelium@common-hpd-after-suspend.html
    - fi-bdw-5557u:       NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-bdw-5557u/igt@kms_chamelium@common-hpd-after-suspend.html
    - fi-snb-2600:        NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-snb-2600/igt@kms_chamelium@common-hpd-after-suspend.html
    - fi-blb-e6850:       NOTRUN -> [SKIP][14] ([fdo#109271])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-blb-e6850/igt@kms_chamelium@common-hpd-after-suspend.html
    - fi-icl-u2:          NOTRUN -> [SKIP][15] ([fdo#111827])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-bxt-dsi/igt@kms_chamelium@hdmi-edid-read.html

  * igt@prime_vgem@basic-userptr:
    - fi-icl-u2:          NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3301])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-icl-u2/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-hsw-g3258:       NOTRUN -> [FAIL][18] ([fdo#109271] / [i915#4312] / [i915#6246])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-hsw-g3258/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-icl-u2:          [INCOMPLETE][19] ([i915#4185] / [i915#4890]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/fi-icl-u2/igt@i915_pm_rpm@basic-rte.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-icl-u2/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_selftest@live@hangcheck:
    - fi-ivb-3770:        [INCOMPLETE][21] ([i915#3303] / [i915#5370]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/fi-ivb-3770/igt@i915_selftest@live@hangcheck.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-ivb-3770/igt@i915_selftest@live@hangcheck.html
    - fi-snb-2600:        [INCOMPLETE][23] ([i915#3921]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@requests:
    - fi-blb-e6850:       [DMESG-FAIL][25] ([i915#4528]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/fi-blb-e6850/igt@i915_selftest@live@requests.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/fi-blb-e6850/igt@i915_selftest@live@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4185]: https://gitlab.freedesktop.org/drm/intel/issues/4185
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5370]: https://gitlab.freedesktop.org/drm/intel/issues/5370
  [i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6641]: https://gitlab.freedesktop.org/drm/intel/issues/6641
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645


Build changes
-------------

  * Linux: CI_DRM_12144 -> Patchwork_106786v10

  CI-20190529: 20190529
  CI_DRM_12144: 55937d402fd885fe101cdd028dcc48df6d7f6b35 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_106786v10: 55937d402fd885fe101cdd028dcc48df6d7f6b35 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

93a60d01a56a drm/i915/mtl: Define engine context layouts
ca5aaa8a48ff drm/i915: Parse and set stepping for platforms with GMD
1de31509a336 drm/i915: Read graphics/media/display arch version from hw

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/index.html

[-- Attachment #2: Type: text/html, Size: 10526 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for Initial Meteorlake Support (rev10)

[Patchwork]

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== Series Details ==

Series: Initial Meteorlake Support (rev10)
URL   : https://patchwork.freedesktop.org/series/106786/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12144_full -> Patchwork_106786v10_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_106786v10_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_106786v10_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_106786v10_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_dc@dc5-psr:
    - shard-iclb:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-iclb3/igt@i915_pm_dc@dc5-psr.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb4/igt@i915_pm_dc@dc5-psr.html

  
Known issues
------------

  Here are the changes found in Patchwork_106786v10_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglb:         [PASS][3] -> [FAIL][4] ([i915#6268])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-tglb8/igt@gem_ctx_exec@basic-nohangcheck.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-tglb3/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_eio@in-flight-contexts-10ms:
    - shard-tglb:         [PASS][5] -> [TIMEOUT][6] ([i915#3063])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-tglb2/igt@gem_eio@in-flight-contexts-10ms.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-tglb8/igt@gem_eio@in-flight-contexts-10ms.html

  * igt@gem_exec_balancer@parallel-bb-first:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([i915#4525])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-iclb4/igt@gem_exec_balancer@parallel-bb-first.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb7/igt@gem_exec_balancer@parallel-bb-first.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][10] -> [SKIP][11] ([i915#2190])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-tglb3/igt@gem_huc_copy@huc-copy.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-tglb7/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-apl:          NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl2/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - shard-apl:          NOTRUN -> [SKIP][13] ([fdo#109271]) +44 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl2/igt@gem_pxp@reject-modify-context-protection-off-3.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk:          [PASS][14] -> [DMESG-WARN][15] ([i915#5566] / [i915#716])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-glk9/igt@gen9_exec_parse@allowed-single.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-glk5/igt@gen9_exec_parse@allowed-single.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3886]) +2 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-hpd-with-enabled-mode:
    - shard-apl:          NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl2/igt@kms_chamelium@dp-hpd-with-enabled-mode.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1:
    - shard-apl:          [PASS][18] -> [DMESG-WARN][19] ([i915#180]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-apl7/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl1/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
    - shard-glk:          [PASS][20] -> [FAIL][21] ([i915#2346])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor@varying-size:
    - shard-iclb:         [PASS][22] -> [FAIL][23] ([i915#2346]) +1 similar issue
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-iclb8/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][24] -> [FAIL][25] ([i915#79])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-iclb:         NOTRUN -> [SKIP][26] ([i915#2587] / [i915#2672]) +4 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][27] ([i915#2672]) +3 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][28] ([i915#2672] / [i915#3555])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-apl:          NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#658])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl2/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [PASS][30] -> [SKIP][31] ([fdo#109441]) +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-iclb2/igt@kms_psr@psr2_basic.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb6/igt@kms_psr@psr2_basic.html

  * igt@nouveau_crc@pipe-b-ctx-flip-detection:
    - shard-glk:          NOTRUN -> [SKIP][32] ([fdo#109271]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-glk7/igt@nouveau_crc@pipe-b-ctx-flip-detection.html

  
#### Possible fixes ####

  * igt@gem_busy@close-race:
    - shard-glk:          [TIMEOUT][33] ([i915#6016]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-glk2/igt@gem_busy@close-race.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-glk7/igt@gem_busy@close-race.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-iclb:         [SKIP][35] ([i915#4525]) -> [PASS][36] +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-iclb6/igt@gem_exec_balancer@parallel-contexts.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][37] ([i915#2842]) -> [PASS][38] +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-iclb:         [FAIL][39] ([i915#2842]) -> [PASS][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-iclb7/igt@gem_exec_fair@basic-pace@vecs0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb2/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - {shard-rkl}:        [SKIP][41] ([fdo#109313]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-rkl-1/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-rkl-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_exec_reloc@basic-range:
    - {shard-rkl}:        [SKIP][43] ([i915#3281]) -> [PASS][44] +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-rkl-1/igt@gem_exec_reloc@basic-range.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-rkl-5/igt@gem_exec_reloc@basic-range.html

  * igt@gem_exec_schedule@wide@rcs0:
    - {shard-tglu}:       [INCOMPLETE][45] ([i915#6772]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-tglu-1/igt@gem_exec_schedule@wide@rcs0.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-tglu-2/igt@gem_exec_schedule@wide@rcs0.html

  * igt@gem_partial_pwrite_pread@write-uncached:
    - {shard-rkl}:        [SKIP][47] ([i915#3282]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-rkl-1/igt@gem_partial_pwrite_pread@write-uncached.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-rkl-5/igt@gem_partial_pwrite_pread@write-uncached.html

  * igt@gen9_exec_parse@shadow-peek:
    - {shard-rkl}:        [SKIP][49] ([i915#2527]) -> [PASS][50] +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-rkl-6/igt@gen9_exec_parse@shadow-peek.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-rkl-5/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [SKIP][51] ([i915#4281]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb4/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
    - {shard-tglu}:       [WARN][53] ([i915#2681]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-tglu-2/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html

  * igt@i915_pm_rps@engine-order:
    - shard-apl:          [FAIL][55] ([i915#6537]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-apl4/igt@i915_pm_rps@engine-order.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl7/igt@i915_pm_rps@engine-order.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
    - shard-apl:          [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-iclb:         [SKIP][59] ([i915#3555]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_psr@psr2_sprite_plane_onoff:
    - shard-iclb:         [SKIP][61] ([fdo#109441]) -> [PASS][62] +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-iclb1/igt@kms_psr@psr2_sprite_plane_onoff.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html

  * igt@perf@polling-parameterized:
    - shard-apl:          [FAIL][63] ([i915#5639]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-apl6/igt@perf@polling-parameterized.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl4/igt@perf@polling-parameterized.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-tglb:         [FAIL][65] ([i915#2876]) -> [FAIL][66] ([i915#2842])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-tglb6/igt@gem_exec_fair@basic-pace@bcs0.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
    - shard-iclb:         [SKIP][67] ([i915#2920]) -> [SKIP][68] ([fdo#111068] / [i915#658])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
    - shard-iclb:         [SKIP][69] ([i915#658]) -> [SKIP][70] ([i915#2920])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][71], [FAIL][72], [FAIL][73], [FAIL][74]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][75], [FAIL][76], [FAIL][77], [FAIL][78]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-apl6/igt@runner@aborted.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-apl1/igt@runner@aborted.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-apl3/igt@runner@aborted.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12144/shard-apl8/igt@runner@aborted.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl8/igt@runner@aborted.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl1/igt@runner@aborted.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl1/igt@runner@aborted.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/shard-apl6/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2876]: https://gitlab.freedesktop.org/drm/intel/issues/2876
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
  [i915#6016]: https://gitlab.freedesktop.org/drm/intel/issues/6016
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
  [i915#6772]: https://gitlab.freedesktop.org/drm/intel/issues/6772
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * Linux: CI_DRM_12144 -> Patchwork_106786v10

  CI-20190529: 20190529
  CI_DRM_12144: 55937d402fd885fe101cdd028dcc48df6d7f6b35 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_106786v10: 55937d402fd885fe101cdd028dcc48df6d7f6b35 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v10/index.html

[-- Attachment #2: Type: text/html, Size: 22726 bytes --]

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Initial Meteorlake Support (rev11)

[Patchwork]

== Series Details ==

Series: Initial Meteorlake Support (rev11)
URL   : https://patchwork.freedesktop.org/series/106786/
State : failure

== Summary ==

Error: patch https://patchwork.freedesktop.org/api/1.0/series/106786/revisions/11/mbox/ not applied
Applying: drm/i915: Read graphics/media/display arch version from hw
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/gt/intel_gt_regs.h
M	drivers/gpu/drm/i915/i915_driver.c
M	drivers/gpu/drm/i915/i915_drv.h
M	drivers/gpu/drm/i915/i915_pci.c
M	drivers/gpu/drm/i915/i915_reg.h
M	drivers/gpu/drm/i915/intel_device_info.c
M	drivers/gpu/drm/i915/intel_device_info.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_device_info.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_device_info.h
Auto-merging drivers/gpu/drm/i915/intel_device_info.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_device_info.c
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Auto-merging drivers/gpu/drm/i915/i915_pci.c
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Auto-merging drivers/gpu/drm/i915/i915_driver.c
Auto-merging drivers/gpu/drm/i915/gt/intel_gt_regs.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_gt_regs.h
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915: Read graphics/media/display arch version from hw
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

[PATCH v4.1] drm/i915/mtl: Define engine context layouts

[Radhakrishna Sripada]

From: Matt Roper <matthew.d.roper@intel.com>

The part of the media and blitter engine contexts that we care about for
setting up an initial state on MTL are nearly similar to DG2 (and PVC).
The difference being PRT_BB_STATE being replaced with NOP.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Add missing nop in xcs offsets(Bala)
v3:
 - Fix the spacing for nop in xcs offset(MattR)
v4:
 - Fix rcs register offset(MattR)
v4.1:
 - Fix commit message(Lucas)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Licas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
 1 file changed, 82 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 82d899f170fb..e84ef3859934 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+	NOP(1),
+	LRI(13, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	NOP(4),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	END
+};
+
 static const u8 gen8_rcs_offsets[] = {
 	NOP(1),
 	LRI(14, POSTED),
@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+	NOP(1),
+	LRI(15, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	REG(0x120),
+	REG(0x124),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	NOP(2),
+	LRI(2, POSTED),
+	REG16(0x5a8),
+	REG16(0x5ac),
+
+	NOP(6),
+	LRI(1, 0),
+	REG(0x0c8),
+
+	END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		   !intel_engine_has_relative_mmio(engine));
 
 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_rcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_rcs_offsets;
 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
 			return xehp_rcs_offsets;
@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		else
 			return gen8_rcs_offsets;
 	} else {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_xcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_xcs_offsets;
 		else if (GRAPHICS_VER(engine->i915) >= 12)
 			return gen12_xcs_offsets;
-- 
2.34.1

Re: [PATCH v4.1] drm/i915/mtl: Define engine context layouts

[Lucas De Marchi]

On Wed, Sep 28, 2022 at 08:55:11AM -0700, Radhakrishna Sripada wrote:
>From: Matt Roper <matthew.d.roper@intel.com>
>
>The part of the media and blitter engine contexts that we care about for
>setting up an initial state on MTL are nearly similar to DG2 (and PVC).
>The difference being PRT_BB_STATE being replaced with NOP.
>
>For render/compute engines, the part of the context images are nearly
>the same, although the layout had a very slight change --- one POSH
>register was removed and the placement of some LRI/noops adjusted
>slightly to compensate.
>
>v2:
> - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> - Add missing nop in xcs offsets(Bala)
>v3:
> - Fix the spacing for nop in xcs offset(MattR)
>v4:
> - Fix rcs register offset(MattR)
>v4.1:
> - Fix commit message(Lucas)
>
>Bspec: 46261, 46260, 45585
>Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>Cc: Licas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

RE: [PATCH v4.1] drm/i915/mtl: Define engine context layouts

[Sripada, Radhakrishna]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Thursday, September 29, 2022 5:11 PM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: Re: [PATCH v4.1] drm/i915/mtl: Define engine context layouts
> 
> On Wed, Sep 28, 2022 at 08:55:11AM -0700, Radhakrishna Sripada wrote:
> >From: Matt Roper <matthew.d.roper@intel.com>
> >
> >The part of the media and blitter engine contexts that we care about for
> >setting up an initial state on MTL are nearly similar to DG2 (and PVC).
> >The difference being PRT_BB_STATE being replaced with NOP.
> >
> >For render/compute engines, the part of the context images are nearly
> >the same, although the layout had a very slight change --- one POSH
> >register was removed and the placement of some LRI/noops adjusted
> >slightly to compensate.
> >
> >v2:
> > - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> > - Add missing nop in xcs offsets(Bala)
> >v3:
> > - Fix the spacing for nop in xcs offset(MattR)
> >v4:
> > - Fix rcs register offset(MattR)
> >v4.1:
> > - Fix commit message(Lucas)
> >
> >Bspec: 46261, 46260, 45585
> >Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> >Cc: Licas De Marchi <lucas.demarchi@intel.com>
> >Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> >Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> 
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Pushed the patch, Thanks for the review.

-Radhakrishna Sripada
> 
> Lucas De Marchi

[PATCH v4 04/11] drm/i915/mtl: Define engine context layouts

[Radhakrishna Sripada]

From: Matt Roper <matthew.d.roper@intel.com>

The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Drop unused registers in mtl rcs offsets.(Bala)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 81 ++++++++++++++++++++++++++++-
 1 file changed, 79 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 070cec4ff8a4..ecb030ee39cd 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,38 @@ static const u8 dg2_xcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+	NOP(1),
+	LRI(13, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	END
+};
+
 static const u8 gen8_rcs_offsets[] = {
 	NOP(1),
 	LRI(14, POSTED),
@@ -606,6 +638,47 @@ static const u8 dg2_rcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+       NOP(1),
+       LRI(13, POSTED),
+       REG16(0x244),
+       REG(0x034),
+       REG(0x030),
+       REG(0x038),
+       REG(0x03c),
+       REG(0x168),
+       REG(0x140),
+       REG(0x110),
+       REG(0x1c0),
+       REG(0x1c4),
+       REG(0x1c8),
+       REG(0x180),
+       REG16(0x2b4),
+
+       NOP(1),
+       LRI(9, POSTED),
+       REG16(0x3a8),
+       REG16(0x28c),
+       REG16(0x288),
+       REG16(0x284),
+       REG16(0x280),
+       REG16(0x27c),
+       REG16(0x278),
+       REG16(0x274),
+       REG16(0x270),
+
+       NOP(2),
+       LRI(2, POSTED),
+       REG16(0x5a8),
+       REG16(0x5ac),
+
+       NOP(6),
+       LRI(1, 0),
+       REG(0x0c8),
+
+       END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +697,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		   !intel_engine_has_relative_mmio(engine));
 
 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_rcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_rcs_offsets;
 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
 			return xehp_rcs_offsets;
@@ -637,7 +712,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		else
 			return gen8_rcs_offsets;
 	} else {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_xcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_xcs_offsets;
 		else if (GRAPHICS_VER(engine->i915) >= 12)
 			return gen12_xcs_offsets;
-- 
2.34.1

[PATCH v4.1] drm/i915/mtl: Define engine context layouts

[Radhakrishna Sripada]

From: Matt Roper <matthew.d.roper@intel.com>

The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Drop unused registers in mtl rcs offsets.(Bala)
 - Add missing nop in xcs offsets(Bala)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 82 ++++++++++++++++++++++++++++-
 1 file changed, 80 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 070cec4ff8a4..a2247d39bdb7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+	NOP(1),
+	LRI(13, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	NOP(1),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	END
+};
+
 static const u8 gen8_rcs_offsets[] = {
 	NOP(1),
 	LRI(14, POSTED),
@@ -606,6 +639,47 @@ static const u8 dg2_rcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+       NOP(1),
+       LRI(13, POSTED),
+       REG16(0x244),
+       REG(0x034),
+       REG(0x030),
+       REG(0x038),
+       REG(0x03c),
+       REG(0x168),
+       REG(0x140),
+       REG(0x110),
+       REG(0x1c0),
+       REG(0x1c4),
+       REG(0x1c8),
+       REG(0x180),
+       REG16(0x2b4),
+
+       NOP(1),
+       LRI(9, POSTED),
+       REG16(0x3a8),
+       REG16(0x28c),
+       REG16(0x288),
+       REG16(0x284),
+       REG16(0x280),
+       REG16(0x27c),
+       REG16(0x278),
+       REG16(0x274),
+       REG16(0x270),
+
+       NOP(2),
+       LRI(2, POSTED),
+       REG16(0x5a8),
+       REG16(0x5ac),
+
+       NOP(6),
+       LRI(1, 0),
+       REG(0x0c8),
+
+       END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +698,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		   !intel_engine_has_relative_mmio(engine));
 
 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_rcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_rcs_offsets;
 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
 			return xehp_rcs_offsets;
@@ -637,7 +713,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		else
 			return gen8_rcs_offsets;
 	} else {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_xcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_xcs_offsets;
 		else if (GRAPHICS_VER(engine->i915) >= 12)
 			return gen12_xcs_offsets;
-- 
2.34.1