From: Serge Semin <Sergey.Semin@baikalelectronics.ru> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Michal Simek <michal.simek@xilinx.com>, Borislav Petkov <bp@alien8.de>, Mauro Carvalho Chehab <mchehab@kernel.org>, Tony Luck <tony.luck@intel.com>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, Serge Semin <fancer.lancer@gmail.com> Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>, Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>, Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>, Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>, Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>, Manish Narani <manish.narani@xilinx.com>, Dinh Nguyen <dinguyen@kernel.org>, James Morse <james.morse@arm.com>, Robert Richter <rric@kernel.org>, Rob Herring <robh@kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v3 02/13] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema Date: Fri, 30 Sep 2022 02:41:10 +0300 [thread overview] Message-ID: <20220929234121.13955-3-Sergey.Semin@baikalelectronics.ru> (raw) In-Reply-To: <20220929234121.13955-1-Sergey.Semin@baikalelectronics.ru> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There are individual IRQs for each ECC and DFI events. The dedicated scrubber clock source is absent since it's fully synchronous to the core clock. In addition to that the DFI-DDR PHY CSRs can be accessed via a separate registers space. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Rob Herring <robh@kernel.org> --- Changelog v2: - Keep the alphabetically ordered compatible strings list. (@Krzysztof) - Fix grammar nitpicks in the patch log. (@Krzysztof) - Drop the PHY CSR region. (@Rob) - Move the device bindings to the separate DT-schema. --- .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml new file mode 100644 index 000000000000..80353a0a676f --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-ddrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 DDR Controller + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: + Baikal-T1 DDRC is based on the DW uMCTL2 DDRC IP-core v2.51a with DDR2 + and DDR3 protocol capability, 32-bit data bus + 8-bit ECC + up to 2 + SDRAM ranks. There are individual IRQs for each ECC and DFI events. + The dedicated scrubber clock source is absent since it's fully + synchronous to the core clock. + +allOf: + - $ref: /schemas/memory-controllers/snps,dw-umctl2-common.yaml# + +properties: + compatible: + const: baikal,bt1-ddrc + + reg: + maxItems: 1 + + interrupts: + maxItems: 4 + + interrupt-names: + items: + - const: dfi_e + - const: ecc_ce + - const: ecc_ue + - const: ecc_sbr + + clocks: + maxItems: 3 + + clock-names: + items: + - const: pclk + - const: aclk + - const: core + + resets: + maxItems: 2 + + reset-names: + items: + - const: arst + - const: core + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/clock/bt1-ccu.h> + #include <dt-bindings/reset/bt1-ccu.h> + + memory-controller@1f042000 { + compatible = "baikal,bt1-ddrc"; + reg = <0x1f042000 0x1000>; + + interrupts = <GIC_SHARED 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 99 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dfi_e", "ecc_ce", "ecc_ue", "ecc_sbr"; + + clocks = <&ccu_sys CCU_SYS_APB_CLK>, + <&ccu_axi CCU_AXI_DDR_CLK>, + <&ccu_pll CCU_DDR_PLL>; + clock-names = "pclk", "aclk", "core"; + + resets = <&ccu_axi CCU_AXI_DDR_RST>, + <&ccu_sys CCU_SYS_DDR_INIT_RST>; + reset-names = "arst", "core"; + }; +... -- 2.37.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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From: Serge Semin <Sergey.Semin@baikalelectronics.ru> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Michal Simek <michal.simek@xilinx.com>, Borislav Petkov <bp@alien8.de>, Mauro Carvalho Chehab <mchehab@kernel.org>, Tony Luck <tony.luck@intel.com>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, Serge Semin <fancer.lancer@gmail.com> Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>, Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>, Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>, Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>, Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>, Manish Narani <manish.narani@xilinx.com>, Dinh Nguyen <dinguyen@kernel.org>, James Morse <james.morse@arm.com>, Robert Richter <rric@kernel.org>, Rob Herring <robh@kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v3 02/13] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema Date: Fri, 30 Sep 2022 02:41:10 +0300 [thread overview] Message-ID: <20220929234121.13955-3-Sergey.Semin@baikalelectronics.ru> (raw) In-Reply-To: <20220929234121.13955-1-Sergey.Semin@baikalelectronics.ru> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There are individual IRQs for each ECC and DFI events. The dedicated scrubber clock source is absent since it's fully synchronous to the core clock. In addition to that the DFI-DDR PHY CSRs can be accessed via a separate registers space. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Rob Herring <robh@kernel.org> --- Changelog v2: - Keep the alphabetically ordered compatible strings list. (@Krzysztof) - Fix grammar nitpicks in the patch log. (@Krzysztof) - Drop the PHY CSR region. (@Rob) - Move the device bindings to the separate DT-schema. --- .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml new file mode 100644 index 000000000000..80353a0a676f --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-ddrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 DDR Controller + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: + Baikal-T1 DDRC is based on the DW uMCTL2 DDRC IP-core v2.51a with DDR2 + and DDR3 protocol capability, 32-bit data bus + 8-bit ECC + up to 2 + SDRAM ranks. There are individual IRQs for each ECC and DFI events. + The dedicated scrubber clock source is absent since it's fully + synchronous to the core clock. + +allOf: + - $ref: /schemas/memory-controllers/snps,dw-umctl2-common.yaml# + +properties: + compatible: + const: baikal,bt1-ddrc + + reg: + maxItems: 1 + + interrupts: + maxItems: 4 + + interrupt-names: + items: + - const: dfi_e + - const: ecc_ce + - const: ecc_ue + - const: ecc_sbr + + clocks: + maxItems: 3 + + clock-names: + items: + - const: pclk + - const: aclk + - const: core + + resets: + maxItems: 2 + + reset-names: + items: + - const: arst + - const: core + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/clock/bt1-ccu.h> + #include <dt-bindings/reset/bt1-ccu.h> + + memory-controller@1f042000 { + compatible = "baikal,bt1-ddrc"; + reg = <0x1f042000 0x1000>; + + interrupts = <GIC_SHARED 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 99 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dfi_e", "ecc_ce", "ecc_ue", "ecc_sbr"; + + clocks = <&ccu_sys CCU_SYS_APB_CLK>, + <&ccu_axi CCU_AXI_DDR_CLK>, + <&ccu_pll CCU_DDR_PLL>; + clock-names = "pclk", "aclk", "core"; + + resets = <&ccu_axi CCU_AXI_DDR_RST>, + <&ccu_sys CCU_SYS_DDR_INIT_RST>; + reset-names = "arst", "core"; + }; +... -- 2.37.3
next prev parent reply other threads:[~2022-09-30 0:00 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-29 23:41 [PATCH v3 00/13] EDAC/synopsys: Add generic resources and Baikal-T1 support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 01/13] dt-bindings: memory: snps: Convert the schema to being generic Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-10-05 13:12 ` Rob Herring 2022-10-05 13:12 ` Rob Herring 2022-09-29 23:41 ` Serge Semin [this message] 2022-09-29 23:41 ` [PATCH v3 02/13] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema Serge Semin 2022-10-03 13:24 ` Rob Herring 2022-10-03 13:24 ` Rob Herring 2022-10-05 14:59 ` Krzysztof Kozlowski 2022-10-05 14:59 ` Krzysztof Kozlowski 2022-10-06 12:26 ` Serge Semin 2022-10-06 12:26 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 03/13] EDAC/synopsys: Add multi-ranked memory support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 04/13] EDAC/synopsys: Add optional ECC Scrub support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 05/13] EDAC/synopsys: Drop ECC poison address from private data Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 06/13] EDAC/synopsys: Add data poisoning disable support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 07/13] EDAC/synopsys: Split up ECC UE/CE IRQs handler Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 08/13] EDAC/synopsys: Add individual named ECC IRQs support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 09/13] EDAC/synopsys: Add DFI alert_n IRQ support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 10/13] EDAC/synopsys: Add reference clocks support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 11/13] EDAC/synopsys: Add ECC Scrubber support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 12/13] EDAC/synopsys: Drop vendor-specific arch dependency Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 13/13] EDAC/synopsys: Add Baikal-T1 DDRC support Serge Semin 2022-09-29 23:41 ` Serge Semin
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