* [PATCH] drm/i915/slpc: Update frequency debugfs for SLPC
@ 2022-10-01 0:41 ` Vinay Belgaumkar
0 siblings, 0 replies; 6+ messages in thread
From: Vinay Belgaumkar @ 2022-10-01 0:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Vinay Belgaumkar
Create a wrapper to print out the frequency debugfs for
SLPC and non-SLPC cases. Most of the RPS related information
is no longer valid when SLPC is enabled.
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 157 +-------------
drivers/gpu/drm/i915/gt/intel_rps.c | 205 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
3 files changed, 208 insertions(+), 156 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 9fd4d9255a97..d5afa08c54e3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -344,162 +344,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
drm_printf(p, "efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(rps, rps->efficient_freq));
} else if (GRAPHICS_VER(i915) >= 6) {
- u32 rp_state_limits;
- u32 gt_perf_status;
- struct intel_rps_freq_caps caps;
- u32 rpmodectl, rpinclimit, rpdeclimit;
- u32 rpstat, cagf, reqf;
- u32 rpcurupei, rpcurup, rpprevup;
- u32 rpcurdownei, rpcurdown, rpprevdown;
- u32 rpupei, rpupt, rpdownei, rpdownt;
- u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
-
- rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
- gen6_rps_get_freq_caps(rps, &caps);
- if (IS_GEN9_LP(i915))
- gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
- else
- gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
-
- /* RPSTAT1 is in the GT power well */
- intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
-
- reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
- if (GRAPHICS_VER(i915) >= 9) {
- reqf >>= 23;
- } else {
- reqf &= ~GEN6_TURBO_DISABLE;
- if (IS_HASWELL(i915) || IS_BROADWELL(i915))
- reqf >>= 24;
- else
- reqf >>= 25;
- }
- reqf = intel_gpu_freq(rps, reqf);
-
- rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
- rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
- rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
-
- rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
- rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
- rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
- rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
- rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
- rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
- rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
-
- rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
- rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
-
- rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
- rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
-
- cagf = intel_rps_read_actual_frequency(rps);
-
- intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
-
- if (GRAPHICS_VER(i915) >= 11) {
- pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
- pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
- /*
- * The equivalent to the PM ISR & IIR cannot be read
- * without affecting the current state of the system
- */
- pm_isr = 0;
- pm_iir = 0;
- } else if (GRAPHICS_VER(i915) >= 8) {
- pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
- pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
- pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
- pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
- } else {
- pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
- pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
- pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
- pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
- }
- pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
-
- drm_printf(p, "Video Turbo Mode: %s\n",
- str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
- drm_printf(p, "HW control enabled: %s\n",
- str_yes_no(rpmodectl & GEN6_RP_ENABLE));
- drm_printf(p, "SW control enabled: %s\n",
- str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
-
- drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
- pm_ier, pm_imr, pm_mask);
- if (GRAPHICS_VER(i915) <= 10)
- drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n",
- pm_isr, pm_iir);
- drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
- rps->pm_intrmsk_mbz);
- drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
- drm_printf(p, "Render p-state ratio: %d\n",
- (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
- drm_printf(p, "Render p-state VID: %d\n",
- gt_perf_status & 0xff);
- drm_printf(p, "Render p-state limit: %d\n",
- rp_state_limits & 0xff);
- drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat);
- drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl);
- drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit);
- drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
- drm_printf(p, "RPNSWREQ: %dMHz\n", reqf);
- drm_printf(p, "CAGF: %dMHz\n", cagf);
- drm_printf(p, "RP CUR UP EI: %d (%lldns)\n",
- rpcurupei,
- intel_gt_pm_interval_to_ns(gt, rpcurupei));
- drm_printf(p, "RP CUR UP: %d (%lldns)\n",
- rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
- drm_printf(p, "RP PREV UP: %d (%lldns)\n",
- rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
- drm_printf(p, "Up threshold: %d%%\n",
- rps->power.up_threshold);
- drm_printf(p, "RP UP EI: %d (%lldns)\n",
- rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
- drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n",
- rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
-
- drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n",
- rpcurdownei,
- intel_gt_pm_interval_to_ns(gt, rpcurdownei));
- drm_printf(p, "RP CUR DOWN: %d (%lldns)\n",
- rpcurdown,
- intel_gt_pm_interval_to_ns(gt, rpcurdown));
- drm_printf(p, "RP PREV DOWN: %d (%lldns)\n",
- rpprevdown,
- intel_gt_pm_interval_to_ns(gt, rpprevdown));
- drm_printf(p, "Down threshold: %d%%\n",
- rps->power.down_threshold);
- drm_printf(p, "RP DOWN EI: %d (%lldns)\n",
- rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
- drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n",
- rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
-
- drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
- intel_gpu_freq(rps, caps.min_freq));
- drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
- intel_gpu_freq(rps, caps.rp1_freq));
- drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
- intel_gpu_freq(rps, caps.rp0_freq));
- drm_printf(p, "Max overclocked frequency: %dMHz\n",
- intel_gpu_freq(rps, rps->max_freq));
-
- drm_printf(p, "Current freq: %d MHz\n",
- intel_gpu_freq(rps, rps->cur_freq));
- drm_printf(p, "Actual freq: %d MHz\n", cagf);
- drm_printf(p, "Idle freq: %d MHz\n",
- intel_gpu_freq(rps, rps->idle_freq));
- drm_printf(p, "Min freq: %d MHz\n",
- intel_gpu_freq(rps, rps->min_freq));
- drm_printf(p, "Boost freq: %d MHz\n",
- intel_gpu_freq(rps, rps->boost_freq));
- drm_printf(p, "Max freq: %d MHz\n",
- intel_gpu_freq(rps, rps->max_freq));
- drm_printf(p,
- "efficient (RPe) frequency: %d MHz\n",
- intel_gpu_freq(rps, rps->efficient_freq));
+ gen6_rps_frequency_dump(rps, p);
} else {
drm_puts(p, "no P-state info available\n");
}
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 17b40b625e31..d0847bd4b90f 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2219,6 +2219,211 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)
return intel_gpu_freq(rps, rps->min_freq);
}
+static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_rps_freq_caps caps;
+ u32 pm_mask;
+
+ gen6_rps_get_freq_caps(rps, &caps);
+ pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
+
+ drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
+ drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1));
+ drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps));
+ drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.min_freq));
+ drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.rp1_freq));
+ drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.rp0_freq));
+ drm_printf(p, "Current freq: %d MHz\n",
+ intel_rps_get_requested_frequency(rps));
+ drm_printf(p, "Actual freq: %d MHz\n",
+ intel_rps_read_actual_frequency(rps));
+ drm_printf(p, "Min freq: %d MHz\n",
+ intel_rps_get_min_frequency(rps));
+ drm_printf(p, "Boost freq: %d MHz\n",
+ intel_rps_get_boost_frequency(rps));
+ drm_printf(p, "Max freq: %d MHz\n",
+ intel_rps_get_max_frequency(rps));
+ drm_printf(p,
+ "efficient (RPe) frequency: %d MHz\n",
+ intel_gpu_freq(rps, caps.rp1_freq));
+}
+
+static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_rps_freq_caps caps;
+ u32 rp_state_limits;
+ u32 gt_perf_status;
+ u32 rpmodectl, rpinclimit, rpdeclimit;
+ u32 rpstat, cagf, reqf;
+ u32 rpcurupei, rpcurup, rpprevup;
+ u32 rpcurdownei, rpcurdown, rpprevdown;
+ u32 rpupei, rpupt, rpdownei, rpdownt;
+ u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
+
+ rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
+ gen6_rps_get_freq_caps(rps, &caps);
+ if (IS_GEN9_LP(i915))
+ gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
+ else
+ gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
+
+ /* RPSTAT1 is in the GT power well */
+ intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
+
+ reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
+ if (GRAPHICS_VER(i915) >= 9) {
+ reqf >>= 23;
+ } else {
+ reqf &= ~GEN6_TURBO_DISABLE;
+ if (IS_HASWELL(i915) || IS_BROADWELL(i915))
+ reqf >>= 24;
+ else
+ reqf >>= 25;
+ }
+ reqf = intel_gpu_freq(rps, reqf);
+
+ rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
+ rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
+ rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
+
+ rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
+ rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
+ rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
+ rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
+ rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
+ rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
+ rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
+
+ rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
+ rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
+
+ rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
+ rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
+
+ cagf = intel_rps_read_actual_frequency(rps);
+
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
+
+ if (GRAPHICS_VER(i915) >= 11) {
+ pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+ pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
+ /*
+ * The equivalent to the PM ISR & IIR cannot be read
+ * without affecting the current state of the system
+ */
+ pm_isr = 0;
+ pm_iir = 0;
+ } else if (GRAPHICS_VER(i915) >= 8) {
+ pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
+ pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
+ pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
+ pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
+ } else {
+ pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
+ pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
+ pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
+ pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
+ }
+ pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
+
+ drm_printf(p, "Video Turbo Mode: %s\n",
+ str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
+ drm_printf(p, "HW control enabled: %s\n",
+ str_yes_no(rpmodectl & GEN6_RP_ENABLE));
+ drm_printf(p, "SW control enabled: %s\n",
+ str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
+
+ drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
+ pm_ier, pm_imr, pm_mask);
+ if (GRAPHICS_VER(i915) <= 10)
+ drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n",
+ pm_isr, pm_iir);
+ drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
+ rps->pm_intrmsk_mbz);
+ drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
+ drm_printf(p, "Render p-state ratio: %d\n",
+ (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
+ drm_printf(p, "Render p-state VID: %d\n",
+ gt_perf_status & 0xff);
+ drm_printf(p, "Render p-state limit: %d\n",
+ rp_state_limits & 0xff);
+ drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat);
+ drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl);
+ drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit);
+ drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
+ drm_printf(p, "RPNSWREQ: %dMHz\n", reqf);
+ drm_printf(p, "CAGF: %dMHz\n", cagf);
+ drm_printf(p, "RP CUR UP EI: %d (%lldns)\n",
+ rpcurupei,
+ intel_gt_pm_interval_to_ns(gt, rpcurupei));
+ drm_printf(p, "RP CUR UP: %d (%lldns)\n",
+ rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
+ drm_printf(p, "RP PREV UP: %d (%lldns)\n",
+ rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
+ drm_printf(p, "Up threshold: %d%%\n",
+ rps->power.up_threshold);
+ drm_printf(p, "RP UP EI: %d (%lldns)\n",
+ rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
+ drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n",
+ rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
+
+ drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n",
+ rpcurdownei,
+ intel_gt_pm_interval_to_ns(gt, rpcurdownei));
+ drm_printf(p, "RP CUR DOWN: %d (%lldns)\n",
+ rpcurdown,
+ intel_gt_pm_interval_to_ns(gt, rpcurdown));
+ drm_printf(p, "RP PREV DOWN: %d (%lldns)\n",
+ rpprevdown,
+ intel_gt_pm_interval_to_ns(gt, rpprevdown));
+ drm_printf(p, "Down threshold: %d%%\n",
+ rps->power.down_threshold);
+ drm_printf(p, "RP DOWN EI: %d (%lldns)\n",
+ rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
+ drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n",
+ rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
+
+ drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.min_freq));
+ drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.rp1_freq));
+ drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.rp0_freq));
+ drm_printf(p, "Max overclocked frequency: %dMHz\n",
+ intel_gpu_freq(rps, rps->max_freq));
+
+ drm_printf(p, "Current freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->cur_freq));
+ drm_printf(p, "Actual freq: %d MHz\n", cagf);
+ drm_printf(p, "Idle freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->idle_freq));
+ drm_printf(p, "Min freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->min_freq));
+ drm_printf(p, "Boost freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->boost_freq));
+ drm_printf(p, "Max freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->max_freq));
+ drm_printf(p,
+ "efficient (RPe) frequency: %d MHz\n",
+ intel_gpu_freq(rps, rps->efficient_freq));
+}
+
+void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
+{
+ if (rps_uses_slpc(rps))
+ return slpc_frequency_dump(rps, p);
+ else
+ return rps_frequency_dump(rps, p);
+}
+
static int set_max_freq(struct intel_rps *rps, u32 val)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index 4509dfdc52e0..c408c26c5192 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -10,6 +10,7 @@
#include "i915_reg_defs.h"
struct i915_request;
+struct drm_printer;
void intel_rps_init_early(struct intel_rps *rps);
void intel_rps_init(struct intel_rps *rps);
@@ -54,6 +55,7 @@ void intel_rps_lower_unslice(struct intel_rps *rps);
u32 intel_rps_read_throttle_reason(struct intel_rps *rps);
bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);
+void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p);
void gen5_rps_irq_handler(struct intel_rps *rps);
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
--
2.35.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/slpc: Update frequency debugfs for SLPC
@ 2022-10-01 0:41 ` Vinay Belgaumkar
0 siblings, 0 replies; 6+ messages in thread
From: Vinay Belgaumkar @ 2022-10-01 0:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Create a wrapper to print out the frequency debugfs for
SLPC and non-SLPC cases. Most of the RPS related information
is no longer valid when SLPC is enabled.
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 157 +-------------
drivers/gpu/drm/i915/gt/intel_rps.c | 205 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
3 files changed, 208 insertions(+), 156 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 9fd4d9255a97..d5afa08c54e3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -344,162 +344,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
drm_printf(p, "efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(rps, rps->efficient_freq));
} else if (GRAPHICS_VER(i915) >= 6) {
- u32 rp_state_limits;
- u32 gt_perf_status;
- struct intel_rps_freq_caps caps;
- u32 rpmodectl, rpinclimit, rpdeclimit;
- u32 rpstat, cagf, reqf;
- u32 rpcurupei, rpcurup, rpprevup;
- u32 rpcurdownei, rpcurdown, rpprevdown;
- u32 rpupei, rpupt, rpdownei, rpdownt;
- u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
-
- rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
- gen6_rps_get_freq_caps(rps, &caps);
- if (IS_GEN9_LP(i915))
- gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
- else
- gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
-
- /* RPSTAT1 is in the GT power well */
- intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
-
- reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
- if (GRAPHICS_VER(i915) >= 9) {
- reqf >>= 23;
- } else {
- reqf &= ~GEN6_TURBO_DISABLE;
- if (IS_HASWELL(i915) || IS_BROADWELL(i915))
- reqf >>= 24;
- else
- reqf >>= 25;
- }
- reqf = intel_gpu_freq(rps, reqf);
-
- rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
- rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
- rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
-
- rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
- rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
- rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
- rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
- rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
- rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
- rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
-
- rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
- rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
-
- rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
- rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
-
- cagf = intel_rps_read_actual_frequency(rps);
-
- intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
-
- if (GRAPHICS_VER(i915) >= 11) {
- pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
- pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
- /*
- * The equivalent to the PM ISR & IIR cannot be read
- * without affecting the current state of the system
- */
- pm_isr = 0;
- pm_iir = 0;
- } else if (GRAPHICS_VER(i915) >= 8) {
- pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
- pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
- pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
- pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
- } else {
- pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
- pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
- pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
- pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
- }
- pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
-
- drm_printf(p, "Video Turbo Mode: %s\n",
- str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
- drm_printf(p, "HW control enabled: %s\n",
- str_yes_no(rpmodectl & GEN6_RP_ENABLE));
- drm_printf(p, "SW control enabled: %s\n",
- str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
-
- drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
- pm_ier, pm_imr, pm_mask);
- if (GRAPHICS_VER(i915) <= 10)
- drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n",
- pm_isr, pm_iir);
- drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
- rps->pm_intrmsk_mbz);
- drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
- drm_printf(p, "Render p-state ratio: %d\n",
- (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
- drm_printf(p, "Render p-state VID: %d\n",
- gt_perf_status & 0xff);
- drm_printf(p, "Render p-state limit: %d\n",
- rp_state_limits & 0xff);
- drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat);
- drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl);
- drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit);
- drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
- drm_printf(p, "RPNSWREQ: %dMHz\n", reqf);
- drm_printf(p, "CAGF: %dMHz\n", cagf);
- drm_printf(p, "RP CUR UP EI: %d (%lldns)\n",
- rpcurupei,
- intel_gt_pm_interval_to_ns(gt, rpcurupei));
- drm_printf(p, "RP CUR UP: %d (%lldns)\n",
- rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
- drm_printf(p, "RP PREV UP: %d (%lldns)\n",
- rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
- drm_printf(p, "Up threshold: %d%%\n",
- rps->power.up_threshold);
- drm_printf(p, "RP UP EI: %d (%lldns)\n",
- rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
- drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n",
- rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
-
- drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n",
- rpcurdownei,
- intel_gt_pm_interval_to_ns(gt, rpcurdownei));
- drm_printf(p, "RP CUR DOWN: %d (%lldns)\n",
- rpcurdown,
- intel_gt_pm_interval_to_ns(gt, rpcurdown));
- drm_printf(p, "RP PREV DOWN: %d (%lldns)\n",
- rpprevdown,
- intel_gt_pm_interval_to_ns(gt, rpprevdown));
- drm_printf(p, "Down threshold: %d%%\n",
- rps->power.down_threshold);
- drm_printf(p, "RP DOWN EI: %d (%lldns)\n",
- rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
- drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n",
- rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
-
- drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
- intel_gpu_freq(rps, caps.min_freq));
- drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
- intel_gpu_freq(rps, caps.rp1_freq));
- drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
- intel_gpu_freq(rps, caps.rp0_freq));
- drm_printf(p, "Max overclocked frequency: %dMHz\n",
- intel_gpu_freq(rps, rps->max_freq));
-
- drm_printf(p, "Current freq: %d MHz\n",
- intel_gpu_freq(rps, rps->cur_freq));
- drm_printf(p, "Actual freq: %d MHz\n", cagf);
- drm_printf(p, "Idle freq: %d MHz\n",
- intel_gpu_freq(rps, rps->idle_freq));
- drm_printf(p, "Min freq: %d MHz\n",
- intel_gpu_freq(rps, rps->min_freq));
- drm_printf(p, "Boost freq: %d MHz\n",
- intel_gpu_freq(rps, rps->boost_freq));
- drm_printf(p, "Max freq: %d MHz\n",
- intel_gpu_freq(rps, rps->max_freq));
- drm_printf(p,
- "efficient (RPe) frequency: %d MHz\n",
- intel_gpu_freq(rps, rps->efficient_freq));
+ gen6_rps_frequency_dump(rps, p);
} else {
drm_puts(p, "no P-state info available\n");
}
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 17b40b625e31..d0847bd4b90f 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2219,6 +2219,211 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)
return intel_gpu_freq(rps, rps->min_freq);
}
+static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_rps_freq_caps caps;
+ u32 pm_mask;
+
+ gen6_rps_get_freq_caps(rps, &caps);
+ pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
+
+ drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
+ drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1));
+ drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps));
+ drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.min_freq));
+ drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.rp1_freq));
+ drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.rp0_freq));
+ drm_printf(p, "Current freq: %d MHz\n",
+ intel_rps_get_requested_frequency(rps));
+ drm_printf(p, "Actual freq: %d MHz\n",
+ intel_rps_read_actual_frequency(rps));
+ drm_printf(p, "Min freq: %d MHz\n",
+ intel_rps_get_min_frequency(rps));
+ drm_printf(p, "Boost freq: %d MHz\n",
+ intel_rps_get_boost_frequency(rps));
+ drm_printf(p, "Max freq: %d MHz\n",
+ intel_rps_get_max_frequency(rps));
+ drm_printf(p,
+ "efficient (RPe) frequency: %d MHz\n",
+ intel_gpu_freq(rps, caps.rp1_freq));
+}
+
+static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_rps_freq_caps caps;
+ u32 rp_state_limits;
+ u32 gt_perf_status;
+ u32 rpmodectl, rpinclimit, rpdeclimit;
+ u32 rpstat, cagf, reqf;
+ u32 rpcurupei, rpcurup, rpprevup;
+ u32 rpcurdownei, rpcurdown, rpprevdown;
+ u32 rpupei, rpupt, rpdownei, rpdownt;
+ u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
+
+ rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
+ gen6_rps_get_freq_caps(rps, &caps);
+ if (IS_GEN9_LP(i915))
+ gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
+ else
+ gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
+
+ /* RPSTAT1 is in the GT power well */
+ intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
+
+ reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
+ if (GRAPHICS_VER(i915) >= 9) {
+ reqf >>= 23;
+ } else {
+ reqf &= ~GEN6_TURBO_DISABLE;
+ if (IS_HASWELL(i915) || IS_BROADWELL(i915))
+ reqf >>= 24;
+ else
+ reqf >>= 25;
+ }
+ reqf = intel_gpu_freq(rps, reqf);
+
+ rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
+ rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
+ rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
+
+ rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
+ rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
+ rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
+ rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
+ rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
+ rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
+ rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
+
+ rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
+ rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
+
+ rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
+ rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
+
+ cagf = intel_rps_read_actual_frequency(rps);
+
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
+
+ if (GRAPHICS_VER(i915) >= 11) {
+ pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+ pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
+ /*
+ * The equivalent to the PM ISR & IIR cannot be read
+ * without affecting the current state of the system
+ */
+ pm_isr = 0;
+ pm_iir = 0;
+ } else if (GRAPHICS_VER(i915) >= 8) {
+ pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
+ pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
+ pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
+ pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
+ } else {
+ pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
+ pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
+ pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
+ pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
+ }
+ pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
+
+ drm_printf(p, "Video Turbo Mode: %s\n",
+ str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
+ drm_printf(p, "HW control enabled: %s\n",
+ str_yes_no(rpmodectl & GEN6_RP_ENABLE));
+ drm_printf(p, "SW control enabled: %s\n",
+ str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
+
+ drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
+ pm_ier, pm_imr, pm_mask);
+ if (GRAPHICS_VER(i915) <= 10)
+ drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n",
+ pm_isr, pm_iir);
+ drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
+ rps->pm_intrmsk_mbz);
+ drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
+ drm_printf(p, "Render p-state ratio: %d\n",
+ (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
+ drm_printf(p, "Render p-state VID: %d\n",
+ gt_perf_status & 0xff);
+ drm_printf(p, "Render p-state limit: %d\n",
+ rp_state_limits & 0xff);
+ drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat);
+ drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl);
+ drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit);
+ drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
+ drm_printf(p, "RPNSWREQ: %dMHz\n", reqf);
+ drm_printf(p, "CAGF: %dMHz\n", cagf);
+ drm_printf(p, "RP CUR UP EI: %d (%lldns)\n",
+ rpcurupei,
+ intel_gt_pm_interval_to_ns(gt, rpcurupei));
+ drm_printf(p, "RP CUR UP: %d (%lldns)\n",
+ rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
+ drm_printf(p, "RP PREV UP: %d (%lldns)\n",
+ rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
+ drm_printf(p, "Up threshold: %d%%\n",
+ rps->power.up_threshold);
+ drm_printf(p, "RP UP EI: %d (%lldns)\n",
+ rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
+ drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n",
+ rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
+
+ drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n",
+ rpcurdownei,
+ intel_gt_pm_interval_to_ns(gt, rpcurdownei));
+ drm_printf(p, "RP CUR DOWN: %d (%lldns)\n",
+ rpcurdown,
+ intel_gt_pm_interval_to_ns(gt, rpcurdown));
+ drm_printf(p, "RP PREV DOWN: %d (%lldns)\n",
+ rpprevdown,
+ intel_gt_pm_interval_to_ns(gt, rpprevdown));
+ drm_printf(p, "Down threshold: %d%%\n",
+ rps->power.down_threshold);
+ drm_printf(p, "RP DOWN EI: %d (%lldns)\n",
+ rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
+ drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n",
+ rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
+
+ drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.min_freq));
+ drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.rp1_freq));
+ drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
+ intel_gpu_freq(rps, caps.rp0_freq));
+ drm_printf(p, "Max overclocked frequency: %dMHz\n",
+ intel_gpu_freq(rps, rps->max_freq));
+
+ drm_printf(p, "Current freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->cur_freq));
+ drm_printf(p, "Actual freq: %d MHz\n", cagf);
+ drm_printf(p, "Idle freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->idle_freq));
+ drm_printf(p, "Min freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->min_freq));
+ drm_printf(p, "Boost freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->boost_freq));
+ drm_printf(p, "Max freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->max_freq));
+ drm_printf(p,
+ "efficient (RPe) frequency: %d MHz\n",
+ intel_gpu_freq(rps, rps->efficient_freq));
+}
+
+void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
+{
+ if (rps_uses_slpc(rps))
+ return slpc_frequency_dump(rps, p);
+ else
+ return rps_frequency_dump(rps, p);
+}
+
static int set_max_freq(struct intel_rps *rps, u32 val)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index 4509dfdc52e0..c408c26c5192 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -10,6 +10,7 @@
#include "i915_reg_defs.h"
struct i915_request;
+struct drm_printer;
void intel_rps_init_early(struct intel_rps *rps);
void intel_rps_init(struct intel_rps *rps);
@@ -54,6 +55,7 @@ void intel_rps_lower_unslice(struct intel_rps *rps);
u32 intel_rps_read_throttle_reason(struct intel_rps *rps);
bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);
+void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p);
void gen5_rps_irq_handler(struct intel_rps *rps);
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
--
2.35.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Update frequency debugfs for SLPC
2022-10-01 0:41 ` [Intel-gfx] " Vinay Belgaumkar
(?)
@ 2022-10-01 1:39 ` Patchwork
-1 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2022-10-01 1:39 UTC (permalink / raw)
To: Vinay Belgaumkar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 9923 bytes --]
== Series Details ==
Series: drm/i915/slpc: Update frequency debugfs for SLPC
URL : https://patchwork.freedesktop.org/series/109328/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12204 -> Patchwork_109328v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/index.html
Participating hosts (48 -> 45)
------------------------------
Additional (2): bat-dg2-11 fi-rkl-11600
Missing (5): fi-hsw-4200u fi-tgl-u2 fi-icl-u2 fi-ctg-p8600 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109328v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@slpc:
- {bat-rpls-2}: [DMESG-FAIL][1] ([i915#6367]) -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/bat-rpls-2/igt@i915_selftest@live@slpc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/bat-rpls-2/igt@i915_selftest@live@slpc.html
Known issues
------------
Here are the changes found in Patchwork_109328v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-bdw-gvtdvm: NOTRUN -> [SKIP][4] ([fdo#109271]) +19 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-bdw-gvtdvm/igt@gem_lmem_swapping@basic.html
- fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@gem_lmem_swapping@basic.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][6] ([i915#3282])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600: NOTRUN -> [SKIP][7] ([i915#3012])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][8] ([i915#4817])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-bdw-gvtdvm/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][9] ([i915#5982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-rkl-11600: NOTRUN -> [SKIP][10] ([fdo#111827]) +7 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600: NOTRUN -> [SKIP][11] ([i915#4103])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [PASS][12] -> [FAIL][13] ([i915#6298])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600: NOTRUN -> [SKIP][14] ([fdo#109285] / [i915#4098])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_page_flip:
- fi-rkl-11600: NOTRUN -> [SKIP][15] ([i915#1072]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@kms_psr@primary_page_flip.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#4098])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-read:
- fi-rkl-11600: NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-userptr:
- fi-rkl-11600: NOTRUN -> [SKIP][18] ([fdo#109295] / [i915#3301] / [i915#3708])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-rkl-11600/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][19] ([i915#4312])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}: [DMESG-WARN][20] ([i915#2867]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_module_load@load:
- fi-bdw-gvtdvm: [DMESG-WARN][22] ([i915#6540]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/fi-bdw-gvtdvm/igt@i915_module_load@load.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-bdw-gvtdvm/igt@i915_module_load@load.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-bdw-gvtdvm: [DMESG-WARN][24] ([i915#5922]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/fi-bdw-gvtdvm/igt@kms_force_connector_basic@force-connector-state.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/fi-bdw-gvtdvm/igt@kms_force_connector_basic@force-connector-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5922]: https://gitlab.freedesktop.org/drm/intel/issues/5922
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6540]: https://gitlab.freedesktop.org/drm/intel/issues/6540
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6816]: https://gitlab.freedesktop.org/drm/intel/issues/6816
Build changes
-------------
* Linux: CI_DRM_12204 -> Patchwork_109328v1
CI-20190529: 20190529
CI_DRM_12204: fd2f9b9a4178e667adad268a662eb8a9c0ddc8f8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6670: d618e9865fe5cbaf511ca43503abad442605d0a5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109328v1: fd2f9b9a4178e667adad268a662eb8a9c0ddc8f8 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
399349ba4f89 drm/i915/slpc: Update frequency debugfs for SLPC
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/index.html
[-- Attachment #2: Type: text/html, Size: 10071 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/slpc: Update frequency debugfs for SLPC
2022-10-01 0:41 ` [Intel-gfx] " Vinay Belgaumkar
(?)
(?)
@ 2022-10-01 20:54 ` Patchwork
-1 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2022-10-01 20:54 UTC (permalink / raw)
To: Vinay Belgaumkar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 23116 bytes --]
== Series Details ==
Series: drm/i915/slpc: Update frequency debugfs for SLPC
URL : https://patchwork.freedesktop.org/series/109328/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12204_full -> Patchwork_109328v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_109328v1_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [FAIL][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#4386]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl3/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl8/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl8/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl8/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl8/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl2/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl6/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl6/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl3/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl2/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl2/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl2/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl3/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl3/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl2/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl2/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl2/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl2/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl1/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl1/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl2/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl7/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl7/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl8/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl8/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl8/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl8/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl8/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][50] ([i915#4991])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@legacy-engines-cleanup:
- shard-snb: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#1099])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-snb2/igt@gem_ctx_persistence@legacy-engines-cleanup.html
* igt@gem_eio@reset-stress:
- shard-tglb: [PASS][52] -> [FAIL][53] ([i915#5784])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-tglb5/igt@gem_eio@reset-stress.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-tglb1/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][54] -> [FAIL][55] ([i915#2842])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#4613])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl8/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_softpin@evict-single-offset:
- shard-apl: NOTRUN -> [FAIL][57] ([i915#4171])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl8/igt@gem_softpin@evict-single-offset.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#1937])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_selftest@live@hangcheck:
- shard-iclb: [PASS][59] -> [INCOMPLETE][60] ([i915#6106])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb7/igt@i915_selftest@live@hangcheck.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb8/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][61] -> [DMESG-WARN][62] ([i915#180]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl3/igt@i915_suspend@sysfs-reader.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl1/igt@i915_suspend@sysfs-reader.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#3886]) +5 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@vga-frame-dump:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [fdo#111827]) +8 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][65] -> [FAIL][66] ([i915#79])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271]) +98 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][68] ([i915#2587] / [i915#2672])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: [PASS][69] -> [SKIP][70] ([i915#3555])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#2672]) +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-cpu:
- shard-snb: NOTRUN -> [SKIP][72] ([fdo#109271]) +38 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-snb2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][73] -> [SKIP][74] ([fdo#109441]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglb: [PASS][75] -> [SKIP][76] ([i915#5519])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-tglb8/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-tglb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
- shard-iclb: [PASS][77] -> [SKIP][78] ([i915#5519])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb8/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#533])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl8/igt@kms_vblank@pipe-d-wait-idle.html
* igt@sysfs_clients@sema-50:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2994])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [SKIP][81] ([i915#4525]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb7/igt@gem_exec_balancer@parallel-contexts.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [FAIL][83] ([i915#2842]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-glk3/igt@gem_exec_fair@basic-none@vcs0.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-glk1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [FAIL][85] ([i915#2842]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb4/igt@gem_exec_fair@basic-pace@bcs0.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb6/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][87] ([i915#2190]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-tglb2/igt@gem_huc_copy@huc-copy.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [DMESG-WARN][89] ([i915#5566] / [i915#716]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/igt@gen9_exec_parse@allowed-single.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-large:
- shard-apl: [TIMEOUT][91] ([i915#4639]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl2/igt@gen9_exec_parse@bb-large.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl1/igt@gen9_exec_parse@bb-large.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][93] ([i915#6992]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-snb4/igt@i915_selftest@live@hangcheck.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@forcewake:
- shard-apl: [DMESG-WARN][95] ([i915#180]) -> [PASS][96] +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/igt@i915_suspend@forcewake.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl8/igt@i915_suspend@forcewake.html
* igt@kms_addfb_basic@legacy-format:
- shard-tglb: [INCOMPLETE][97] ([i915#6987]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-tglb3/igt@kms_addfb_basic@legacy-format.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-tglb7/igt@kms_addfb_basic@legacy-format.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][99] ([i915#2346]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [SKIP][101] ([i915#5235]) -> [PASS][102] +2 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-iclb: [SKIP][103] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb3/igt@kms_psr2_su@page_flip-xrgb8888.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb2/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: [SKIP][105] ([fdo#109441]) -> [PASS][106] +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb3/igt@kms_psr@psr2_sprite_plane_onoff.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@perf@polling-parameterized:
- shard-tglb: [FAIL][107] ([i915#5639]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-tglb7/igt@perf@polling-parameterized.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-tglb2/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][109] ([i915#588]) -> [SKIP][110] ([i915#658])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb4/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][111] ([i915#658]) -> [SKIP][112] ([i915#2920])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb3/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][113] ([i915#2920]) -> [SKIP][114] ([i915#658])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@runner@aborted:
- shard-apl: ([FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123]) ([i915#180] / [i915#3002] / [i915#4312])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl2/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl1/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl3/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl6/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/shard-apl8/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4639]: https://gitlab.freedesktop.org/drm/intel/issues/4639
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#6106]: https://gitlab.freedesktop.org/drm/intel/issues/6106
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6987]: https://gitlab.freedesktop.org/drm/intel/issues/6987
[i915#6992]: https://gitlab.freedesktop.org/drm/intel/issues/6992
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12204 -> Patchwork_109328v1
CI-20190529: 20190529
CI_DRM_12204: fd2f9b9a4178e667adad268a662eb8a9c0ddc8f8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6670: d618e9865fe5cbaf511ca43503abad442605d0a5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109328v1: fd2f9b9a4178e667adad268a662eb8a9c0ddc8f8 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109328v1/index.html
[-- Attachment #2: Type: text/html, Size: 26427 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/slpc: Update frequency debugfs for SLPC
2022-10-01 0:41 ` [Intel-gfx] " Vinay Belgaumkar
@ 2022-10-03 11:17 ` Jani Nikula
-1 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2022-10-03 11:17 UTC (permalink / raw)
To: Vinay Belgaumkar, intel-gfx, dri-devel; +Cc: Vinay Belgaumkar
On Fri, 30 Sep 2022, Vinay Belgaumkar <vinay.belgaumkar@intel.com> wrote:
> Create a wrapper to print out the frequency debugfs for
> SLPC and non-SLPC cases. Most of the RPS related information
> is no longer valid when SLPC is enabled.
Please split code movement and functional changes to separate patches.
BR,
Jani.
>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 157 +-------------
> drivers/gpu/drm/i915/gt/intel_rps.c | 205 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
> 3 files changed, 208 insertions(+), 156 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 9fd4d9255a97..d5afa08c54e3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -344,162 +344,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
> drm_printf(p, "efficient (RPe) frequency: %d MHz\n",
> intel_gpu_freq(rps, rps->efficient_freq));
> } else if (GRAPHICS_VER(i915) >= 6) {
> - u32 rp_state_limits;
> - u32 gt_perf_status;
> - struct intel_rps_freq_caps caps;
> - u32 rpmodectl, rpinclimit, rpdeclimit;
> - u32 rpstat, cagf, reqf;
> - u32 rpcurupei, rpcurup, rpprevup;
> - u32 rpcurdownei, rpcurdown, rpprevdown;
> - u32 rpupei, rpupt, rpdownei, rpdownt;
> - u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
> -
> - rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
> - gen6_rps_get_freq_caps(rps, &caps);
> - if (IS_GEN9_LP(i915))
> - gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
> - else
> - gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
> -
> - /* RPSTAT1 is in the GT power well */
> - intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> -
> - reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
> - if (GRAPHICS_VER(i915) >= 9) {
> - reqf >>= 23;
> - } else {
> - reqf &= ~GEN6_TURBO_DISABLE;
> - if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> - reqf >>= 24;
> - else
> - reqf >>= 25;
> - }
> - reqf = intel_gpu_freq(rps, reqf);
> -
> - rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
> - rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
> - rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
> -
> - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
> - rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
> - rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
> - rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
> - rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
> - rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
> - rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
> -
> - rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
> - rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
> -
> - rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
> - rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
> -
> - cagf = intel_rps_read_actual_frequency(rps);
> -
> - intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> -
> - if (GRAPHICS_VER(i915) >= 11) {
> - pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> - pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
> - /*
> - * The equivalent to the PM ISR & IIR cannot be read
> - * without affecting the current state of the system
> - */
> - pm_isr = 0;
> - pm_iir = 0;
> - } else if (GRAPHICS_VER(i915) >= 8) {
> - pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
> - pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
> - pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
> - pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
> - } else {
> - pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
> - pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
> - pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
> - pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
> - }
> - pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
> -
> - drm_printf(p, "Video Turbo Mode: %s\n",
> - str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
> - drm_printf(p, "HW control enabled: %s\n",
> - str_yes_no(rpmodectl & GEN6_RP_ENABLE));
> - drm_printf(p, "SW control enabled: %s\n",
> - str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
> -
> - drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
> - pm_ier, pm_imr, pm_mask);
> - if (GRAPHICS_VER(i915) <= 10)
> - drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n",
> - pm_isr, pm_iir);
> - drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
> - rps->pm_intrmsk_mbz);
> - drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> - drm_printf(p, "Render p-state ratio: %d\n",
> - (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> - drm_printf(p, "Render p-state VID: %d\n",
> - gt_perf_status & 0xff);
> - drm_printf(p, "Render p-state limit: %d\n",
> - rp_state_limits & 0xff);
> - drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat);
> - drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl);
> - drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit);
> - drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
> - drm_printf(p, "RPNSWREQ: %dMHz\n", reqf);
> - drm_printf(p, "CAGF: %dMHz\n", cagf);
> - drm_printf(p, "RP CUR UP EI: %d (%lldns)\n",
> - rpcurupei,
> - intel_gt_pm_interval_to_ns(gt, rpcurupei));
> - drm_printf(p, "RP CUR UP: %d (%lldns)\n",
> - rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
> - drm_printf(p, "RP PREV UP: %d (%lldns)\n",
> - rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
> - drm_printf(p, "Up threshold: %d%%\n",
> - rps->power.up_threshold);
> - drm_printf(p, "RP UP EI: %d (%lldns)\n",
> - rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
> - drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n",
> - rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
> -
> - drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n",
> - rpcurdownei,
> - intel_gt_pm_interval_to_ns(gt, rpcurdownei));
> - drm_printf(p, "RP CUR DOWN: %d (%lldns)\n",
> - rpcurdown,
> - intel_gt_pm_interval_to_ns(gt, rpcurdown));
> - drm_printf(p, "RP PREV DOWN: %d (%lldns)\n",
> - rpprevdown,
> - intel_gt_pm_interval_to_ns(gt, rpprevdown));
> - drm_printf(p, "Down threshold: %d%%\n",
> - rps->power.down_threshold);
> - drm_printf(p, "RP DOWN EI: %d (%lldns)\n",
> - rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
> - drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n",
> - rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
> -
> - drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
> - intel_gpu_freq(rps, caps.min_freq));
> - drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
> - intel_gpu_freq(rps, caps.rp1_freq));
> - drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
> - intel_gpu_freq(rps, caps.rp0_freq));
> - drm_printf(p, "Max overclocked frequency: %dMHz\n",
> - intel_gpu_freq(rps, rps->max_freq));
> -
> - drm_printf(p, "Current freq: %d MHz\n",
> - intel_gpu_freq(rps, rps->cur_freq));
> - drm_printf(p, "Actual freq: %d MHz\n", cagf);
> - drm_printf(p, "Idle freq: %d MHz\n",
> - intel_gpu_freq(rps, rps->idle_freq));
> - drm_printf(p, "Min freq: %d MHz\n",
> - intel_gpu_freq(rps, rps->min_freq));
> - drm_printf(p, "Boost freq: %d MHz\n",
> - intel_gpu_freq(rps, rps->boost_freq));
> - drm_printf(p, "Max freq: %d MHz\n",
> - intel_gpu_freq(rps, rps->max_freq));
> - drm_printf(p,
> - "efficient (RPe) frequency: %d MHz\n",
> - intel_gpu_freq(rps, rps->efficient_freq));
> + gen6_rps_frequency_dump(rps, p);
> } else {
> drm_puts(p, "no P-state info available\n");
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 17b40b625e31..d0847bd4b90f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2219,6 +2219,211 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)
> return intel_gpu_freq(rps, rps->min_freq);
> }
>
> +static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
> +{
> + struct intel_gt *gt = rps_to_gt(rps);
> + struct intel_uncore *uncore = gt->uncore;
> + struct intel_rps_freq_caps caps;
> + u32 pm_mask;
> +
> + gen6_rps_get_freq_caps(rps, &caps);
> + pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
> +
> + drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
> + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1));
> + drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps));
> + drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.min_freq));
> + drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.rp1_freq));
> + drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.rp0_freq));
> + drm_printf(p, "Current freq: %d MHz\n",
> + intel_rps_get_requested_frequency(rps));
> + drm_printf(p, "Actual freq: %d MHz\n",
> + intel_rps_read_actual_frequency(rps));
> + drm_printf(p, "Min freq: %d MHz\n",
> + intel_rps_get_min_frequency(rps));
> + drm_printf(p, "Boost freq: %d MHz\n",
> + intel_rps_get_boost_frequency(rps));
> + drm_printf(p, "Max freq: %d MHz\n",
> + intel_rps_get_max_frequency(rps));
> + drm_printf(p,
> + "efficient (RPe) frequency: %d MHz\n",
> + intel_gpu_freq(rps, caps.rp1_freq));
> +}
> +
> +static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
> +{
> + struct intel_gt *gt = rps_to_gt(rps);
> + struct drm_i915_private *i915 = gt->i915;
> + struct intel_uncore *uncore = gt->uncore;
> + struct intel_rps_freq_caps caps;
> + u32 rp_state_limits;
> + u32 gt_perf_status;
> + u32 rpmodectl, rpinclimit, rpdeclimit;
> + u32 rpstat, cagf, reqf;
> + u32 rpcurupei, rpcurup, rpprevup;
> + u32 rpcurdownei, rpcurdown, rpprevdown;
> + u32 rpupei, rpupt, rpdownei, rpdownt;
> + u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
> +
> + rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
> + gen6_rps_get_freq_caps(rps, &caps);
> + if (IS_GEN9_LP(i915))
> + gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
> + else
> + gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
> +
> + /* RPSTAT1 is in the GT power well */
> + intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> +
> + reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
> + if (GRAPHICS_VER(i915) >= 9) {
> + reqf >>= 23;
> + } else {
> + reqf &= ~GEN6_TURBO_DISABLE;
> + if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> + reqf >>= 24;
> + else
> + reqf >>= 25;
> + }
> + reqf = intel_gpu_freq(rps, reqf);
> +
> + rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
> + rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
> + rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
> +
> + rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
> + rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
> + rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
> + rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
> + rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
> + rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
> + rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
> +
> + rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
> + rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
> +
> + rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
> + rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
> +
> + cagf = intel_rps_read_actual_frequency(rps);
> +
> + intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> +
> + if (GRAPHICS_VER(i915) >= 11) {
> + pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> + pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
> + /*
> + * The equivalent to the PM ISR & IIR cannot be read
> + * without affecting the current state of the system
> + */
> + pm_isr = 0;
> + pm_iir = 0;
> + } else if (GRAPHICS_VER(i915) >= 8) {
> + pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
> + pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
> + pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
> + pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
> + } else {
> + pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
> + pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
> + pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
> + pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
> + }
> + pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
> +
> + drm_printf(p, "Video Turbo Mode: %s\n",
> + str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
> + drm_printf(p, "HW control enabled: %s\n",
> + str_yes_no(rpmodectl & GEN6_RP_ENABLE));
> + drm_printf(p, "SW control enabled: %s\n",
> + str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
> +
> + drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
> + pm_ier, pm_imr, pm_mask);
> + if (GRAPHICS_VER(i915) <= 10)
> + drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n",
> + pm_isr, pm_iir);
> + drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
> + rps->pm_intrmsk_mbz);
> + drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> + drm_printf(p, "Render p-state ratio: %d\n",
> + (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> + drm_printf(p, "Render p-state VID: %d\n",
> + gt_perf_status & 0xff);
> + drm_printf(p, "Render p-state limit: %d\n",
> + rp_state_limits & 0xff);
> + drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat);
> + drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl);
> + drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit);
> + drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
> + drm_printf(p, "RPNSWREQ: %dMHz\n", reqf);
> + drm_printf(p, "CAGF: %dMHz\n", cagf);
> + drm_printf(p, "RP CUR UP EI: %d (%lldns)\n",
> + rpcurupei,
> + intel_gt_pm_interval_to_ns(gt, rpcurupei));
> + drm_printf(p, "RP CUR UP: %d (%lldns)\n",
> + rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
> + drm_printf(p, "RP PREV UP: %d (%lldns)\n",
> + rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
> + drm_printf(p, "Up threshold: %d%%\n",
> + rps->power.up_threshold);
> + drm_printf(p, "RP UP EI: %d (%lldns)\n",
> + rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
> + drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n",
> + rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
> +
> + drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n",
> + rpcurdownei,
> + intel_gt_pm_interval_to_ns(gt, rpcurdownei));
> + drm_printf(p, "RP CUR DOWN: %d (%lldns)\n",
> + rpcurdown,
> + intel_gt_pm_interval_to_ns(gt, rpcurdown));
> + drm_printf(p, "RP PREV DOWN: %d (%lldns)\n",
> + rpprevdown,
> + intel_gt_pm_interval_to_ns(gt, rpprevdown));
> + drm_printf(p, "Down threshold: %d%%\n",
> + rps->power.down_threshold);
> + drm_printf(p, "RP DOWN EI: %d (%lldns)\n",
> + rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
> + drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n",
> + rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
> +
> + drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.min_freq));
> + drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.rp1_freq));
> + drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.rp0_freq));
> + drm_printf(p, "Max overclocked frequency: %dMHz\n",
> + intel_gpu_freq(rps, rps->max_freq));
> +
> + drm_printf(p, "Current freq: %d MHz\n",
> + intel_gpu_freq(rps, rps->cur_freq));
> + drm_printf(p, "Actual freq: %d MHz\n", cagf);
> + drm_printf(p, "Idle freq: %d MHz\n",
> + intel_gpu_freq(rps, rps->idle_freq));
> + drm_printf(p, "Min freq: %d MHz\n",
> + intel_gpu_freq(rps, rps->min_freq));
> + drm_printf(p, "Boost freq: %d MHz\n",
> + intel_gpu_freq(rps, rps->boost_freq));
> + drm_printf(p, "Max freq: %d MHz\n",
> + intel_gpu_freq(rps, rps->max_freq));
> + drm_printf(p,
> + "efficient (RPe) frequency: %d MHz\n",
> + intel_gpu_freq(rps, rps->efficient_freq));
> +}
> +
> +void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
> +{
> + if (rps_uses_slpc(rps))
> + return slpc_frequency_dump(rps, p);
> + else
> + return rps_frequency_dump(rps, p);
> +}
> +
> static int set_max_freq(struct intel_rps *rps, u32 val)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
> index 4509dfdc52e0..c408c26c5192 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.h
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h
> @@ -10,6 +10,7 @@
> #include "i915_reg_defs.h"
>
> struct i915_request;
> +struct drm_printer;
>
> void intel_rps_init_early(struct intel_rps *rps);
> void intel_rps_init(struct intel_rps *rps);
> @@ -54,6 +55,7 @@ void intel_rps_lower_unslice(struct intel_rps *rps);
> u32 intel_rps_read_throttle_reason(struct intel_rps *rps);
> bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);
>
> +void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p);
> void gen5_rps_irq_handler(struct intel_rps *rps);
> void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
> void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/slpc: Update frequency debugfs for SLPC
@ 2022-10-03 11:17 ` Jani Nikula
0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2022-10-03 11:17 UTC (permalink / raw)
To: Vinay Belgaumkar, intel-gfx, dri-devel
On Fri, 30 Sep 2022, Vinay Belgaumkar <vinay.belgaumkar@intel.com> wrote:
> Create a wrapper to print out the frequency debugfs for
> SLPC and non-SLPC cases. Most of the RPS related information
> is no longer valid when SLPC is enabled.
Please split code movement and functional changes to separate patches.
BR,
Jani.
>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 157 +-------------
> drivers/gpu/drm/i915/gt/intel_rps.c | 205 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
> 3 files changed, 208 insertions(+), 156 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 9fd4d9255a97..d5afa08c54e3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -344,162 +344,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
> drm_printf(p, "efficient (RPe) frequency: %d MHz\n",
> intel_gpu_freq(rps, rps->efficient_freq));
> } else if (GRAPHICS_VER(i915) >= 6) {
> - u32 rp_state_limits;
> - u32 gt_perf_status;
> - struct intel_rps_freq_caps caps;
> - u32 rpmodectl, rpinclimit, rpdeclimit;
> - u32 rpstat, cagf, reqf;
> - u32 rpcurupei, rpcurup, rpprevup;
> - u32 rpcurdownei, rpcurdown, rpprevdown;
> - u32 rpupei, rpupt, rpdownei, rpdownt;
> - u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
> -
> - rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
> - gen6_rps_get_freq_caps(rps, &caps);
> - if (IS_GEN9_LP(i915))
> - gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
> - else
> - gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
> -
> - /* RPSTAT1 is in the GT power well */
> - intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> -
> - reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
> - if (GRAPHICS_VER(i915) >= 9) {
> - reqf >>= 23;
> - } else {
> - reqf &= ~GEN6_TURBO_DISABLE;
> - if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> - reqf >>= 24;
> - else
> - reqf >>= 25;
> - }
> - reqf = intel_gpu_freq(rps, reqf);
> -
> - rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
> - rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
> - rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
> -
> - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
> - rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
> - rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
> - rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
> - rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
> - rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
> - rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
> -
> - rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
> - rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
> -
> - rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
> - rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
> -
> - cagf = intel_rps_read_actual_frequency(rps);
> -
> - intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> -
> - if (GRAPHICS_VER(i915) >= 11) {
> - pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> - pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
> - /*
> - * The equivalent to the PM ISR & IIR cannot be read
> - * without affecting the current state of the system
> - */
> - pm_isr = 0;
> - pm_iir = 0;
> - } else if (GRAPHICS_VER(i915) >= 8) {
> - pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
> - pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
> - pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
> - pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
> - } else {
> - pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
> - pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
> - pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
> - pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
> - }
> - pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
> -
> - drm_printf(p, "Video Turbo Mode: %s\n",
> - str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
> - drm_printf(p, "HW control enabled: %s\n",
> - str_yes_no(rpmodectl & GEN6_RP_ENABLE));
> - drm_printf(p, "SW control enabled: %s\n",
> - str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
> -
> - drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
> - pm_ier, pm_imr, pm_mask);
> - if (GRAPHICS_VER(i915) <= 10)
> - drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n",
> - pm_isr, pm_iir);
> - drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
> - rps->pm_intrmsk_mbz);
> - drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> - drm_printf(p, "Render p-state ratio: %d\n",
> - (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> - drm_printf(p, "Render p-state VID: %d\n",
> - gt_perf_status & 0xff);
> - drm_printf(p, "Render p-state limit: %d\n",
> - rp_state_limits & 0xff);
> - drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat);
> - drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl);
> - drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit);
> - drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
> - drm_printf(p, "RPNSWREQ: %dMHz\n", reqf);
> - drm_printf(p, "CAGF: %dMHz\n", cagf);
> - drm_printf(p, "RP CUR UP EI: %d (%lldns)\n",
> - rpcurupei,
> - intel_gt_pm_interval_to_ns(gt, rpcurupei));
> - drm_printf(p, "RP CUR UP: %d (%lldns)\n",
> - rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
> - drm_printf(p, "RP PREV UP: %d (%lldns)\n",
> - rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
> - drm_printf(p, "Up threshold: %d%%\n",
> - rps->power.up_threshold);
> - drm_printf(p, "RP UP EI: %d (%lldns)\n",
> - rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
> - drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n",
> - rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
> -
> - drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n",
> - rpcurdownei,
> - intel_gt_pm_interval_to_ns(gt, rpcurdownei));
> - drm_printf(p, "RP CUR DOWN: %d (%lldns)\n",
> - rpcurdown,
> - intel_gt_pm_interval_to_ns(gt, rpcurdown));
> - drm_printf(p, "RP PREV DOWN: %d (%lldns)\n",
> - rpprevdown,
> - intel_gt_pm_interval_to_ns(gt, rpprevdown));
> - drm_printf(p, "Down threshold: %d%%\n",
> - rps->power.down_threshold);
> - drm_printf(p, "RP DOWN EI: %d (%lldns)\n",
> - rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
> - drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n",
> - rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
> -
> - drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
> - intel_gpu_freq(rps, caps.min_freq));
> - drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
> - intel_gpu_freq(rps, caps.rp1_freq));
> - drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
> - intel_gpu_freq(rps, caps.rp0_freq));
> - drm_printf(p, "Max overclocked frequency: %dMHz\n",
> - intel_gpu_freq(rps, rps->max_freq));
> -
> - drm_printf(p, "Current freq: %d MHz\n",
> - intel_gpu_freq(rps, rps->cur_freq));
> - drm_printf(p, "Actual freq: %d MHz\n", cagf);
> - drm_printf(p, "Idle freq: %d MHz\n",
> - intel_gpu_freq(rps, rps->idle_freq));
> - drm_printf(p, "Min freq: %d MHz\n",
> - intel_gpu_freq(rps, rps->min_freq));
> - drm_printf(p, "Boost freq: %d MHz\n",
> - intel_gpu_freq(rps, rps->boost_freq));
> - drm_printf(p, "Max freq: %d MHz\n",
> - intel_gpu_freq(rps, rps->max_freq));
> - drm_printf(p,
> - "efficient (RPe) frequency: %d MHz\n",
> - intel_gpu_freq(rps, rps->efficient_freq));
> + gen6_rps_frequency_dump(rps, p);
> } else {
> drm_puts(p, "no P-state info available\n");
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 17b40b625e31..d0847bd4b90f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2219,6 +2219,211 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)
> return intel_gpu_freq(rps, rps->min_freq);
> }
>
> +static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
> +{
> + struct intel_gt *gt = rps_to_gt(rps);
> + struct intel_uncore *uncore = gt->uncore;
> + struct intel_rps_freq_caps caps;
> + u32 pm_mask;
> +
> + gen6_rps_get_freq_caps(rps, &caps);
> + pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
> +
> + drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
> + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1));
> + drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps));
> + drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.min_freq));
> + drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.rp1_freq));
> + drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.rp0_freq));
> + drm_printf(p, "Current freq: %d MHz\n",
> + intel_rps_get_requested_frequency(rps));
> + drm_printf(p, "Actual freq: %d MHz\n",
> + intel_rps_read_actual_frequency(rps));
> + drm_printf(p, "Min freq: %d MHz\n",
> + intel_rps_get_min_frequency(rps));
> + drm_printf(p, "Boost freq: %d MHz\n",
> + intel_rps_get_boost_frequency(rps));
> + drm_printf(p, "Max freq: %d MHz\n",
> + intel_rps_get_max_frequency(rps));
> + drm_printf(p,
> + "efficient (RPe) frequency: %d MHz\n",
> + intel_gpu_freq(rps, caps.rp1_freq));
> +}
> +
> +static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
> +{
> + struct intel_gt *gt = rps_to_gt(rps);
> + struct drm_i915_private *i915 = gt->i915;
> + struct intel_uncore *uncore = gt->uncore;
> + struct intel_rps_freq_caps caps;
> + u32 rp_state_limits;
> + u32 gt_perf_status;
> + u32 rpmodectl, rpinclimit, rpdeclimit;
> + u32 rpstat, cagf, reqf;
> + u32 rpcurupei, rpcurup, rpprevup;
> + u32 rpcurdownei, rpcurdown, rpprevdown;
> + u32 rpupei, rpupt, rpdownei, rpdownt;
> + u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
> +
> + rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
> + gen6_rps_get_freq_caps(rps, &caps);
> + if (IS_GEN9_LP(i915))
> + gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
> + else
> + gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
> +
> + /* RPSTAT1 is in the GT power well */
> + intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> +
> + reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
> + if (GRAPHICS_VER(i915) >= 9) {
> + reqf >>= 23;
> + } else {
> + reqf &= ~GEN6_TURBO_DISABLE;
> + if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> + reqf >>= 24;
> + else
> + reqf >>= 25;
> + }
> + reqf = intel_gpu_freq(rps, reqf);
> +
> + rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
> + rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
> + rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
> +
> + rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
> + rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
> + rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
> + rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
> + rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
> + rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
> + rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
> +
> + rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
> + rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
> +
> + rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
> + rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
> +
> + cagf = intel_rps_read_actual_frequency(rps);
> +
> + intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> +
> + if (GRAPHICS_VER(i915) >= 11) {
> + pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> + pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
> + /*
> + * The equivalent to the PM ISR & IIR cannot be read
> + * without affecting the current state of the system
> + */
> + pm_isr = 0;
> + pm_iir = 0;
> + } else if (GRAPHICS_VER(i915) >= 8) {
> + pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
> + pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
> + pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
> + pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
> + } else {
> + pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
> + pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
> + pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
> + pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
> + }
> + pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
> +
> + drm_printf(p, "Video Turbo Mode: %s\n",
> + str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
> + drm_printf(p, "HW control enabled: %s\n",
> + str_yes_no(rpmodectl & GEN6_RP_ENABLE));
> + drm_printf(p, "SW control enabled: %s\n",
> + str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
> +
> + drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
> + pm_ier, pm_imr, pm_mask);
> + if (GRAPHICS_VER(i915) <= 10)
> + drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n",
> + pm_isr, pm_iir);
> + drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
> + rps->pm_intrmsk_mbz);
> + drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> + drm_printf(p, "Render p-state ratio: %d\n",
> + (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> + drm_printf(p, "Render p-state VID: %d\n",
> + gt_perf_status & 0xff);
> + drm_printf(p, "Render p-state limit: %d\n",
> + rp_state_limits & 0xff);
> + drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat);
> + drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl);
> + drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit);
> + drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
> + drm_printf(p, "RPNSWREQ: %dMHz\n", reqf);
> + drm_printf(p, "CAGF: %dMHz\n", cagf);
> + drm_printf(p, "RP CUR UP EI: %d (%lldns)\n",
> + rpcurupei,
> + intel_gt_pm_interval_to_ns(gt, rpcurupei));
> + drm_printf(p, "RP CUR UP: %d (%lldns)\n",
> + rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
> + drm_printf(p, "RP PREV UP: %d (%lldns)\n",
> + rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
> + drm_printf(p, "Up threshold: %d%%\n",
> + rps->power.up_threshold);
> + drm_printf(p, "RP UP EI: %d (%lldns)\n",
> + rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
> + drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n",
> + rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
> +
> + drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n",
> + rpcurdownei,
> + intel_gt_pm_interval_to_ns(gt, rpcurdownei));
> + drm_printf(p, "RP CUR DOWN: %d (%lldns)\n",
> + rpcurdown,
> + intel_gt_pm_interval_to_ns(gt, rpcurdown));
> + drm_printf(p, "RP PREV DOWN: %d (%lldns)\n",
> + rpprevdown,
> + intel_gt_pm_interval_to_ns(gt, rpprevdown));
> + drm_printf(p, "Down threshold: %d%%\n",
> + rps->power.down_threshold);
> + drm_printf(p, "RP DOWN EI: %d (%lldns)\n",
> + rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
> + drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n",
> + rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
> +
> + drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.min_freq));
> + drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.rp1_freq));
> + drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
> + intel_gpu_freq(rps, caps.rp0_freq));
> + drm_printf(p, "Max overclocked frequency: %dMHz\n",
> + intel_gpu_freq(rps, rps->max_freq));
> +
> + drm_printf(p, "Current freq: %d MHz\n",
> + intel_gpu_freq(rps, rps->cur_freq));
> + drm_printf(p, "Actual freq: %d MHz\n", cagf);
> + drm_printf(p, "Idle freq: %d MHz\n",
> + intel_gpu_freq(rps, rps->idle_freq));
> + drm_printf(p, "Min freq: %d MHz\n",
> + intel_gpu_freq(rps, rps->min_freq));
> + drm_printf(p, "Boost freq: %d MHz\n",
> + intel_gpu_freq(rps, rps->boost_freq));
> + drm_printf(p, "Max freq: %d MHz\n",
> + intel_gpu_freq(rps, rps->max_freq));
> + drm_printf(p,
> + "efficient (RPe) frequency: %d MHz\n",
> + intel_gpu_freq(rps, rps->efficient_freq));
> +}
> +
> +void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
> +{
> + if (rps_uses_slpc(rps))
> + return slpc_frequency_dump(rps, p);
> + else
> + return rps_frequency_dump(rps, p);
> +}
> +
> static int set_max_freq(struct intel_rps *rps, u32 val)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
> index 4509dfdc52e0..c408c26c5192 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.h
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h
> @@ -10,6 +10,7 @@
> #include "i915_reg_defs.h"
>
> struct i915_request;
> +struct drm_printer;
>
> void intel_rps_init_early(struct intel_rps *rps);
> void intel_rps_init(struct intel_rps *rps);
> @@ -54,6 +55,7 @@ void intel_rps_lower_unslice(struct intel_rps *rps);
> u32 intel_rps_read_throttle_reason(struct intel_rps *rps);
> bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);
>
> +void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p);
> void gen5_rps_irq_handler(struct intel_rps *rps);
> void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
> void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-10-03 11:17 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-01 0:41 [PATCH] drm/i915/slpc: Update frequency debugfs for SLPC Vinay Belgaumkar
2022-10-01 0:41 ` [Intel-gfx] " Vinay Belgaumkar
2022-10-01 1:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-10-01 20:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-10-03 11:17 ` [PATCH] " Jani Nikula
2022-10-03 11:17 ` [Intel-gfx] " Jani Nikula
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