* [PATCH bpf-next] bpf,x64: Remove unnecessary check on existence of SSE2
@ 2022-10-03 1:17 Jie Meng
2022-10-04 1:04 ` KP Singh
0 siblings, 1 reply; 7+ messages in thread
From: Jie Meng @ 2022-10-03 1:17 UTC (permalink / raw)
To: bpf, ast, andrii, daniel; +Cc: Jie Meng
SSE2 and hence lfence are architectural in x86-64 and no need to check
whether they're supported in CPU.
Signed-off-by: Jie Meng <jmeng@fb.com>
---
arch/x86/net/bpf_jit_comp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
index d09c54f3d2e0..b2124521305e 100644
--- a/arch/x86/net/bpf_jit_comp.c
+++ b/arch/x86/net/bpf_jit_comp.c
@@ -1289,8 +1289,7 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image
/* speculation barrier */
case BPF_ST | BPF_NOSPEC:
- if (boot_cpu_has(X86_FEATURE_XMM2))
- EMIT_LFENCE();
+ EMIT_LFENCE();
break;
/* ST: *(u8*)(dst_reg + off) = imm */
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH bpf-next] bpf,x64: Remove unnecessary check on existence of SSE2
2022-10-03 1:17 [PATCH bpf-next] bpf,x64: Remove unnecessary check on existence of SSE2 Jie Meng
@ 2022-10-04 1:04 ` KP Singh
2022-10-04 3:50 ` Jie Meng
0 siblings, 1 reply; 7+ messages in thread
From: KP Singh @ 2022-10-04 1:04 UTC (permalink / raw)
To: Jie Meng; +Cc: bpf, ast, andrii, daniel
On Mon, Oct 3, 2022 at 3:17 AM Jie Meng <jmeng@fb.com> wrote:
>
> SSE2 and hence lfence are architectural in x86-64 and no need to check
> whether they're supported in CPU.
Why do you say this?
The Instruction set reference does mention that:
Exceptions:
#UD If CPUID.01H:EDX.SSE2[bit 26] = 0
(undefined instruction when the CPUID.SSE2 bit is unset)
and also that the CPUID feature flag is SSE2
>
> Signed-off-by: Jie Meng <jmeng@fb.com>
> ---
> arch/x86/net/bpf_jit_comp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
> index d09c54f3d2e0..b2124521305e 100644
> --- a/arch/x86/net/bpf_jit_comp.c
> +++ b/arch/x86/net/bpf_jit_comp.c
> @@ -1289,8 +1289,7 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image
>
> /* speculation barrier */
> case BPF_ST | BPF_NOSPEC:
> - if (boot_cpu_has(X86_FEATURE_XMM2))
> - EMIT_LFENCE();
> + EMIT_LFENCE();
> break;
>
> /* ST: *(u8*)(dst_reg + off) = imm */
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH bpf-next] bpf,x64: Remove unnecessary check on existence of SSE2
2022-10-04 1:04 ` KP Singh
@ 2022-10-04 3:50 ` Jie Meng
2022-10-05 0:30 ` KP Singh
0 siblings, 1 reply; 7+ messages in thread
From: Jie Meng @ 2022-10-04 3:50 UTC (permalink / raw)
To: KP Singh; +Cc: bpf, ast, andrii, daniel
On Tue, Oct 04, 2022 at 03:04:20AM +0200, KP Singh wrote:
> On Mon, Oct 3, 2022 at 3:17 AM Jie Meng <jmeng@fb.com> wrote:
> >
> > SSE2 and hence lfence are architectural in x86-64 and no need to check
> > whether they're supported in CPU.
>
> Why do you say this?
>
> The Instruction set reference does mention that:
>
> Exceptions:
>
> #UD If CPUID.01H:EDX.SSE2[bit 26] = 0
>
> (undefined instruction when the CPUID.SSE2 bit is unset)
>
> and also that the CPUID feature flag is SSE2
Many x86 extensions predate x86-64. When they designed x86-64, AMD
decided to make some mandatory (and hence architectural) and SSE2 is
one of them[1]. CMOV, NOPL, PAE, NX etc. are other examples.
These extensions' CPUID flags are still set. If code is to be shared
between x86 and x86-64 one can still check CPUID, but bpf_jit_comp.c
is compiled under x86-64 only so the check is redundant.
There's an example Within kernel code too: arch/x86/lib/copy_user_64.S
uses SSE (sfence) and SSE2 (movnti) instructions and doesn't check
CPUID for their presence.
---
[1] https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels
> >
> > Signed-off-by: Jie Meng <jmeng@fb.com>
> > ---
> > arch/x86/net/bpf_jit_comp.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
> > index d09c54f3d2e0..b2124521305e 100644
> > --- a/arch/x86/net/bpf_jit_comp.c
> > +++ b/arch/x86/net/bpf_jit_comp.c
> > @@ -1289,8 +1289,7 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image
> >
> > /* speculation barrier */
> > case BPF_ST | BPF_NOSPEC:
> > - if (boot_cpu_has(X86_FEATURE_XMM2))
> > - EMIT_LFENCE();
> > + EMIT_LFENCE();
> > break;
> >
> > /* ST: *(u8*)(dst_reg + off) = imm */
> > --
> > 2.30.2
> >
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH bpf-next] bpf,x64: Remove unnecessary check on existence of SSE2
2022-10-04 3:50 ` Jie Meng
@ 2022-10-05 0:30 ` KP Singh
2022-10-05 17:00 ` [PATCH bpf-next v2] " Jie Meng
0 siblings, 1 reply; 7+ messages in thread
From: KP Singh @ 2022-10-05 0:30 UTC (permalink / raw)
To: Jie Meng; +Cc: bpf, ast, andrii, daniel
On Tue, Oct 4, 2022 at 5:50 AM Jie Meng <jmeng@fb.com> wrote:
>
> On Tue, Oct 04, 2022 at 03:04:20AM +0200, KP Singh wrote:
> > On Mon, Oct 3, 2022 at 3:17 AM Jie Meng <jmeng@fb.com> wrote:
> > >
> > > SSE2 and hence lfence are architectural in x86-64 and no need to check
> > > whether they're supported in CPU.
> >
> > Why do you say this?
> >
> > The Instruction set reference does mention that:
> >
> > Exceptions:
> >
> > #UD If CPUID.01H:EDX.SSE2[bit 26] = 0
> >
> > (undefined instruction when the CPUID.SSE2 bit is unset)
> >
> > and also that the CPUID feature flag is SSE2
>
> Many x86 extensions predate x86-64. When they designed x86-64, AMD
> decided to make some mandatory (and hence architectural) and SSE2 is
> one of them[1]. CMOV, NOPL, PAE, NX etc. are other examples.
>
> These extensions' CPUID flags are still set. If code is to be shared
> between x86 and x86-64 one can still check CPUID, but bpf_jit_comp.c
> is compiled under x86-64 only so the check is redundant.
>
> There's an example Within kernel code too: arch/x86/lib/copy_user_64.S
> uses SSE (sfence) and SSE2 (movnti) instructions and doesn't check
> CPUID for their presence.
>
Thanks, it makes sense.
Can you please add the explanation to the commit description?
> ---
> [1] https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels
>
> > >
> > > Signed-off-by: Jie Meng <jmeng@fb.com>
> > > ---
> > > arch/x86/net/bpf_jit_comp.c | 3 +--
> > > 1 file changed, 1 insertion(+), 2 deletions(-)
> > >
> > > diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
> > > index d09c54f3d2e0..b2124521305e 100644
> > > --- a/arch/x86/net/bpf_jit_comp.c
> > > +++ b/arch/x86/net/bpf_jit_comp.c
> > > @@ -1289,8 +1289,7 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image
> > >
> > > /* speculation barrier */
> > > case BPF_ST | BPF_NOSPEC:
> > > - if (boot_cpu_has(X86_FEATURE_XMM2))
> > > - EMIT_LFENCE();
> > > + EMIT_LFENCE();
> > > break;
> > >
> > > /* ST: *(u8*)(dst_reg + off) = imm */
> > > --
> > > 2.30.2
> > >
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH bpf-next v2] bpf,x64: Remove unnecessary check on existence of SSE2
2022-10-05 0:30 ` KP Singh
@ 2022-10-05 17:00 ` Jie Meng
2022-10-06 0:58 ` KP Singh
2022-10-07 14:30 ` patchwork-bot+netdevbpf
0 siblings, 2 replies; 7+ messages in thread
From: Jie Meng @ 2022-10-05 17:00 UTC (permalink / raw)
To: kpsingh, bpf, ast, andrii, daniel; +Cc: Jie Meng
SSE2 and hence lfence are architectural in x86-64 and no need to check
whether they're supported in CPU. SSE2's CPUID flag is still set to
maintain backward compatibility with older code or code shared with x86,
but bpf_jit_comp.c is compiled under x86-64 exclusively so the check is
redundant.
Signed-off-by: Jie Meng <jmeng@fb.com>
---
arch/x86/net/bpf_jit_comp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
index d09c54f3d2e0..b2124521305e 100644
--- a/arch/x86/net/bpf_jit_comp.c
+++ b/arch/x86/net/bpf_jit_comp.c
@@ -1289,8 +1289,7 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image
/* speculation barrier */
case BPF_ST | BPF_NOSPEC:
- if (boot_cpu_has(X86_FEATURE_XMM2))
- EMIT_LFENCE();
+ EMIT_LFENCE();
break;
/* ST: *(u8*)(dst_reg + off) = imm */
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH bpf-next v2] bpf,x64: Remove unnecessary check on existence of SSE2
2022-10-05 17:00 ` [PATCH bpf-next v2] " Jie Meng
@ 2022-10-06 0:58 ` KP Singh
2022-10-07 14:30 ` patchwork-bot+netdevbpf
1 sibling, 0 replies; 7+ messages in thread
From: KP Singh @ 2022-10-06 0:58 UTC (permalink / raw)
To: Jie Meng; +Cc: bpf, ast, andrii, daniel
On Wed, Oct 5, 2022 at 10:01 AM Jie Meng <jmeng@fb.com> wrote:
>
> SSE2 and hence lfence are architectural in x86-64 and no need to check
> whether they're supported in CPU. SSE2's CPUID flag is still set to
> maintain backward compatibility with older code or code shared with x86,
> but bpf_jit_comp.c is compiled under x86-64 exclusively so the check is
> redundant.
>
> Signed-off-by: Jie Meng <jmeng@fb.com>
Acked-by: KP Singh <kpsingh@kernel.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH bpf-next v2] bpf,x64: Remove unnecessary check on existence of SSE2
2022-10-05 17:00 ` [PATCH bpf-next v2] " Jie Meng
2022-10-06 0:58 ` KP Singh
@ 2022-10-07 14:30 ` patchwork-bot+netdevbpf
1 sibling, 0 replies; 7+ messages in thread
From: patchwork-bot+netdevbpf @ 2022-10-07 14:30 UTC (permalink / raw)
To: Jie Meng; +Cc: kpsingh, bpf, ast, andrii, daniel
Hello:
This patch was applied to bpf/bpf-next.git (master)
by Daniel Borkmann <daniel@iogearbox.net>:
On Wed, 5 Oct 2022 10:00:39 -0700 you wrote:
> SSE2 and hence lfence are architectural in x86-64 and no need to check
> whether they're supported in CPU. SSE2's CPUID flag is still set to
> maintain backward compatibility with older code or code shared with x86,
> but bpf_jit_comp.c is compiled under x86-64 exclusively so the check is
> redundant.
>
> Signed-off-by: Jie Meng <jmeng@fb.com>
>
> [...]
Here is the summary with links:
- [bpf-next,v2] bpf,x64: Remove unnecessary check on existence of SSE2
https://git.kernel.org/bpf/bpf-next/c/2e30960097f6
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-10-07 14:30 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-03 1:17 [PATCH bpf-next] bpf,x64: Remove unnecessary check on existence of SSE2 Jie Meng
2022-10-04 1:04 ` KP Singh
2022-10-04 3:50 ` Jie Meng
2022-10-05 0:30 ` KP Singh
2022-10-05 17:00 ` [PATCH bpf-next v2] " Jie Meng
2022-10-06 0:58 ` KP Singh
2022-10-07 14:30 ` patchwork-bot+netdevbpf
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.