* [PATCH v3 1/2] drm/i915: enable PS64 support for DG2
@ 2022-10-04 11:49 ` Matthew Auld
0 siblings, 0 replies; 21+ messages in thread
From: Matthew Auld @ 2022-10-04 11:49 UTC (permalink / raw)
To: intel-gfx
Cc: Thomas Hellström, Yang A Shi, Jordan Justen,
Lionel Landwerlin, Stuart Summers, Michal Mrozek, dri-devel,
Niranjana Vishwanathapura, Nirmoy Das
It turns out that on production DG2/ATS HW we should have support for
PS64. This feature allows to provide a 64K TLB hint at the PTE level,
which is a lot more flexible than the current method of enabling 64K GTT
pages for the entire page-table, since that leads to all kinds of
annoying restrictions, as documented in:
commit caa574ffc4aaf4f29b890223878c63e2e7772f62
Author: Matthew Auld <matthew.auld@intel.com>
Date: Sat Feb 19 00:17:49 2022 +0530
drm/i915/uapi: document behaviour for DG2 64K support
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.
With PS64, we can now drop the 2M GTT alignment restriction, and instead
only require 64K or larger when dealing with lmem. We still use the
compact-pt layout when possible, but only when we are certain that this
doesn't interfere with userspace.
Note that this is a change in uAPI behaviour, but hopefully shouldn't be
a concern (IGT is at least able to autodetect the alignment), since we
are only making the GTT alignment constraint less restrictive.
Based on a patch from CQ Tang.
v2: update the comment wrt scratch page
v3: (Nirmoy)
- Fix the selftest to actually use the random size, plus some comment
improvements, also drop the rem stuff.
Reported-by: Michal Mrozek <michal.mrozek@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Yang A Shi <yang.a.shi@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Acked-by: Michal Mrozek <michal.mrozek@intel.com>
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 157 +++++++++++++++++-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 81 +++++----
drivers/gpu/drm/i915/gt/intel_gtt.c | 21 +--
drivers/gpu/drm/i915/gt/intel_gtt.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 7 -
drivers/gpu/drm/i915/i915_pci.c | 2 -
drivers/gpu/drm/i915/i915_vma.c | 9 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 9 +-
include/uapi/drm/i915_drm.h | 36 ++--
10 files changed, 218 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index c570cf780079..0cb99e75b0bc 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1161,7 +1161,8 @@ static int igt_write_huge(struct drm_i915_private *i915,
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
size = obj->base.size;
- if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K)
+ if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&
+ !HAS_64K_PAGES(i915))
size = round_up(size, I915_GTT_PAGE_SIZE_2M);
n = 0;
@@ -1214,6 +1215,10 @@ static int igt_write_huge(struct drm_i915_private *i915,
* size and ensure the vma offset is at the start of the pt
* boundary, however to improve coverage we opt for testing both
* aligned and unaligned offsets.
+ *
+ * With PS64 this is no longer the case, but to ensure we
+ * sometimes get the compact layout for smaller objects, apply
+ * the round_up anyway.
*/
if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K)
offset_low = round_down(offset_low,
@@ -1411,6 +1416,7 @@ static int igt_ppgtt_sanity_check(void *arg)
{ SZ_2M + SZ_4K, SZ_64K | SZ_4K },
{ SZ_2M + SZ_4K, SZ_2M | SZ_4K },
{ SZ_2M + SZ_64K, SZ_2M | SZ_64K },
+ { SZ_2M + SZ_64K, SZ_64K },
};
int i, j;
int err;
@@ -1540,6 +1546,154 @@ static int igt_ppgtt_compact(void *arg)
return err;
}
+static int igt_ppgtt_mixed(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ const unsigned long flags = PIN_OFFSET_FIXED | PIN_USER;
+ struct drm_i915_gem_object *obj, *on;
+ struct i915_gem_engines *engines;
+ struct i915_gem_engines_iter it;
+ struct i915_address_space *vm;
+ struct i915_gem_context *ctx;
+ struct intel_context *ce;
+ struct file *file;
+ I915_RND_STATE(prng);
+ LIST_HEAD(objects);
+ struct intel_memory_region *mr;
+ struct i915_vma *vma;
+ unsigned int count;
+ u32 i, addr;
+ int *order;
+ int n, err;
+
+ /*
+ * Sanity check mixing 4K and 64K pages within the same page-table via
+ * the new PS64 TLB hint.
+ */
+
+ if (!HAS_64K_PAGES(i915)) {
+ pr_info("device lacks PS64, skipping\n");
+ return 0;
+ }
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ ctx = hugepage_ctx(i915, file);
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto out;
+ }
+ vm = i915_gem_context_get_eb_vm(ctx);
+
+ i = 0;
+ addr = 0;
+ do {
+ u32 sz;
+
+ sz = i915_prandom_u32_max_state(SZ_4M, &prng);
+ sz = max_t(u32, sz, SZ_4K);
+
+ mr = i915->mm.regions[INTEL_REGION_LMEM_0];
+ if (i & 1)
+ mr = i915->mm.regions[INTEL_REGION_SMEM];
+
+ obj = i915_gem_object_create_region(mr, sz, 0, 0);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto out_vm;
+ }
+
+ list_add_tail(&obj->st_link, &objects);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_put;
+ }
+
+ addr = round_up(addr, mr->min_page_size);
+ err = i915_vma_pin(vma, 0, 0, addr | flags);
+ if (err)
+ goto err_put;
+
+ if (mr->type == INTEL_MEMORY_LOCAL &&
+ (vma->resource->page_sizes_gtt & I915_GTT_PAGE_SIZE_4K)) {
+ err = -EINVAL;
+ goto err_put;
+ }
+
+ addr += obj->base.size;
+ i++;
+ } while (addr <= SZ_16M);
+
+ n = 0;
+ count = 0;
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ count++;
+ if (!intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ n++;
+ }
+ i915_gem_context_unlock_engines(ctx);
+ if (!n)
+ goto err_put;
+
+ order = i915_random_order(count * count, &prng);
+ if (!order) {
+ err = -ENOMEM;
+ goto err_put;
+ }
+
+ i = 0;
+ addr = 0;
+ engines = i915_gem_context_lock_engines(ctx);
+ list_for_each_entry(obj, &objects, st_link) {
+ u32 rnd = i915_prandom_u32_max_state(UINT_MAX, &prng);
+
+ addr = round_up(addr, obj->mm.region->min_page_size);
+
+ ce = engines->engines[order[i] % engines->num_engines];
+ i = (i + 1) % (count * count);
+ if (!ce || !intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ err = __igt_write_huge(ce, obj, obj->base.size, addr, 0, rnd);
+ if (err)
+ break;
+
+ err = __igt_write_huge(ce, obj, obj->base.size, addr,
+ offset_in_page(rnd) / sizeof(u32), rnd + 1);
+ if (err)
+ break;
+
+ err = __igt_write_huge(ce, obj, obj->base.size, addr,
+ (PAGE_SIZE / sizeof(u32)) - 1,
+ rnd + 2);
+ if (err)
+ break;
+
+ addr += obj->base.size;
+
+ cond_resched();
+ }
+
+ i915_gem_context_unlock_engines(ctx);
+ kfree(order);
+err_put:
+ list_for_each_entry_safe(obj, on, &objects, st_link) {
+ list_del(&obj->st_link);
+ i915_gem_object_put(obj);
+ }
+out_vm:
+ i915_vm_put(vm);
+out:
+ fput(file);
+ return err;
+}
+
static int igt_tmpfs_fallback(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -1803,6 +1957,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_ppgtt_smoke_huge),
SUBTEST(igt_ppgtt_sanity_check),
SUBTEST(igt_ppgtt_compact),
+ SUBTEST(igt_ppgtt_mixed),
};
if (!HAS_PPGTT(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 8dd60d5ef905..4daaa6f55668 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -476,6 +476,7 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
unsigned int rem = sg_dma_len(iter->sg);
u64 start = vma_res->start;
+ u64 end = start + vma_res->vma_size;
GEM_BUG_ON(!i915_vm_is_4lvl(vm));
@@ -489,9 +490,10 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
gen8_pte_t encode = pte_encode;
unsigned int page_size;
gen8_pte_t *vaddr;
- u16 index, max;
+ u16 index, max, nent, i;
max = I915_PDES;
+ nent = 1;
if (vma_res->bi.page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
@@ -503,25 +505,37 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
vaddr = px_vaddr(pd);
} else {
- if (encode & GEN12_PPGTT_PTE_LM) {
- GEM_BUG_ON(__gen8_pte_index(start, 0) % 16);
- GEM_BUG_ON(rem < I915_GTT_PAGE_SIZE_64K);
- GEM_BUG_ON(!IS_ALIGNED(iter->dma,
- I915_GTT_PAGE_SIZE_64K));
-
- index = __gen8_pte_index(start, 0) / 16;
- page_size = I915_GTT_PAGE_SIZE_64K;
-
- max /= 16;
-
- vaddr = px_vaddr(pd);
- vaddr[__gen8_pte_index(start, 1)] |= GEN12_PDE_64K;
+ index = __gen8_pte_index(start, 0);
+ page_size = I915_GTT_PAGE_SIZE;
- pt->is_compact = true;
- } else {
- GEM_BUG_ON(pt->is_compact);
- index = __gen8_pte_index(start, 0);
- page_size = I915_GTT_PAGE_SIZE;
+ if (vma_res->bi.page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
+ /*
+ * Device local-memory on these platforms should
+ * always use 64K pages or larger (including GTT
+ * alignment), therefore if we know the whole
+ * page-table needs to be filled we can always
+ * safely use the compact-layout. Otherwise fall
+ * back to the TLB hint with PS64. If this is
+ * system memory we only bother with PS64.
+ */
+ if ((encode & GEN12_PPGTT_PTE_LM) &&
+ end - start >= SZ_2M && !index) {
+ index = __gen8_pte_index(start, 0) / 16;
+ page_size = I915_GTT_PAGE_SIZE_64K;
+
+ max /= 16;
+
+ vaddr = px_vaddr(pd);
+ vaddr[__gen8_pte_index(start, 1)] |= GEN12_PDE_64K;
+
+ pt->is_compact = true;
+ } else if (IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
+ rem >= I915_GTT_PAGE_SIZE_64K &&
+ !(index % 16)) {
+ encode |= GEN12_PTE_PS64;
+ page_size = I915_GTT_PAGE_SIZE_64K;
+ nent = 16;
+ }
}
vaddr = px_vaddr(pt);
@@ -529,7 +543,12 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
do {
GEM_BUG_ON(rem < page_size);
- vaddr[index++] = encode | iter->dma;
+
+ for (i = 0; i < nent; i++) {
+ vaddr[index++] =
+ encode | (iter->dma + i *
+ I915_GTT_PAGE_SIZE);
+ }
start += page_size;
iter->dma += page_size;
@@ -745,6 +764,8 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
GEM_BUG_ON(!IS_ALIGNED(addr, SZ_64K));
GEM_BUG_ON(!IS_ALIGNED(offset, SZ_64K));
+ /* XXX: we don't strictly need to use this layout */
+
if (!pt->is_compact) {
vaddr = px_vaddr(pd);
vaddr[gen8_pd_index(idx, 1)] |= GEN12_PDE_64K;
@@ -935,22 +956,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
/*
- * On some platforms the hw has dropped support for 4K GTT pages
- * when dealing with LMEM, and due to the design of 64K GTT
- * pages in the hw, we can only mark the *entire* page-table as
- * operating in 64K GTT mode, since the enable bit is still on
- * the pde, and not the pte. And since we still need to allow
- * 4K GTT pages for SMEM objects, we can't have a "normal" 4K
- * page-table with scratch pointing to LMEM, since that's
- * undefined from the hw pov. The simplest solution is to just
- * move the 64K scratch page to SMEM on all platforms and call
- * it a day, since that should work for all configurations.
- *
- * Using SMEM instead of LMEM has the additional advantage of
- * not reserving high performance memory for a "never" used
- * filler page. It also removes the device access that would
- * be required to initialise the scratch page, reducing pressure
- * on an even scarcer resource.
+ * Using SMEM here instead of LMEM has the advantage of not reserving
+ * high performance memory for a "never" used filler page. It also
+ * removes the device access that would be required to initialise the
+ * scratch page, reducing pressure on an even scarcer resource.
*/
ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 2eaeba14319e..13e411187fd5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -269,11 +269,7 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass)
memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
ARRAY_SIZE(vm->min_alignment));
- if (HAS_64K_PAGES(vm->i915) && NEEDS_COMPACT_PT(vm->i915) &&
- subclass == VM_CLASS_PPGTT) {
- vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_2M;
- vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_2M;
- } else if (HAS_64K_PAGES(vm->i915)) {
+ if (HAS_64K_PAGES(vm->i915)) {
vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_64K;
vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_64K;
}
@@ -343,7 +339,8 @@ int setup_scratch_page(struct i915_address_space *vm)
*/
size = I915_GTT_PAGE_SIZE_4K;
if (i915_vm_is_4lvl(vm) &&
- HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K))
+ HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K) &&
+ !HAS_64K_PAGES(vm->i915))
size = I915_GTT_PAGE_SIZE_64K;
do {
@@ -385,18 +382,6 @@ int setup_scratch_page(struct i915_address_space *vm)
if (size == I915_GTT_PAGE_SIZE_4K)
return -ENOMEM;
- /*
- * If we need 64K minimum GTT pages for device local-memory,
- * like on XEHPSDV, then we need to fail the allocation here,
- * otherwise we can't safely support the insertion of
- * local-memory pages for this vm, since the HW expects the
- * correct physical alignment and size when the page-table is
- * operating in 64K GTT mode, which includes any scratch PTEs,
- * since userspace can still touch them.
- */
- if (HAS_64K_PAGES(vm->i915))
- return -ENOMEM;
-
size = I915_GTT_PAGE_SIZE_4K;
} while (1);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index c0ca53cba9f0..062b78333fb2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -93,6 +93,7 @@ typedef u64 gen8_pte_t;
#define GEN12_GGTT_PTE_LM BIT_ULL(1)
#define GEN12_PDE_64K BIT(6)
+#define GEN12_PTE_PS64 BIT(8)
/*
* Cacheability Control is a 4-bit value. The low three bits are stored in bits
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90ed8e6db2fe..c9147e50fa5d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -902,13 +902,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
*/
#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
-/*
- * Set this flag when platform doesn't allow both 64k pages and 4k pages in
- * the same PT. this flag means we need to support compact PT layout for the
- * ppGTT when using the 64K GTT pages.
- */
-#define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
-
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 38460a0bd7cb..40bb06c5cdc0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1042,7 +1042,6 @@ static const struct intel_device_info xehpsdv_info = {
PLATFORM(INTEL_XEHPSDV),
NO_DISPLAY,
.has_64k_pages = 1,
- .needs_compact_pt = 1,
.has_media_ratio_mode = 1,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
@@ -1064,7 +1063,6 @@ static const struct intel_device_info xehpsdv_info = {
.has_64k_pages = 1, \
.has_guc_deprivilege = 1, \
.has_heci_pxp = 1, \
- .needs_compact_pt = 1, \
.has_media_ratio_mode = 1, \
.__runtime.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index f17c09ead7d7..c39488eb9eeb 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -776,12 +776,6 @@ i915_vma_insert(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
alignment = max(alignment, i915_vm_obj_min_alignment(vma->vm, vma->obj));
- /*
- * for compact-pt we round up the reservation to prevent
- * any smaller pages being used within the same PDE
- */
- if (NEEDS_COMPACT_PT(vma->vm->i915))
- size = round_up(size, alignment);
/* If binding the object/GGTT view requires more space than the entire
* aperture has, reject it early before evicting everything in a vain
@@ -820,7 +814,8 @@ i915_vma_insert(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
* forseeable future. See also i915_ggtt_offset().
*/
if (upper_32_bits(end - 1) &&
- vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
+ vma->page_sizes.sg > I915_GTT_PAGE_SIZE &&
+ !HAS_64K_PAGES(vma->vm->i915)) {
/*
* We can't mix 64K and 4K PTEs in the same page-table
* (2M block), and so to avoid the ugliness and
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index bc87d3156b14..58539660a1ec 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -146,7 +146,6 @@ enum intel_ppgtt_type {
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(has_64k_pages); \
- func(needs_compact_pt); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_3d_pipeline); \
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index ea2cf1080979..27c733b00976 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1114,15 +1114,8 @@ static int misaligned_case(struct i915_address_space *vm, struct intel_memory_re
expected_node_size = expected_vma_size;
if (HAS_64K_PAGES(vm->i915) && i915_gem_object_is_lmem(obj)) {
- /*
- * The compact-pt should expand lmem node to 2MB for the ppGTT,
- * for all other cases we should only expect 64K.
- */
expected_vma_size = round_up(size, I915_GTT_PAGE_SIZE_64K);
- if (NEEDS_COMPACT_PT(vm->i915) && !i915_is_ggtt(vm))
- expected_node_size = round_up(size, I915_GTT_PAGE_SIZE_2M);
- else
- expected_node_size = round_up(size, I915_GTT_PAGE_SIZE_64K);
+ expected_node_size = round_up(size, I915_GTT_PAGE_SIZE_64K);
}
if (vma->size != expected_vma_size || vma->node.size != expected_node_size) {
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 629198f1d8d8..08d69e36fb66 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3509,27 +3509,13 @@ struct drm_i915_gem_create_ext {
*
* The (page-aligned) allocated size for the object will be returned.
*
- * DG2 64K min page size implications:
+ * On platforms like DG2/ATS the kernel will always use 64K or larger
+ * pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a
+ * minimum of 64K GTT alignment for such objects.
*
- * On discrete platforms, starting from DG2, we have to contend with GTT
- * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
- * objects. Specifically the hardware only supports 64K or larger GTT
- * page sizes for such memory. The kernel will already ensure that all
- * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
- * sizes underneath.
- *
- * Note that the returned size here will always reflect any required
- * rounding up done by the kernel, i.e 4K will now become 64K on devices
- * such as DG2. The kernel will always select the largest minimum
- * page-size for the set of possible placements as the value to use when
- * rounding up the @size.
- *
- * Special DG2 GTT address alignment requirement:
- *
- * The GTT alignment will also need to be at least 2M for such objects.
- *
- * Note that due to how the hardware implements 64K GTT page support, we
- * have some further complications:
+ * NOTE: Previously the ABI here required a minimum GTT alignment of 2M
+ * on DG2/ATS, due to how the hardware implemented 64K GTT page support,
+ * where we had the following complications:
*
* 1) The entire PDE (which covers a 2MB virtual address range), must
* contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
@@ -3538,12 +3524,10 @@ struct drm_i915_gem_create_ext {
* 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
* objects.
*
- * To keep things simple for userland, we mandate that any GTT mappings
- * must be aligned to and rounded up to 2MB. The kernel will internally
- * pad them out to the next 2MB boundary. As this only wastes virtual
- * address space and avoids userland having to copy any needlessly
- * complicated PDE sharing scheme (coloring) and only affects DG2, this
- * is deemed to be a good compromise.
+ * However on actual production HW this was completely changed to now
+ * allow setting a TLB hint at the PTE level (see PS64), which is a lot
+ * more flexible than the above. With this the 2M restriction was
+ * dropped where we now only require 64K.
*/
__u64 size;
--
2.37.3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH v3 1/2] drm/i915: enable PS64 support for DG2
@ 2022-10-04 11:49 ` Matthew Auld
0 siblings, 0 replies; 21+ messages in thread
From: Matthew Auld @ 2022-10-04 11:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Thomas Hellström, Michal Mrozek, dri-devel, Nirmoy Das
It turns out that on production DG2/ATS HW we should have support for
PS64. This feature allows to provide a 64K TLB hint at the PTE level,
which is a lot more flexible than the current method of enabling 64K GTT
pages for the entire page-table, since that leads to all kinds of
annoying restrictions, as documented in:
commit caa574ffc4aaf4f29b890223878c63e2e7772f62
Author: Matthew Auld <matthew.auld@intel.com>
Date: Sat Feb 19 00:17:49 2022 +0530
drm/i915/uapi: document behaviour for DG2 64K support
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.
With PS64, we can now drop the 2M GTT alignment restriction, and instead
only require 64K or larger when dealing with lmem. We still use the
compact-pt layout when possible, but only when we are certain that this
doesn't interfere with userspace.
Note that this is a change in uAPI behaviour, but hopefully shouldn't be
a concern (IGT is at least able to autodetect the alignment), since we
are only making the GTT alignment constraint less restrictive.
Based on a patch from CQ Tang.
v2: update the comment wrt scratch page
v3: (Nirmoy)
- Fix the selftest to actually use the random size, plus some comment
improvements, also drop the rem stuff.
Reported-by: Michal Mrozek <michal.mrozek@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Yang A Shi <yang.a.shi@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Acked-by: Michal Mrozek <michal.mrozek@intel.com>
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 157 +++++++++++++++++-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 81 +++++----
drivers/gpu/drm/i915/gt/intel_gtt.c | 21 +--
drivers/gpu/drm/i915/gt/intel_gtt.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 7 -
drivers/gpu/drm/i915/i915_pci.c | 2 -
drivers/gpu/drm/i915/i915_vma.c | 9 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 9 +-
include/uapi/drm/i915_drm.h | 36 ++--
10 files changed, 218 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index c570cf780079..0cb99e75b0bc 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1161,7 +1161,8 @@ static int igt_write_huge(struct drm_i915_private *i915,
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
size = obj->base.size;
- if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K)
+ if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&
+ !HAS_64K_PAGES(i915))
size = round_up(size, I915_GTT_PAGE_SIZE_2M);
n = 0;
@@ -1214,6 +1215,10 @@ static int igt_write_huge(struct drm_i915_private *i915,
* size and ensure the vma offset is at the start of the pt
* boundary, however to improve coverage we opt for testing both
* aligned and unaligned offsets.
+ *
+ * With PS64 this is no longer the case, but to ensure we
+ * sometimes get the compact layout for smaller objects, apply
+ * the round_up anyway.
*/
if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K)
offset_low = round_down(offset_low,
@@ -1411,6 +1416,7 @@ static int igt_ppgtt_sanity_check(void *arg)
{ SZ_2M + SZ_4K, SZ_64K | SZ_4K },
{ SZ_2M + SZ_4K, SZ_2M | SZ_4K },
{ SZ_2M + SZ_64K, SZ_2M | SZ_64K },
+ { SZ_2M + SZ_64K, SZ_64K },
};
int i, j;
int err;
@@ -1540,6 +1546,154 @@ static int igt_ppgtt_compact(void *arg)
return err;
}
+static int igt_ppgtt_mixed(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ const unsigned long flags = PIN_OFFSET_FIXED | PIN_USER;
+ struct drm_i915_gem_object *obj, *on;
+ struct i915_gem_engines *engines;
+ struct i915_gem_engines_iter it;
+ struct i915_address_space *vm;
+ struct i915_gem_context *ctx;
+ struct intel_context *ce;
+ struct file *file;
+ I915_RND_STATE(prng);
+ LIST_HEAD(objects);
+ struct intel_memory_region *mr;
+ struct i915_vma *vma;
+ unsigned int count;
+ u32 i, addr;
+ int *order;
+ int n, err;
+
+ /*
+ * Sanity check mixing 4K and 64K pages within the same page-table via
+ * the new PS64 TLB hint.
+ */
+
+ if (!HAS_64K_PAGES(i915)) {
+ pr_info("device lacks PS64, skipping\n");
+ return 0;
+ }
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ ctx = hugepage_ctx(i915, file);
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto out;
+ }
+ vm = i915_gem_context_get_eb_vm(ctx);
+
+ i = 0;
+ addr = 0;
+ do {
+ u32 sz;
+
+ sz = i915_prandom_u32_max_state(SZ_4M, &prng);
+ sz = max_t(u32, sz, SZ_4K);
+
+ mr = i915->mm.regions[INTEL_REGION_LMEM_0];
+ if (i & 1)
+ mr = i915->mm.regions[INTEL_REGION_SMEM];
+
+ obj = i915_gem_object_create_region(mr, sz, 0, 0);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto out_vm;
+ }
+
+ list_add_tail(&obj->st_link, &objects);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_put;
+ }
+
+ addr = round_up(addr, mr->min_page_size);
+ err = i915_vma_pin(vma, 0, 0, addr | flags);
+ if (err)
+ goto err_put;
+
+ if (mr->type == INTEL_MEMORY_LOCAL &&
+ (vma->resource->page_sizes_gtt & I915_GTT_PAGE_SIZE_4K)) {
+ err = -EINVAL;
+ goto err_put;
+ }
+
+ addr += obj->base.size;
+ i++;
+ } while (addr <= SZ_16M);
+
+ n = 0;
+ count = 0;
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ count++;
+ if (!intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ n++;
+ }
+ i915_gem_context_unlock_engines(ctx);
+ if (!n)
+ goto err_put;
+
+ order = i915_random_order(count * count, &prng);
+ if (!order) {
+ err = -ENOMEM;
+ goto err_put;
+ }
+
+ i = 0;
+ addr = 0;
+ engines = i915_gem_context_lock_engines(ctx);
+ list_for_each_entry(obj, &objects, st_link) {
+ u32 rnd = i915_prandom_u32_max_state(UINT_MAX, &prng);
+
+ addr = round_up(addr, obj->mm.region->min_page_size);
+
+ ce = engines->engines[order[i] % engines->num_engines];
+ i = (i + 1) % (count * count);
+ if (!ce || !intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ err = __igt_write_huge(ce, obj, obj->base.size, addr, 0, rnd);
+ if (err)
+ break;
+
+ err = __igt_write_huge(ce, obj, obj->base.size, addr,
+ offset_in_page(rnd) / sizeof(u32), rnd + 1);
+ if (err)
+ break;
+
+ err = __igt_write_huge(ce, obj, obj->base.size, addr,
+ (PAGE_SIZE / sizeof(u32)) - 1,
+ rnd + 2);
+ if (err)
+ break;
+
+ addr += obj->base.size;
+
+ cond_resched();
+ }
+
+ i915_gem_context_unlock_engines(ctx);
+ kfree(order);
+err_put:
+ list_for_each_entry_safe(obj, on, &objects, st_link) {
+ list_del(&obj->st_link);
+ i915_gem_object_put(obj);
+ }
+out_vm:
+ i915_vm_put(vm);
+out:
+ fput(file);
+ return err;
+}
+
static int igt_tmpfs_fallback(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -1803,6 +1957,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_ppgtt_smoke_huge),
SUBTEST(igt_ppgtt_sanity_check),
SUBTEST(igt_ppgtt_compact),
+ SUBTEST(igt_ppgtt_mixed),
};
if (!HAS_PPGTT(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 8dd60d5ef905..4daaa6f55668 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -476,6 +476,7 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
unsigned int rem = sg_dma_len(iter->sg);
u64 start = vma_res->start;
+ u64 end = start + vma_res->vma_size;
GEM_BUG_ON(!i915_vm_is_4lvl(vm));
@@ -489,9 +490,10 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
gen8_pte_t encode = pte_encode;
unsigned int page_size;
gen8_pte_t *vaddr;
- u16 index, max;
+ u16 index, max, nent, i;
max = I915_PDES;
+ nent = 1;
if (vma_res->bi.page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
@@ -503,25 +505,37 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
vaddr = px_vaddr(pd);
} else {
- if (encode & GEN12_PPGTT_PTE_LM) {
- GEM_BUG_ON(__gen8_pte_index(start, 0) % 16);
- GEM_BUG_ON(rem < I915_GTT_PAGE_SIZE_64K);
- GEM_BUG_ON(!IS_ALIGNED(iter->dma,
- I915_GTT_PAGE_SIZE_64K));
-
- index = __gen8_pte_index(start, 0) / 16;
- page_size = I915_GTT_PAGE_SIZE_64K;
-
- max /= 16;
-
- vaddr = px_vaddr(pd);
- vaddr[__gen8_pte_index(start, 1)] |= GEN12_PDE_64K;
+ index = __gen8_pte_index(start, 0);
+ page_size = I915_GTT_PAGE_SIZE;
- pt->is_compact = true;
- } else {
- GEM_BUG_ON(pt->is_compact);
- index = __gen8_pte_index(start, 0);
- page_size = I915_GTT_PAGE_SIZE;
+ if (vma_res->bi.page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
+ /*
+ * Device local-memory on these platforms should
+ * always use 64K pages or larger (including GTT
+ * alignment), therefore if we know the whole
+ * page-table needs to be filled we can always
+ * safely use the compact-layout. Otherwise fall
+ * back to the TLB hint with PS64. If this is
+ * system memory we only bother with PS64.
+ */
+ if ((encode & GEN12_PPGTT_PTE_LM) &&
+ end - start >= SZ_2M && !index) {
+ index = __gen8_pte_index(start, 0) / 16;
+ page_size = I915_GTT_PAGE_SIZE_64K;
+
+ max /= 16;
+
+ vaddr = px_vaddr(pd);
+ vaddr[__gen8_pte_index(start, 1)] |= GEN12_PDE_64K;
+
+ pt->is_compact = true;
+ } else if (IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
+ rem >= I915_GTT_PAGE_SIZE_64K &&
+ !(index % 16)) {
+ encode |= GEN12_PTE_PS64;
+ page_size = I915_GTT_PAGE_SIZE_64K;
+ nent = 16;
+ }
}
vaddr = px_vaddr(pt);
@@ -529,7 +543,12 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
do {
GEM_BUG_ON(rem < page_size);
- vaddr[index++] = encode | iter->dma;
+
+ for (i = 0; i < nent; i++) {
+ vaddr[index++] =
+ encode | (iter->dma + i *
+ I915_GTT_PAGE_SIZE);
+ }
start += page_size;
iter->dma += page_size;
@@ -745,6 +764,8 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
GEM_BUG_ON(!IS_ALIGNED(addr, SZ_64K));
GEM_BUG_ON(!IS_ALIGNED(offset, SZ_64K));
+ /* XXX: we don't strictly need to use this layout */
+
if (!pt->is_compact) {
vaddr = px_vaddr(pd);
vaddr[gen8_pd_index(idx, 1)] |= GEN12_PDE_64K;
@@ -935,22 +956,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
/*
- * On some platforms the hw has dropped support for 4K GTT pages
- * when dealing with LMEM, and due to the design of 64K GTT
- * pages in the hw, we can only mark the *entire* page-table as
- * operating in 64K GTT mode, since the enable bit is still on
- * the pde, and not the pte. And since we still need to allow
- * 4K GTT pages for SMEM objects, we can't have a "normal" 4K
- * page-table with scratch pointing to LMEM, since that's
- * undefined from the hw pov. The simplest solution is to just
- * move the 64K scratch page to SMEM on all platforms and call
- * it a day, since that should work for all configurations.
- *
- * Using SMEM instead of LMEM has the additional advantage of
- * not reserving high performance memory for a "never" used
- * filler page. It also removes the device access that would
- * be required to initialise the scratch page, reducing pressure
- * on an even scarcer resource.
+ * Using SMEM here instead of LMEM has the advantage of not reserving
+ * high performance memory for a "never" used filler page. It also
+ * removes the device access that would be required to initialise the
+ * scratch page, reducing pressure on an even scarcer resource.
*/
ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 2eaeba14319e..13e411187fd5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -269,11 +269,7 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass)
memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
ARRAY_SIZE(vm->min_alignment));
- if (HAS_64K_PAGES(vm->i915) && NEEDS_COMPACT_PT(vm->i915) &&
- subclass == VM_CLASS_PPGTT) {
- vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_2M;
- vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_2M;
- } else if (HAS_64K_PAGES(vm->i915)) {
+ if (HAS_64K_PAGES(vm->i915)) {
vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_64K;
vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_64K;
}
@@ -343,7 +339,8 @@ int setup_scratch_page(struct i915_address_space *vm)
*/
size = I915_GTT_PAGE_SIZE_4K;
if (i915_vm_is_4lvl(vm) &&
- HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K))
+ HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K) &&
+ !HAS_64K_PAGES(vm->i915))
size = I915_GTT_PAGE_SIZE_64K;
do {
@@ -385,18 +382,6 @@ int setup_scratch_page(struct i915_address_space *vm)
if (size == I915_GTT_PAGE_SIZE_4K)
return -ENOMEM;
- /*
- * If we need 64K minimum GTT pages for device local-memory,
- * like on XEHPSDV, then we need to fail the allocation here,
- * otherwise we can't safely support the insertion of
- * local-memory pages for this vm, since the HW expects the
- * correct physical alignment and size when the page-table is
- * operating in 64K GTT mode, which includes any scratch PTEs,
- * since userspace can still touch them.
- */
- if (HAS_64K_PAGES(vm->i915))
- return -ENOMEM;
-
size = I915_GTT_PAGE_SIZE_4K;
} while (1);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index c0ca53cba9f0..062b78333fb2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -93,6 +93,7 @@ typedef u64 gen8_pte_t;
#define GEN12_GGTT_PTE_LM BIT_ULL(1)
#define GEN12_PDE_64K BIT(6)
+#define GEN12_PTE_PS64 BIT(8)
/*
* Cacheability Control is a 4-bit value. The low three bits are stored in bits
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90ed8e6db2fe..c9147e50fa5d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -902,13 +902,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
*/
#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
-/*
- * Set this flag when platform doesn't allow both 64k pages and 4k pages in
- * the same PT. this flag means we need to support compact PT layout for the
- * ppGTT when using the 64K GTT pages.
- */
-#define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
-
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 38460a0bd7cb..40bb06c5cdc0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1042,7 +1042,6 @@ static const struct intel_device_info xehpsdv_info = {
PLATFORM(INTEL_XEHPSDV),
NO_DISPLAY,
.has_64k_pages = 1,
- .needs_compact_pt = 1,
.has_media_ratio_mode = 1,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
@@ -1064,7 +1063,6 @@ static const struct intel_device_info xehpsdv_info = {
.has_64k_pages = 1, \
.has_guc_deprivilege = 1, \
.has_heci_pxp = 1, \
- .needs_compact_pt = 1, \
.has_media_ratio_mode = 1, \
.__runtime.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index f17c09ead7d7..c39488eb9eeb 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -776,12 +776,6 @@ i915_vma_insert(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
alignment = max(alignment, i915_vm_obj_min_alignment(vma->vm, vma->obj));
- /*
- * for compact-pt we round up the reservation to prevent
- * any smaller pages being used within the same PDE
- */
- if (NEEDS_COMPACT_PT(vma->vm->i915))
- size = round_up(size, alignment);
/* If binding the object/GGTT view requires more space than the entire
* aperture has, reject it early before evicting everything in a vain
@@ -820,7 +814,8 @@ i915_vma_insert(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
* forseeable future. See also i915_ggtt_offset().
*/
if (upper_32_bits(end - 1) &&
- vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
+ vma->page_sizes.sg > I915_GTT_PAGE_SIZE &&
+ !HAS_64K_PAGES(vma->vm->i915)) {
/*
* We can't mix 64K and 4K PTEs in the same page-table
* (2M block), and so to avoid the ugliness and
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index bc87d3156b14..58539660a1ec 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -146,7 +146,6 @@ enum intel_ppgtt_type {
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(has_64k_pages); \
- func(needs_compact_pt); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_3d_pipeline); \
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index ea2cf1080979..27c733b00976 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1114,15 +1114,8 @@ static int misaligned_case(struct i915_address_space *vm, struct intel_memory_re
expected_node_size = expected_vma_size;
if (HAS_64K_PAGES(vm->i915) && i915_gem_object_is_lmem(obj)) {
- /*
- * The compact-pt should expand lmem node to 2MB for the ppGTT,
- * for all other cases we should only expect 64K.
- */
expected_vma_size = round_up(size, I915_GTT_PAGE_SIZE_64K);
- if (NEEDS_COMPACT_PT(vm->i915) && !i915_is_ggtt(vm))
- expected_node_size = round_up(size, I915_GTT_PAGE_SIZE_2M);
- else
- expected_node_size = round_up(size, I915_GTT_PAGE_SIZE_64K);
+ expected_node_size = round_up(size, I915_GTT_PAGE_SIZE_64K);
}
if (vma->size != expected_vma_size || vma->node.size != expected_node_size) {
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 629198f1d8d8..08d69e36fb66 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3509,27 +3509,13 @@ struct drm_i915_gem_create_ext {
*
* The (page-aligned) allocated size for the object will be returned.
*
- * DG2 64K min page size implications:
+ * On platforms like DG2/ATS the kernel will always use 64K or larger
+ * pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a
+ * minimum of 64K GTT alignment for such objects.
*
- * On discrete platforms, starting from DG2, we have to contend with GTT
- * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
- * objects. Specifically the hardware only supports 64K or larger GTT
- * page sizes for such memory. The kernel will already ensure that all
- * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
- * sizes underneath.
- *
- * Note that the returned size here will always reflect any required
- * rounding up done by the kernel, i.e 4K will now become 64K on devices
- * such as DG2. The kernel will always select the largest minimum
- * page-size for the set of possible placements as the value to use when
- * rounding up the @size.
- *
- * Special DG2 GTT address alignment requirement:
- *
- * The GTT alignment will also need to be at least 2M for such objects.
- *
- * Note that due to how the hardware implements 64K GTT page support, we
- * have some further complications:
+ * NOTE: Previously the ABI here required a minimum GTT alignment of 2M
+ * on DG2/ATS, due to how the hardware implemented 64K GTT page support,
+ * where we had the following complications:
*
* 1) The entire PDE (which covers a 2MB virtual address range), must
* contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
@@ -3538,12 +3524,10 @@ struct drm_i915_gem_create_ext {
* 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
* objects.
*
- * To keep things simple for userland, we mandate that any GTT mappings
- * must be aligned to and rounded up to 2MB. The kernel will internally
- * pad them out to the next 2MB boundary. As this only wastes virtual
- * address space and avoids userland having to copy any needlessly
- * complicated PDE sharing scheme (coloring) and only affects DG2, this
- * is deemed to be a good compromise.
+ * However on actual production HW this was completely changed to now
+ * allow setting a TLB hint at the PTE level (see PS64), which is a lot
+ * more flexible than the above. With this the 2M restriction was
+ * dropped where we now only require 64K.
*/
__u64 size;
--
2.37.3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
@ 2022-10-04 11:49 ` Matthew Auld
-1 siblings, 0 replies; 21+ messages in thread
From: Matthew Auld @ 2022-10-04 11:49 UTC (permalink / raw)
To: intel-gfx
Cc: Thomas Hellström, Yang A Shi, Jordan Justen,
Lionel Landwerlin, Stuart Summers, Michal Mrozek, dri-devel,
Niranjana Vishwanathapura, Nirmoy Das
On some platforms we potentially have different alignment restrictions
depending on the memory type. We also now have different alignment
restrictions for the same region across different kernel versions.
Extend the region query to return the minimum required GTT alignment.
Testcase: igt@gem_create@create-ext-placement-alignment
Testcase: igt@i915_query@query-regions-sanity-check
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Michal Mrozek <michal.mrozek@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Yang A Shi <yang.a.shi@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
drivers/gpu/drm/i915/i915_query.c | 1 +
include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++++++++--
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 6ec9c9fb7b0d..111377f210ed 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -498,6 +498,7 @@ static int query_memregion_info(struct drm_i915_private *i915,
info.region.memory_class = mr->type;
info.region.memory_instance = mr->instance;
info.probed_size = mr->total;
+ info.gtt_alignment = mr->min_page_size;
if (mr->type == INTEL_MEMORY_LOCAL)
info.probed_cpu_visible_size = mr->io_size;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 08d69e36fb66..2e613109356b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3346,8 +3346,33 @@ struct drm_i915_memory_region_info {
/** @region: The class:instance pair encoding */
struct drm_i915_gem_memory_class_instance region;
- /** @rsvd0: MBZ */
- __u32 rsvd0;
+ union {
+ /** @rsvd0: MBZ */
+ __u32 rsvd0;
+ /**
+ * @gtt_alignment:
+ *
+ * The minimum required GTT alignment for this type of memory.
+ * When allocating a GTT address it must be aligned to this
+ * value or larger. On some platforms the kernel might opt to
+ * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
+ * pages can then be used if we also use 64K GTT alignment.
+ *
+ * NOTE: If this is zero then this must be an older
+ * kernel which lacks support for this field.
+ *
+ * Side note: For larger objects (especially for
+ * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
+ * consider potentially bumping the GTT alignment to say 2M,
+ * which could potentially increase the likelihood of the kernel
+ * being able to utilise 2M GTT pages underneath, if the layout
+ * of the physical pages allows it. On some configurations we
+ * can then also use a more efficient page-table layout, if we
+ * can't use the more desirable 2M GTT page, so long as we know
+ * that the entire page-table will be used by this object.
+ */
+ __u32 gtt_alignment;
+ };
/**
* @probed_size: Memory probed by the driver
--
2.37.3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
@ 2022-10-04 11:49 ` Matthew Auld
0 siblings, 0 replies; 21+ messages in thread
From: Matthew Auld @ 2022-10-04 11:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Thomas Hellström, Michal Mrozek, dri-devel, Nirmoy Das
On some platforms we potentially have different alignment restrictions
depending on the memory type. We also now have different alignment
restrictions for the same region across different kernel versions.
Extend the region query to return the minimum required GTT alignment.
Testcase: igt@gem_create@create-ext-placement-alignment
Testcase: igt@i915_query@query-regions-sanity-check
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Michal Mrozek <michal.mrozek@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Yang A Shi <yang.a.shi@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
drivers/gpu/drm/i915/i915_query.c | 1 +
include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++++++++--
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 6ec9c9fb7b0d..111377f210ed 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -498,6 +498,7 @@ static int query_memregion_info(struct drm_i915_private *i915,
info.region.memory_class = mr->type;
info.region.memory_instance = mr->instance;
info.probed_size = mr->total;
+ info.gtt_alignment = mr->min_page_size;
if (mr->type == INTEL_MEMORY_LOCAL)
info.probed_cpu_visible_size = mr->io_size;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 08d69e36fb66..2e613109356b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3346,8 +3346,33 @@ struct drm_i915_memory_region_info {
/** @region: The class:instance pair encoding */
struct drm_i915_gem_memory_class_instance region;
- /** @rsvd0: MBZ */
- __u32 rsvd0;
+ union {
+ /** @rsvd0: MBZ */
+ __u32 rsvd0;
+ /**
+ * @gtt_alignment:
+ *
+ * The minimum required GTT alignment for this type of memory.
+ * When allocating a GTT address it must be aligned to this
+ * value or larger. On some platforms the kernel might opt to
+ * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
+ * pages can then be used if we also use 64K GTT alignment.
+ *
+ * NOTE: If this is zero then this must be an older
+ * kernel which lacks support for this field.
+ *
+ * Side note: For larger objects (especially for
+ * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
+ * consider potentially bumping the GTT alignment to say 2M,
+ * which could potentially increase the likelihood of the kernel
+ * being able to utilise 2M GTT pages underneath, if the layout
+ * of the physical pages allows it. On some configurations we
+ * can then also use a more efficient page-table layout, if we
+ * can't use the more desirable 2M GTT page, so long as we know
+ * that the entire page-table will be used by this object.
+ */
+ __u32 gtt_alignment;
+ };
/**
* @probed_size: Memory probed by the driver
--
2.37.3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
(?)
(?)
@ 2022-10-04 12:35 ` Patchwork
-1 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-10-04 12:35 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2
URL : https://patchwork.freedesktop.org/series/109384/
State : warning
== Summary ==
Error: dim checkpatch failed
88944e5bbc43 drm/i915: enable PS64 support for DG2
-:15: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit caa574ffc4aa ("drm/i915/uapi: document behaviour for DG2 64K support")'
#15:
commit caa574ffc4aaf4f29b890223878c63e2e7772f62
-:101: WARNING:LINE_SPACING: Missing a blank line after declarations
#101: FILE: drivers/gpu/drm/i915/gem/selftests/huge_pages.c:1560:
+ struct file *file;
+ I915_RND_STATE(prng);
total: 1 errors, 1 warnings, 0 checks, 473 lines checked
6f272c04e933 drm/i915/uapi: expose GTT alignment
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
` (2 preceding siblings ...)
(?)
@ 2022-10-04 12:55 ` Patchwork
-1 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-10-04 12:55 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6303 bytes --]
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2
URL : https://patchwork.freedesktop.org/series/109384/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12210 -> Patchwork_109384v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/index.html
Participating hosts (44 -> 42)
------------------------------
Additional (1): fi-hsw-4770
Missing (3): fi-bxt-dsi fi-bdw-samus fi-hsw-4200u
Known issues
------------
Here are the changes found in Patchwork_109384v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770: NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/fi-hsw-4770/igt@gem_softpin@allocator-basic-reserve.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#3012])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/fi-hsw-4770/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: NOTRUN -> [INCOMPLETE][3] ([i915#4785])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +7 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/fi-hsw-4770/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [PASS][5] -> [FAIL][6] ([i915#6298])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1072]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#4312] / [i915#5594])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/fi-hsw-4770/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}: [DMESG-WARN][9] ([i915#2867]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [DMESG-FAIL][11] ([i915#62]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u: [DMESG-WARN][13] ([i915#5904]) -> [PASS][14] +30 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [DMESG-WARN][15] ([i915#5904] / [i915#62]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-WARN][17] ([i915#62]) -> [PASS][18] +12 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
[i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6818]: https://gitlab.freedesktop.org/drm/intel/issues/6818
Build changes
-------------
* Linux: CI_DRM_12210 -> Patchwork_109384v1
CI-20190529: 20190529
CI_DRM_12210: 707950e821d9dbd362f71726ecbd03c9e42dad05 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6676: 4730ad6fa95e74b30a7c7acff7041b591e6ce276 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109384v1: 707950e821d9dbd362f71726ecbd03c9e42dad05 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
d78abd576430 drm/i915/uapi: expose GTT alignment
3e792815dc5e drm/i915: enable PS64 support for DG2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/index.html
[-- Attachment #2: Type: text/html, Size: 7408 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
@ 2022-10-04 14:08 ` Das, Nirmoy
-1 siblings, 0 replies; 21+ messages in thread
From: Das, Nirmoy @ 2022-10-04 14:08 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
Cc: Thomas Hellström, Yang A Shi, Jordan Justen,
Lionel Landwerlin, Stuart Summers, Michal Mrozek, dri-devel,
Niranjana Vishwanathapura, Nirmoy Das
On 10/4/2022 1:49 PM, Matthew Auld wrote:
> On some platforms we potentially have different alignment restrictions
> depending on the memory type. We also now have different alignment
> restrictions for the same region across different kernel versions.
> Extend the region query to return the minimum required GTT alignment.
>
> Testcase: igt@gem_create@create-ext-placement-alignment
> Testcase: igt@i915_query@query-regions-sanity-check
> Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Michal Mrozek <michal.mrozek@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Yang A Shi <yang.a.shi@intel.com>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> ---
> drivers/gpu/drm/i915/i915_query.c | 1 +
> include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++++++++--
> 2 files changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 6ec9c9fb7b0d..111377f210ed 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -498,6 +498,7 @@ static int query_memregion_info(struct drm_i915_private *i915,
> info.region.memory_class = mr->type;
> info.region.memory_instance = mr->instance;
> info.probed_size = mr->total;
> + info.gtt_alignment = mr->min_page_size;
>
> if (mr->type == INTEL_MEMORY_LOCAL)
> info.probed_cpu_visible_size = mr->io_size;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 08d69e36fb66..2e613109356b 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -3346,8 +3346,33 @@ struct drm_i915_memory_region_info {
> /** @region: The class:instance pair encoding */
> struct drm_i915_gem_memory_class_instance region;
>
> - /** @rsvd0: MBZ */
> - __u32 rsvd0;
> + union {
> + /** @rsvd0: MBZ */
> + __u32 rsvd0;
> + /**
> + * @gtt_alignment:
> + *
> + * The minimum required GTT alignment for this type of memory.
> + * When allocating a GTT address it must be aligned to this
> + * value or larger. On some platforms the kernel might opt to
> + * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
> + * pages can then be used if we also use 64K GTT alignment.
> + *
> + * NOTE: If this is zero then this must be an older
> + * kernel which lacks support for this field.
> + *
> + * Side note: For larger objects (especially for
> + * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
> + * consider potentially bumping the GTT alignment to say 2M,
> + * which could potentially increase the likelihood of the kernel
> + * being able to utilise 2M GTT pages underneath, if the layout
> + * of the physical pages allows it. On some configurations we
> + * can then also use a more efficient page-table layout, if we
> + * can't use the more desirable 2M GTT page, so long as we know
> + * that the entire page-table will be used by this object.
> + */
> + __u32 gtt_alignment;
> + };
>
> /**
> * @probed_size: Memory probed by the driver
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
@ 2022-10-04 14:08 ` Das, Nirmoy
0 siblings, 0 replies; 21+ messages in thread
From: Das, Nirmoy @ 2022-10-04 14:08 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
Cc: Thomas Hellström, Michal Mrozek, dri-devel, Nirmoy Das
On 10/4/2022 1:49 PM, Matthew Auld wrote:
> On some platforms we potentially have different alignment restrictions
> depending on the memory type. We also now have different alignment
> restrictions for the same region across different kernel versions.
> Extend the region query to return the minimum required GTT alignment.
>
> Testcase: igt@gem_create@create-ext-placement-alignment
> Testcase: igt@i915_query@query-regions-sanity-check
> Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Michal Mrozek <michal.mrozek@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Yang A Shi <yang.a.shi@intel.com>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> ---
> drivers/gpu/drm/i915/i915_query.c | 1 +
> include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++++++++--
> 2 files changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 6ec9c9fb7b0d..111377f210ed 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -498,6 +498,7 @@ static int query_memregion_info(struct drm_i915_private *i915,
> info.region.memory_class = mr->type;
> info.region.memory_instance = mr->instance;
> info.probed_size = mr->total;
> + info.gtt_alignment = mr->min_page_size;
>
> if (mr->type == INTEL_MEMORY_LOCAL)
> info.probed_cpu_visible_size = mr->io_size;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 08d69e36fb66..2e613109356b 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -3346,8 +3346,33 @@ struct drm_i915_memory_region_info {
> /** @region: The class:instance pair encoding */
> struct drm_i915_gem_memory_class_instance region;
>
> - /** @rsvd0: MBZ */
> - __u32 rsvd0;
> + union {
> + /** @rsvd0: MBZ */
> + __u32 rsvd0;
> + /**
> + * @gtt_alignment:
> + *
> + * The minimum required GTT alignment for this type of memory.
> + * When allocating a GTT address it must be aligned to this
> + * value or larger. On some platforms the kernel might opt to
> + * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
> + * pages can then be used if we also use 64K GTT alignment.
> + *
> + * NOTE: If this is zero then this must be an older
> + * kernel which lacks support for this field.
> + *
> + * Side note: For larger objects (especially for
> + * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
> + * consider potentially bumping the GTT alignment to say 2M,
> + * which could potentially increase the likelihood of the kernel
> + * being able to utilise 2M GTT pages underneath, if the layout
> + * of the physical pages allows it. On some configurations we
> + * can then also use a more efficient page-table layout, if we
> + * can't use the more desirable 2M GTT page, so long as we know
> + * that the entire page-table will be used by this object.
> + */
> + __u32 gtt_alignment;
> + };
>
> /**
> * @probed_size: Memory probed by the driver
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
` (3 preceding siblings ...)
(?)
@ 2022-10-04 17:48 ` Patchwork
-1 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-10-04 17:48 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 38646 bytes --]
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2
URL : https://patchwork.freedesktop.org/series/109384/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12210_full -> Patchwork_109384v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_109384v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109384v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109384v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_query@query-regions-garbage-items:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb5/igt@i915_query@query-regions-garbage-items.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb1/igt@i915_query@query-regions-garbage-items.html
- shard-snb: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-snb4/igt@i915_query@query-regions-garbage-items.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-snb5/igt@i915_query@query-regions-garbage-items.html
- shard-tglb: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-tglb3/igt@i915_query@query-regions-garbage-items.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb7/igt@i915_query@query-regions-garbage-items.html
Known issues
------------
Here are the changes found in Patchwork_109384v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-apl: ([PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30]) -> ([PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [FAIL][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55]) ([i915#4386])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl3/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl3/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl3/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl6/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl6/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl6/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl6/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl7/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl7/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl7/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl7/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl8/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl8/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl8/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl8/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl1/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl1/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl2/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl2/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl2/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl2/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl2/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl1/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl1/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl1/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl1/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl1/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl2/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl2/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl2/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl2/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl2/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl3/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl3/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl3/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl6/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl6/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl6/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl6/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl7/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl7/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl7/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl7/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl7/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl8/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl8/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl8/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl8/boot.html
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [FAIL][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80]) ([i915#4392]) -> ([PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk1/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk1/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk1/boot.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk2/boot.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk2/boot.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk2/boot.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk3/boot.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk3/boot.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk3/boot.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk5/boot.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk5/boot.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk5/boot.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk6/boot.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk6/boot.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk6/boot.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk7/boot.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk7/boot.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk7/boot.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk8/boot.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk8/boot.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk8/boot.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk8/boot.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk9/boot.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk9/boot.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk9/boot.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk1/boot.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk1/boot.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk1/boot.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk2/boot.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk2/boot.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk2/boot.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk3/boot.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk3/boot.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk3/boot.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk5/boot.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk5/boot.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk5/boot.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk6/boot.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk6/boot.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk6/boot.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk6/boot.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk7/boot.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk7/boot.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk7/boot.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk8/boot.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk8/boot.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk8/boot.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk9/boot.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk9/boot.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk9/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][106] -> [FAIL][107] ([i915#6268])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-tglb8/igt@gem_ctx_exec@basic-nohangcheck.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-snb: [PASS][108] -> [FAIL][109] ([i915#4409])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-snb4/igt@gem_eio@in-flight-contexts-1us.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-snb5/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_eio@reset-stress:
- shard-tglb: [PASS][110] -> [FAIL][111] ([i915#5784]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-tglb1/igt@gem_eio@reset-stress.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][112] ([i915#2842])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-tglb: NOTRUN -> [SKIP][113] ([fdo#109313])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_whisper@basic-queues-priority-all:
- shard-iclb: [PASS][114] -> [INCOMPLETE][115] ([i915#6755])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb7/igt@gem_exec_whisper@basic-queues-priority-all.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb3/igt@gem_exec_whisper@basic-queues-priority-all.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][116] -> [SKIP][117] ([i915#2190])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-tglb3/igt@gem_huc_copy@huc-copy.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb7/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-random:
- shard-tglb: NOTRUN -> [SKIP][118] ([i915#4613])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_lmem_swapping@parallel-random:
- shard-glk: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#4613])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk1/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@verify-random:
- shard-apl: NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#4613]) +2 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl3/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][121] ([i915#2658])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl3/igt@gem_pread@exhaustion.html
* igt@gem_softpin@evict-single-offset:
- shard-iclb: [PASS][122] -> [FAIL][123] ([i915#4171])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb7/igt@gem_softpin@evict-single-offset.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb6/igt@gem_softpin@evict-single-offset.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-tglb: NOTRUN -> [SKIP][124] ([fdo#109289])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][125] -> [DMESG-WARN][126] ([i915#5566] / [i915#716]) +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk6/igt@gen9_exec_parse@allowed-all.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk1/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][127] -> [DMESG-WARN][128] ([i915#5566] / [i915#716])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl1/igt@gen9_exec_parse@allowed-single.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl6/igt@gen9_exec_parse@allowed-single.html
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [PASS][129] -> [DMESG-WARN][130] ([i915#5591])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-tglb1/igt@i915_selftest@live@hangcheck.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@i915_selftest@live@hangcheck.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-vga-1:
- shard-snb: [PASS][131] -> [FAIL][132] ([i915#2521])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-snb4/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-vga-1.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-snb5/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-vga-1.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-glk: NOTRUN -> [SKIP][133] ([fdo#109271]) +31 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][134] ([fdo#111614])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-tglb: NOTRUN -> [SKIP][135] ([fdo#111615])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][136] ([i915#3689])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:
- shard-tglb: NOTRUN -> [SKIP][137] ([i915#6095]) +1 similar issue
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#3886]) +2 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl8/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#3886]) +1 similar issue
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk1/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][140] ([fdo#111615] / [i915#3689])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
- shard-tglb: NOTRUN -> [SKIP][141] ([i915#3689] / [i915#6095]) +1 similar issue
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html
* igt@kms_chamelium@hdmi-crc-single:
- shard-glk: NOTRUN -> [SKIP][142] ([fdo#109271] / [fdo#111827]) +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk1/igt@kms_chamelium@hdmi-crc-single.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-apl: NOTRUN -> [SKIP][143] ([fdo#109271] / [fdo#111827]) +2 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl8/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [PASS][144] -> [FAIL][145] ([i915#2346])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor@toggle:
- shard-iclb: [PASS][146] -> [FAIL][147] ([i915#2346]) +2 similar issues
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp1:
- shard-apl: [PASS][148] -> [FAIL][149] ([i915#79])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl8/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl7/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][150] ([i915#2672]) +1 similar issue
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][151] ([i915#2672] / [i915#3555])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][152] ([i915#2587] / [i915#2672]) +2 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][153] ([i915#3555])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-tglb: NOTRUN -> [SKIP][154] ([fdo#109280] / [fdo#111825]) +3 similar issues
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-apl: NOTRUN -> [SKIP][155] ([fdo#109271]) +109 similar issues
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-tglb: NOTRUN -> [SKIP][156] ([i915#3555])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
- shard-iclb: [PASS][157] -> [SKIP][158] ([i915#5176]) +2 similar issues
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb3/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1:
- shard-iclb: [PASS][159] -> [SKIP][160] ([i915#5235]) +2 similar issues
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_prime@basic-crc-hybrid:
- shard-tglb: NOTRUN -> [SKIP][161] ([i915#6524])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][162] ([fdo#109271] / [i915#658]) +1 similar issue
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl3/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [PASS][163] -> [SKIP][164] ([fdo#109642] / [fdo#111068] / [i915#658])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb6/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [PASS][165] -> [SKIP][166] ([fdo#109441])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb4/igt@kms_psr@psr2_primary_blt.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][167] ([fdo#109271] / [i915#2437])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl3/igt@kms_writeback@writeback-fb-id.html
* igt@perf@stress-open-close:
- shard-glk: NOTRUN -> [INCOMPLETE][168] ([i915#5213])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk1/igt@perf@stress-open-close.html
* igt@sysfs_clients@fair-3:
- shard-glk: NOTRUN -> [SKIP][169] ([fdo#109271] / [i915#2994]) +1 similar issue
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk1/igt@sysfs_clients@fair-3.html
* igt@sysfs_heartbeat_interval@nopreempt@vcs0:
- shard-tglb: [PASS][170] -> [FAIL][171] ([i915#6015]) +4 similar issues
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-tglb5/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb1/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel:
- shard-iclb: [SKIP][172] ([i915#4525]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb6/igt@gem_exec_balancer@parallel.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb4/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][174] ([i915#2842]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@i915_pm_rps@engine-order:
- shard-apl: [FAIL][176] ([i915#6537]) -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl3/igt@i915_pm_rps@engine-order.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl6/igt@i915_pm_rps@engine-order.html
* igt@i915_selftest@live@execlists:
- shard-tglb: [INCOMPLETE][178] ([i915#2411]) -> [PASS][179]
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-tglb1/igt@i915_selftest@live@execlists.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [DMESG-FAIL][180] ([i915#5334]) -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl6/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [FAIL][182] ([i915#2346]) -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][184] ([i915#2122]) -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-apl: [DMESG-WARN][186] ([i915#180]) -> [PASS][187] +1 similar issue
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl2/igt@kms_flip@flip-vs-suspend@b-dp1.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl1/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][188] ([fdo#109441]) -> [PASS][189] +2 similar issues
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb8/igt@kms_psr@psr2_basic.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-iclb: [SKIP][190] ([i915#5519]) -> [PASS][191]
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@perf@polling-parameterized:
- shard-tglb: [FAIL][192] ([i915#5639]) -> [PASS][193]
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-tglb1/igt@perf@polling-parameterized.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [FAIL][194] ([i915#6117]) -> [SKIP][195] ([i915#4525])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [SKIP][196] ([i915#2848]) -> [FAIL][197] ([i915#2842]) +5 similar issues
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-tglb1/igt@gem_exec_fair@basic-pace@vcs1.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-tglb3/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-glk: [DMESG-FAIL][198] ([i915#118] / [i915#1888]) -> [FAIL][199] ([i915#1888])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-glk2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][200] ([i915#658]) -> [SKIP][201] ([i915#2920]) +1 similar issue
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb3/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: [FAIL][202] ([i915#5939]) -> [SKIP][203] ([fdo#109642] / [fdo#111068] / [i915#658])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-iclb3/igt@kms_psr2_su@page_flip-p010.html
* igt@runner@aborted:
- shard-apl: ([FAIL][204], [FAIL][205], [FAIL][206], [FAIL][207]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][208], [FAIL][209]) ([fdo#109271] / [i915#3002] / [i915#4312])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl2/igt@runner@aborted.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl2/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl6/igt@runner@aborted.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12210/shard-apl7/igt@runner@aborted.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl6/igt@runner@aborted.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/shard-apl1/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2848]: https://gitlab.freedesktop.org/drm/intel/issues/2848
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4409]: https://gitlab.freedesktop.org/drm/intel/issues/4409
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12210 -> Patchwork_109384v1
CI-20190529: 20190529
CI_DRM_12210: 707950e821d9dbd362f71726ecbd03c9e42dad05 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6676: 4730ad6fa95e74b30a7c7acff7041b591e6ce276 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109384v1: 707950e821d9dbd362f71726ecbd03c9e42dad05 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v1/index.html
[-- Attachment #2: Type: text/html, Size: 43784 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 (rev2)
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
` (4 preceding siblings ...)
(?)
@ 2022-10-06 10:17 ` Patchwork
-1 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-10-06 10:17 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/109384/
State : warning
== Summary ==
Error: dim checkpatch failed
cd65a7e6406b drm/i915: enable PS64 support for DG2
-:15: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit caa574ffc4aa ("drm/i915/uapi: document behaviour for DG2 64K support")'
#15:
commit caa574ffc4aaf4f29b890223878c63e2e7772f62
-:101: WARNING:LINE_SPACING: Missing a blank line after declarations
#101: FILE: drivers/gpu/drm/i915/gem/selftests/huge_pages.c:1560:
+ struct file *file;
+ I915_RND_STATE(prng);
total: 1 errors, 1 warnings, 0 checks, 473 lines checked
b51b3b01bf54 drm/i915/uapi: expose GTT alignment
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 (rev2)
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
` (5 preceding siblings ...)
(?)
@ 2022-10-06 10:17 ` Patchwork
-1 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-10-06 10:17 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/109384/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 (rev2)
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
` (6 preceding siblings ...)
(?)
@ 2022-10-06 10:41 ` Patchwork
-1 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-10-06 10:41 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5904 bytes --]
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/109384/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12222 -> Patchwork_109384v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/index.html
Participating hosts (43 -> 41)
------------------------------
Additional (1): fi-tgl-dsi
Missing (3): fi-ctg-p8600 fi-bxt-dsi fi-hsw-4200u
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109384v2:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-rte:
- {bat-rplp-1}: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
Known issues
------------
Here are the changes found in Patchwork_109384v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/fi-apl-guc/igt@gem_lmem_swapping@basic.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/fi-apl-guc/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][5] ([fdo#109271]) +11 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html
#### Possible fixes ####
* igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [INCOMPLETE][6] -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/fi-apl-guc/igt@gem_render_tiled_blits@basic.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/fi-apl-guc/igt@gem_render_tiled_blits@basic.html
* igt@i915_selftest@live@guc:
- {bat-rpls-2}: [DMESG-WARN][8] ([i915#6471]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/bat-rpls-2/igt@i915_selftest@live@guc.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/bat-rpls-2/igt@i915_selftest@live@guc.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-2:
- {bat-dg2-11}: [FAIL][10] ([i915#6818]) -> [PASS][11] +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-2.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-2.html
#### Warnings ####
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [FAIL][12] ([fdo#103375]) -> [INCOMPLETE][13] ([i915#5982])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6471]: https://gitlab.freedesktop.org/drm/intel/issues/6471
[i915#6818]: https://gitlab.freedesktop.org/drm/intel/issues/6818
[i915#6856]: https://gitlab.freedesktop.org/drm/intel/issues/6856
[i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029
[i915#7031]: https://gitlab.freedesktop.org/drm/intel/issues/7031
Build changes
-------------
* Linux: CI_DRM_12222 -> Patchwork_109384v2
CI-20190529: 20190529
CI_DRM_12222: 6278acf81fd635214b7e310bb325c218e72e0349 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7001: d21216f0db39457717274d74b4d2e3db6683aa63 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109384v2: 6278acf81fd635214b7e310bb325c218e72e0349 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f24cbcba21aa drm/i915/uapi: expose GTT alignment
3f9bc3790b30 drm/i915: enable PS64 support for DG2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/index.html
[-- Attachment #2: Type: text/html, Size: 5764 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 (rev2)
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
` (7 preceding siblings ...)
(?)
@ 2022-10-07 1:59 ` Patchwork
-1 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-10-07 1:59 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 38449 bytes --]
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/109384/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12222_full -> Patchwork_109384v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_109384v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109384v2_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 12)
------------------------------
Additional (3): shard-rkl shard-dg1 shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109384v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pipe_stress@stress-xrgb8888-ytiled:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-iclb2/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb4/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
* igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [INCOMPLETE][3] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl9/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size.html
Known issues
------------
Here are the changes found in Patchwork_109384v2_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [FAIL][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#4392])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk1/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk1/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk1/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk2/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk2/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk2/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk3/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk3/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk3/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk6/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk7/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk7/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk7/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk8/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk8/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk8/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk9/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk9/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk9/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk9/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk9/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk9/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk8/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk8/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk8/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk7/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk7/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk7/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk6/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk5/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk5/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk5/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk3/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk3/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk3/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk2/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk2/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk2/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk1/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk1/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][54] ([i915#2842])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: [PASS][55] -> [FAIL][56] ([i915#2842])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-glk9/igt@gem_exec_fair@basic-pace@vecs0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-glk7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_lmem_swapping@random:
- shard-iclb: NOTRUN -> [SKIP][57] ([i915#4613])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@gem_lmem_swapping@random.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-iclb: NOTRUN -> [SKIP][58] ([i915#4270])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gen7_exec_parse@bitmasks:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109289])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@gen7_exec_parse@bitmasks.html
* igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][60] ([i915#2856])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@gen9_exec_parse@secure-batches.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: NOTRUN -> [FAIL][61] ([i915#454])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl7/igt@i915_pm_dc@dc6-psr.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
- shard-skl: [PASS][62] -> [FAIL][63] ([i915#2521])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271]) +11 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-apl3/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-iclb: NOTRUN -> [SKIP][65] ([i915#5286]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][66] ([fdo#110725] / [fdo#111614])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][67] ([fdo#110723])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_big_joiner@invalid-modeset:
- shard-iclb: NOTRUN -> [SKIP][68] ([i915#2705])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109278] / [i915#3886])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][70] ([fdo#109278]) +4 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#3886]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl1/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-iclb: NOTRUN -> [SKIP][72] ([fdo#109284] / [fdo#111827]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_chamelium@vga-hpd-after-suspend.html
* igt@kms_color@ctm-0-25@pipe-c-edp-1:
- shard-iclb: NOTRUN -> [FAIL][73] ([i915#315] / [i915#6946]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_color@ctm-0-25@pipe-c-edp-1.html
* igt@kms_color_chamelium@ctm-0-50:
- shard-skl: NOTRUN -> [SKIP][74] ([fdo#109271] / [fdo#111827])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl1/igt@kms_color_chamelium@ctm-0-50.html
* igt@kms_content_protection@srm:
- shard-iclb: NOTRUN -> [SKIP][75] ([fdo#109300] / [fdo#111066])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-iclb: NOTRUN -> [SKIP][76] ([i915#3359])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-iclb: NOTRUN -> [SKIP][77] ([i915#3555])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1:
- shard-apl: [PASS][78] -> [DMESG-WARN][79] ([i915#180])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-apl7/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-apl8/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
* igt@kms_flip@2x-blocking-wf_vblank:
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109274]) +5 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_flip@2x-blocking-wf_vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][81] -> [FAIL][82] ([i915#79]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][83] ([i915#2587] / [i915#2672])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][84] ([i915#2672]) +2 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][85] ([i915#2672] / [i915#3555]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][86] ([fdo#109280]) +7 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-edp-1:
- shard-iclb: NOTRUN -> [SKIP][87] ([i915#5176]) +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-edp-1.html
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-a-edp-1:
- shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271]) +42 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl7/igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-a-edp-1.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: NOTRUN -> [SKIP][89] ([fdo#109441])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html
* igt@perf_pmu@event-wait@rcs0:
- shard-iclb: NOTRUN -> [SKIP][90] ([fdo#112283])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@perf_pmu@event-wait@rcs0.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-apl: [DMESG-WARN][91] ([i915#180]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-apl6/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-apl3/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [SKIP][93] ([i915#4525]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-iclb3/igt@gem_exec_balancer@parallel-bb-first.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb4/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][95] ([i915#2842]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][97] ([i915#4281]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-iclb: [INCOMPLETE][99] -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-iclb7/igt@i915_pm_rpm@system-suspend-modeset.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb7/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@i915_selftest@live@evict:
- shard-skl: [INCOMPLETE][101] -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-skl1/igt@i915_selftest@live@evict.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl9/igt@i915_selftest@live@evict.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [DMESG-FAIL][103] ([i915#5334]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-skl1/igt@i915_selftest@live@gt_heartbeat.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl9/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-skl: [FAIL][105] ([i915#2521]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [FAIL][107] ([i915#4767]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-skl1/igt@kms_fbcon_fbt@psr-suspend.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl9/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [FAIL][109] ([i915#79]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode:
- shard-iclb: [SKIP][111] ([i915#6375]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-skl: [INCOMPLETE][113] ([i915#4939]) -> [PASS][114] +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][115] ([fdo#109441]) -> [PASS][116] +2 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf@blocking:
- shard-skl: [FAIL][117] ([i915#1542]) -> [PASS][118] +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-skl6/igt@perf@blocking.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl9/igt@perf@blocking.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][119] ([i915#5639]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-skl7/igt@perf@polling-parameterized.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-skl4/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][121] ([i915#4525]) -> [FAIL][122] ([i915#6117])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][123] ([i915#2920]) -> [SKIP][124] ([i915#658])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb3/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-iclb: [SKIP][125] ([fdo#111068] / [i915#658]) -> [SKIP][126] ([i915#2920])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][127] ([i915#2920]) -> [SKIP][128] ([fdo#111068] / [i915#658])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: [FAIL][129] ([i915#5939]) -> [SKIP][130] ([fdo#109642] / [fdo#111068] / [i915#658])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-iclb4/igt@kms_psr2_su@page_flip-p010.html
* igt@runner@aborted:
- shard-apl: ([FAIL][131], [FAIL][132], [FAIL][133]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][134], [FAIL][135], [FAIL][136]) ([i915#3002] / [i915#4312])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-apl2/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-apl6/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12222/shard-apl8/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-apl8/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-apl1/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/shard-apl1/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6375]: https://gitlab.freedesktop.org/drm/intel/issues/6375
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6458]: https://gitlab.freedesktop.org/drm/intel/issues/6458
[i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6987]: https://gitlab.freedesktop.org/drm/intel/issues/6987
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12222 -> Patchwork_109384v2
CI-20190529: 20190529
CI_DRM_12222: 6278acf81fd635214b7e310bb325c218e72e0349 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7001: d21216f0db39457717274d74b4d2e3db6683aa63 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109384v2: 6278acf81fd635214b7e310bb325c218e72e0349 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109384v2/index.html
[-- Attachment #2: Type: text/html, Size: 32511 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
@ 2022-10-14 7:20 ` Jordan Justen
-1 siblings, 0 replies; 21+ messages in thread
From: Jordan Justen @ 2022-10-14 7:20 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
Cc: Thomas Hellström, Yang A Shi, Lionel Landwerlin,
Stuart Summers, Michal Mrozek, dri-devel,
Niranjana Vishwanathapura, Nirmoy Das
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
On 2022-10-04 04:49:15, Matthew Auld wrote:
> On some platforms we potentially have different alignment restrictions
> depending on the memory type. We also now have different alignment
> restrictions for the same region across different kernel versions.
> Extend the region query to return the minimum required GTT alignment.
>
> Testcase: igt@gem_create@create-ext-placement-alignment
> Testcase: igt@i915_query@query-regions-sanity-check
> Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Michal Mrozek <michal.mrozek@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Yang A Shi <yang.a.shi@intel.com>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> ---
> drivers/gpu/drm/i915/i915_query.c | 1 +
> include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++++++++--
> 2 files changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 6ec9c9fb7b0d..111377f210ed 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -498,6 +498,7 @@ static int query_memregion_info(struct drm_i915_private *i915,
> info.region.memory_class = mr->type;
> info.region.memory_instance = mr->instance;
> info.probed_size = mr->total;
> + info.gtt_alignment = mr->min_page_size;
>
> if (mr->type == INTEL_MEMORY_LOCAL)
> info.probed_cpu_visible_size = mr->io_size;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 08d69e36fb66..2e613109356b 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -3346,8 +3346,33 @@ struct drm_i915_memory_region_info {
> /** @region: The class:instance pair encoding */
> struct drm_i915_gem_memory_class_instance region;
>
> - /** @rsvd0: MBZ */
> - __u32 rsvd0;
> + union {
> + /** @rsvd0: MBZ */
> + __u32 rsvd0;
> + /**
> + * @gtt_alignment:
> + *
> + * The minimum required GTT alignment for this type of memory.
> + * When allocating a GTT address it must be aligned to this
> + * value or larger. On some platforms the kernel might opt to
> + * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
> + * pages can then be used if we also use 64K GTT alignment.
> + *
> + * NOTE: If this is zero then this must be an older
> + * kernel which lacks support for this field.
> + *
> + * Side note: For larger objects (especially for
> + * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
> + * consider potentially bumping the GTT alignment to say 2M,
> + * which could potentially increase the likelihood of the kernel
> + * being able to utilise 2M GTT pages underneath, if the layout
> + * of the physical pages allows it. On some configurations we
> + * can then also use a more efficient page-table layout, if we
> + * can't use the more desirable 2M GTT page, so long as we know
> + * that the entire page-table will be used by this object.
> + */
> + __u32 gtt_alignment;
> + };
>
> /**
> * @probed_size: Memory probed by the driver
> --
> 2.37.3
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
@ 2022-10-14 7:20 ` Jordan Justen
0 siblings, 0 replies; 21+ messages in thread
From: Jordan Justen @ 2022-10-14 7:20 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
Cc: Thomas Hellström, Michal Mrozek, dri-devel, Nirmoy Das
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
On 2022-10-04 04:49:15, Matthew Auld wrote:
> On some platforms we potentially have different alignment restrictions
> depending on the memory type. We also now have different alignment
> restrictions for the same region across different kernel versions.
> Extend the region query to return the minimum required GTT alignment.
>
> Testcase: igt@gem_create@create-ext-placement-alignment
> Testcase: igt@i915_query@query-regions-sanity-check
> Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Michal Mrozek <michal.mrozek@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Yang A Shi <yang.a.shi@intel.com>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> ---
> drivers/gpu/drm/i915/i915_query.c | 1 +
> include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++++++++--
> 2 files changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 6ec9c9fb7b0d..111377f210ed 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -498,6 +498,7 @@ static int query_memregion_info(struct drm_i915_private *i915,
> info.region.memory_class = mr->type;
> info.region.memory_instance = mr->instance;
> info.probed_size = mr->total;
> + info.gtt_alignment = mr->min_page_size;
>
> if (mr->type == INTEL_MEMORY_LOCAL)
> info.probed_cpu_visible_size = mr->io_size;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 08d69e36fb66..2e613109356b 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -3346,8 +3346,33 @@ struct drm_i915_memory_region_info {
> /** @region: The class:instance pair encoding */
> struct drm_i915_gem_memory_class_instance region;
>
> - /** @rsvd0: MBZ */
> - __u32 rsvd0;
> + union {
> + /** @rsvd0: MBZ */
> + __u32 rsvd0;
> + /**
> + * @gtt_alignment:
> + *
> + * The minimum required GTT alignment for this type of memory.
> + * When allocating a GTT address it must be aligned to this
> + * value or larger. On some platforms the kernel might opt to
> + * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
> + * pages can then be used if we also use 64K GTT alignment.
> + *
> + * NOTE: If this is zero then this must be an older
> + * kernel which lacks support for this field.
> + *
> + * Side note: For larger objects (especially for
> + * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
> + * consider potentially bumping the GTT alignment to say 2M,
> + * which could potentially increase the likelihood of the kernel
> + * being able to utilise 2M GTT pages underneath, if the layout
> + * of the physical pages allows it. On some configurations we
> + * can then also use a more efficient page-table layout, if we
> + * can't use the more desirable 2M GTT page, so long as we know
> + * that the entire page-table will be used by this object.
> + */
> + __u32 gtt_alignment;
> + };
>
> /**
> * @probed_size: Memory probed by the driver
> --
> 2.37.3
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
2022-10-14 7:20 ` [Intel-gfx] " Jordan Justen
@ 2022-10-14 10:58 ` Matthew Auld
-1 siblings, 0 replies; 21+ messages in thread
From: Matthew Auld @ 2022-10-14 10:58 UTC (permalink / raw)
To: Jordan Justen, intel-gfx
Cc: Thomas Hellström, Yang A Shi, Lionel Landwerlin,
Stuart Summers, Michal Mrozek, dri-devel,
Niranjana Vishwanathapura, Nirmoy Das
On 14/10/2022 08:20, Jordan Justen wrote:
> Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Thanks. Can I take that as ack for merging the series from Mesa POV? I
think Lionel was going to test this, but I think keeps getting swamped
with other stuff. We kind of urgently need to land this series.
>
> On 2022-10-04 04:49:15, Matthew Auld wrote:
>> On some platforms we potentially have different alignment restrictions
>> depending on the memory type. We also now have different alignment
>> restrictions for the same region across different kernel versions.
>> Extend the region query to return the minimum required GTT alignment.
>>
>> Testcase: igt@gem_create@create-ext-placement-alignment
>> Testcase: igt@i915_query@query-regions-sanity-check
>> Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Michal Mrozek <michal.mrozek@intel.com>
>> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Cc: Stuart Summers <stuart.summers@intel.com>
>> Cc: Jordan Justen <jordan.l.justen@intel.com>
>> Cc: Yang A Shi <yang.a.shi@intel.com>
>> Cc: Nirmoy Das <nirmoy.das@intel.com>
>> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_query.c | 1 +
>> include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++++++++--
>> 2 files changed, 28 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
>> index 6ec9c9fb7b0d..111377f210ed 100644
>> --- a/drivers/gpu/drm/i915/i915_query.c
>> +++ b/drivers/gpu/drm/i915/i915_query.c
>> @@ -498,6 +498,7 @@ static int query_memregion_info(struct drm_i915_private *i915,
>> info.region.memory_class = mr->type;
>> info.region.memory_instance = mr->instance;
>> info.probed_size = mr->total;
>> + info.gtt_alignment = mr->min_page_size;
>>
>> if (mr->type == INTEL_MEMORY_LOCAL)
>> info.probed_cpu_visible_size = mr->io_size;
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index 08d69e36fb66..2e613109356b 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -3346,8 +3346,33 @@ struct drm_i915_memory_region_info {
>> /** @region: The class:instance pair encoding */
>> struct drm_i915_gem_memory_class_instance region;
>>
>> - /** @rsvd0: MBZ */
>> - __u32 rsvd0;
>> + union {
>> + /** @rsvd0: MBZ */
>> + __u32 rsvd0;
>> + /**
>> + * @gtt_alignment:
>> + *
>> + * The minimum required GTT alignment for this type of memory.
>> + * When allocating a GTT address it must be aligned to this
>> + * value or larger. On some platforms the kernel might opt to
>> + * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
>> + * pages can then be used if we also use 64K GTT alignment.
>> + *
>> + * NOTE: If this is zero then this must be an older
>> + * kernel which lacks support for this field.
>> + *
>> + * Side note: For larger objects (especially for
>> + * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
>> + * consider potentially bumping the GTT alignment to say 2M,
>> + * which could potentially increase the likelihood of the kernel
>> + * being able to utilise 2M GTT pages underneath, if the layout
>> + * of the physical pages allows it. On some configurations we
>> + * can then also use a more efficient page-table layout, if we
>> + * can't use the more desirable 2M GTT page, so long as we know
>> + * that the entire page-table will be used by this object.
>> + */
>> + __u32 gtt_alignment;
>> + };
>>
>> /**
>> * @probed_size: Memory probed by the driver
>> --
>> 2.37.3
>>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
@ 2022-10-14 10:58 ` Matthew Auld
0 siblings, 0 replies; 21+ messages in thread
From: Matthew Auld @ 2022-10-14 10:58 UTC (permalink / raw)
To: Jordan Justen, intel-gfx
Cc: Thomas Hellström, Michal Mrozek, dri-devel, Nirmoy Das
On 14/10/2022 08:20, Jordan Justen wrote:
> Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Thanks. Can I take that as ack for merging the series from Mesa POV? I
think Lionel was going to test this, but I think keeps getting swamped
with other stuff. We kind of urgently need to land this series.
>
> On 2022-10-04 04:49:15, Matthew Auld wrote:
>> On some platforms we potentially have different alignment restrictions
>> depending on the memory type. We also now have different alignment
>> restrictions for the same region across different kernel versions.
>> Extend the region query to return the minimum required GTT alignment.
>>
>> Testcase: igt@gem_create@create-ext-placement-alignment
>> Testcase: igt@i915_query@query-regions-sanity-check
>> Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Michal Mrozek <michal.mrozek@intel.com>
>> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Cc: Stuart Summers <stuart.summers@intel.com>
>> Cc: Jordan Justen <jordan.l.justen@intel.com>
>> Cc: Yang A Shi <yang.a.shi@intel.com>
>> Cc: Nirmoy Das <nirmoy.das@intel.com>
>> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_query.c | 1 +
>> include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++++++++--
>> 2 files changed, 28 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
>> index 6ec9c9fb7b0d..111377f210ed 100644
>> --- a/drivers/gpu/drm/i915/i915_query.c
>> +++ b/drivers/gpu/drm/i915/i915_query.c
>> @@ -498,6 +498,7 @@ static int query_memregion_info(struct drm_i915_private *i915,
>> info.region.memory_class = mr->type;
>> info.region.memory_instance = mr->instance;
>> info.probed_size = mr->total;
>> + info.gtt_alignment = mr->min_page_size;
>>
>> if (mr->type == INTEL_MEMORY_LOCAL)
>> info.probed_cpu_visible_size = mr->io_size;
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index 08d69e36fb66..2e613109356b 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -3346,8 +3346,33 @@ struct drm_i915_memory_region_info {
>> /** @region: The class:instance pair encoding */
>> struct drm_i915_gem_memory_class_instance region;
>>
>> - /** @rsvd0: MBZ */
>> - __u32 rsvd0;
>> + union {
>> + /** @rsvd0: MBZ */
>> + __u32 rsvd0;
>> + /**
>> + * @gtt_alignment:
>> + *
>> + * The minimum required GTT alignment for this type of memory.
>> + * When allocating a GTT address it must be aligned to this
>> + * value or larger. On some platforms the kernel might opt to
>> + * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
>> + * pages can then be used if we also use 64K GTT alignment.
>> + *
>> + * NOTE: If this is zero then this must be an older
>> + * kernel which lacks support for this field.
>> + *
>> + * Side note: For larger objects (especially for
>> + * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
>> + * consider potentially bumping the GTT alignment to say 2M,
>> + * which could potentially increase the likelihood of the kernel
>> + * being able to utilise 2M GTT pages underneath, if the layout
>> + * of the physical pages allows it. On some configurations we
>> + * can then also use a more efficient page-table layout, if we
>> + * can't use the more desirable 2M GTT page, so long as we know
>> + * that the entire page-table will be used by this object.
>> + */
>> + __u32 gtt_alignment;
>> + };
>>
>> /**
>> * @probed_size: Memory probed by the driver
>> --
>> 2.37.3
>>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
2022-10-14 10:58 ` [Intel-gfx] " Matthew Auld
@ 2022-10-14 16:51 ` Jordan Justen
-1 siblings, 0 replies; 21+ messages in thread
From: Jordan Justen @ 2022-10-14 16:51 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
Cc: Thomas Hellström, Yang A Shi, Lionel Landwerlin,
Stuart Summers, Michal Mrozek, dri-devel,
Niranjana Vishwanathapura, Nirmoy Das
On 2022-10-14 03:58:12, Matthew Auld wrote:
> On 14/10/2022 08:20, Jordan Justen wrote:
> > Acked-by: Jordan Justen <jordan.l.justen@intel.com>
>
> Thanks. Can I take that as ack for merging the series from Mesa POV? I
> think Lionel was going to test this, but I think keeps getting swamped
> with other stuff. We kind of urgently need to land this series.
Speaking from the uapi perspective, I would would say, yes, it looks
seems good to merge. I looked over your igt patches, and they seem to
test the uapi well. The uapi change is pretty simple, and the related
documentation changes look good.
No, we haven't gotten the chance to test the uapi implementation with
Mesa, but I expect we will soon, once it's in drm-tip.
-Jordan
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
@ 2022-10-14 16:51 ` Jordan Justen
0 siblings, 0 replies; 21+ messages in thread
From: Jordan Justen @ 2022-10-14 16:51 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
Cc: Thomas Hellström, Michal Mrozek, dri-devel, Nirmoy Das
On 2022-10-14 03:58:12, Matthew Auld wrote:
> On 14/10/2022 08:20, Jordan Justen wrote:
> > Acked-by: Jordan Justen <jordan.l.justen@intel.com>
>
> Thanks. Can I take that as ack for merging the series from Mesa POV? I
> think Lionel was going to test this, but I think keeps getting swamped
> with other stuff. We kind of urgently need to land this series.
Speaking from the uapi perspective, I would would say, yes, it looks
seems good to merge. I looked over your igt patches, and they seem to
test the uapi well. The uapi change is pretty simple, and the related
documentation changes look good.
No, we haven't gotten the chance to test the uapi implementation with
Mesa, but I expect we will soon, once it's in drm-tip.
-Jordan
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
2022-10-14 16:51 ` [Intel-gfx] " Jordan Justen
@ 2022-10-14 17:26 ` Matthew Auld
-1 siblings, 0 replies; 21+ messages in thread
From: Matthew Auld @ 2022-10-14 17:26 UTC (permalink / raw)
To: Jordan Justen, intel-gfx
Cc: Thomas Hellström, Yang A Shi, Lionel Landwerlin,
Stuart Summers, Michal Mrozek, dri-devel,
Niranjana Vishwanathapura, Nirmoy Das
On 14/10/2022 17:51, Jordan Justen wrote:
> On 2022-10-14 03:58:12, Matthew Auld wrote:
>> On 14/10/2022 08:20, Jordan Justen wrote:
>>> Acked-by: Jordan Justen <jordan.l.justen@intel.com>
>>
>> Thanks. Can I take that as ack for merging the series from Mesa POV? I
>> think Lionel was going to test this, but I think keeps getting swamped
>> with other stuff. We kind of urgently need to land this series.
>
> Speaking from the uapi perspective, I would would say, yes, it looks
> seems good to merge. I looked over your igt patches, and they seem to
> test the uapi well. The uapi change is pretty simple, and the related
> documentation changes look good.
>
> No, we haven't gotten the chance to test the uapi implementation with
> Mesa, but I expect we will soon, once it's in drm-tip.
Pushed to drm-tip. Thanks.
>
> -Jordan
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment
@ 2022-10-14 17:26 ` Matthew Auld
0 siblings, 0 replies; 21+ messages in thread
From: Matthew Auld @ 2022-10-14 17:26 UTC (permalink / raw)
To: Jordan Justen, intel-gfx
Cc: Thomas Hellström, Michal Mrozek, dri-devel, Nirmoy Das
On 14/10/2022 17:51, Jordan Justen wrote:
> On 2022-10-14 03:58:12, Matthew Auld wrote:
>> On 14/10/2022 08:20, Jordan Justen wrote:
>>> Acked-by: Jordan Justen <jordan.l.justen@intel.com>
>>
>> Thanks. Can I take that as ack for merging the series from Mesa POV? I
>> think Lionel was going to test this, but I think keeps getting swamped
>> with other stuff. We kind of urgently need to land this series.
>
> Speaking from the uapi perspective, I would would say, yes, it looks
> seems good to merge. I looked over your igt patches, and they seem to
> test the uapi well. The uapi change is pretty simple, and the related
> documentation changes look good.
>
> No, we haven't gotten the chance to test the uapi implementation with
> Mesa, but I expect we will soon, once it's in drm-tip.
Pushed to drm-tip. Thanks.
>
> -Jordan
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2022-10-14 17:26 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-04 11:49 [PATCH v3 1/2] drm/i915: enable PS64 support for DG2 Matthew Auld
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
2022-10-04 11:49 ` [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment Matthew Auld
2022-10-04 11:49 ` [Intel-gfx] " Matthew Auld
2022-10-04 14:08 ` Das, Nirmoy
2022-10-04 14:08 ` [Intel-gfx] " Das, Nirmoy
2022-10-14 7:20 ` Jordan Justen
2022-10-14 7:20 ` [Intel-gfx] " Jordan Justen
2022-10-14 10:58 ` Matthew Auld
2022-10-14 10:58 ` [Intel-gfx] " Matthew Auld
2022-10-14 16:51 ` Jordan Justen
2022-10-14 16:51 ` [Intel-gfx] " Jordan Justen
2022-10-14 17:26 ` Matthew Auld
2022-10-14 17:26 ` [Intel-gfx] " Matthew Auld
2022-10-04 12:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 Patchwork
2022-10-04 12:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-04 17:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-06 10:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 (rev2) Patchwork
2022-10-06 10:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-06 10:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-07 1:59 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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