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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v2 02/36] tcg: Tidy tcg_reg_alloc_op
Date: Fri, 21 Oct 2022 17:15:15 +1000	[thread overview]
Message-ID: <20221021071549.2398137-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221021071549.2398137-1-richard.henderson@linaro.org>

Replace goto allocate_in_reg with a boolean.
Remove o_preferred_regs which isn't used, except to copy.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg.c | 45 +++++++++++++++++++++------------------------
 1 file changed, 21 insertions(+), 24 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index c9e664ee31..660d5eb098 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3606,7 +3606,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
 
     /* satisfy input constraints */ 
     for (k = 0; k < nb_iargs; k++) {
-        TCGRegSet i_preferred_regs, o_preferred_regs;
+        TCGRegSet i_preferred_regs;
+        bool allocate_new_reg;
 
         i = def->args_ct[nb_oargs + k].sort_index;
         arg = op->args[i];
@@ -3621,9 +3622,12 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
             continue;
         }
 
-        i_preferred_regs = o_preferred_regs = 0;
+        reg = ts->reg;
+        i_preferred_regs = 0;
+        allocate_new_reg = false;
+
         if (arg_ct->ialias) {
-            o_preferred_regs = op->output_pref[arg_ct->alias_index];
+            i_preferred_regs = op->output_pref[arg_ct->alias_index];
 
             /*
              * If the input is readonly, then it cannot also be an
@@ -3632,30 +3636,23 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
              * register and move it.
              */
             if (temp_readonly(ts) || !IS_DEAD_ARG(i)) {
-                goto allocate_in_reg;
+                allocate_new_reg = true;
+            } else if (ts->val_type == TEMP_VAL_REG) {
+                /*
+                 * Check if the current register has already been
+                 * allocated for another input.
+                 */
+                allocate_new_reg = tcg_regset_test_reg(i_allocated_regs, reg);
             }
-
-            /*
-             * Check if the current register has already been allocated
-             * for another input aliased to an output.
-             */
-            if (ts->val_type == TEMP_VAL_REG) {
-                reg = ts->reg;
-                for (int k2 = 0; k2 < k; k2++) {
-                    int i2 = def->args_ct[nb_oargs + k2].sort_index;
-                    if (def->args_ct[i2].ialias && reg == new_args[i2]) {
-                        goto allocate_in_reg;
-                    }
-                }
-            }
-            i_preferred_regs = o_preferred_regs;
         }
 
-        temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
-        reg = ts->reg;
+        if (!allocate_new_reg) {
+            temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
+            reg = ts->reg;
+            allocate_new_reg = !tcg_regset_test_reg(arg_ct->regs, reg);
+        }
 
-        if (!tcg_regset_test_reg(arg_ct->regs, reg)) {
- allocate_in_reg:
+        if (allocate_new_reg) {
             /*
              * Allocate a new register matching the constraint
              * and move the temporary register into it.
@@ -3663,7 +3660,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
             temp_load(s, ts, tcg_target_available_regs[ts->type],
                       i_allocated_regs, 0);
             reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,
-                                o_preferred_regs, ts->indirect_base);
+                                i_preferred_regs, ts->indirect_base);
             if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
                 /*
                  * Cross register class move not supported.  Sync the
-- 
2.34.1



  parent reply	other threads:[~2022-10-21  7:35 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-21  7:15 [PATCH v2 00/36] tcg: Support for Int128 with helpers Richard Henderson
2022-10-21  7:15 ` [PATCH v2 01/36] include/qemu/atomic128: Support 16-byte atomic read/write for Intel AVX Richard Henderson
2022-10-21  7:15 ` Richard Henderson [this message]
2022-10-25 15:26   ` [PATCH v2 02/36] tcg: Tidy tcg_reg_alloc_op Philippe Mathieu-Daudé
2022-10-21  7:15 ` [PATCH v2 03/36] tcg: Introduce paired register allocation Richard Henderson
2022-10-21  7:15 ` [PATCH v2 04/36] tcg/s390x: Use register pair allocation for div and mulu2 Richard Henderson
2022-10-21  7:15 ` [PATCH v2 05/36] tcg/arm: Use register pair allocation for qemu_{ld, st}_i64 Richard Henderson
2022-10-21  7:15 ` [PATCH v2 06/36] meson: Move CONFIG_TCG_INTERPRETER to config_host Richard Henderson
2022-10-21  7:15 ` [PATCH v2 07/36] tcg: Remove TCG_TARGET_STACK_GROWSUP Richard Henderson
2022-10-21  7:15 ` [PATCH v2 08/36] accel/tcg: Set cflags_next_tb in cpu_common_initfn Richard Henderson
2022-10-21  7:15 ` [PATCH v2 09/36] target/sparc: Avoid TCGV_{LOW,HIGH} Richard Henderson
2022-10-21  7:15 ` [PATCH v2 10/36] tcg: Move TCG_{LOW,HIGH} to tcg-internal.h Richard Henderson
2022-10-21  7:15 ` [PATCH v2 11/36] tcg: Add temp_subindex to TCGTemp Richard Henderson
2022-10-21  7:15 ` [PATCH v2 12/36] tcg: Simplify calls to temp_sync vs mem_coherent Richard Henderson
2022-10-21  7:15 ` [PATCH v2 13/36] tcg: Allocate TCGTemp pairs in host memory order Richard Henderson
2022-10-21  7:15 ` [PATCH v2 14/36] tcg: Move TCG_TYPE_COUNT outside enum Richard Henderson
2022-10-21  7:15 ` [PATCH v2 15/36] tcg: Introduce tcg_type_size Richard Henderson
2022-10-21  7:15 ` [PATCH v2 16/36] tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind Richard Henderson
2022-10-21  7:15 ` [PATCH v2 17/36] tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64 Richard Henderson
2022-10-21 10:28   ` Philippe Mathieu-Daudé
2022-10-21  7:15 ` [PATCH v2 18/36] tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32 Richard Henderson
2022-10-21 10:33   ` Philippe Mathieu-Daudé
2022-10-21  7:15 ` [PATCH v2 19/36] tcg: Use TCG_CALL_ARG_EVEN for TCI special case Richard Henderson
2022-10-25 20:14   ` Ilya Leoshkevich
2022-10-21  7:15 ` [PATCH v2 20/36] tcg: Reorg function calls Richard Henderson
2022-10-21  7:15 ` [PATCH v2 21/36] tcg: Move ffi_cif pointer into TCGHelperInfo Richard Henderson
2022-10-21  7:15 ` [PATCH v2 22/36] tcg: Add TCGHelperInfo argument to tcg_out_call Richard Henderson
2022-10-21  7:15 ` [PATCH v2 23/36] tcg: Define TCG_TYPE_I128 and related helper macros Richard Henderson
2022-10-21  7:15 ` [PATCH v2 24/36] tcg: Add TCG_CALL_{RET,ARG}_NORMAL_4 Richard Henderson
2022-10-21  7:15 ` [PATCH v2 25/36] tcg: Allocate objects contiguously in temp_allocate_frame Richard Henderson
2022-10-21  7:15 ` [PATCH v2 26/36] tcg: Introduce tcg_out_addi_ptr Richard Henderson
2022-10-21  7:15 ` [PATCH v2 27/36] tcg: Add TCG_CALL_{RET,ARG}_BY_REF Richard Henderson
2022-10-21  7:15 ` [PATCH v2 28/36] tcg: Introduce tcg_target_call_oarg_reg Richard Henderson
2022-10-21  7:15 ` [PATCH v2 29/36] tcg: Add TCG_CALL_RET_BY_VEC Richard Henderson
2022-10-21  7:15 ` [PATCH v2 30/36] include/qemu/int128: Use Int128 structure for TCI Richard Henderson
2022-10-21  7:15 ` [PATCH v2 31/36] tcg/i386: Add TCG_TARGET_CALL_{RET,ARG}_I128 Richard Henderson
2022-10-21  7:15 ` [PATCH v2 32/36] tcg/tci: Fix big-endian return register ordering Richard Henderson
2022-10-21  7:15 ` [PATCH v2 33/36] tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128 Richard Henderson
2022-10-21 10:47   ` Philippe Mathieu-Daudé
2022-10-22  3:48     ` Richard Henderson
2022-10-21  7:15 ` [PATCH v2 34/36] tcg: " Richard Henderson
2022-10-21  7:15 ` [PATCH v2 35/36] tcg: Add temp allocation for TCGv_i128 Richard Henderson
2022-10-21  7:15 ` [PATCH v2 36/36] tcg: Add tcg_gen_extr_i128_i64, tcg_gen_concat_i64_i128 Richard Henderson

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