* [Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions
2022-10-21 21:39 [Intel-gfx] [PATCH 0/4] Prep series - CDCLK code churn Anusha Srivatsa
@ 2022-10-21 21:39 ` Anusha Srivatsa
2022-10-25 17:41 ` Balasubramani Vivekanandan
2022-10-21 21:39 ` [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro Anusha Srivatsa
` (4 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Anusha Srivatsa @ 2022-10-21 21:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Balasubramani Vivekanandan
No functional changes. Changing terminolgy in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad401357ab66..0f5add2fc51b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1220,7 +1220,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
-static bool has_cdclk_squasher(struct drm_i915_private *i915)
+static bool has_cdclk_squash(struct drm_i915_private *i915)
{
return IS_DG2(i915);
}
@@ -1520,7 +1520,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (has_cdclk_squasher(dev_priv))
+ if (has_cdclk_squash(dev_priv))
squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1747,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
else
clock = cdclk;
- if (has_cdclk_squasher(dev_priv)) {
+ if (has_cdclk_squash(dev_priv)) {
u32 squash_ctl = 0;
if (waveform)
@@ -1845,7 +1845,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
expected = skl_cdclk_decimal(cdclk);
/* Figure out what CD2X divider we should be using for this cdclk */
- if (has_cdclk_squasher(dev_priv))
+ if (has_cdclk_squash(dev_priv))
clock = dev_priv->display.cdclk.hw.vco / 2;
else
clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1976,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
* the moment all platforms with squasher use a fixed cd2x
* divider.
*/
- if (!has_cdclk_squasher(dev_priv))
+ if (!has_cdclk_squash(dev_priv))
return false;
return a->cdclk != b->cdclk &&
@@ -2028,7 +2028,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
* the moment all platforms with squasher use a fixed cd2x
* divider.
*/
- if (has_cdclk_squasher(dev_priv))
+ if (has_cdclk_squash(dev_priv))
return false;
return a->cdclk != b->cdclk &&
@@ -2754,12 +2754,12 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
drm_dbg_kms(&dev_priv->drm,
- "Can change cdclk via squasher\n");
+ "Can change cdclk via squashing\n");
} else if (intel_cdclk_can_crawl(dev_priv,
&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
drm_dbg_kms(&dev_priv->drm,
- "Can change cdclk via crawl\n");
+ "Can change cdclk via crawling\n");
} else if (pipe != INVALID_PIPE) {
new_cdclk_state->pipe = pipe;
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions
2022-10-21 21:39 ` [Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions Anusha Srivatsa
@ 2022-10-25 17:41 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 15+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-25 17:41 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
On 21.10.2022 14:39, Anusha Srivatsa wrote:
> No functional changes. Changing terminolgy in some
> print statements. s/has_cdclk_squasher/has_cdclk_squash,
> s/crawler/crawl and s/squasher/squash.
>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ad401357ab66..0f5add2fc51b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1220,7 +1220,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
> skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
>
> -static bool has_cdclk_squasher(struct drm_i915_private *i915)
> +static bool has_cdclk_squash(struct drm_i915_private *i915)
> {
> return IS_DG2(i915);
> }
> @@ -1520,7 +1520,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> return;
> }
>
> - if (has_cdclk_squasher(dev_priv))
> + if (has_cdclk_squash(dev_priv))
> squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
>
> if (squash_ctl & CDCLK_SQUASH_ENABLE) {
> @@ -1747,7 +1747,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> else
> clock = cdclk;
>
> - if (has_cdclk_squasher(dev_priv)) {
> + if (has_cdclk_squash(dev_priv)) {
> u32 squash_ctl = 0;
>
> if (waveform)
> @@ -1845,7 +1845,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
> expected = skl_cdclk_decimal(cdclk);
>
> /* Figure out what CD2X divider we should be using for this cdclk */
> - if (has_cdclk_squasher(dev_priv))
> + if (has_cdclk_squash(dev_priv))
> clock = dev_priv->display.cdclk.hw.vco / 2;
> else
> clock = dev_priv->display.cdclk.hw.cdclk;
> @@ -1976,7 +1976,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
> * the moment all platforms with squasher use a fixed cd2x
> * divider.
> */
> - if (!has_cdclk_squasher(dev_priv))
> + if (!has_cdclk_squash(dev_priv))
> return false;
>
> return a->cdclk != b->cdclk &&
> @@ -2028,7 +2028,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
> * the moment all platforms with squasher use a fixed cd2x
> * divider.
> */
> - if (has_cdclk_squasher(dev_priv))
> + if (has_cdclk_squash(dev_priv))
> return false;
>
> return a->cdclk != b->cdclk &&
> @@ -2754,12 +2754,12 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> &old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> drm_dbg_kms(&dev_priv->drm,
> - "Can change cdclk via squasher\n");
> + "Can change cdclk via squashing\n");
> } else if (intel_cdclk_can_crawl(dev_priv,
> &old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> drm_dbg_kms(&dev_priv->drm,
> - "Can change cdclk via crawl\n");
> + "Can change cdclk via crawling\n");
> } else if (pipe != INVALID_PIPE) {
> new_cdclk_state->pipe = pipe;
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
2022-10-21 21:39 [Intel-gfx] [PATCH 0/4] Prep series - CDCLK code churn Anusha Srivatsa
2022-10-21 21:39 ` [Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions Anusha Srivatsa
@ 2022-10-21 21:39 ` Anusha Srivatsa
2022-10-25 17:42 ` Balasubramani Vivekanandan
2022-10-21 21:39 ` [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk() Anusha Srivatsa
` (3 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Anusha Srivatsa @ 2022-10-21 21:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Balasubramani Vivekanandan
Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++----------
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0f5add2fc51b..45babbc6290f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
-static bool has_cdclk_squash(struct drm_i915_private *i915)
-{
- return IS_DG2(i915);
-}
-
struct intel_cdclk_vals {
u32 cdclk;
u16 refclk;
@@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (has_cdclk_squash(dev_priv))
+ if (HAS_CDCLK_SQUASH(dev_priv))
squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
else
clock = cdclk;
- if (has_cdclk_squash(dev_priv)) {
+ if (HAS_CDCLK_SQUASH(dev_priv)) {
u32 squash_ctl = 0;
if (waveform)
@@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
expected = skl_cdclk_decimal(cdclk);
/* Figure out what CD2X divider we should be using for this cdclk */
- if (has_cdclk_squash(dev_priv))
+ if (HAS_CDCLK_SQUASH(dev_priv))
clock = dev_priv->display.cdclk.hw.vco / 2;
else
clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
* the moment all platforms with squasher use a fixed cd2x
* divider.
*/
- if (!has_cdclk_squash(dev_priv))
+ if (!HAS_CDCLK_SQUASH(dev_priv))
return false;
return a->cdclk != b->cdclk &&
@@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
* the moment all platforms with squasher use a fixed cd2x
* divider.
*/
- if (has_cdclk_squash(dev_priv))
+ if (HAS_CDCLK_SQUASH(dev_priv))
return false;
return a->cdclk != b->cdclk &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7b8eb9d4117..db51050e3ba2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
#define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
+#define HAS_CDCLK_SQUASH(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 19bf5ef6a20d..a88e1439a426 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1064,6 +1064,7 @@ static const struct intel_device_info xehpsdv_info = {
.has_guc_deprivilege = 1, \
.has_heci_pxp = 1, \
.has_media_ratio_mode = 1, \
+ .display.has_cdclk_squash = 1, \
.__runtime.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
BIT(VECS0) | BIT(VECS1) | \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index cdf78728dcad..67d8759c802c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,6 +180,7 @@ enum intel_ppgtt_type {
/* Keep in alphabetical order */ \
func(cursor_needs_physical); \
func(has_cdclk_crawl); \
+ func(has_cdclk_squash); \
func(has_ddi); \
func(has_dp_mst); \
func(has_dsb); \
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
2022-10-21 21:39 ` [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro Anusha Srivatsa
@ 2022-10-25 17:42 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 15+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-25 17:42 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
On 21.10.2022 14:39, Anusha Srivatsa wrote:
> Driver had discrepancy in how cdclk squash and crawl support
> were checked. Like crawl, add squash as a 1 bit feature flag
> to the display section of DG2.
>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++----------
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 4 files changed, 8 insertions(+), 10 deletions(-)
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0f5add2fc51b..45babbc6290f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
> skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
>
> -static bool has_cdclk_squash(struct drm_i915_private *i915)
> -{
> - return IS_DG2(i915);
> -}
> -
> struct intel_cdclk_vals {
> u32 cdclk;
> u16 refclk;
> @@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> return;
> }
>
> - if (has_cdclk_squash(dev_priv))
> + if (HAS_CDCLK_SQUASH(dev_priv))
> squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
>
> if (squash_ctl & CDCLK_SQUASH_ENABLE) {
> @@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> else
> clock = cdclk;
>
> - if (has_cdclk_squash(dev_priv)) {
> + if (HAS_CDCLK_SQUASH(dev_priv)) {
> u32 squash_ctl = 0;
>
> if (waveform)
> @@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
> expected = skl_cdclk_decimal(cdclk);
>
> /* Figure out what CD2X divider we should be using for this cdclk */
> - if (has_cdclk_squash(dev_priv))
> + if (HAS_CDCLK_SQUASH(dev_priv))
> clock = dev_priv->display.cdclk.hw.vco / 2;
> else
> clock = dev_priv->display.cdclk.hw.cdclk;
> @@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
> * the moment all platforms with squasher use a fixed cd2x
> * divider.
> */
> - if (!has_cdclk_squash(dev_priv))
> + if (!HAS_CDCLK_SQUASH(dev_priv))
> return false;
>
> return a->cdclk != b->cdclk &&
> @@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
> * the moment all platforms with squasher use a fixed cd2x
> * divider.
> */
> - if (has_cdclk_squash(dev_priv))
> + if (HAS_CDCLK_SQUASH(dev_priv))
> return false;
>
> return a->cdclk != b->cdclk &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d7b8eb9d4117..db51050e3ba2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>
> #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
> +#define HAS_CDCLK_SQUASH(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
> #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
> #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
> #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 19bf5ef6a20d..a88e1439a426 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1064,6 +1064,7 @@ static const struct intel_device_info xehpsdv_info = {
> .has_guc_deprivilege = 1, \
> .has_heci_pxp = 1, \
> .has_media_ratio_mode = 1, \
> + .display.has_cdclk_squash = 1, \
> .__runtime.platform_engine_mask = \
> BIT(RCS0) | BIT(BCS0) | \
> BIT(VECS0) | BIT(VECS1) | \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index cdf78728dcad..67d8759c802c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -180,6 +180,7 @@ enum intel_ppgtt_type {
> /* Keep in alphabetical order */ \
> func(cursor_needs_physical); \
> func(has_cdclk_crawl); \
> + func(has_cdclk_squash); \
> func(has_ddi); \
> func(has_dp_mst); \
> func(has_dsb); \
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()
2022-10-21 21:39 [Intel-gfx] [PATCH 0/4] Prep series - CDCLK code churn Anusha Srivatsa
2022-10-21 21:39 ` [Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions Anusha Srivatsa
2022-10-21 21:39 ` [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro Anusha Srivatsa
@ 2022-10-21 21:39 ` Anusha Srivatsa
2022-10-25 17:43 ` Balasubramani Vivekanandan
2022-10-21 21:39 ` [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function Anusha Srivatsa
` (2 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Anusha Srivatsa @ 2022-10-21 21:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Balasubramani Vivekanandan
No functional change. Moving segments out to simplify
bxt_set_cdlck()
v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++++++++++++++--------
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 45babbc6290f..3893779e0c23 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1684,6 +1684,27 @@ static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
return 0xffff;
}
+static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+{
+ if (i915->display.cdclk.hw.vco != 0 &&
+ i915->display.cdclk.hw.vco != vco)
+ icl_cdclk_pll_disable(i915);
+
+ if (i915->display.cdclk.hw.vco != vco)
+ icl_cdclk_pll_enable(i915, vco);
+}
+
+static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+{
+ if (i915->display.cdclk.hw.vco != 0 &&
+ i915->display.cdclk.hw.vco != vco)
+ bxt_de_pll_disable(i915);
+
+ if (i915->display.cdclk.hw.vco != vco)
+ bxt_de_pll_enable(i915, vco);
+
+}
+
static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
@@ -1719,21 +1740,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
if (dev_priv->display.cdclk.hw.vco != vco)
adlp_cdclk_pll_crawl(dev_priv, vco);
- } else if (DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->display.cdclk.hw.vco != 0 &&
- dev_priv->display.cdclk.hw.vco != vco)
- icl_cdclk_pll_disable(dev_priv);
-
- if (dev_priv->display.cdclk.hw.vco != vco)
- icl_cdclk_pll_enable(dev_priv, vco);
- } else {
- if (dev_priv->display.cdclk.hw.vco != 0 &&
- dev_priv->display.cdclk.hw.vco != vco)
- bxt_de_pll_disable(dev_priv);
-
- if (dev_priv->display.cdclk.hw.vco != vco)
- bxt_de_pll_enable(dev_priv, vco);
- }
+ } else if (DISPLAY_VER(dev_priv) >= 11)
+ icl_cdclk_pll_update(dev_priv, vco);
+ else
+ bxt_cdclk_pll_update(dev_priv, vco);
waveform = cdclk_squash_waveform(dev_priv, cdclk);
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()
2022-10-21 21:39 ` [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk() Anusha Srivatsa
@ 2022-10-25 17:43 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 15+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-25 17:43 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
On 21.10.2022 14:39, Anusha Srivatsa wrote:
> No functional change. Moving segments out to simplify
> bxt_set_cdlck()
>
> v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++++++++++++++--------
> 1 file changed, 25 insertions(+), 15 deletions(-)
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 45babbc6290f..3893779e0c23 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1684,6 +1684,27 @@ static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
> return 0xffff;
> }
>
> +static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
> +{
> + if (i915->display.cdclk.hw.vco != 0 &&
> + i915->display.cdclk.hw.vco != vco)
> + icl_cdclk_pll_disable(i915);
> +
> + if (i915->display.cdclk.hw.vco != vco)
> + icl_cdclk_pll_enable(i915, vco);
> +}
> +
> +static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
> +{
> + if (i915->display.cdclk.hw.vco != 0 &&
> + i915->display.cdclk.hw.vco != vco)
> + bxt_de_pll_disable(i915);
> +
> + if (i915->display.cdclk.hw.vco != vco)
> + bxt_de_pll_enable(i915, vco);
> +
> +}
> +
> static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> @@ -1719,21 +1740,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
> if (dev_priv->display.cdclk.hw.vco != vco)
> adlp_cdclk_pll_crawl(dev_priv, vco);
> - } else if (DISPLAY_VER(dev_priv) >= 11) {
> - if (dev_priv->display.cdclk.hw.vco != 0 &&
> - dev_priv->display.cdclk.hw.vco != vco)
> - icl_cdclk_pll_disable(dev_priv);
> -
> - if (dev_priv->display.cdclk.hw.vco != vco)
> - icl_cdclk_pll_enable(dev_priv, vco);
> - } else {
> - if (dev_priv->display.cdclk.hw.vco != 0 &&
> - dev_priv->display.cdclk.hw.vco != vco)
> - bxt_de_pll_disable(dev_priv);
> -
> - if (dev_priv->display.cdclk.hw.vco != vco)
> - bxt_de_pll_enable(dev_priv, vco);
> - }
> + } else if (DISPLAY_VER(dev_priv) >= 11)
> + icl_cdclk_pll_update(dev_priv, vco);
> + else
> + bxt_cdclk_pll_update(dev_priv, vco);
>
> waveform = cdclk_squash_waveform(dev_priv, cdclk);
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function
2022-10-21 21:39 [Intel-gfx] [PATCH 0/4] Prep series - CDCLK code churn Anusha Srivatsa
` (2 preceding siblings ...)
2022-10-21 21:39 ` [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk() Anusha Srivatsa
@ 2022-10-21 21:39 ` Anusha Srivatsa
2022-10-25 17:44 ` Balasubramani Vivekanandan
2022-10-21 22:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Prep series - CDCLK code churn (rev2) Patchwork
2022-10-21 22:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
5 siblings, 1 reply; 15+ messages in thread
From: Anusha Srivatsa @ 2022-10-21 21:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Balasubramani Vivekanandan
No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.
v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3893779e0c23..e21cd0fbe29a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
}
+static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
+ u16 waveform)
+{
+ u32 squash_ctl = 0;
+
+ if (waveform)
+ squash_ctl = CDCLK_SQUASH_ENABLE |
+ CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
+
+ intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
+}
+
static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
@@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
else
clock = cdclk;
- if (HAS_CDCLK_SQUASH(dev_priv)) {
- u32 squash_ctl = 0;
-
- if (waveform)
- squash_ctl = CDCLK_SQUASH_ENABLE |
- CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
-
- intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
- }
+ if (HAS_CDCLK_SQUASH(dev_priv))
+ dg2_cdclk_squash_program(dev_priv, waveform);
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function
2022-10-21 21:39 ` [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function Anusha Srivatsa
@ 2022-10-25 17:44 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 15+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-25 17:44 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
On 21.10.2022 14:39, Anusha Srivatsa wrote:
> No functional change. Introduce dg2_cdclk_squash_program and
> move squash_ctl register programming bits to this.
>
> v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++++---------
> 1 file changed, 14 insertions(+), 9 deletions(-)
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 3893779e0c23..e21cd0fbe29a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
>
> }
>
> +static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
> + u16 waveform)
> +{
> + u32 squash_ctl = 0;
> +
> + if (waveform)
> + squash_ctl = CDCLK_SQUASH_ENABLE |
> + CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> +
> + intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
> +}
> +
> static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> @@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> else
> clock = cdclk;
>
> - if (HAS_CDCLK_SQUASH(dev_priv)) {
> - u32 squash_ctl = 0;
> -
> - if (waveform)
> - squash_ctl = CDCLK_SQUASH_ENABLE |
> - CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> -
> - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> - }
> + if (HAS_CDCLK_SQUASH(dev_priv))
> + dg2_cdclk_squash_program(dev_priv, waveform);
>
> val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
> bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Prep series - CDCLK code churn (rev2)
2022-10-21 21:39 [Intel-gfx] [PATCH 0/4] Prep series - CDCLK code churn Anusha Srivatsa
` (3 preceding siblings ...)
2022-10-21 21:39 ` [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function Anusha Srivatsa
@ 2022-10-21 22:37 ` Patchwork
2022-10-21 22:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
5 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2022-10-21 22:37 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: Prep series - CDCLK code churn (rev2)
URL : https://patchwork.freedesktop.org/series/109974/
State : warning
== Summary ==
Error: dim checkpatch failed
750f09e493d8 drm/i915/display: Change terminology for cdclk actions
7e35fba6b197 drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
e7d2804a8d53 drm/i915/display: Move chunks of code out of bxt_set_cdclk()
-:46: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#46: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1706:
+
+}
total: 0 errors, 0 warnings, 1 checks, 52 lines checked
b54115c43c27 drm/i915/display: Move squash_ctl register programming to its own function
-:29: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#29: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1709:
+static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
+ u16 waveform)
total: 0 errors, 0 warnings, 1 checks, 35 lines checked
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Prep series - CDCLK code churn (rev2)
2022-10-21 21:39 [Intel-gfx] [PATCH 0/4] Prep series - CDCLK code churn Anusha Srivatsa
` (4 preceding siblings ...)
2022-10-21 22:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Prep series - CDCLK code churn (rev2) Patchwork
@ 2022-10-21 22:59 ` Patchwork
5 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2022-10-21 22:59 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8983 bytes --]
== Series Details ==
Series: Prep series - CDCLK code churn (rev2)
URL : https://patchwork.freedesktop.org/series/109974/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12277 -> Patchwork_109974v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_109974v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109974v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/index.html
Participating hosts (43 -> 40)
------------------------------
Missing (3): fi-ctg-p8600 fi-bdw-samus bat-jsl-1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109974v2:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@basic-flip-before-cursor@atomic-transitions:
- fi-elk-e7500: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12277/fi-elk-e7500/igt@kms_cursor_legacy@basic-flip-before-cursor@atomic-transitions.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/fi-elk-e7500/igt@kms_cursor_legacy@basic-flip-before-cursor@atomic-transitions.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-rte:
- {bat-rplp-1}: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12277/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
Known issues
------------
Here are the changes found in Patchwork_109974v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/fi-bdw-5557u/igt@kms_chamelium@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][6] ([fdo#111827])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/bat-adlp-4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [PASS][7] -> [FAIL][8] ([i915#6298])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12277/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#3546])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/bat-adlp-4/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-2:
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][10] ([i915#146])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/fi-bdw-5557u/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-2.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}: [DMESG-WARN][11] ([i915#2867]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12277/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_huc_copy@huc-copy:
- {bat-atsm-1}: [FAIL][13] ([i915#7029]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12277/bat-atsm-1/igt@gem_huc_copy@huc-copy.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/bat-atsm-1/igt@gem_huc_copy@huc-copy.html
* igt@i915_module_load@load:
- {bat-dg2-8}: [FAIL][15] -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12277/bat-dg2-8/igt@i915_module_load@load.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/bat-dg2-8/igt@i915_module_load@load.html
* igt@i915_selftest@live@migrate:
- bat-adlp-4: [INCOMPLETE][17] ([i915#7308]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12277/bat-adlp-4/igt@i915_selftest@live@migrate.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/bat-adlp-4/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][19] ([i915#4983]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12277/bat-rpls-1/igt@i915_selftest@live@reset.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u: [INCOMPLETE][21] ([i915#146]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12277/fi-bdw-5557u/igt@i915_suspend@basic-s3-without-i915.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/fi-bdw-5557u/igt@i915_suspend@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029
[i915#7308]: https://gitlab.freedesktop.org/drm/intel/issues/7308
Build changes
-------------
* Linux: CI_DRM_12277 -> Patchwork_109974v2
CI-20190529: 20190529
CI_DRM_12277: 382f329699fb46e1fccb50f6ada2af090d07686d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7022: d73b21e653555d2e0370789071799aa0037049c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109974v2: 382f329699fb46e1fccb50f6ada2af090d07686d @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1134d43a0088 drm/i915/display: Move squash_ctl register programming to its own function
697abfe9951c drm/i915/display: Move chunks of code out of bxt_set_cdclk()
d48d1d03731f drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
91ca1cfa7696 drm/i915/display: Change terminology for cdclk actions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v2/index.html
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