[PATCH 00/13] LoongArch: Better backtraces

[PATCH 00/13] LoongArch: Better backtraces

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Hi,

Here are some long overdue cleanups of MIPS legacy stuff from
arch/loongarch codebase , and a bunch of tweaks to the backtrace code so
the Quality of Life for unfortunate LoongArch kernel devs (including but
not limited to, myself) could be marginally improved by relieving them of
having to mentally decode the register names and CSR bitfields.

Before:

> [   17.879976] $ 0   : 0000000000000000 9000000000cc980c 90000001002cc000 90000001002cfe30
> [   17.887936] $ 4   : 0000000000000010 9000000000f1f770 90000001002cc000 9000000000cc3468
> [   17.895895] $ 8   : 900000010028fd00 0000000000000001 000055558e569190 0000000000000004
> [   17.903853] $12   : 0000000000000000 0000000000000004 9000000001026000 900000000132b2d8
> [   17.911811] $16   : 9000000001026000 000000006674b539 9000000000d51d10 0000000000000001
> [   17.919769] $20   : 0000000000000000 900000000025c27c 0000000000000004 0000000000000002
> [   17.927727] $24   : 900000000102e5b0 900000000102e508 0000000000000000 0000000000000004
> [   17.935686] $28   : 9000000009007840 0000000000000004 0000000000000000 0000000000000004
> [   17.943644] era   : 90000000002215a0 __arch_cpu_idle+0x20/0x24
> [   17.949438] ra    : 9000000000cc980c default_idle_call+0x34/0x5c
> [   17.955406] CSR crmd: 000000b0
> [   17.955408] CSR prmd: 00000004
> [   17.958521] CSR euen: 00000000
> [   17.961635] CSR ecfg: 00071c1c
> [   17.964748] CSR estat: 00001000
> [   17.971062] ExcCode : 0 (SubCode 0)
> [   17.974522] PrId  : 0014c010 (Loongson-64bit)

After:

> [   45.869200]  pc 90000000002215a0 ra 9000000000ce86bc tp 90000001002cc000
> [   45.875858]  sp 90000001002cfe30 a0 0000000000000018 a1 9000000000f41ee0
> [   45.882516]  a2 0000000000000001 a3 000000000000000a a4 90000000098032c0
> [   45.889173]  a5 000000000000001b a6 000000008ea4398a a7 0000000000000004
> [   45.895831]  t0 0000000000000000 t1 0000000000000004 t2 0000000000003c00
> [   45.902488]  t3 0000000000cccccd t4 ffffffffffffffff t5 000000010d1ff6c8
> [   45.909146]  t6 0000000000000000 t7 0000000000000000 t8 000000000000005b
> [   45.915803] r21 0000000a390fa6c0 s9 0000000000000001 s0 0000000000000003
> [   45.922460]  s1 90000000010565c0 s2 9000000001056518 s3 0000000000000000
> [   45.929118]  s4 0000000000000004 s5 0000000000000004 s6 9000000000228194
> [   45.935775]  s7 900000000102e220 s8 9000000100093e58
> [   45.940704]    pc: 90000000002215a0 __arch_cpu_idle+0x20/0x24
> [   45.946412]    ra: 9000000000ce86bc default_idle_call+0x34/0x5c
> [   45.952294]  crmd: 000000b0 (-WE DACM=CC DACF=CC +PG -DA -IE PLV0)
> [   45.958443]  prmd: 00000004 (-PWE +PIE PPLV0)
> [   45.962772]  euen: 00000000 (-BTE -ASXE -SXE -FPE)
> [   45.967532]  ecfg: 00071c1c (VS=7 LIE=2-4,10-12)
> [   45.972119] estat: 00001000 [INT] (EsubCode=0 ECode=0 IS=12)
> [   45.977741]  prid: 0014c010 (Loongson-64bit)

Please review, and let the bikeshedding begin!

WANG Xuerui (13):
  LoongArch: Unify CSR.EUEN and CSR.ECFG bitfield names with the ISA
    manual
  LoongArch: Rename CSR_ESTAT_EXC -> CSR_ESTAT_ECODE
  LoongArch: Unify the exception code definitions with the manual
  LoongArch: Clean up the architectural interrupt definitions
  LoongArch: Print GPRs with ABI names when showing registers
  LoongArch: Print symbol info for PC and $ra only for kernel-mode
    contexts
  LoongArch: Fix format of CSR lines during show_regs
  LoongArch: Humanize the CRMD line when showing registers
  LoongArch: Humanize the PRMD line when showing registers
  LoongArch: Humanize the EUEN line when showing registers
  LoongArch: Humanize the ECFG line when showing registers
  LoongArch: Humanize the ESTAT line when showing registers
  LoongArch: Use lowercase ISA manual names for BADV and CPUCFG.PRID
    lines in show_regs

 arch/loongarch/include/asm/fpu.h       |  10 +-
 arch/loongarch/include/asm/loongarch.h | 147 ++++++++-------
 arch/loongarch/kernel/fpu.S            |   2 +-
 arch/loongarch/kernel/irq.c            |   2 +-
 arch/loongarch/kernel/perf_event.c     |   2 +-
 arch/loongarch/kernel/process.c        |   2 +-
 arch/loongarch/kernel/time.c           |   2 +-
 arch/loongarch/kernel/traps.c          | 245 ++++++++++++++++++++-----
 arch/loongarch/mm/fault.c              |   4 +-
 arch/loongarch/mm/tlb.c                |  14 +-
 drivers/irqchip/irq-loongarch-cpu.c    |   2 +-
 11 files changed, 294 insertions(+), 138 deletions(-)

-- 
2.38.0

[PATCH 01/13] LoongArch: Unify CSR.EUEN and CSR.ECFG bitfield names with the ISA manual

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

The current field names of CSR.EUEN and CSR.ECFG are not consistent with
the LoongArch ISA manual v1.02, and seems to be leftover from an earlier
time. Change to the ISA manual names.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/include/asm/fpu.h       | 10 +++++-----
 arch/loongarch/include/asm/loongarch.h | 22 +++++++++++-----------
 arch/loongarch/kernel/fpu.S            |  2 +-
 arch/loongarch/kernel/process.c        |  2 +-
 4 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/loongarch/include/asm/fpu.h b/arch/loongarch/include/asm/fpu.h
index 358b254d9c1d..a5015b6536bc 100644
--- a/arch/loongarch/include/asm/fpu.h
+++ b/arch/loongarch/include/asm/fpu.h
@@ -37,13 +37,13 @@ static inline unsigned long mask_fcsr_x(unsigned long fcsr)
 
 static inline int is_fp_enabled(void)
 {
-	return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_FPEN) ?
+	return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_FPE) ?
 		1 : 0;
 }
 
-#define enable_fpu()		set_csr_euen(CSR_EUEN_FPEN)
+#define enable_fpu()		set_csr_euen(CSR_EUEN_FPE)
 
-#define disable_fpu()		clear_csr_euen(CSR_EUEN_FPEN)
+#define disable_fpu()		clear_csr_euen(CSR_EUEN_FPE)
 
 #define clear_fpu_owner()	clear_thread_flag(TIF_USEDFPU)
 
@@ -56,7 +56,7 @@ static inline void __own_fpu(void)
 {
 	enable_fpu();
 	set_thread_flag(TIF_USEDFPU);
-	KSTK_EUEN(current) |= CSR_EUEN_FPEN;
+	KSTK_EUEN(current) |= CSR_EUEN_FPE;
 }
 
 static inline void own_fpu_inatomic(int restore)
@@ -83,7 +83,7 @@ static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
 		disable_fpu();
 		clear_tsk_thread_flag(tsk, TIF_USEDFPU);
 	}
-	KSTK_EUEN(tsk) &= ~(CSR_EUEN_FPEN | CSR_EUEN_LSXEN | CSR_EUEN_LASXEN);
+	KSTK_EUEN(tsk) &= ~(CSR_EUEN_FPE | CSR_EUEN_SXE | CSR_EUEN_ASXE);
 }
 
 static inline void lose_fpu(int save)
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 7f8d57a61c8b..534352d6ed18 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -295,14 +295,14 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
 #define  CSR_PRMD_PPLV			(_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT)
 
 #define LOONGARCH_CSR_EUEN		0x2	/* Extended unit enable */
-#define  CSR_EUEN_LBTEN_SHIFT		3
-#define  CSR_EUEN_LBTEN			(_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT)
-#define  CSR_EUEN_LASXEN_SHIFT		2
-#define  CSR_EUEN_LASXEN		(_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT)
-#define  CSR_EUEN_LSXEN_SHIFT		1
-#define  CSR_EUEN_LSXEN			(_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT)
-#define  CSR_EUEN_FPEN_SHIFT		0
-#define  CSR_EUEN_FPEN			(_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT)
+#define  CSR_EUEN_BTE_SHIFT		3
+#define  CSR_EUEN_BTE			(_ULCAST_(0x1) << CSR_EUEN_BTE_SHIFT)
+#define  CSR_EUEN_ASXE_SHIFT		2
+#define  CSR_EUEN_ASXE			(_ULCAST_(0x1) << CSR_EUEN_ASXE_SHIFT)
+#define  CSR_EUEN_SXE_SHIFT		1
+#define  CSR_EUEN_SXE			(_ULCAST_(0x1) << CSR_EUEN_SXE_SHIFT)
+#define  CSR_EUEN_FPE_SHIFT		0
+#define  CSR_EUEN_FPE			(_ULCAST_(0x1) << CSR_EUEN_FPE_SHIFT)
 
 #define LOONGARCH_CSR_MISC		0x3	/* Misc config */
 
@@ -310,9 +310,9 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
 #define  CSR_ECFG_VS_SHIFT		16
 #define  CSR_ECFG_VS_WIDTH		3
 #define  CSR_ECFG_VS			(_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
-#define  CSR_ECFG_IM_SHIFT		0
-#define  CSR_ECFG_IM_WIDTH		13
-#define  CSR_ECFG_IM			(_ULCAST_(0x1fff) << CSR_ECFG_IM_SHIFT)
+#define  CSR_ECFG_LIE_SHIFT		0
+#define  CSR_ECFG_LIE_WIDTH		13
+#define  CSR_ECFG_LIE			(_ULCAST_(0x1fff) << CSR_ECFG_LIE_SHIFT)
 
 #define LOONGARCH_CSR_ESTAT		0x5	/* Exception status */
 #define  CSR_ESTAT_ESUBCODE_SHIFT	22
diff --git a/arch/loongarch/kernel/fpu.S b/arch/loongarch/kernel/fpu.S
index ccde94140c89..7b1691f67509 100644
--- a/arch/loongarch/kernel/fpu.S
+++ b/arch/loongarch/kernel/fpu.S
@@ -175,7 +175,7 @@ SYM_FUNC_END(_restore_fp)
  */
 
 SYM_FUNC_START(_init_fpu)
-	li.w	t1, CSR_EUEN_FPEN
+	li.w	t1, CSR_EUEN_FPE
 	csrxchg	t1, t1, LOONGARCH_CSR_EUEN
 
 	movgr2fcsr	fcsr0, a0
diff --git a/arch/loongarch/kernel/process.c b/arch/loongarch/kernel/process.c
index 1256e3582475..b88a5864e03d 100644
--- a/arch/loongarch/kernel/process.c
+++ b/arch/loongarch/kernel/process.c
@@ -79,7 +79,7 @@ void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp)
 	prmd |= PLV_USER;
 	regs->csr_prmd = prmd;
 
-	euen = regs->csr_euen & ~(CSR_EUEN_FPEN);
+	euen = regs->csr_euen & ~(CSR_EUEN_FPE);
 	regs->csr_euen = euen;
 	lose_fpu(0);
 
-- 
2.38.0

[PATCH 02/13] LoongArch: Rename CSR_ESTAT_EXC -> CSR_ESTAT_ECODE

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Clean up more MIPS leftover, where exception codes are named
"exc"-something instead of "ecode".

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/include/asm/loongarch.h | 10 +++++-----
 arch/loongarch/kernel/traps.c          |  8 ++++----
 arch/loongarch/mm/fault.c              |  4 ++--
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 534352d6ed18..ca01d04c784e 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -318,9 +318,9 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
 #define  CSR_ESTAT_ESUBCODE_SHIFT	22
 #define  CSR_ESTAT_ESUBCODE_WIDTH	9
 #define  CSR_ESTAT_ESUBCODE		(_ULCAST_(0x1ff) << CSR_ESTAT_ESUBCODE_SHIFT)
-#define  CSR_ESTAT_EXC_SHIFT		16
-#define  CSR_ESTAT_EXC_WIDTH		6
-#define  CSR_ESTAT_EXC			(_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT)
+#define  CSR_ESTAT_ECODE_SHIFT		16
+#define  CSR_ESTAT_ECODE_WIDTH		6
+#define  CSR_ESTAT_ECODE		(_ULCAST_(0x3f) << CSR_ESTAT_ECODE_SHIFT)
 #define  CSR_ESTAT_IS_SHIFT		0
 #define  CSR_ESTAT_IS_WIDTH		15
 #define  CSR_ESTAT_IS			(_ULCAST_(0x7fff) << CSR_ESTAT_IS_SHIFT)
@@ -1194,9 +1194,9 @@ static inline void csr_any_send(unsigned int addr, unsigned int data,
 	iocsr_write64(val, LOONGARCH_IOCSR_ANY_SEND);
 }
 
-static inline unsigned int read_csr_excode(void)
+static inline unsigned int read_csr_ecode(void)
 {
-	return (csr_read32(LOONGARCH_CSR_ESTAT) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
+	return (csr_read32(LOONGARCH_CSR_ESTAT) & CSR_ESTAT_ECODE) >> CSR_ESTAT_ECODE_SHIFT;
 }
 
 static inline void write_csr_index(unsigned int idx)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 7ea62faeeadb..8d959e853ec3 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -194,7 +194,7 @@ static void __show_regs(const struct pt_regs *regs)
 
 	pr_cont("\n");
 
-	exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
+	exccode = ((regs->csr_estat) & CSR_ESTAT_ECODE) >> CSR_ESTAT_ECODE_SHIFT;
 	excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT;
 	printk("ExcCode : %x (SubCode %x)\n", exccode, excsubcode);
 
@@ -436,7 +436,7 @@ asmlinkage void noinstr do_bp(struct pt_regs *regs)
 	irqentry_state_t state = irqentry_enter(regs);
 
 	local_irq_enable();
-	current->thread.trap_nr = read_csr_excode();
+	current->thread.trap_nr = read_csr_ecode();
 	if (__get_inst(&opcode, (u32 *)era, user))
 		goto out_sigsegv;
 
@@ -520,7 +520,7 @@ asmlinkage void noinstr do_ri(struct pt_regs *regs)
 	irqentry_state_t state = irqentry_enter(regs);
 
 	local_irq_enable();
-	current->thread.trap_nr = read_csr_excode();
+	current->thread.trap_nr = read_csr_ecode();
 
 	if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
 		       SIGILL) == NOTIFY_STOP)
@@ -612,7 +612,7 @@ asmlinkage void noinstr do_reserved(struct pt_regs *regs)
 	 * caused by a fatal error after another hardware/software error.
 	 */
 	pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n",
-		read_csr_excode(), current->pid, current->comm);
+		read_csr_ecode(), current->pid, current->comm);
 	die_if_kernel("do_reserved exception", regs);
 	force_sig(SIGUNUSED);
 
diff --git a/arch/loongarch/mm/fault.c b/arch/loongarch/mm/fault.c
index 1ccd53655cab..062632205020 100644
--- a/arch/loongarch/mm/fault.c
+++ b/arch/loongarch/mm/fault.c
@@ -78,7 +78,7 @@ static void __kprobes do_sigbus(struct pt_regs *regs,
 	 * or user mode.
 	 */
 	current->thread.csr_badvaddr = address;
-	current->thread.trap_nr = read_csr_excode();
+	current->thread.trap_nr = read_csr_ecode();
 	force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)address);
 }
 
@@ -100,7 +100,7 @@ static void __kprobes do_sigsegv(struct pt_regs *regs,
 		current->thread.error_code = 1;
 	else
 		current->thread.error_code = 2;
-	current->thread.trap_nr = read_csr_excode();
+	current->thread.trap_nr = read_csr_ecode();
 
 	if (show_unhandled_signals &&
 	    unhandled_signal(current, SIGSEGV) && __ratelimit(&ratelimit_state)) {
-- 
2.38.0

[PATCH 03/13] LoongArch: Unify the exception code definitions with the manual

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

There is apparently much MIPS leftover in those definitions. Amend the
names and comments according to the LoongArch ISA manual.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/include/asm/loongarch.h | 68 +++++++++++++-------------
 arch/loongarch/kernel/traps.c          | 26 +++++-----
 arch/loongarch/mm/tlb.c                | 14 +++---
 3 files changed, 55 insertions(+), 53 deletions(-)

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index ca01d04c784e..143e9ce912ae 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1381,39 +1381,41 @@ __BUILD_CSR_OP(tlbidx)
 #error Bad page size configuration for hugetlbfs!
 #endif
 
-/* ExStatus.ExcCode */
-#define EXCCODE_RSV		0	/* Reserved */
-#define EXCCODE_TLBL		1	/* TLB miss on a load */
-#define EXCCODE_TLBS		2	/* TLB miss on a store */
-#define EXCCODE_TLBI		3	/* TLB miss on a ifetch */
-#define EXCCODE_TLBM		4	/* TLB modified fault */
-#define EXCCODE_TLBNR		5	/* TLB Read-Inhibit exception */
-#define EXCCODE_TLBNX		6	/* TLB Execution-Inhibit exception */
-#define EXCCODE_TLBPE		7	/* TLB Privilege Error */
-#define EXCCODE_ADE		8	/* Address Error */
-	#define EXSUBCODE_ADEF		0	/* Fetch Instruction */
-	#define EXSUBCODE_ADEM		1	/* Access Memory*/
-#define EXCCODE_ALE		9	/* Unalign Access */
-#define EXCCODE_OOB		10	/* Out of bounds */
-#define EXCCODE_SYS		11	/* System call */
-#define EXCCODE_BP		12	/* Breakpoint */
-#define EXCCODE_INE		13	/* Inst. Not Exist */
-#define EXCCODE_IPE		14	/* Inst. Privileged Error */
-#define EXCCODE_FPDIS		15	/* FPU Disabled */
-#define EXCCODE_LSXDIS		16	/* LSX Disabled */
-#define EXCCODE_LASXDIS		17	/* LASX Disabled */
-#define EXCCODE_FPE		18	/* Floating Point Exception */
-	#define EXCSUBCODE_FPE		0	/* Floating Point Exception */
-	#define EXCSUBCODE_VFPE		1	/* Vector Exception */
-#define EXCCODE_WATCH		19	/* Watch address reference */
-#define EXCCODE_BTDIS		20	/* Binary Trans. Disabled */
-#define EXCCODE_BTE		21	/* Binary Trans. Exception */
-#define EXCCODE_PSI		22	/* Guest Privileged Error */
-#define EXCCODE_HYP		23	/* Hypercall */
-#define EXCCODE_GCM		24	/* Guest CSR modified */
-	#define EXCSUBCODE_GCSC		0	/* Software caused */
-	#define EXCSUBCODE_GCHC		1	/* Hardware caused */
-#define EXCCODE_SE		25	/* Security */
+/* CSR.ESTAT.ECode & EsubCode */
+#define ECODE_INT		0	/* INTerrupt */
+#define ECODE_PIL		1	/* Page Invalid for Load */
+#define ECODE_PIS		2	/* Page Invalid for Store */
+#define ECODE_PIF		3	/* Page Invalid for instruction Fetch */
+#define ECODE_PME		4	/* Page Modified Exception */
+#define ECODE_PNR		5	/* Page Non-Readable */
+#define ECODE_PNX		6	/* Page Non-eXecutable */
+#define ECODE_PPI		7	/* Page Privilege level Illegal */
+#define ECODE_ADE		8	/* ADdress Error */
+	#define ESUBCODE_ADEF		0	/* ... on instruction Fetch */
+	#define ESUBCODE_ADEM		1	/* ... on Memory access */
+#define ECODE_ALE		9	/* ALignment Exception */
+#define ECODE_BCE		10	/* Bound Check Error */
+#define ECODE_SYS		11	/* SYStem call */
+#define ECODE_BRK		12	/* BReaKpoint */
+#define ECODE_INE		13	/* Instruction Non-Existent */
+#define ECODE_IPE		14	/* Instruction Privilege Error */
+#define ECODE_FPD		15	/* FPU Disabled */
+#define ECODE_SXD		16	/* LSX unit Disabled */
+#define ECODE_ASXD		17	/* LASX unit Disabled */
+#define ECODE_FPE		18	/* FP Exception */
+	#define ESUBCODE_FPE		0	/* FPU Exception */
+	#define ESUBCODE_VFPE		1	/* Vector FPU Exception */
+#define ECODE_WPE		19	/* WatchPoint Exception */
+	#define ESUBCODE_WPEF		0	/* ... on instruction Fetch */
+	#define ESUBCODE_WPEM		1	/* ... on Memory access */
+#define ECODE_BTD		20	/* LBT unit Disabled */
+#define ECODE_BTE		21	/* LBT unit Exception */
+#define ECODE_GSPR		22	/* Guest Sensitive Privileged Resource exception */
+#define ECODE_HVC		23	/* HyperVisor Call */
+#define ECODE_GCM		24	/* Guest CSR modified */
+	#define ESUBCODE_GCSC		0	/* ..., Software Caused */
+	#define ESUBCODE_GCHC		1	/* ..., Hardware Caused */
+#define ECODE_SE		25	/* Undocumented: Security */
 
 #define EXCCODE_INT_START   64
 #define EXCCODE_SIP0        64
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 8d959e853ec3..8e4691801e34 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -198,7 +198,7 @@ static void __show_regs(const struct pt_regs *regs)
 	excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT;
 	printk("ExcCode : %x (SubCode %x)\n", exccode, excsubcode);
 
-	if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
+	if (exccode >= ECODE_PIL && exccode <= ECODE_ALE)
 		printk("BadVA : %0*lx\n", field, regs->csr_badvaddr);
 
 	printk("PrId  : %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
@@ -746,18 +746,18 @@ void __init trap_init(void)
 	for (i = EXCCODE_INT_START; i < EXCCODE_INT_END; i++)
 		set_handler(i * VECSIZE, handle_vint, VECSIZE);
 
-	set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE);
-	set_handler(EXCCODE_ALE * VECSIZE, handle_ale, VECSIZE);
-	set_handler(EXCCODE_SYS * VECSIZE, handle_sys, VECSIZE);
-	set_handler(EXCCODE_BP * VECSIZE, handle_bp, VECSIZE);
-	set_handler(EXCCODE_INE * VECSIZE, handle_ri, VECSIZE);
-	set_handler(EXCCODE_IPE * VECSIZE, handle_ri, VECSIZE);
-	set_handler(EXCCODE_FPDIS * VECSIZE, handle_fpu, VECSIZE);
-	set_handler(EXCCODE_LSXDIS * VECSIZE, handle_lsx, VECSIZE);
-	set_handler(EXCCODE_LASXDIS * VECSIZE, handle_lasx, VECSIZE);
-	set_handler(EXCCODE_FPE * VECSIZE, handle_fpe, VECSIZE);
-	set_handler(EXCCODE_BTDIS * VECSIZE, handle_lbt, VECSIZE);
-	set_handler(EXCCODE_WATCH * VECSIZE, handle_watch, VECSIZE);
+	set_handler(ECODE_ADE * VECSIZE, handle_ade, VECSIZE);
+	set_handler(ECODE_ALE * VECSIZE, handle_ale, VECSIZE);
+	set_handler(ECODE_SYS * VECSIZE, handle_sys, VECSIZE);
+	set_handler(ECODE_BRK * VECSIZE, handle_bp, VECSIZE);
+	set_handler(ECODE_INE * VECSIZE, handle_ri, VECSIZE);
+	set_handler(ECODE_IPE * VECSIZE, handle_ri, VECSIZE);
+	set_handler(ECODE_FPD * VECSIZE, handle_fpu, VECSIZE);
+	set_handler(ECODE_SXD * VECSIZE, handle_lsx, VECSIZE);
+	set_handler(ECODE_ASXD * VECSIZE, handle_lasx, VECSIZE);
+	set_handler(ECODE_FPE * VECSIZE, handle_fpe, VECSIZE);
+	set_handler(ECODE_BTD * VECSIZE, handle_lbt, VECSIZE);
+	set_handler(ECODE_WPE * VECSIZE, handle_watch, VECSIZE);
 
 	cache_error_setup();
 
diff --git a/arch/loongarch/mm/tlb.c b/arch/loongarch/mm/tlb.c
index da3681f131c8..caaf70e8f5ec 100644
--- a/arch/loongarch/mm/tlb.c
+++ b/arch/loongarch/mm/tlb.c
@@ -264,13 +264,13 @@ void setup_tlb_handler(int cpu)
 	if (cpu == 0) {
 		memcpy((void *)tlbrentry, handle_tlb_refill, 0x80);
 		local_flush_icache_range(tlbrentry, tlbrentry + 0x80);
-		set_handler(EXCCODE_TLBI * VECSIZE, handle_tlb_load, VECSIZE);
-		set_handler(EXCCODE_TLBL * VECSIZE, handle_tlb_load, VECSIZE);
-		set_handler(EXCCODE_TLBS * VECSIZE, handle_tlb_store, VECSIZE);
-		set_handler(EXCCODE_TLBM * VECSIZE, handle_tlb_modify, VECSIZE);
-		set_handler(EXCCODE_TLBNR * VECSIZE, handle_tlb_protect, VECSIZE);
-		set_handler(EXCCODE_TLBNX * VECSIZE, handle_tlb_protect, VECSIZE);
-		set_handler(EXCCODE_TLBPE * VECSIZE, handle_tlb_protect, VECSIZE);
+		set_handler(ECODE_PIF * VECSIZE, handle_tlb_load, VECSIZE);
+		set_handler(ECODE_PIL * VECSIZE, handle_tlb_load, VECSIZE);
+		set_handler(ECODE_PIS * VECSIZE, handle_tlb_store, VECSIZE);
+		set_handler(ECODE_PME * VECSIZE, handle_tlb_modify, VECSIZE);
+		set_handler(ECODE_PNR * VECSIZE, handle_tlb_protect, VECSIZE);
+		set_handler(ECODE_PNX * VECSIZE, handle_tlb_protect, VECSIZE);
+		set_handler(ECODE_PPI * VECSIZE, handle_tlb_protect, VECSIZE);
 	}
 #ifdef CONFIG_NUMA
 	else {
-- 
2.38.0

[PATCH 04/13] LoongArch: Clean up the architectural interrupt definitions

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

While interrupts are assigned ECodes `64 + interrupt number`, all
existing use sites of interrupt numbers want the 64 subtracted.
Re-arrange the definitions so that the actual interrupt number is used
everywhere.

While at it, document an ISA manual erratum that is confirmed by Huacai
but not yet officially fixed in the official (Chinese) version of the
manual.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/include/asm/loongarch.h | 45 ++++++++++++++++----------
 arch/loongarch/kernel/irq.c            |  2 +-
 arch/loongarch/kernel/perf_event.c     |  2 +-
 arch/loongarch/kernel/time.c           |  2 +-
 arch/loongarch/kernel/traps.c          |  2 +-
 drivers/irqchip/irq-loongarch-cpu.c    |  2 +-
 6 files changed, 33 insertions(+), 22 deletions(-)

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 143e9ce912ae..86fe0eda1534 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1417,23 +1417,34 @@ __BUILD_CSR_OP(tlbidx)
 	#define ESUBCODE_GCHC		1	/* ..., Hardware Caused */
 #define ECODE_SE		25	/* Undocumented: Security */
 
-#define EXCCODE_INT_START   64
-#define EXCCODE_SIP0        64
-#define EXCCODE_SIP1        65
-#define EXCCODE_IP0         66
-#define EXCCODE_IP1         67
-#define EXCCODE_IP2         68
-#define EXCCODE_IP3         69
-#define EXCCODE_IP4         70
-#define EXCCODE_IP5         71
-#define EXCCODE_IP6         72
-#define EXCCODE_IP7         73
-#define EXCCODE_PMC         74 /* Performance Counter */
-#define EXCCODE_TIMER       75
-#define EXCCODE_IPI         76
-#define EXCCODE_NMI         77
-#define EXCCODE_INT_END     78
-#define EXCCODE_INT_NUM	    (EXCCODE_INT_END - EXCCODE_INT_START)
+/*
+ * Interrupt numbers
+ *
+ * The LoongArch ISA manual v1.02 says there are 13 interrupts in total (see
+ * the description about CSR.ESTAT, Volume 1, section 7.4.6), unfortunately
+ * in this case the manual is wrong, and the definitions here shall prevail.
+ * In other words, the widths of CSR.ECFG.LIE and CSR.ESTAT.IS are 14 bits,
+ * instead of 13 as the manual suggests otherwise.
+ */
+#define INT_SWI0	0	/* Software Interrupts */
+#define INT_SWI1	1
+#define INT_HWI0	2	/* Hardware Interrupts */
+#define INT_HWI1	3
+#define INT_HWI2	4
+#define INT_HWI3	5
+#define INT_HWI4	6
+#define INT_HWI5	7
+#define INT_HWI6	8
+#define INT_HWI7	9
+#define INT_PCOV	10	/* Performance Counter Overflow */
+#define INT_TI		11	/* Timer */
+#define INT_IPI		12
+#define INT_NMI		13
+#define INT_NUM		(INT_NMI - INT_SWI0)
+
+/* ECodes corresponding to interrupts */
+#define ECODE_INT_START	64
+#define ECODE_INT_END	(ECODE_INT_START + INT_NUM)
 
 /* FPU register names */
 #define LOONGARCH_FCSR0	$r0
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 1ba19c76563e..242c22a0b994 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -92,7 +92,7 @@ static int __init get_ipi_irq(void)
 	struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
 
 	if (d)
-		return irq_create_mapping(d, EXCCODE_IPI - EXCCODE_INT_START);
+		return irq_create_mapping(d, INT_IPI);
 
 	return -EINVAL;
 }
diff --git a/arch/loongarch/kernel/perf_event.c b/arch/loongarch/kernel/perf_event.c
index 707bd32e5c4f..ff28f99b47d7 100644
--- a/arch/loongarch/kernel/perf_event.c
+++ b/arch/loongarch/kernel/perf_event.c
@@ -461,7 +461,7 @@ static int get_pmc_irq(void)
 	struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
 
 	if (d)
-		return irq_create_mapping(d, EXCCODE_PMC - EXCCODE_INT_START);
+		return irq_create_mapping(d, INT_PCOV);
 
 	return -EINVAL;
 }
diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c
index 786735dcc8d6..571a7e639e64 100644
--- a/arch/loongarch/kernel/time.c
+++ b/arch/loongarch/kernel/time.c
@@ -128,7 +128,7 @@ static int get_timer_irq(void)
 	struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
 
 	if (d)
-		return irq_create_mapping(d, EXCCODE_TIMER - EXCCODE_INT_START);
+		return irq_create_mapping(d, INT_TI);
 
 	return -EINVAL;
 }
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 8e4691801e34..d4dc35c39296 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -743,7 +743,7 @@ void __init trap_init(void)
 	long i;
 
 	/* Set interrupt vector handler */
-	for (i = EXCCODE_INT_START; i < EXCCODE_INT_END; i++)
+	for (i = ECODE_INT_START; i < ECODE_INT_END; i++)
 		set_handler(i * VECSIZE, handle_vint, VECSIZE);
 
 	set_handler(ECODE_ADE * VECSIZE, handle_ade, VECSIZE);
diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
index 093609c8eaa7..3fc5c9ea426a 100644
--- a/drivers/irqchip/irq-loongarch-cpu.c
+++ b/drivers/irqchip/irq-loongarch-cpu.c
@@ -125,7 +125,7 @@ static int __init cpuintc_acpi_init(union acpi_subtable_headers *header,
 	clear_csr_estat(ESTATF_IP);
 
 	cpuintc_handle = irq_domain_alloc_named_fwnode("CPUINTC");
-	irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM,
+	irq_domain = irq_domain_create_linear(cpuintc_handle, INT_NUM,
 					&loongarch_cpu_intc_irq_domain_ops, NULL);
 
 	if (!irq_domain)
-- 
2.38.0

[PATCH 05/13] LoongArch: Print GPRs with ABI names when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Print 3 registers per line to fit the entire line within 75 columns even
with timestamp prefixed to each line, to ease future copy-pastes for all.

And show PC (CSR.ERA) in place of $zero, like what arch/riscv does.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 36 ++++++++++++++++++++++-------------
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index d4dc35c39296..c6fe09bc5ccc 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -161,22 +161,32 @@ static void __show_regs(const struct pt_regs *regs)
 	const int field = 2 * sizeof(unsigned long);
 	unsigned int excsubcode;
 	unsigned int exccode;
-	int i;
 
 	show_regs_print_info(KERN_DEFAULT);
 
-	/*
-	 * Saved main processor registers
-	 */
-	for (i = 0; i < 32; ) {
-		if ((i % 4) == 0)
-			printk("$%2d   :", i);
-		pr_cont(" %0*lx", field, regs->regs[i]);
-
-		i++;
-		if ((i % 4) == 0)
-			pr_cont("\n");
-	}
+	/* Print PC and GPRs, 3 per row to fit output in 75 columns */
+	pr_cont(" pc %0*lx ra %0*lx tp %0*lx\n",
+		field, regs->csr_era, field, regs->regs[1], field, regs->regs[2]);
+	pr_cont(" sp %0*lx a0 %0*lx a1 %0*lx\n",
+		field, regs->regs[3], field, regs->regs[4], field, regs->regs[5]);
+	pr_cont(" a2 %0*lx a3 %0*lx a4 %0*lx\n",
+		field, regs->regs[6], field, regs->regs[7], field, regs->regs[8]);
+	pr_cont(" a5 %0*lx a6 %0*lx a7 %0*lx\n",
+		field, regs->regs[9], field, regs->regs[10], field, regs->regs[11]);
+	pr_cont(" t0 %0*lx t1 %0*lx t2 %0*lx\n",
+		field, regs->regs[12], field, regs->regs[13], field, regs->regs[14]);
+	pr_cont(" t3 %0*lx t4 %0*lx t5 %0*lx\n",
+		field, regs->regs[15], field, regs->regs[16], field, regs->regs[17]);
+	pr_cont(" t6 %0*lx t7 %0*lx t8 %0*lx\n",
+		field, regs->regs[18], field, regs->regs[19], field, regs->regs[20]);
+	pr_cont("r21 %0*lx s9 %0*lx s0 %0*lx\n",
+		field, regs->regs[21], field, regs->regs[22], field, regs->regs[23]);
+	pr_cont(" s1 %0*lx s2 %0*lx s3 %0*lx\n",
+		field, regs->regs[24], field, regs->regs[25], field, regs->regs[26]);
+	pr_cont(" s4 %0*lx s5 %0*lx s6 %0*lx\n",
+		field, regs->regs[27], field, regs->regs[28], field, regs->regs[29]);
+	pr_cont(" s7 %0*lx s8 %0*lx\n",
+		field, regs->regs[30], field, regs->regs[31]);
 
 	/*
 	 * Saved csr registers
-- 
2.38.0

[PATCH 06/13] LoongArch: Print symbol info for PC and $ra only for kernel-mode contexts

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Otherwise the addresses wouldn't make sense at all. And show "pc"
instead of "era" for a tiny bit of user friendliness.

While at it, align the "map keys" to maintain right-alignment with the
"estat:" line too.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index c6fe09bc5ccc..e24435c78086 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -188,14 +188,12 @@ static void __show_regs(const struct pt_regs *regs)
 	pr_cont(" s7 %0*lx s8 %0*lx\n",
 		field, regs->regs[30], field, regs->regs[31]);
 
-	/*
-	 * Saved csr registers
-	 */
-	printk("era   : %0*lx %pS\n", field, regs->csr_era,
-	       (void *) regs->csr_era);
-	printk("ra    : %0*lx %pS\n", field, regs->regs[1],
-	       (void *) regs->regs[1]);
+	if (!user_mode(regs)) {
+		pr_cont("   pc: %0*lx %pS\n", field, regs->csr_era, (void *) regs->csr_era);
+		pr_cont("   ra: %0*lx %pS\n", field, regs->regs[1], (void *) regs->regs[1]);
+	}
 
+	/* Print important CSRs */
 	printk("CSR crmd: %08lx	", regs->csr_crmd);
 	printk("CSR prmd: %08lx	", regs->csr_prmd);
 	printk("CSR euen: %08lx	", regs->csr_euen);
-- 
2.38.0

[PATCH 07/13] LoongArch: Fix format of CSR lines during show_regs

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Use lowercase CSR names throughout, and right-align the keys. The "CSR"
part is inferrable from context, hence dropped for more horizontal
space.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index e24435c78086..92a12f544f5e 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -194,13 +194,11 @@ static void __show_regs(const struct pt_regs *regs)
 	}
 
 	/* Print important CSRs */
-	printk("CSR crmd: %08lx	", regs->csr_crmd);
-	printk("CSR prmd: %08lx	", regs->csr_prmd);
-	printk("CSR euen: %08lx	", regs->csr_euen);
-	printk("CSR ecfg: %08lx	", regs->csr_ecfg);
-	printk("CSR estat: %08lx	", regs->csr_estat);
-
-	pr_cont("\n");
+	pr_cont(" crmd: %08lx\n", regs->csr_crmd);
+	pr_cont(" prmd: %08lx\n", regs->csr_prmd);
+	pr_cont(" euen: %08lx\n", regs->csr_euen);
+	pr_cont(" ecfg: %08lx\n", regs->csr_ecfg);
+	pr_cont("estat: %08lx\n", regs->csr_estat);
 
 	exccode = ((regs->csr_estat) & CSR_ESTAT_ECODE) >> CSR_ESTAT_ECODE_SHIFT;
 	excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT;
-- 
2.38.0

[PATCH 08/13] LoongArch: Humanize the CRMD line when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Example output looks like:

[   xx.xxxxxx]  crmd: 000000b0 (-WE DACM=CC DACF=CC +PG -DA -IE PLV0)

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 46 ++++++++++++++++++++++++++++++++++-
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 92a12f544f5e..760119e02820 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -3,6 +3,7 @@
  * Author: Huacai Chen <chenhuacai@loongson.cn>
  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  */
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/bug.h>
 #include <linux/compiler.h>
@@ -156,6 +157,49 @@ static void show_code(unsigned int *pc, bool user)
 	pr_cont("\n");
 }
 
+static void print_bool_fragment(const char *key, unsigned long val, bool first)
+{
+	/* e.g. "+PG", "-DA" */
+	pr_cont("%s%c%s", first ? "" : " ", val ? '+' : '-', key);
+}
+
+static void print_plv_fragment(const char *key, int val)
+{
+	/* e.g. "PLV0", "PPLV3" */
+	pr_cont(" %s%d", key, val);
+}
+
+static void print_memory_type_fragment(const char *key, unsigned long val)
+{
+	/* e.g. "DATM=WUC" */
+	const char *humanized_type = NULL;
+
+	switch (val) {
+	case 0: humanized_type = "SUC"; break;
+	case 1: humanized_type = "CC"; break;
+	case 2: humanized_type = "WUC"; break;
+	}
+
+	if (humanized_type) {
+		pr_cont(" %s=%s", key, humanized_type);
+	} else {
+		pr_cont(" %s=Reserved(%lu)", key, val);
+	}
+}
+
+static void print_crmd(unsigned long x)
+{
+	pr_cont(" crmd: %08lx (", x);
+	print_bool_fragment("WE", FIELD_GET(CSR_CRMD_WE, x), true);
+	print_memory_type_fragment("DACM", FIELD_GET(CSR_CRMD_DACM, x));
+	print_memory_type_fragment("DACF", FIELD_GET(CSR_CRMD_DACF, x));
+	print_bool_fragment("PG", FIELD_GET(CSR_CRMD_PG, x), false);
+	print_bool_fragment("DA", FIELD_GET(CSR_CRMD_DA, x), false);
+	print_bool_fragment("IE", FIELD_GET(CSR_CRMD_IE, x), false);
+	print_plv_fragment("PLV", (int) FIELD_GET(CSR_CRMD_PLV, x));
+	pr_cont(")\n");
+}
+
 static void __show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
@@ -194,7 +238,7 @@ static void __show_regs(const struct pt_regs *regs)
 	}
 
 	/* Print important CSRs */
-	pr_cont(" crmd: %08lx\n", regs->csr_crmd);
+	print_crmd(regs->csr_crmd);
 	pr_cont(" prmd: %08lx\n", regs->csr_prmd);
 	pr_cont(" euen: %08lx\n", regs->csr_euen);
 	pr_cont(" ecfg: %08lx\n", regs->csr_ecfg);
-- 
2.38.0

[PATCH 09/13] LoongArch: Humanize the PRMD line when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Example output looks like:

[   xx.xxxxxx]  prmd: 00000004 (-PWE +PIE PPLV0)

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 760119e02820..570f93303588 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -200,6 +200,15 @@ static void print_crmd(unsigned long x)
 	pr_cont(")\n");
 }
 
+static void print_prmd(unsigned long x)
+{
+	pr_cont(" prmd: %08lx (", x);
+	print_bool_fragment("PWE", FIELD_GET(CSR_PRMD_PWE, x), true);
+	print_bool_fragment("PIE", FIELD_GET(CSR_PRMD_PIE, x), false);
+	print_plv_fragment("PPLV", (int) FIELD_GET(CSR_PRMD_PPLV, x));
+	pr_cont(")\n");
+}
+
 static void __show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
@@ -239,7 +248,7 @@ static void __show_regs(const struct pt_regs *regs)
 
 	/* Print important CSRs */
 	print_crmd(regs->csr_crmd);
-	pr_cont(" prmd: %08lx\n", regs->csr_prmd);
+	print_prmd(regs->csr_prmd);
 	pr_cont(" euen: %08lx\n", regs->csr_euen);
 	pr_cont(" ecfg: %08lx\n", regs->csr_ecfg);
 	pr_cont("estat: %08lx\n", regs->csr_estat);
-- 
2.38.0

[PATCH 10/13] LoongArch: Humanize the EUEN line when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Example output looks like:

[   xx.xxxxxx]  euen: 00000000 (-BTE -ASXE -SXE -FPE)

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 570f93303588..b95e473eee58 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -209,6 +209,16 @@ static void print_prmd(unsigned long x)
 	pr_cont(")\n");
 }
 
+static void print_euen(unsigned long x)
+{
+	pr_cont(" euen: %08lx (", x);
+	print_bool_fragment("BTE", FIELD_GET(CSR_EUEN_BTE, x), true);
+	print_bool_fragment("ASXE", FIELD_GET(CSR_EUEN_ASXE, x), false);
+	print_bool_fragment("SXE", FIELD_GET(CSR_EUEN_SXE, x), false);
+	print_bool_fragment("FPE", FIELD_GET(CSR_EUEN_FPE, x), false);
+	pr_cont(")\n");
+}
+
 static void __show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
@@ -249,7 +259,7 @@ static void __show_regs(const struct pt_regs *regs)
 	/* Print important CSRs */
 	print_crmd(regs->csr_crmd);
 	print_prmd(regs->csr_prmd);
-	pr_cont(" euen: %08lx\n", regs->csr_euen);
+	print_euen(regs->csr_euen);
 	pr_cont(" ecfg: %08lx\n", regs->csr_ecfg);
 	pr_cont("estat: %08lx\n", regs->csr_estat);
 
-- 
2.38.0

[PATCH 11/13] LoongArch: Humanize the ECFG line when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Example output looks like:

[   xx.xxxxxx]  ecfg: 00071c1c (VS=7 LIE=2-4,10-12)

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index b95e473eee58..1d3879d4aeeb 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -187,6 +187,12 @@ static void print_memory_type_fragment(const char *key, unsigned long val)
 	}
 }
 
+static void print_intr_fragment(const char *key, unsigned long val)
+{
+	/* e.g. "LIE=0-1,3,5-7" */
+	pr_cont(" %s=%*pbl", key, INT_NUM, &val);
+}
+
 static void print_crmd(unsigned long x)
 {
 	pr_cont(" crmd: %08lx (", x);
@@ -219,6 +225,13 @@ static void print_euen(unsigned long x)
 	pr_cont(")\n");
 }
 
+static void print_ecfg(unsigned long x)
+{
+	pr_cont(" ecfg: %08lx (VS=%d", x, (int) FIELD_GET(CSR_ECFG_VS, x));
+	print_intr_fragment("LIE", FIELD_GET(CSR_ECFG_LIE, x));
+	pr_cont(")\n");
+}
+
 static void __show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
@@ -260,7 +273,7 @@ static void __show_regs(const struct pt_regs *regs)
 	print_crmd(regs->csr_crmd);
 	print_prmd(regs->csr_prmd);
 	print_euen(regs->csr_euen);
-	pr_cont(" ecfg: %08lx\n", regs->csr_ecfg);
+	print_ecfg(regs->csr_ecfg);
 	pr_cont("estat: %08lx\n", regs->csr_estat);
 
 	exccode = ((regs->csr_estat) & CSR_ESTAT_ECODE) >> CSR_ESTAT_ECODE_SHIFT;
-- 
2.38.0

[PATCH 12/13] LoongArch: Humanize the ESTAT line when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Example output looks like:

[   xx.xxxxxx] estat: 00001000 [INT] (EsubCode=0 ECode=0 IS=12)

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 77 +++++++++++++++++++++++++++++++----
 1 file changed, 69 insertions(+), 8 deletions(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 1d3879d4aeeb..27a4ac049d64 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -232,11 +232,76 @@ static void print_ecfg(unsigned long x)
 	pr_cont(")\n");
 }
 
+static const char *humanize_exc_name(unsigned int ecode, unsigned int esubcode)
+{
+	switch (ecode) {
+	case ECODE_INT: return "INT";
+	case ECODE_PIL: return "PIL";
+	case ECODE_PIS: return "PIS";
+	case ECODE_PIF: return "PIF";
+	case ECODE_PME: return "PME";
+	case ECODE_PNR: return "PNR";
+	case ECODE_PNX: return "PNX";
+	case ECODE_PPI: return "PPI";
+	case ECODE_ADE:
+		switch (esubcode) {
+		case ESUBCODE_ADEF: return "ADEF";
+		case ESUBCODE_ADEM: return "ADEM";
+		}
+		break;
+	case ECODE_ALE: return "ALE";
+	case ECODE_BCE: return "BCE";
+	case ECODE_SYS: return "SYS";
+	case ECODE_BRK: return "BRK";
+	case ECODE_INE: return "INE";
+	case ECODE_IPE: return "IPE";
+	case ECODE_FPD: return "FPD";
+	case ECODE_SXD: return "SXD";
+	case ECODE_ASXD: return "ASXD";
+	case ECODE_FPE:
+		switch (esubcode) {
+		case ESUBCODE_FPE: return "FPE";
+		case ESUBCODE_VFPE: return "VFPE";
+		}
+		break;
+	case ECODE_WPE:
+		switch (esubcode) {
+		case ESUBCODE_WPEF: return "WPEF";
+		case ESUBCODE_WPEM: return "WPEM";
+		}
+		break;
+	case ECODE_BTD: return "BTD";
+	case ECODE_BTE: return "BTE";
+	case ECODE_GSPR: return "GSPR";
+	case ECODE_HVC: return "HVC";
+	case ECODE_GCM:
+		switch (esubcode) {
+		case ESUBCODE_GCSC: return "GCSC";
+		case ESUBCODE_GCHC: return "GCHC";
+		}
+		break;
+	}
+
+	return "???";
+}
+
+static void print_estat(unsigned long x)
+{
+	unsigned int ecode = FIELD_GET(CSR_ESTAT_ECODE, x);
+	unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, x);
+
+	pr_cont("estat: %08lx [%s] (EsubCode=%d ECode=%d", x,
+		humanize_exc_name(ecode, esubcode),
+		(int) FIELD_GET(CSR_ESTAT_ESUBCODE, x),
+		(int) FIELD_GET(CSR_ESTAT_ECODE, x));
+	print_intr_fragment("IS", FIELD_GET(CSR_ESTAT_IS, x));
+	pr_cont(")\n");
+}
+
 static void __show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
-	unsigned int excsubcode;
-	unsigned int exccode;
+	unsigned int ecode = FIELD_GET(CSR_ESTAT_ECODE, regs->csr_estat);
 
 	show_regs_print_info(KERN_DEFAULT);
 
@@ -274,13 +339,9 @@ static void __show_regs(const struct pt_regs *regs)
 	print_prmd(regs->csr_prmd);
 	print_euen(regs->csr_euen);
 	print_ecfg(regs->csr_ecfg);
-	pr_cont("estat: %08lx\n", regs->csr_estat);
-
-	exccode = ((regs->csr_estat) & CSR_ESTAT_ECODE) >> CSR_ESTAT_ECODE_SHIFT;
-	excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT;
-	printk("ExcCode : %x (SubCode %x)\n", exccode, excsubcode);
+	print_estat(regs->csr_estat);
 
-	if (exccode >= ECODE_PIL && exccode <= ECODE_ALE)
+	if (ecode >= ECODE_PIL && ecode <= ECODE_ALE)
 		printk("BadVA : %0*lx\n", field, regs->csr_badvaddr);
 
 	printk("PrId  : %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
-- 
2.38.0

[PATCH 13/13] LoongArch: Use lowercase ISA manual names for BADV and CPUCFG.PRID lines in show_regs

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 27a4ac049d64..d1b9f5a891dd 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -342,9 +342,9 @@ static void __show_regs(const struct pt_regs *regs)
 	print_estat(regs->csr_estat);
 
 	if (ecode >= ECODE_PIL && ecode <= ECODE_ALE)
-		printk("BadVA : %0*lx\n", field, regs->csr_badvaddr);
+		printk(" badv: %0*lx\n", field, regs->csr_badvaddr);
 
-	printk("PrId  : %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
+	printk(" prid: %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
 	       cpu_family_string());
 }
 
-- 
2.38.0

Re: [PATCH 01/13] LoongArch: Unify CSR.EUEN and CSR.ECFG bitfield names with the ISA manual

[Huacai Chen]

On Mon, Oct 24, 2022 at 8:13 PM WANG Xuerui <kernel@xen0n.name> wrote:
>
> From: WANG Xuerui <git@xen0n.name>
>
> The current field names of CSR.EUEN and CSR.ECFG are not consistent with
> the LoongArch ISA manual v1.02, and seems to be leftover from an earlier
> time. Change to the ISA manual names.
>
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> ---
>  arch/loongarch/include/asm/fpu.h       | 10 +++++-----
>  arch/loongarch/include/asm/loongarch.h | 22 +++++++++++-----------
>  arch/loongarch/kernel/fpu.S            |  2 +-
>  arch/loongarch/kernel/process.c        |  2 +-
>  4 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/fpu.h b/arch/loongarch/include/asm/fpu.h
> index 358b254d9c1d..a5015b6536bc 100644
> --- a/arch/loongarch/include/asm/fpu.h
> +++ b/arch/loongarch/include/asm/fpu.h
> @@ -37,13 +37,13 @@ static inline unsigned long mask_fcsr_x(unsigned long fcsr)
>
>  static inline int is_fp_enabled(void)
>  {
> -       return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_FPEN) ?
> +       return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_FPE) ?
>                 1 : 0;
>  }
>
> -#define enable_fpu()           set_csr_euen(CSR_EUEN_FPEN)
> +#define enable_fpu()           set_csr_euen(CSR_EUEN_FPE)
I don't think code should be exactly the same as manual, especially
FPE may be misunderstood as "FP Exception".

Huacai

>
> -#define disable_fpu()          clear_csr_euen(CSR_EUEN_FPEN)
> +#define disable_fpu()          clear_csr_euen(CSR_EUEN_FPE)
>
>  #define clear_fpu_owner()      clear_thread_flag(TIF_USEDFPU)
>
> @@ -56,7 +56,7 @@ static inline void __own_fpu(void)
>  {
>         enable_fpu();
>         set_thread_flag(TIF_USEDFPU);
> -       KSTK_EUEN(current) |= CSR_EUEN_FPEN;
> +       KSTK_EUEN(current) |= CSR_EUEN_FPE;
>  }
>
>  static inline void own_fpu_inatomic(int restore)
> @@ -83,7 +83,7 @@ static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
>                 disable_fpu();
>                 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
>         }
> -       KSTK_EUEN(tsk) &= ~(CSR_EUEN_FPEN | CSR_EUEN_LSXEN | CSR_EUEN_LASXEN);
> +       KSTK_EUEN(tsk) &= ~(CSR_EUEN_FPE | CSR_EUEN_SXE | CSR_EUEN_ASXE);
>  }
>
>  static inline void lose_fpu(int save)
> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
> index 7f8d57a61c8b..534352d6ed18 100644
> --- a/arch/loongarch/include/asm/loongarch.h
> +++ b/arch/loongarch/include/asm/loongarch.h
> @@ -295,14 +295,14 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
>  #define  CSR_PRMD_PPLV                 (_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT)
>
>  #define LOONGARCH_CSR_EUEN             0x2     /* Extended unit enable */
> -#define  CSR_EUEN_LBTEN_SHIFT          3
> -#define  CSR_EUEN_LBTEN                        (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT)
> -#define  CSR_EUEN_LASXEN_SHIFT         2
> -#define  CSR_EUEN_LASXEN               (_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT)
> -#define  CSR_EUEN_LSXEN_SHIFT          1
> -#define  CSR_EUEN_LSXEN                        (_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT)
> -#define  CSR_EUEN_FPEN_SHIFT           0
> -#define  CSR_EUEN_FPEN                 (_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT)
> +#define  CSR_EUEN_BTE_SHIFT            3
> +#define  CSR_EUEN_BTE                  (_ULCAST_(0x1) << CSR_EUEN_BTE_SHIFT)
> +#define  CSR_EUEN_ASXE_SHIFT           2
> +#define  CSR_EUEN_ASXE                 (_ULCAST_(0x1) << CSR_EUEN_ASXE_SHIFT)
> +#define  CSR_EUEN_SXE_SHIFT            1
> +#define  CSR_EUEN_SXE                  (_ULCAST_(0x1) << CSR_EUEN_SXE_SHIFT)
> +#define  CSR_EUEN_FPE_SHIFT            0
> +#define  CSR_EUEN_FPE                  (_ULCAST_(0x1) << CSR_EUEN_FPE_SHIFT)
>
>  #define LOONGARCH_CSR_MISC             0x3     /* Misc config */
>
> @@ -310,9 +310,9 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
>  #define  CSR_ECFG_VS_SHIFT             16
>  #define  CSR_ECFG_VS_WIDTH             3
>  #define  CSR_ECFG_VS                   (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
> -#define  CSR_ECFG_IM_SHIFT             0
> -#define  CSR_ECFG_IM_WIDTH             13
> -#define  CSR_ECFG_IM                   (_ULCAST_(0x1fff) << CSR_ECFG_IM_SHIFT)
> +#define  CSR_ECFG_LIE_SHIFT            0
> +#define  CSR_ECFG_LIE_WIDTH            13
> +#define  CSR_ECFG_LIE                  (_ULCAST_(0x1fff) << CSR_ECFG_LIE_SHIFT)
>
>  #define LOONGARCH_CSR_ESTAT            0x5     /* Exception status */
>  #define  CSR_ESTAT_ESUBCODE_SHIFT      22
> diff --git a/arch/loongarch/kernel/fpu.S b/arch/loongarch/kernel/fpu.S
> index ccde94140c89..7b1691f67509 100644
> --- a/arch/loongarch/kernel/fpu.S
> +++ b/arch/loongarch/kernel/fpu.S
> @@ -175,7 +175,7 @@ SYM_FUNC_END(_restore_fp)
>   */
>
>  SYM_FUNC_START(_init_fpu)
> -       li.w    t1, CSR_EUEN_FPEN
> +       li.w    t1, CSR_EUEN_FPE
>         csrxchg t1, t1, LOONGARCH_CSR_EUEN
>
>         movgr2fcsr      fcsr0, a0
> diff --git a/arch/loongarch/kernel/process.c b/arch/loongarch/kernel/process.c
> index 1256e3582475..b88a5864e03d 100644
> --- a/arch/loongarch/kernel/process.c
> +++ b/arch/loongarch/kernel/process.c
> @@ -79,7 +79,7 @@ void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp)
>         prmd |= PLV_USER;
>         regs->csr_prmd = prmd;
>
> -       euen = regs->csr_euen & ~(CSR_EUEN_FPEN);
> +       euen = regs->csr_euen & ~(CSR_EUEN_FPE);
>         regs->csr_euen = euen;
>         lose_fpu(0);
>
> --
> 2.38.0
>
>

Re: [PATCH 00/13] LoongArch: Better backtraces

[Huacai Chen]

Generally, I agree to improve the output format, but I don't think we
need to modify the register definitions.

Huacai

On Mon, Oct 24, 2022 at 8:13 PM WANG Xuerui <kernel@xen0n.name> wrote:
>
> From: WANG Xuerui <git@xen0n.name>
>
> Hi,
>
> Here are some long overdue cleanups of MIPS legacy stuff from
> arch/loongarch codebase , and a bunch of tweaks to the backtrace code so
> the Quality of Life for unfortunate LoongArch kernel devs (including but
> not limited to, myself) could be marginally improved by relieving them of
> having to mentally decode the register names and CSR bitfields.
>
> Before:
>
> > [   17.879976] $ 0   : 0000000000000000 9000000000cc980c 90000001002cc000 90000001002cfe30
> > [   17.887936] $ 4   : 0000000000000010 9000000000f1f770 90000001002cc000 9000000000cc3468
> > [   17.895895] $ 8   : 900000010028fd00 0000000000000001 000055558e569190 0000000000000004
> > [   17.903853] $12   : 0000000000000000 0000000000000004 9000000001026000 900000000132b2d8
> > [   17.911811] $16   : 9000000001026000 000000006674b539 9000000000d51d10 0000000000000001
> > [   17.919769] $20   : 0000000000000000 900000000025c27c 0000000000000004 0000000000000002
> > [   17.927727] $24   : 900000000102e5b0 900000000102e508 0000000000000000 0000000000000004
> > [   17.935686] $28   : 9000000009007840 0000000000000004 0000000000000000 0000000000000004
> > [   17.943644] era   : 90000000002215a0 __arch_cpu_idle+0x20/0x24
> > [   17.949438] ra    : 9000000000cc980c default_idle_call+0x34/0x5c
> > [   17.955406] CSR crmd: 000000b0
> > [   17.955408] CSR prmd: 00000004
> > [   17.958521] CSR euen: 00000000
> > [   17.961635] CSR ecfg: 00071c1c
> > [   17.964748] CSR estat: 00001000
> > [   17.971062] ExcCode : 0 (SubCode 0)
> > [   17.974522] PrId  : 0014c010 (Loongson-64bit)
>
> After:
>
> > [   45.869200]  pc 90000000002215a0 ra 9000000000ce86bc tp 90000001002cc000
> > [   45.875858]  sp 90000001002cfe30 a0 0000000000000018 a1 9000000000f41ee0
> > [   45.882516]  a2 0000000000000001 a3 000000000000000a a4 90000000098032c0
> > [   45.889173]  a5 000000000000001b a6 000000008ea4398a a7 0000000000000004
> > [   45.895831]  t0 0000000000000000 t1 0000000000000004 t2 0000000000003c00
> > [   45.902488]  t3 0000000000cccccd t4 ffffffffffffffff t5 000000010d1ff6c8
> > [   45.909146]  t6 0000000000000000 t7 0000000000000000 t8 000000000000005b
> > [   45.915803] r21 0000000a390fa6c0 s9 0000000000000001 s0 0000000000000003
> > [   45.922460]  s1 90000000010565c0 s2 9000000001056518 s3 0000000000000000
> > [   45.929118]  s4 0000000000000004 s5 0000000000000004 s6 9000000000228194
> > [   45.935775]  s7 900000000102e220 s8 9000000100093e58
> > [   45.940704]    pc: 90000000002215a0 __arch_cpu_idle+0x20/0x24
> > [   45.946412]    ra: 9000000000ce86bc default_idle_call+0x34/0x5c
> > [   45.952294]  crmd: 000000b0 (-WE DACM=CC DACF=CC +PG -DA -IE PLV0)
> > [   45.958443]  prmd: 00000004 (-PWE +PIE PPLV0)
> > [   45.962772]  euen: 00000000 (-BTE -ASXE -SXE -FPE)
> > [   45.967532]  ecfg: 00071c1c (VS=7 LIE=2-4,10-12)
> > [   45.972119] estat: 00001000 [INT] (EsubCode=0 ECode=0 IS=12)
> > [   45.977741]  prid: 0014c010 (Loongson-64bit)
>
> Please review, and let the bikeshedding begin!
>
> WANG Xuerui (13):
>   LoongArch: Unify CSR.EUEN and CSR.ECFG bitfield names with the ISA
>     manual
>   LoongArch: Rename CSR_ESTAT_EXC -> CSR_ESTAT_ECODE
>   LoongArch: Unify the exception code definitions with the manual
>   LoongArch: Clean up the architectural interrupt definitions
>   LoongArch: Print GPRs with ABI names when showing registers
>   LoongArch: Print symbol info for PC and $ra only for kernel-mode
>     contexts
>   LoongArch: Fix format of CSR lines during show_regs
>   LoongArch: Humanize the CRMD line when showing registers
>   LoongArch: Humanize the PRMD line when showing registers
>   LoongArch: Humanize the EUEN line when showing registers
>   LoongArch: Humanize the ECFG line when showing registers
>   LoongArch: Humanize the ESTAT line when showing registers
>   LoongArch: Use lowercase ISA manual names for BADV and CPUCFG.PRID
>     lines in show_regs
>
>  arch/loongarch/include/asm/fpu.h       |  10 +-
>  arch/loongarch/include/asm/loongarch.h | 147 ++++++++-------
>  arch/loongarch/kernel/fpu.S            |   2 +-
>  arch/loongarch/kernel/irq.c            |   2 +-
>  arch/loongarch/kernel/perf_event.c     |   2 +-
>  arch/loongarch/kernel/process.c        |   2 +-
>  arch/loongarch/kernel/time.c           |   2 +-
>  arch/loongarch/kernel/traps.c          | 245 ++++++++++++++++++++-----
>  arch/loongarch/mm/fault.c              |   4 +-
>  arch/loongarch/mm/tlb.c                |  14 +-
>  drivers/irqchip/irq-loongarch-cpu.c    |   2 +-
>  11 files changed, 294 insertions(+), 138 deletions(-)
>
> --
> 2.38.0
>
>

Re: [PATCH 01/13] LoongArch: Unify CSR.EUEN and CSR.ECFG bitfield names with the ISA manual

[Xi Ruoyao]

On Mon, 2022-10-24 at 22:53 +0800, Huacai Chen wrote:
> > diff --git a/arch/loongarch/include/asm/fpu.h b/arch/loongarch/include/asm/fpu.h
> > index 358b254d9c1d..a5015b6536bc 100644
> > --- a/arch/loongarch/include/asm/fpu.h
> > +++ b/arch/loongarch/include/asm/fpu.h
> > @@ -37,13 +37,13 @@ static inline unsigned long mask_fcsr_x(unsigned long fcsr)
> > 
> >   static inline int is_fp_enabled(void)
> >   {
> > -       return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_FPEN) ?
> > +       return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_FPE) ?
> >                  1 : 0;
> >   }
> > 
> > -#define enable_fpu()           set_csr_euen(CSR_EUEN_FPEN)
> > +#define enable_fpu()           set_csr_euen(CSR_EUEN_FPE)
> I don't think code should be exactly the same as manual, especially
> FPE may be misunderstood as "FP Exception".

If I were naming this field I'd say "CSR_EUEN_FP".  After all "EN" in
"EUEN" already means "enable".

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University