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From: Prabhakar <prabhakar.csengg@gmail.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Conor Dooley <conor.dooley@microchip.com>,
	Guo Ren <guoren@kernel.org>, Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@rivosinc.com>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
Date: Fri, 28 Oct 2022 17:59:21 +0100	[thread overview]
Message-ID: <20221028165921.94487-8-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20221028165921.94487-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable Renesas RZ/Five SoC config in defconfig. It allows the default
upstream kernel to boot on RZ/Five SMARC EVK board.

Alongside enable SERIAL_SH_SCI config so that the serial driver used by
RZ/Five SoC is built-in.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4 -> v5
* No change

v3 -> v4
* Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
  tags with this change)
* Used riscv instead of RISC-V in subject line

v2 -> v3
* Included RB tags
* Updated commit description

v1 -> v2
* New patch
---
 arch/riscv/configs/defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 05fd5fcf24f9..97fba7884d7a 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_SOC_VIRT=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R9A07G043=y
 CONFIG_SMP=y
 CONFIG_HOTPLUG_CPU=y
 CONFIG_PM=y
@@ -123,6 +125,7 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SH_SCI=y
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_VIRTIO=y
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Prabhakar <prabhakar.csengg@gmail.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Conor Dooley <conor.dooley@microchip.com>,
	Guo Ren <guoren@kernel.org>, Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@rivosinc.com>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
Date: Fri, 28 Oct 2022 17:59:21 +0100	[thread overview]
Message-ID: <20221028165921.94487-8-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20221028165921.94487-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable Renesas RZ/Five SoC config in defconfig. It allows the default
upstream kernel to boot on RZ/Five SMARC EVK board.

Alongside enable SERIAL_SH_SCI config so that the serial driver used by
RZ/Five SoC is built-in.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4 -> v5
* No change

v3 -> v4
* Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
  tags with this change)
* Used riscv instead of RISC-V in subject line

v2 -> v3
* Included RB tags
* Updated commit description

v1 -> v2
* New patch
---
 arch/riscv/configs/defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 05fd5fcf24f9..97fba7884d7a 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_SOC_VIRT=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R9A07G043=y
 CONFIG_SMP=y
 CONFIG_HOTPLUG_CPU=y
 CONFIG_PM=y
@@ -123,6 +125,7 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SH_SCI=y
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_VIRTIO=y
-- 
2.25.1


_______________________________________________
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linux-riscv@lists.infradead.org
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  parent reply	other threads:[~2022-10-28 17:01 UTC|newest]

Thread overview: 92+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-28 16:59 [PATCH v5 0/7] Add support for Renesas RZ/Five SoC Prabhakar
2022-10-28 16:59 ` Prabhakar
2022-10-28 16:59 ` [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
2022-10-28 16:59   ` Prabhakar
2022-10-29  4:20   ` Guo Ren
2022-10-29  4:20     ` Guo Ren
2022-10-28 16:59 ` [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
2022-10-28 16:59   ` Prabhakar
2022-10-29  4:20   ` Guo Ren
2022-10-29  4:20     ` Guo Ren
2022-10-28 16:59 ` [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Prabhakar
2022-10-28 16:59   ` Prabhakar
2022-10-29  4:18   ` Guo Ren
2022-10-29  4:18     ` Guo Ren
2022-11-08 15:37   ` Geert Uytterhoeven
2022-11-08 15:37     ` Geert Uytterhoeven
2022-10-28 16:59 ` [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar
2022-10-28 16:59   ` Prabhakar
2022-10-29  4:25   ` Guo Ren
2022-10-29  4:25     ` Guo Ren
2022-10-29 19:10     ` Lad, Prabhakar
2022-10-29 19:10       ` Lad, Prabhakar
2022-10-30  0:02       ` Guo Ren
2022-10-30  0:02         ` Guo Ren
2022-10-30 18:16         ` Conor Dooley
2022-10-30 18:16           ` Conor Dooley
2022-10-30 22:27           ` Lad, Prabhakar
2022-10-30 22:27             ` Lad, Prabhakar
2022-10-30 22:39             ` Conor Dooley
2022-10-30 22:39               ` Conor Dooley
2022-10-31  1:11             ` Guo Ren
2022-10-31  1:11               ` Guo Ren
2022-10-31  0:45           ` Guo Ren
2022-10-31  0:45             ` Guo Ren
2022-10-30 22:23         ` Lad, Prabhakar
2022-10-30 22:23           ` Lad, Prabhakar
2022-11-08 15:43   ` Geert Uytterhoeven
2022-11-08 15:43     ` Geert Uytterhoeven
2022-10-28 16:59 ` [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
2022-10-28 16:59   ` Prabhakar
2022-10-29  4:26   ` Guo Ren
2022-10-29  4:26     ` Guo Ren
2022-10-29 19:14     ` Lad, Prabhakar
2022-10-29 19:14       ` Lad, Prabhakar
2022-11-08 15:44   ` Geert Uytterhoeven
2022-11-08 15:44     ` Geert Uytterhoeven
2022-10-28 16:59 ` [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V Prabhakar
2022-10-28 16:59   ` Prabhakar
2022-10-29  4:27   ` Guo Ren
2022-10-29  4:27     ` Guo Ren
2022-10-28 16:59 ` Prabhakar [this message]
2022-10-28 16:59   ` [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar
2022-10-29  4:28   ` Guo Ren
2022-10-29  4:28     ` Guo Ren
2022-11-08 15:51   ` Geert Uytterhoeven
2022-11-08 15:51     ` Geert Uytterhoeven
2022-11-08 16:06     ` Lad, Prabhakar
2022-11-08 16:06       ` Lad, Prabhakar
2022-11-08 16:12       ` Geert Uytterhoeven
2022-11-08 16:12         ` Geert Uytterhoeven
2022-11-08 17:22         ` Lad, Prabhakar
2022-11-08 17:22           ` Lad, Prabhakar
2022-11-08 19:19           ` Geert Uytterhoeven
2022-11-08 19:19             ` Geert Uytterhoeven
2022-11-08 22:01             ` Lad, Prabhakar
2022-11-08 22:01               ` Lad, Prabhakar
2022-11-09  7:46               ` Geert Uytterhoeven
2022-11-09  7:46                 ` Geert Uytterhoeven
2022-11-09  9:16                 ` Lad, Prabhakar
2022-11-09  9:16                   ` Lad, Prabhakar
2022-10-30 18:24 ` [PATCH v5 0/7] Add support for " Conor Dooley
2022-10-30 18:24   ` Conor Dooley
2022-10-30 22:37   ` Lad, Prabhakar
2022-10-30 22:37     ` Lad, Prabhakar
2022-10-30 22:45     ` Conor Dooley
2022-10-30 22:45       ` Conor Dooley
2022-10-30 23:01       ` Lad, Prabhakar
2022-10-30 23:01         ` Lad, Prabhakar
2022-11-07 18:03         ` Lad, Prabhakar
2022-11-07 18:03           ` Lad, Prabhakar
2022-11-07 18:17           ` Conor Dooley
2022-11-07 18:17             ` Conor Dooley
2022-11-08 16:02             ` Geert Uytterhoeven
2022-11-08 16:02               ` Geert Uytterhoeven
2022-11-08 19:29               ` Conor Dooley
2022-11-08 19:29                 ` Conor Dooley
2022-11-09 19:55 ` Palmer Dabbelt
2022-11-09 19:55   ` Palmer Dabbelt
2022-11-09 21:21   ` Conor Dooley
2022-11-09 21:21     ` Conor Dooley
2022-11-10 16:17     ` Geert Uytterhoeven
2022-11-10 16:17       ` Geert Uytterhoeven

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