* Re: [PATCH v7 2/2] arm64: dts: qcom: add SA8540P ride(Qdrive-3)
2022-11-02 10:35 ` [PATCH v7 2/2] arm64: dts: qcom: add SA8540P ride(Qdrive-3) Parikshit Pareek
@ 2022-11-02 18:40 ` Eric Chanudet
2022-11-02 18:58 ` Krzysztof Kozlowski
2022-11-02 19:57 ` Andrew Halaney
2 siblings, 0 replies; 6+ messages in thread
From: Eric Chanudet @ 2022-11-02 18:40 UTC (permalink / raw)
To: Parikshit Pareek
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel,
Andrew Halaney, Shazad Hussain, Brian Masney, Johan Hovold
On Wed, Nov 02, 2022 at 04:05:52PM +0530, Parikshit Pareek wrote:
> Introduce the Qualcomm SA8540P ride automotive platform, also known as
> Qdrive-3 development board.
>
> This initial contribution supports SMP, CPUFreq, cluster idle, UFS, RPMh
> regulators, debug UART, PMICs, remoteprocs and USB.
>
> The SA8540P ride contains four PM8450 PMICs. A separate DTSI file has
> been created for PMIC, so that it can be used for future SA8540P based
> boards.
>
> Signed-off-by: Parikshit Pareek <quic_ppareek@quicinc.com>
> Tested-by: Brian Masney <bmasney@redhat.com>
> Reviewed-by: Brian Masney <bmasney@redhat.com>
Using the default defconfig on next-20221102, preventing
qcom_q6v5_pas.ko to load avoids the board crash observed in v5, as
found during v6 review by Brian.
Tested-by: Eric Chanudet <echanude@redhat.com>
Reviewed-by: Eric Chanudet <echanude@redhat.com>
--
Eric Chanudet
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v7 2/2] arm64: dts: qcom: add SA8540P ride(Qdrive-3)
2022-11-02 10:35 ` [PATCH v7 2/2] arm64: dts: qcom: add SA8540P ride(Qdrive-3) Parikshit Pareek
2022-11-02 18:40 ` Eric Chanudet
@ 2022-11-02 18:58 ` Krzysztof Kozlowski
2022-11-02 19:57 ` Andrew Halaney
2 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 18:58 UTC (permalink / raw)
To: Parikshit Pareek, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Andrew Halaney,
Shazad Hussain, Brian Masney, Johan Hovold
On 02/11/2022 06:35, Parikshit Pareek wrote:
> Introduce the Qualcomm SA8540P ride automotive platform, also known as
> Qdrive-3 development board.
>
> This initial contribution supports SMP, CPUFreq, cluster idle, UFS, RPMh
> regulators, debug UART, PMICs, remoteprocs and USB.
>
> The SA8540P ride contains four PM8450 PMICs. A separate DTSI file has
> been created for PMIC, so that it can be used for future SA8540P based
> boards.
>
> Signed-off-by: Parikshit Pareek <quic_ppareek@quicinc.com>
> Tested-by: Brian Masney <bmasney@redhat.com>
> Reviewed-by: Brian Masney <bmasney@redhat.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/pm8450a.dtsi | 77 ++++++++
> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 227 ++++++++++++++++++++++
> 3 files changed, 305 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/pm8450a.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/sa8540p-ride.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index b0558d3389e5..c89d44756791 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
> diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
> new file mode 100644
> index 000000000000..34fc72896761
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Linaro Limited
> + */
> +
> +#include <dt-bindings/spmi/spmi.h>
> +
> +&spmi_bus {
> + pm8450a: pmic@0 {
> + compatible = "qcom,pm8150", "qcom,spmi-pmic";
> + reg = <0x0 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8450a_gpios: gpio@c000 {
> + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + gpio-ranges = <&pm8450a_gpios 0 0 10>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + pm8450c: pmic@4 {
> + compatible = "qcom,pm8150", "qcom,spmi-pmic";
> + reg = <0x4 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8450c_gpios: gpio@c000 {
> + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + gpio-ranges = <&pm8450c_gpios 0 0 10>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + pm8450e: pmic@8 {
> + compatible = "qcom,pm8150", "qcom,spmi-pmic";
> + reg = <0x8 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8450e_gpios: gpio@c000 {
> + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + gpio-ranges = <&pm8450e_gpios 0 0 10>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + pm8450g: pmic@c {
> + compatible = "qcom,pm8150", "qcom,spmi-pmic";
> + reg = <0xc SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8450g_gpios: gpio@c000 {
> + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + gpio-ranges = <&pm8450g_gpios 0 0 10>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> new file mode 100644
> index 000000000000..b480b4927549
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> @@ -0,0 +1,227 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Linaro Limited
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +
> +#include "sa8540p.dtsi"
> +#include "pm8450a.dtsi"
> +
> +/ {
> + model = "Qualcomm SA8540P Ride";
> + compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
> +
> + aliases {
> + serial0 = &qup2_uart17;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&apps_rsc {
> + pmm8540-a-regulators {
I expect schema to be changed like that:
https://lore.kernel.org/linux-devicetree/ad1d4135-031e-9393-07af-7b81c9ecffb5@linaro.org/
thus I am not sure if it is worth adding something which is going to be
changed soon...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v7 2/2] arm64: dts: qcom: add SA8540P ride(Qdrive-3)
2022-11-02 10:35 ` [PATCH v7 2/2] arm64: dts: qcom: add SA8540P ride(Qdrive-3) Parikshit Pareek
2022-11-02 18:40 ` Eric Chanudet
2022-11-02 18:58 ` Krzysztof Kozlowski
@ 2022-11-02 19:57 ` Andrew Halaney
2 siblings, 0 replies; 6+ messages in thread
From: Andrew Halaney @ 2022-11-02 19:57 UTC (permalink / raw)
To: Parikshit Pareek
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel,
Shazad Hussain, Brian Masney, Johan Hovold
On Wed, Nov 02, 2022 at 04:05:52PM +0530, Parikshit Pareek wrote:
> Introduce the Qualcomm SA8540P ride automotive platform, also known as
> Qdrive-3 development board.
>
> This initial contribution supports SMP, CPUFreq, cluster idle, UFS, RPMh
> regulators, debug UART, PMICs, remoteprocs and USB.
>
> The SA8540P ride contains four PM8450 PMICs. A separate DTSI file has
> been created for PMIC, so that it can be used for future SA8540P based
> boards.
>
> Signed-off-by: Parikshit Pareek <quic_ppareek@quicinc.com>
> Tested-by: Brian Masney <bmasney@redhat.com>
> Reviewed-by: Brian Masney <bmasney@redhat.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/pm8450a.dtsi | 77 ++++++++
> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 227 ++++++++++++++++++++++
> 3 files changed, 305 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/pm8450a.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/sa8540p-ride.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index b0558d3389e5..c89d44756791 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
> diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
> new file mode 100644
> index 000000000000..34fc72896761
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Linaro Limited
> + */
> +
> +#include <dt-bindings/spmi/spmi.h>
> +
> +&spmi_bus {
> + pm8450a: pmic@0 {
> + compatible = "qcom,pm8150", "qcom,spmi-pmic";
> + reg = <0x0 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8450a_gpios: gpio@c000 {
> + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + gpio-ranges = <&pm8450a_gpios 0 0 10>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + pm8450c: pmic@4 {
> + compatible = "qcom,pm8150", "qcom,spmi-pmic";
> + reg = <0x4 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8450c_gpios: gpio@c000 {
> + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + gpio-ranges = <&pm8450c_gpios 0 0 10>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + pm8450e: pmic@8 {
> + compatible = "qcom,pm8150", "qcom,spmi-pmic";
> + reg = <0x8 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8450e_gpios: gpio@c000 {
> + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + gpio-ranges = <&pm8450e_gpios 0 0 10>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + pm8450g: pmic@c {
> + compatible = "qcom,pm8150", "qcom,spmi-pmic";
> + reg = <0xc SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8450g_gpios: gpio@c000 {
> + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + gpio-ranges = <&pm8450g_gpios 0 0 10>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> new file mode 100644
> index 000000000000..b480b4927549
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> @@ -0,0 +1,227 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Linaro Limited
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +
> +#include "sa8540p.dtsi"
> +#include "pm8450a.dtsi"
> +
> +/ {
> + model = "Qualcomm SA8540P Ride";
> + compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
> +
> + aliases {
> + serial0 = &qup2_uart17;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&apps_rsc {
> + pmm8540-a-regulators {
> + compatible = "qcom,pm8150-rpmh-regulators";
> + qcom,pmic-id = "a";
> +
> + vreg_l3a: ldo3 {
> + regulator-name = "vreg_l3a";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1208000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l5a: ldo5 {
> + regulator-name = "vreg_l5a";
> + regulator-min-microvolt = <912000>;
> + regulator-max-microvolt = <912000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l7a: ldo7 {
> + regulator-name = "vreg_l7a";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l13a: ldo13 {
> + regulator-name = "vreg_l13a";
> + regulator-min-microvolt = <3072000>;
> + regulator-max-microvolt = <3072000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + pmm8540-c-regulators {
> + compatible = "qcom,pm8150-rpmh-regulators";
> + qcom,pmic-id = "c";
> +
> + vreg_l1c: ldo1 {
> + regulator-name = "vreg_l1c";
> + regulator-min-microvolt = <912000>;
> + regulator-max-microvolt = <912000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l2c: ldo2 {
> + regulator-name = "vreg_l2c";
> + regulator-min-microvolt = <3072000>;
> + regulator-max-microvolt = <3072000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l4c: ldo4 {
> + regulator-name = "vreg_l4c";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1208000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l6c: ldo6 {
> + regulator-name = "vreg_l6c";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allowed-modes =
> + <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + };
> +
> + vreg_l7c: ldo7 {
> + regulator-name = "vreg_l7c";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l17c: ldo17 {
> + regulator-name = "vreg_l17c";
> + regulator-min-microvolt = <2504000>;
> + regulator-max-microvolt = <2504000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allowed-modes =
> + <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + };
> + };
> +
> + pmm8540-g-regulators {
> + compatible = "qcom,pm8150-rpmh-regulators";
> + qcom,pmic-id = "g";
> +
> + vreg_l3g: ldo3 {
> + regulator-name = "vreg_l3g";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l7g: ldo7 {
> + regulator-name = "vreg_l7g";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l8g: ldo8 {
> + regulator-name = "vreg_l8g";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <880000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +};
> +
> +&qup2 {
> + status = "okay";
> +};
> +
> +&qup2_uart17 {
> + compatible = "qcom,geni-debug-uart";
> + status = "okay";
> +};
> +
> +&remoteproc_adsp {
> + firmware-name = "qcom/sa8540p/adsp.mbn";
> + status = "okay";
Is this actually on the SoC? I thought I had heard it was not.
> +};
> +
> +&remoteproc_nsp0 {
> + firmware-name = "qcom/sa8540p/cdsp.mbn";
> + status = "okay";
> +};
> +
> +&remoteproc_nsp1 {
> + firmware-name = "qcom/sa8540p/cdsp1.mbn";
> + status = "okay";
> +};
> +
> +&ufs_mem_hc {
> + reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
> +
> + vcc-supply = <&vreg_l17c>;
> + vcc-max-microamp = <800000>;
> + vccq-supply = <&vreg_l6c>;
> + vccq-max-microamp = <900000>;
> +
> + status = "okay";
> +};
> +
> +&ufs_mem_phy {
> + vdda-phy-supply = <&vreg_l8g>;
> + vdda-pll-supply = <&vreg_l3g>;
> +
> + status = "okay";
> +};
> +
> +&usb_0 {
> + status = "okay";
> +};
> +
> +&usb_0_dwc3 {
> + /* TODO: Define USB-C connector properly */
Is this really TODO? It seems like copy-pasta from other
dts's.
> + dr_mode = "peripheral";
> +};
> +
> +&usb_0_hsphy {
> + vdda-pll-supply = <&vreg_l5a>;
> + vdda18-supply = <&vreg_l7a>;
> + vdda33-supply = <&vreg_l13a>;
> +
> + status = "okay";
> +};
> +
> +&usb_0_qmpphy {
> + vdda-phy-supply = <&vreg_l3a>;
> + vdda-pll-supply = <&vreg_l5a>;
> +
> + status = "okay";
> +};
> +
> +&usb_2_hsphy0 {
> + vdda-pll-supply = <&vreg_l5a>;
> + vdda18-supply = <&vreg_l7g>;
> + vdda33-supply = <&vreg_l13a>;
> +
> + status = "okay";
> +};
> +
> +&usb_2_qmpphy0 {
> + vdda-phy-supply = <&vreg_l3a>;
> + vdda-pll-supply = <&vreg_l5a>;
> +
> + status = "okay";
> +};
> +
> +&xo_board_clk {
> + clock-frequency = <38400000>;
> +};
> --
> 2.17.1
>
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