* [Intel-gfx] [PATCH v2 0/5] drm/i915: Introduce the GSC CS
@ 2022-11-02 17:10 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 20+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-11-02 17:10 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
Starting on MTL, the GSC microcontroller resides inside the media GT
and the driver can communicate with it via a new Command Streamer, the
GSC CS. As a first step in supporting the GSC integration within the
media GT, this series adds the required defines and basic support for
this CS. Note that, given that the only user of this CS is i915 itself,
we don't need to expose it to userspace.
The CS has been purposely not added to the engine mask for MTL yet,
because it is only used in conjunction with the GSC FW, so there is
nothing we can do with it until we add support for the FW, which will
come as a separate next step.
v2: clean up interrupt code and rename GSC engine
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Daniele Ceraolo Spurio (5):
drm/i915/mtl: add initial definitions for GSC CS
drm/i915/mtl: pass the GSC CS info to the GuC
drm/i915/mtl: add GSC CS interrupt support
drm/i915/mtl: add GSC CS reset support
drm/i915/mtl: don't expose GSC command streamer to the user
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_engine_user.c | 28 ++++++--
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 75 +++++++++++---------
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 11 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 7 +-
drivers/gpu/drm/i915/i915_reg.h | 1 +
8 files changed, 84 insertions(+), 49 deletions(-)
--
2.37.3
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 1/5] drm/i915/mtl: add initial definitions for GSC CS
2022-11-02 17:10 ` [Intel-gfx] " Daniele Ceraolo Spurio
@ 2022-11-02 17:10 ` Daniele Ceraolo Spurio
-1 siblings, 0 replies; 20+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-11-02 17:10 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Starting on MTL, the GSC is no longer managed with direct MMIO access,
but we instead have a dedicated command streamer for it. As a first step
for adding support for this CS, add the required definitions.
Note that, although it is now a CS, the GSC retains its old
class:instance value (OTHER_CLASS instance 6)
Bspec: 65308, 45605
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 ++++++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3b7d750ad054..e0fbfac03979 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
}
},
+ [GSC0] = {
+ .class = OTHER_CLASS,
+ .instance = OTHER_GSC_INSTANCE,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
+ }
+ },
};
/**
@@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
case VIDEO_DECODE_CLASS:
case VIDEO_ENHANCEMENT_CLASS:
case COPY_ENGINE_CLASS:
+ case OTHER_CLASS:
if (GRAPHICS_VER(gt->i915) < 8)
return 0;
return GEN8_LR_CONTEXT_OTHER_SIZE;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 6b5d4ea22b67..4fd54fb8810f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -136,6 +136,7 @@ enum intel_engine_id {
CCS2,
CCS3,
#define _CCS(n) (CCS0 + (n))
+ GSC0,
I915_NUM_ENGINES
#define INVALID_ENGINE ((enum intel_engine_id)-1)
};
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 46a174f8aa00..79312b734690 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
[COPY_ENGINE_CLASS] = "bcs",
[VIDEO_DECODE_CLASS] = "vcs",
[VIDEO_ENHANCEMENT_CLASS] = "vecs",
+ [OTHER_CLASS] = "other",
[COMPUTE_CLASS] = "ccs",
};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c0da50c0dc7..d056c3117ef2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -970,6 +970,7 @@
#define GEN11_VEBOX2_RING_BASE 0x1d8000
#define XEHP_VEBOX3_RING_BASE 0x1e8000
#define XEHP_VEBOX4_RING_BASE 0x1f8000
+#define MTL_GSC_RING_BASE 0x11a000
#define GEN12_COMPUTE0_RING_BASE 0x1a000
#define GEN12_COMPUTE1_RING_BASE 0x1c000
#define GEN12_COMPUTE2_RING_BASE 0x1e000
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 1/5] drm/i915/mtl: add initial definitions for GSC CS
@ 2022-11-02 17:10 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 20+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-11-02 17:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniele Ceraolo Spurio, dri-devel
Starting on MTL, the GSC is no longer managed with direct MMIO access,
but we instead have a dedicated command streamer for it. As a first step
for adding support for this CS, add the required definitions.
Note that, although it is now a CS, the GSC retains its old
class:instance value (OTHER_CLASS instance 6)
Bspec: 65308, 45605
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 ++++++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3b7d750ad054..e0fbfac03979 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
}
},
+ [GSC0] = {
+ .class = OTHER_CLASS,
+ .instance = OTHER_GSC_INSTANCE,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
+ }
+ },
};
/**
@@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
case VIDEO_DECODE_CLASS:
case VIDEO_ENHANCEMENT_CLASS:
case COPY_ENGINE_CLASS:
+ case OTHER_CLASS:
if (GRAPHICS_VER(gt->i915) < 8)
return 0;
return GEN8_LR_CONTEXT_OTHER_SIZE;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 6b5d4ea22b67..4fd54fb8810f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -136,6 +136,7 @@ enum intel_engine_id {
CCS2,
CCS3,
#define _CCS(n) (CCS0 + (n))
+ GSC0,
I915_NUM_ENGINES
#define INVALID_ENGINE ((enum intel_engine_id)-1)
};
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 46a174f8aa00..79312b734690 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
[COPY_ENGINE_CLASS] = "bcs",
[VIDEO_DECODE_CLASS] = "vcs",
[VIDEO_ENHANCEMENT_CLASS] = "vecs",
+ [OTHER_CLASS] = "other",
[COMPUTE_CLASS] = "ccs",
};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c0da50c0dc7..d056c3117ef2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -970,6 +970,7 @@
#define GEN11_VEBOX2_RING_BASE 0x1d8000
#define XEHP_VEBOX3_RING_BASE 0x1e8000
#define XEHP_VEBOX4_RING_BASE 0x1f8000
+#define MTL_GSC_RING_BASE 0x11a000
#define GEN12_COMPUTE0_RING_BASE 0x1a000
#define GEN12_COMPUTE1_RING_BASE 0x1c000
#define GEN12_COMPUTE2_RING_BASE 0x1e000
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/5] drm/i915/mtl: pass the GSC CS info to the GuC
2022-11-02 17:10 ` [Intel-gfx] " Daniele Ceraolo Spurio
@ 2022-11-02 17:10 ` Daniele Ceraolo Spurio
-1 siblings, 0 replies; 20+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-11-02 17:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniele Ceraolo Spurio, dri-devel
We need to tell the GuC that the GSC CS is there.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 11 +++++------
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 7 +++++--
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index a419d60166c8..a7f737c4792e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -488,6 +488,11 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], BCS_MASK(gt));
info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
+
+ /* The GSC engine is an instance (6) of OTHER_CLASS */
+ if (gt->engine[GSC0])
+ info_map_write(info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
+ BIT(gt->engine[GSC0]->instance));
}
#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
@@ -529,9 +534,6 @@ static int guc_prep_golden_context(struct intel_guc *guc)
}
for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
- if (engine_class == OTHER_CLASS)
- continue;
-
guc_class = engine_class_to_guc_class(engine_class);
if (!info_map_read(&info_map, engine_enabled_masks[guc_class]))
@@ -609,9 +611,6 @@ static void guc_init_golden_context(struct intel_guc *guc)
addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
- if (engine_class == OTHER_CLASS)
- continue;
-
guc_class = engine_class_to_guc_class(engine_class);
if (!ads_blob_read(guc, system_info.engine_enabled_masks[guc_class]))
continue;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 968ebd79dce7..4ae5fc2f6002 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -47,7 +47,8 @@
#define GUC_VIDEOENHANCE_CLASS 2
#define GUC_BLITTER_CLASS 3
#define GUC_COMPUTE_CLASS 4
-#define GUC_LAST_ENGINE_CLASS GUC_COMPUTE_CLASS
+#define GUC_GSC_OTHER_CLASS 5
+#define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS
#define GUC_MAX_ENGINE_CLASSES 16
#define GUC_MAX_INSTANCES_PER_CLASS 32
@@ -169,6 +170,7 @@ static u8 engine_class_guc_class_map[] = {
[COPY_ENGINE_CLASS] = GUC_BLITTER_CLASS,
[VIDEO_DECODE_CLASS] = GUC_VIDEO_CLASS,
[VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,
+ [OTHER_CLASS] = GUC_GSC_OTHER_CLASS,
[COMPUTE_CLASS] = GUC_COMPUTE_CLASS,
};
@@ -178,12 +180,13 @@ static u8 guc_class_engine_class_map[] = {
[GUC_VIDEO_CLASS] = VIDEO_DECODE_CLASS,
[GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,
[GUC_COMPUTE_CLASS] = COMPUTE_CLASS,
+ [GUC_GSC_OTHER_CLASS] = OTHER_CLASS,
};
static inline u8 engine_class_to_guc_class(u8 class)
{
BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1);
- GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
+ GEM_BUG_ON(class > MAX_ENGINE_CLASS);
return engine_class_guc_class_map[class];
}
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH v2 2/5] drm/i915/mtl: pass the GSC CS info to the GuC
@ 2022-11-02 17:10 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 20+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-11-02 17:10 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
We need to tell the GuC that the GSC CS is there.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 11 +++++------
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 7 +++++--
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index a419d60166c8..a7f737c4792e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -488,6 +488,11 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], BCS_MASK(gt));
info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
+
+ /* The GSC engine is an instance (6) of OTHER_CLASS */
+ if (gt->engine[GSC0])
+ info_map_write(info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
+ BIT(gt->engine[GSC0]->instance));
}
#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
@@ -529,9 +534,6 @@ static int guc_prep_golden_context(struct intel_guc *guc)
}
for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
- if (engine_class == OTHER_CLASS)
- continue;
-
guc_class = engine_class_to_guc_class(engine_class);
if (!info_map_read(&info_map, engine_enabled_masks[guc_class]))
@@ -609,9 +611,6 @@ static void guc_init_golden_context(struct intel_guc *guc)
addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
- if (engine_class == OTHER_CLASS)
- continue;
-
guc_class = engine_class_to_guc_class(engine_class);
if (!ads_blob_read(guc, system_info.engine_enabled_masks[guc_class]))
continue;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 968ebd79dce7..4ae5fc2f6002 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -47,7 +47,8 @@
#define GUC_VIDEOENHANCE_CLASS 2
#define GUC_BLITTER_CLASS 3
#define GUC_COMPUTE_CLASS 4
-#define GUC_LAST_ENGINE_CLASS GUC_COMPUTE_CLASS
+#define GUC_GSC_OTHER_CLASS 5
+#define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS
#define GUC_MAX_ENGINE_CLASSES 16
#define GUC_MAX_INSTANCES_PER_CLASS 32
@@ -169,6 +170,7 @@ static u8 engine_class_guc_class_map[] = {
[COPY_ENGINE_CLASS] = GUC_BLITTER_CLASS,
[VIDEO_DECODE_CLASS] = GUC_VIDEO_CLASS,
[VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,
+ [OTHER_CLASS] = GUC_GSC_OTHER_CLASS,
[COMPUTE_CLASS] = GUC_COMPUTE_CLASS,
};
@@ -178,12 +180,13 @@ static u8 guc_class_engine_class_map[] = {
[GUC_VIDEO_CLASS] = VIDEO_DECODE_CLASS,
[GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,
[GUC_COMPUTE_CLASS] = COMPUTE_CLASS,
+ [GUC_GSC_OTHER_CLASS] = OTHER_CLASS,
};
static inline u8 engine_class_to_guc_class(u8 class)
{
BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1);
- GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
+ GEM_BUG_ON(class > MAX_ENGINE_CLASS);
return engine_class_guc_class_map[class];
}
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/5] drm/i915/mtl: add GSC CS interrupt support
2022-11-02 17:10 ` [Intel-gfx] " Daniele Ceraolo Spurio
@ 2022-11-02 17:10 ` Daniele Ceraolo Spurio
-1 siblings, 0 replies; 20+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-11-02 17:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Tvrtko Ursulin, Daniele Ceraolo Spurio, dri-devel
The GSC CS re-uses the same interrupt bits that the GSC used in older
platforms. This means that we can now have an engine interrupt coming
out of OTHER_CLASS, so we need to handle that appropriately.
v2: clean up the if statement for the engine irq (Tvrtko)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com> #v1
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 75 ++++++++++++++------------
1 file changed, 40 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f26882fdc24c..b197f0e9794f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
instance, iir);
}
-static void
-gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
- const u8 instance, const u16 iir)
+static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
{
- struct intel_engine_cs *engine;
-
- /*
- * Platforms with standalone media have their media engines in another
- * GT.
- */
- if (MEDIA_VER(gt->i915) >= 13 &&
- (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
- if (!gt->i915->media_gt)
- goto err;
+ struct intel_gt *media_gt = gt->i915->media_gt;
- gt = gt->i915->media_gt;
+ /* we expect the non-media gt to be passed in */
+ GEM_BUG_ON(gt == media_gt);
+
+ if (!media_gt)
+ return gt;
+
+ switch (class) {
+ case VIDEO_DECODE_CLASS:
+ case VIDEO_ENHANCEMENT_CLASS:
+ return media_gt;
+ case OTHER_CLASS:
+ if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
+ return media_gt;
+ fallthrough;
+ default:
+ return gt;
}
-
- if (instance <= MAX_ENGINE_INSTANCE)
- engine = gt->engine_class[class][instance];
- else
- engine = NULL;
-
- if (likely(engine))
- return intel_engine_cs_irq(engine, iir);
-
-err:
- WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
- class, instance);
}
static void
@@ -122,8 +114,17 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
if (unlikely(!intr))
return;
- if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
- return gen11_engine_irq_handler(gt, class, instance, intr);
+ /*
+ * Platforms with standalone media have the media and GSC engines in
+ * another GT.
+ */
+ gt = pick_gt(gt, class, instance);
+
+ if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) {
+ struct intel_engine_cs *engine = gt->engine_class[class][instance];
+ if (engine)
+ return intel_engine_cs_irq(engine, intr);
+ }
if (class == OTHER_CLASS)
return gen11_other_irq_handler(gt, instance, intr);
@@ -206,7 +207,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
if (CCS_MASK(gt))
intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
- if (HAS_HECI_GSC(gt->i915))
+ if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
@@ -233,7 +234,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
- if (HAS_HECI_GSC(gt->i915))
+ if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
@@ -249,7 +250,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
u32 irqs = GT_RENDER_USER_INTERRUPT;
- const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+ u32 gsc_mask = 0;
u32 dmask;
u32 smask;
@@ -261,6 +262,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
dmask = irqs << 16 | irqs;
smask = irqs << 16;
+ if (HAS_ENGINE(gt, GSC0))
+ gsc_mask = irqs;
+ else if (HAS_HECI_GSC(gt->i915))
+ gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+
BUILD_BUG_ON(irqs & 0xffff0000);
/* Enable RCS, BCS, VCS and VECS class interrupts. */
@@ -268,9 +274,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
if (CCS_MASK(gt))
intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
- if (HAS_HECI_GSC(gt->i915))
- intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
- gsc_mask);
+ if (gsc_mask)
+ intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
@@ -296,7 +301,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
- if (HAS_HECI_GSC(gt->i915))
+ if (gsc_mask)
intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
/*
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH v2 3/5] drm/i915/mtl: add GSC CS interrupt support
@ 2022-11-02 17:10 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 20+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-11-02 17:10 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
The GSC CS re-uses the same interrupt bits that the GSC used in older
platforms. This means that we can now have an engine interrupt coming
out of OTHER_CLASS, so we need to handle that appropriately.
v2: clean up the if statement for the engine irq (Tvrtko)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com> #v1
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 75 ++++++++++++++------------
1 file changed, 40 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f26882fdc24c..b197f0e9794f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
instance, iir);
}
-static void
-gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
- const u8 instance, const u16 iir)
+static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
{
- struct intel_engine_cs *engine;
-
- /*
- * Platforms with standalone media have their media engines in another
- * GT.
- */
- if (MEDIA_VER(gt->i915) >= 13 &&
- (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
- if (!gt->i915->media_gt)
- goto err;
+ struct intel_gt *media_gt = gt->i915->media_gt;
- gt = gt->i915->media_gt;
+ /* we expect the non-media gt to be passed in */
+ GEM_BUG_ON(gt == media_gt);
+
+ if (!media_gt)
+ return gt;
+
+ switch (class) {
+ case VIDEO_DECODE_CLASS:
+ case VIDEO_ENHANCEMENT_CLASS:
+ return media_gt;
+ case OTHER_CLASS:
+ if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
+ return media_gt;
+ fallthrough;
+ default:
+ return gt;
}
-
- if (instance <= MAX_ENGINE_INSTANCE)
- engine = gt->engine_class[class][instance];
- else
- engine = NULL;
-
- if (likely(engine))
- return intel_engine_cs_irq(engine, iir);
-
-err:
- WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
- class, instance);
}
static void
@@ -122,8 +114,17 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
if (unlikely(!intr))
return;
- if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
- return gen11_engine_irq_handler(gt, class, instance, intr);
+ /*
+ * Platforms with standalone media have the media and GSC engines in
+ * another GT.
+ */
+ gt = pick_gt(gt, class, instance);
+
+ if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) {
+ struct intel_engine_cs *engine = gt->engine_class[class][instance];
+ if (engine)
+ return intel_engine_cs_irq(engine, intr);
+ }
if (class == OTHER_CLASS)
return gen11_other_irq_handler(gt, instance, intr);
@@ -206,7 +207,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
if (CCS_MASK(gt))
intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
- if (HAS_HECI_GSC(gt->i915))
+ if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
@@ -233,7 +234,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
- if (HAS_HECI_GSC(gt->i915))
+ if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
@@ -249,7 +250,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
u32 irqs = GT_RENDER_USER_INTERRUPT;
- const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+ u32 gsc_mask = 0;
u32 dmask;
u32 smask;
@@ -261,6 +262,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
dmask = irqs << 16 | irqs;
smask = irqs << 16;
+ if (HAS_ENGINE(gt, GSC0))
+ gsc_mask = irqs;
+ else if (HAS_HECI_GSC(gt->i915))
+ gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+
BUILD_BUG_ON(irqs & 0xffff0000);
/* Enable RCS, BCS, VCS and VECS class interrupts. */
@@ -268,9 +274,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
if (CCS_MASK(gt))
intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
- if (HAS_HECI_GSC(gt->i915))
- intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
- gsc_mask);
+ if (gsc_mask)
+ intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
@@ -296,7 +301,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
- if (HAS_HECI_GSC(gt->i915))
+ if (gsc_mask)
intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
/*
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 3/5] drm/i915/mtl: add GSC CS interrupt support
2022-11-02 17:10 ` [Intel-gfx] " Daniele Ceraolo Spurio
@ 2022-11-07 18:32 ` Matt Roper
-1 siblings, 0 replies; 20+ messages in thread
From: Matt Roper @ 2022-11-07 18:32 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Tvrtko Ursulin, intel-gfx, dri-devel
On Wed, Nov 02, 2022 at 10:10:45AM -0700, Daniele Ceraolo Spurio wrote:
> The GSC CS re-uses the same interrupt bits that the GSC used in older
> platforms. This means that we can now have an engine interrupt coming
> out of OTHER_CLASS, so we need to handle that appropriately.
>
> v2: clean up the if statement for the engine irq (Tvrtko)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> #v1
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
for v2 as well.
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 75 ++++++++++++++------------
> 1 file changed, 40 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index f26882fdc24c..b197f0e9794f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
> instance, iir);
> }
>
> -static void
> -gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
> - const u8 instance, const u16 iir)
> +static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
> {
> - struct intel_engine_cs *engine;
> -
> - /*
> - * Platforms with standalone media have their media engines in another
> - * GT.
> - */
> - if (MEDIA_VER(gt->i915) >= 13 &&
> - (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
> - if (!gt->i915->media_gt)
> - goto err;
> + struct intel_gt *media_gt = gt->i915->media_gt;
>
> - gt = gt->i915->media_gt;
> + /* we expect the non-media gt to be passed in */
> + GEM_BUG_ON(gt == media_gt);
> +
> + if (!media_gt)
> + return gt;
> +
> + switch (class) {
> + case VIDEO_DECODE_CLASS:
> + case VIDEO_ENHANCEMENT_CLASS:
> + return media_gt;
> + case OTHER_CLASS:
> + if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
> + return media_gt;
> + fallthrough;
> + default:
> + return gt;
> }
> -
> - if (instance <= MAX_ENGINE_INSTANCE)
> - engine = gt->engine_class[class][instance];
> - else
> - engine = NULL;
> -
> - if (likely(engine))
> - return intel_engine_cs_irq(engine, iir);
> -
> -err:
> - WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
> - class, instance);
> }
>
> static void
> @@ -122,8 +114,17 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
> if (unlikely(!intr))
> return;
>
> - if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
> - return gen11_engine_irq_handler(gt, class, instance, intr);
> + /*
> + * Platforms with standalone media have the media and GSC engines in
> + * another GT.
> + */
> + gt = pick_gt(gt, class, instance);
> +
> + if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) {
> + struct intel_engine_cs *engine = gt->engine_class[class][instance];
> + if (engine)
> + return intel_engine_cs_irq(engine, intr);
> + }
>
> if (class == OTHER_CLASS)
> return gen11_other_irq_handler(gt, instance, intr);
> @@ -206,7 +207,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
> if (CCS_MASK(gt))
> intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
> - if (HAS_HECI_GSC(gt->i915))
> + if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
> intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
>
> /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> @@ -233,7 +234,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
> if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
> intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
> - if (HAS_HECI_GSC(gt->i915))
> + if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
> intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
>
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
> @@ -249,7 +250,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> {
> struct intel_uncore *uncore = gt->uncore;
> u32 irqs = GT_RENDER_USER_INTERRUPT;
> - const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
> + u32 gsc_mask = 0;
> u32 dmask;
> u32 smask;
>
> @@ -261,6 +262,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> dmask = irqs << 16 | irqs;
> smask = irqs << 16;
>
> + if (HAS_ENGINE(gt, GSC0))
> + gsc_mask = irqs;
> + else if (HAS_HECI_GSC(gt->i915))
> + gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
> +
> BUILD_BUG_ON(irqs & 0xffff0000);
>
> /* Enable RCS, BCS, VCS and VECS class interrupts. */
> @@ -268,9 +274,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
> if (CCS_MASK(gt))
> intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
> - if (HAS_HECI_GSC(gt->i915))
> - intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
> - gsc_mask);
> + if (gsc_mask)
> + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
>
> /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
> @@ -296,7 +301,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
> if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
> intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
> - if (HAS_HECI_GSC(gt->i915))
> + if (gsc_mask)
> intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
>
> /*
> --
> 2.37.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH v2 3/5] drm/i915/mtl: add GSC CS interrupt support
@ 2022-11-07 18:32 ` Matt Roper
0 siblings, 0 replies; 20+ messages in thread
From: Matt Roper @ 2022-11-07 18:32 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, dri-devel
On Wed, Nov 02, 2022 at 10:10:45AM -0700, Daniele Ceraolo Spurio wrote:
> The GSC CS re-uses the same interrupt bits that the GSC used in older
> platforms. This means that we can now have an engine interrupt coming
> out of OTHER_CLASS, so we need to handle that appropriately.
>
> v2: clean up the if statement for the engine irq (Tvrtko)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> #v1
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
for v2 as well.
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 75 ++++++++++++++------------
> 1 file changed, 40 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index f26882fdc24c..b197f0e9794f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
> instance, iir);
> }
>
> -static void
> -gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
> - const u8 instance, const u16 iir)
> +static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
> {
> - struct intel_engine_cs *engine;
> -
> - /*
> - * Platforms with standalone media have their media engines in another
> - * GT.
> - */
> - if (MEDIA_VER(gt->i915) >= 13 &&
> - (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
> - if (!gt->i915->media_gt)
> - goto err;
> + struct intel_gt *media_gt = gt->i915->media_gt;
>
> - gt = gt->i915->media_gt;
> + /* we expect the non-media gt to be passed in */
> + GEM_BUG_ON(gt == media_gt);
> +
> + if (!media_gt)
> + return gt;
> +
> + switch (class) {
> + case VIDEO_DECODE_CLASS:
> + case VIDEO_ENHANCEMENT_CLASS:
> + return media_gt;
> + case OTHER_CLASS:
> + if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
> + return media_gt;
> + fallthrough;
> + default:
> + return gt;
> }
> -
> - if (instance <= MAX_ENGINE_INSTANCE)
> - engine = gt->engine_class[class][instance];
> - else
> - engine = NULL;
> -
> - if (likely(engine))
> - return intel_engine_cs_irq(engine, iir);
> -
> -err:
> - WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
> - class, instance);
> }
>
> static void
> @@ -122,8 +114,17 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
> if (unlikely(!intr))
> return;
>
> - if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
> - return gen11_engine_irq_handler(gt, class, instance, intr);
> + /*
> + * Platforms with standalone media have the media and GSC engines in
> + * another GT.
> + */
> + gt = pick_gt(gt, class, instance);
> +
> + if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) {
> + struct intel_engine_cs *engine = gt->engine_class[class][instance];
> + if (engine)
> + return intel_engine_cs_irq(engine, intr);
> + }
>
> if (class == OTHER_CLASS)
> return gen11_other_irq_handler(gt, instance, intr);
> @@ -206,7 +207,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
> if (CCS_MASK(gt))
> intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
> - if (HAS_HECI_GSC(gt->i915))
> + if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
> intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
>
> /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> @@ -233,7 +234,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
> if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
> intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
> - if (HAS_HECI_GSC(gt->i915))
> + if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
> intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
>
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
> @@ -249,7 +250,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> {
> struct intel_uncore *uncore = gt->uncore;
> u32 irqs = GT_RENDER_USER_INTERRUPT;
> - const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
> + u32 gsc_mask = 0;
> u32 dmask;
> u32 smask;
>
> @@ -261,6 +262,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> dmask = irqs << 16 | irqs;
> smask = irqs << 16;
>
> + if (HAS_ENGINE(gt, GSC0))
> + gsc_mask = irqs;
> + else if (HAS_HECI_GSC(gt->i915))
> + gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
> +
> BUILD_BUG_ON(irqs & 0xffff0000);
>
> /* Enable RCS, BCS, VCS and VECS class interrupts. */
> @@ -268,9 +274,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
> if (CCS_MASK(gt))
> intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
> - if (HAS_HECI_GSC(gt->i915))
> - intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
> - gsc_mask);
> + if (gsc_mask)
> + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
>
> /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
> @@ -296,7 +301,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
> if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
> intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
> - if (HAS_HECI_GSC(gt->i915))
> + if (gsc_mask)
> intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
>
> /*
> --
> 2.37.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 4/5] drm/i915/mtl: add GSC CS reset support
2022-11-02 17:10 ` [Intel-gfx] " Daniele Ceraolo Spurio
@ 2022-11-02 17:10 ` Daniele Ceraolo Spurio
-1 siblings, 0 replies; 20+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-11-02 17:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniele Ceraolo Spurio, dri-devel
The GSC CS has its own dedicated bit in the GDRST register.
Bspec: 52549
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index e0fbfac03979..f63829abf66c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -423,6 +423,7 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
[CCS1] = GEN11_GRDOM_RENDER,
[CCS2] = GEN11_GRDOM_RENDER,
[CCS3] = GEN11_GRDOM_RENDER,
+ [GSC0] = GEN12_GRDOM_GSC,
};
GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
!engine_reset_domains[id]);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 70177d3f2e94..8aa06b0327e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -643,6 +643,7 @@
#define XEHPC_GRDOM_BLT3 REG_BIT(26)
#define XEHPC_GRDOM_BLT2 REG_BIT(25)
#define XEHPC_GRDOM_BLT1 REG_BIT(24)
+#define GEN12_GRDOM_GSC REG_BIT(21)
#define GEN11_GRDOM_SFC3 REG_BIT(20)
#define GEN11_GRDOM_SFC2 REG_BIT(19)
#define GEN11_GRDOM_SFC1 REG_BIT(18)
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 4/5] drm/i915/mtl: add GSC CS reset support
@ 2022-11-02 17:10 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 20+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-11-02 17:10 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
The GSC CS has its own dedicated bit in the GDRST register.
Bspec: 52549
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index e0fbfac03979..f63829abf66c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -423,6 +423,7 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
[CCS1] = GEN11_GRDOM_RENDER,
[CCS2] = GEN11_GRDOM_RENDER,
[CCS3] = GEN11_GRDOM_RENDER,
+ [GSC0] = GEN12_GRDOM_GSC,
};
GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
!engine_reset_domains[id]);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 70177d3f2e94..8aa06b0327e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -643,6 +643,7 @@
#define XEHPC_GRDOM_BLT3 REG_BIT(26)
#define XEHPC_GRDOM_BLT2 REG_BIT(25)
#define XEHPC_GRDOM_BLT1 REG_BIT(24)
+#define GEN12_GRDOM_GSC REG_BIT(21)
#define GEN11_GRDOM_SFC3 REG_BIT(20)
#define GEN11_GRDOM_SFC2 REG_BIT(19)
#define GEN11_GRDOM_SFC1 REG_BIT(18)
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 5/5] drm/i915/mtl: don't expose GSC command streamer to the user
2022-11-02 17:10 ` [Intel-gfx] " Daniele Ceraolo Spurio
@ 2022-11-02 17:10 ` Daniele Ceraolo Spurio
-1 siblings, 0 replies; 20+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-11-02 17:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniele Ceraolo Spurio, dri-devel
There is no userspace user for this CS yet, we only need it for internal
kernel ops (e.g. HuC, PXP), so don't expose it.
v2: even if it's not exposed, rename the engine so it is easier to
identify in the debug logs (Matt)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 27 ++++++++++++++++-----
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 79312b734690..cd4f1b126f75 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -191,6 +191,15 @@ static void add_legacy_ring(struct legacy_ring *ring,
ring->instance++;
}
+static void engine_rename(struct intel_engine_cs *engine, const char *name, u16 instance)
+{
+ char old[sizeof(engine->name)];
+
+ memcpy(old, engine->name, sizeof(engine->name));
+ scnprintf(engine->name, sizeof(engine->name), "%s%u", name, instance);
+ drm_dbg(&engine->i915->drm, "renamed %s to %s\n", old, engine->name);
+}
+
void intel_engines_driver_register(struct drm_i915_private *i915)
{
struct legacy_ring ring = {};
@@ -206,11 +215,19 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
struct intel_engine_cs *engine =
container_of((struct rb_node *)it, typeof(*engine),
uabi_node);
- char old[sizeof(engine->name)];
if (intel_gt_has_unrecoverable_error(engine->gt))
continue; /* ignore incomplete engines */
+ /*
+ * We don't want to expose the GSC engine to the users, but we
+ * still rename it so it is easier to identify in the debug logs
+ */
+ if (engine->id == GSC0) {
+ engine_rename(engine, "gsc", 0);
+ continue;
+ }
+
GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
engine->uabi_class = uabi_classes[engine->class];
@@ -220,11 +237,9 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
i915->engine_uabi_class_count[engine->uabi_class]++;
/* Replace the internal name with the final user facing name */
- memcpy(old, engine->name, sizeof(engine->name));
- scnprintf(engine->name, sizeof(engine->name), "%s%u",
- intel_engine_class_repr(engine->class),
- engine->uabi_instance);
- DRM_DEBUG_DRIVER("renamed %s to %s\n", old, engine->name);
+ engine_rename(engine,
+ intel_engine_class_repr(engine->class),
+ engine->uabi_instance);
rb_link_node(&engine->uabi_node, prev, p);
rb_insert_color(&engine->uabi_node, &i915->uabi_engines);
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH v2 5/5] drm/i915/mtl: don't expose GSC command streamer to the user
@ 2022-11-02 17:10 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 20+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-11-02 17:10 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
There is no userspace user for this CS yet, we only need it for internal
kernel ops (e.g. HuC, PXP), so don't expose it.
v2: even if it's not exposed, rename the engine so it is easier to
identify in the debug logs (Matt)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 27 ++++++++++++++++-----
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 79312b734690..cd4f1b126f75 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -191,6 +191,15 @@ static void add_legacy_ring(struct legacy_ring *ring,
ring->instance++;
}
+static void engine_rename(struct intel_engine_cs *engine, const char *name, u16 instance)
+{
+ char old[sizeof(engine->name)];
+
+ memcpy(old, engine->name, sizeof(engine->name));
+ scnprintf(engine->name, sizeof(engine->name), "%s%u", name, instance);
+ drm_dbg(&engine->i915->drm, "renamed %s to %s\n", old, engine->name);
+}
+
void intel_engines_driver_register(struct drm_i915_private *i915)
{
struct legacy_ring ring = {};
@@ -206,11 +215,19 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
struct intel_engine_cs *engine =
container_of((struct rb_node *)it, typeof(*engine),
uabi_node);
- char old[sizeof(engine->name)];
if (intel_gt_has_unrecoverable_error(engine->gt))
continue; /* ignore incomplete engines */
+ /*
+ * We don't want to expose the GSC engine to the users, but we
+ * still rename it so it is easier to identify in the debug logs
+ */
+ if (engine->id == GSC0) {
+ engine_rename(engine, "gsc", 0);
+ continue;
+ }
+
GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
engine->uabi_class = uabi_classes[engine->class];
@@ -220,11 +237,9 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
i915->engine_uabi_class_count[engine->uabi_class]++;
/* Replace the internal name with the final user facing name */
- memcpy(old, engine->name, sizeof(engine->name));
- scnprintf(engine->name, sizeof(engine->name), "%s%u",
- intel_engine_class_repr(engine->class),
- engine->uabi_instance);
- DRM_DEBUG_DRIVER("renamed %s to %s\n", old, engine->name);
+ engine_rename(engine,
+ intel_engine_class_repr(engine->class),
+ engine->uabi_instance);
rb_link_node(&engine->uabi_node, prev, p);
rb_insert_color(&engine->uabi_node, &i915->uabi_engines);
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 5/5] drm/i915/mtl: don't expose GSC command streamer to the user
2022-11-02 17:10 ` [Intel-gfx] " Daniele Ceraolo Spurio
@ 2022-11-04 17:25 ` Matt Roper
-1 siblings, 0 replies; 20+ messages in thread
From: Matt Roper @ 2022-11-04 17:25 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, dri-devel
On Wed, Nov 02, 2022 at 10:10:47AM -0700, Daniele Ceraolo Spurio wrote:
> There is no userspace user for this CS yet, we only need it for internal
> kernel ops (e.g. HuC, PXP), so don't expose it.
>
> v2: even if it's not exposed, rename the engine so it is easier to
> identify in the debug logs (Matt)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 27 ++++++++++++++++-----
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 79312b734690..cd4f1b126f75 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -191,6 +191,15 @@ static void add_legacy_ring(struct legacy_ring *ring,
> ring->instance++;
> }
>
> +static void engine_rename(struct intel_engine_cs *engine, const char *name, u16 instance)
> +{
> + char old[sizeof(engine->name)];
> +
> + memcpy(old, engine->name, sizeof(engine->name));
> + scnprintf(engine->name, sizeof(engine->name), "%s%u", name, instance);
> + drm_dbg(&engine->i915->drm, "renamed %s to %s\n", old, engine->name);
> +}
> +
> void intel_engines_driver_register(struct drm_i915_private *i915)
> {
> struct legacy_ring ring = {};
> @@ -206,11 +215,19 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
> struct intel_engine_cs *engine =
> container_of((struct rb_node *)it, typeof(*engine),
> uabi_node);
> - char old[sizeof(engine->name)];
>
> if (intel_gt_has_unrecoverable_error(engine->gt))
> continue; /* ignore incomplete engines */
>
> + /*
> + * We don't want to expose the GSC engine to the users, but we
> + * still rename it so it is easier to identify in the debug logs
> + */
> + if (engine->id == GSC0) {
> + engine_rename(engine, "gsc", 0);
> + continue;
> + }
> +
> GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
> engine->uabi_class = uabi_classes[engine->class];
>
> @@ -220,11 +237,9 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
> i915->engine_uabi_class_count[engine->uabi_class]++;
>
> /* Replace the internal name with the final user facing name */
> - memcpy(old, engine->name, sizeof(engine->name));
> - scnprintf(engine->name, sizeof(engine->name), "%s%u",
> - intel_engine_class_repr(engine->class),
> - engine->uabi_instance);
> - DRM_DEBUG_DRIVER("renamed %s to %s\n", old, engine->name);
> + engine_rename(engine,
> + intel_engine_class_repr(engine->class),
> + engine->uabi_instance);
>
> rb_link_node(&engine->uabi_node, prev, p);
> rb_insert_color(&engine->uabi_node, &i915->uabi_engines);
> --
> 2.37.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH v2 5/5] drm/i915/mtl: don't expose GSC command streamer to the user
@ 2022-11-04 17:25 ` Matt Roper
0 siblings, 0 replies; 20+ messages in thread
From: Matt Roper @ 2022-11-04 17:25 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, dri-devel
On Wed, Nov 02, 2022 at 10:10:47AM -0700, Daniele Ceraolo Spurio wrote:
> There is no userspace user for this CS yet, we only need it for internal
> kernel ops (e.g. HuC, PXP), so don't expose it.
>
> v2: even if it's not exposed, rename the engine so it is easier to
> identify in the debug logs (Matt)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 27 ++++++++++++++++-----
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 79312b734690..cd4f1b126f75 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -191,6 +191,15 @@ static void add_legacy_ring(struct legacy_ring *ring,
> ring->instance++;
> }
>
> +static void engine_rename(struct intel_engine_cs *engine, const char *name, u16 instance)
> +{
> + char old[sizeof(engine->name)];
> +
> + memcpy(old, engine->name, sizeof(engine->name));
> + scnprintf(engine->name, sizeof(engine->name), "%s%u", name, instance);
> + drm_dbg(&engine->i915->drm, "renamed %s to %s\n", old, engine->name);
> +}
> +
> void intel_engines_driver_register(struct drm_i915_private *i915)
> {
> struct legacy_ring ring = {};
> @@ -206,11 +215,19 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
> struct intel_engine_cs *engine =
> container_of((struct rb_node *)it, typeof(*engine),
> uabi_node);
> - char old[sizeof(engine->name)];
>
> if (intel_gt_has_unrecoverable_error(engine->gt))
> continue; /* ignore incomplete engines */
>
> + /*
> + * We don't want to expose the GSC engine to the users, but we
> + * still rename it so it is easier to identify in the debug logs
> + */
> + if (engine->id == GSC0) {
> + engine_rename(engine, "gsc", 0);
> + continue;
> + }
> +
> GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
> engine->uabi_class = uabi_classes[engine->class];
>
> @@ -220,11 +237,9 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
> i915->engine_uabi_class_count[engine->uabi_class]++;
>
> /* Replace the internal name with the final user facing name */
> - memcpy(old, engine->name, sizeof(engine->name));
> - scnprintf(engine->name, sizeof(engine->name), "%s%u",
> - intel_engine_class_repr(engine->class),
> - engine->uabi_instance);
> - DRM_DEBUG_DRIVER("renamed %s to %s\n", old, engine->name);
> + engine_rename(engine,
> + intel_engine_class_repr(engine->class),
> + engine->uabi_instance);
>
> rb_link_node(&engine->uabi_node, prev, p);
> rb_insert_color(&engine->uabi_node, &i915->uabi_engines);
> --
> 2.37.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Introduce the GSC CS
2022-11-02 17:10 ` [Intel-gfx] " Daniele Ceraolo Spurio
` (5 preceding siblings ...)
(?)
@ 2022-11-02 19:00 ` Patchwork
-1 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-11-02 19:00 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Introduce the GSC CS
URL : https://patchwork.freedesktop.org/series/110432/
State : warning
== Summary ==
Error: dim checkpatch failed
0cfd9bdf1be5 drm/i915/mtl: add initial definitions for GSC CS
31fe0d686c6a drm/i915/mtl: pass the GSC CS info to the GuC
-:81: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#81: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:189:
+ GEM_BUG_ON(class > MAX_ENGINE_CLASS);
total: 0 errors, 1 warnings, 0 checks, 59 lines checked
868116c95df8 drm/i915/mtl: add GSC CS interrupt support
-:44: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#44: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq.c:89:
+ GEM_BUG_ON(gt == media_gt);
-:89: WARNING:LINE_SPACING: Missing a blank line after declarations
#89: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq.c:125:
+ struct intel_engine_cs *engine = gt->engine_class[class][instance];
+ if (engine)
total: 0 errors, 2 warnings, 0 checks, 126 lines checked
603ebc899715 drm/i915/mtl: add GSC CS reset support
2beaa04d916b drm/i915/mtl: don't expose GSC command streamer to the user
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Introduce the GSC CS
2022-11-02 17:10 ` [Intel-gfx] " Daniele Ceraolo Spurio
` (6 preceding siblings ...)
(?)
@ 2022-11-02 19:00 ` Patchwork
-1 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-11-02 19:00 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Introduce the GSC CS
URL : https://patchwork.freedesktop.org/series/110432/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Introduce the GSC CS
2022-11-02 17:10 ` [Intel-gfx] " Daniele Ceraolo Spurio
` (7 preceding siblings ...)
(?)
@ 2022-11-02 19:20 ` Patchwork
-1 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-11-02 19:20 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4808 bytes --]
== Series Details ==
Series: drm/i915: Introduce the GSC CS
URL : https://patchwork.freedesktop.org/series/110432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12332 -> Patchwork_110432v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/index.html
Participating hosts (40 -> 28)
------------------------------
Missing (12): bat-dg2-8 bat-adlm-1 fi-icl-u2 bat-dg2-9 bat-adlp-6 bat-adlp-4 bat-adln-1 bat-rplp-1 bat-rpls-1 bat-rpls-2 bat-dg2-11 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_110432v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [PASS][1] -> [INCOMPLETE][2] ([i915#146])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-apl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#180] / [i915#5904] / [i915#62])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/fi-apl-guc/igt@i915_suspend@basic-s2idle-without-i915.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/fi-apl-guc/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/fi-hsw-g3258/igt@kms_chamelium@common-hpd-after-suspend.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][6] ([i915#5334]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-adl-ddr5: [DMESG-WARN][8] ([i915#5591]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/fi-adl-ddr5/igt@i915_selftest@live@hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/fi-adl-ddr5/igt@i915_selftest@live@hangcheck.html
- fi-hsw-g3258: [INCOMPLETE][10] ([i915#3303] / [i915#4785]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
[i915#6106]: https://gitlab.freedesktop.org/drm/intel/issues/6106
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
Build changes
-------------
* Linux: CI_DRM_12332 -> Patchwork_110432v1
CI-20190529: 20190529
CI_DRM_12332: 601b2ef606e4b83d5518aa6a5011bb2b1c5954d9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7038: 5389b3f3b9b75df6bd8506e4aa3da357fd0c0ab1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110432v1: 601b2ef606e4b83d5518aa6a5011bb2b1c5954d9 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
7d2de4ea4087 drm/i915/mtl: don't expose GSC command streamer to the user
4599feae72b5 drm/i915/mtl: add GSC CS reset support
185e307fcee2 drm/i915/mtl: add GSC CS interrupt support
c78ef35317d2 drm/i915/mtl: pass the GSC CS info to the GuC
79f993a2f4c4 drm/i915/mtl: add initial definitions for GSC CS
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/index.html
[-- Attachment #2: Type: text/html, Size: 5236 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Introduce the GSC CS
2022-11-02 17:10 ` [Intel-gfx] " Daniele Ceraolo Spurio
` (8 preceding siblings ...)
(?)
@ 2022-11-03 0:52 ` Patchwork
-1 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-11-03 0:52 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 25160 bytes --]
== Series Details ==
Series: drm/i915: Introduce the GSC CS
URL : https://patchwork.freedesktop.org/series/110432/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12332_full -> Patchwork_110432v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_110432v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110432v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_110432v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb7/igt@gem_exec_whisper@basic-queues-forked-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb6/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@kms_cursor_legacy@cursor-vs-flip@atomic:
- shard-skl: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl1/igt@kms_cursor_legacy@cursor-vs-flip@atomic.html
Known issues
------------
Here are the changes found in Patchwork_110432v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#658])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb2/igt@feature_discovery@psr2.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb6/igt@feature_discovery@psr2.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#6268])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-tglb5/igt@gem_ctx_exec@basic-nohangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-tglb1/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#2846])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-glk8/igt@gem_exec_fair@basic-deadline.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-glk9/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-apl: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-apl2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_whisper@basic-contexts-priority:
- shard-iclb: [PASS][16] -> [INCOMPLETE][17] ([i915#6755])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb7/igt@gem_exec_whisper@basic-contexts-priority.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb7/igt@gem_exec_whisper@basic-contexts-priority.html
* igt@gem_lmem_swapping@basic:
- shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl1/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random:
- shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl6/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [INCOMPLETE][20] ([i915#7248])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl3/igt@gem_pread@exhaustion.html
* igt@gem_softpin@evict-single-offset:
- shard-apl: NOTRUN -> [FAIL][21] ([i915#4171])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl6/igt@gem_softpin@evict-single-offset.html
- shard-tglb: [PASS][22] -> [FAIL][23] ([i915#4171])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-tglb3/igt@gem_softpin@evict-single-offset.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-tglb7/igt@gem_softpin@evict-single-offset.html
* igt@gem_tiled_wb:
- shard-skl: NOTRUN -> [TIMEOUT][24] ([i915#6990])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl9/igt@gem_tiled_wb.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-1:
- shard-apl: [PASS][25] -> [FAIL][26] ([i915#2521])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-apl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-1.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3886]) +5 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl2/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl2/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_color_chamelium@gamma:
- shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl1/igt@kms_color_chamelium@gamma.html
* igt@kms_cursor_crc@cursor-sliding-32x32:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271]) +63 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl6/igt@kms_cursor_crc@cursor-sliding-32x32.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
- shard-skl: NOTRUN -> [FAIL][31] ([i915#2346])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#2122]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-skl6/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl1/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][34] ([i915#2587] / [i915#2672]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][35] ([i915#2672]) +5 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][36] ([i915#2672] / [i915#3555])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271]) +60 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl1/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1:
- shard-apl: NOTRUN -> [FAIL][38] ([i915#4573]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl6/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1.html
* igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2:
- shard-glk: [PASS][39] -> [DMESG-WARN][40] ([i915#118])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-glk9/igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-glk3/igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2.html
* igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-2:
- shard-glk: [PASS][41] -> [FAIL][42] ([i915#1036] / [i915#7307])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-glk9/igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-2.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-glk3/igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-2.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1:
- shard-iclb: [PASS][43] -> [SKIP][44] ([i915#5235]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#658]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl1/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [PASS][46] -> [SKIP][47] ([fdo#109441]) +2 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_vblank@pipe-c-accuracy-idle:
- shard-skl: [PASS][48] -> [FAIL][49] ([i915#43])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-skl10/igt@kms_vblank@pipe-c-accuracy-idle.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl4/igt@kms_vblank@pipe-c-accuracy-idle.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#2437])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl1/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf_pmu@idle@rcs0:
- shard-skl: NOTRUN -> [FAIL][51] ([i915#4349])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl1/igt@perf_pmu@idle@rcs0.html
* igt@sysfs_clients@split-10:
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#2994])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl10/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [SKIP][53] ([i915#4525]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb5/igt@gem_exec_balancer@parallel-bb-first.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb1/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][55] ([i915#2842]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][57] ([i915#2842]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_mmap_offset@bad-object:
- shard-skl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-skl4/igt@gem_mmap_offset@bad-object.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl6/igt@gem_mmap_offset@bad-object.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-skl: [WARN][61] ([i915#1804]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-skl7/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl4/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- shard-iclb: [FAIL][63] -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb3/igt@i915_pm_rpm@basic-pci-d3-state.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb2/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_cursor_legacy@cursor-vs-flip@toggle:
- shard-skl: [INCOMPLETE][65] -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-skl6/igt@kms_cursor_legacy@cursor-vs-flip@toggle.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl1/igt@kms_cursor_legacy@cursor-vs-flip@toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][67] ([i915#2346]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1:
- shard-skl: [FAIL][69] ([i915#2122]) -> [PASS][70] +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-skl5/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl6/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][71] ([i915#79]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
- shard-iclb: [SKIP][73] ([i915#3555]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
- shard-iclb: [SKIP][75] ([i915#5176]) -> [PASS][76] +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb6/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1:
- shard-iclb: [SKIP][77] ([i915#5235]) -> [PASS][78] +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][79] ([fdo#109441]) -> [PASS][80] +3 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_cpu.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-iclb: [SKIP][81] ([i915#5519]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][83] ([i915#180]) -> [PASS][84] +3 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-apl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@perf@polling:
- shard-skl: [FAIL][85] ([i915#1542]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-skl9/igt@perf@polling.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl4/igt@perf@polling.html
* igt@prime_mmap_coherency@ioctl-errors:
- shard-skl: [INCOMPLETE][87] ([i915#2295]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-skl3/igt@prime_mmap_coherency@ioctl-errors.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl9/igt@prime_mmap_coherency@ioctl-errors.html
#### Warnings ####
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: [TIMEOUT][89] ([i915#7248]) -> [INCOMPLETE][90] ([i915#7248])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-skl3/igt@gem_pwrite@basic-exhaustion.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-skl1/igt@gem_pwrite@basic-exhaustion.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][91] ([i915#588]) -> [SKIP][92] ([i915#658])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][93] ([i915#2920]) -> [SKIP][94] ([i915#658])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb6/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][95] ([i915#658]) -> [SKIP][96] ([i915#2920])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-iclb8/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@runner@aborted:
- shard-apl: ([FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][103], [FAIL][104]) ([i915#3002] / [i915#4312])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-apl2/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-apl3/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-apl3/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-apl8/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-apl1/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12332/shard-apl6/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl1/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/shard-apl6/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1036]: https://gitlab.freedesktop.org/drm/intel/issues/1036
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755
[i915#6990]: https://gitlab.freedesktop.org/drm/intel/issues/6990
[i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
[i915#7307]: https://gitlab.freedesktop.org/drm/intel/issues/7307
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12332 -> Patchwork_110432v1
CI-20190529: 20190529
CI_DRM_12332: 601b2ef606e4b83d5518aa6a5011bb2b1c5954d9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7038: 5389b3f3b9b75df6bd8506e4aa3da357fd0c0ab1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110432v1: 601b2ef606e4b83d5518aa6a5011bb2b1c5954d9 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110432v1/index.html
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