* [RFC PATCH v2 00/11] iommu/arm-smmu-qcom: Rework Qualcomm SMMU bindings and implementation
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
The main goal of this patchset is to define a generic qcom,smmu-500
binding to be used by newer Qualcomm platforms instead of defining each
and every SoC line with no actual differences between the compats.
While preparing this change it was required to cleanup the existing
bindings and to rework the way the arm-smmu-qcom implementation handles
binding to IOMMU devices.
Changes since RFC v1:
- Added the dts patch fixing order of clocks in msm8996.dtsi
- Fixed the DT bot errors
- Added separate clause for Google Cheza devices
Dmitry Baryshkov (11):
arm64: dts: qcom: msm8996: change order of SMMU clocks on this
platform
dt-bindings: arm-smmu: Add missing Qualcomm SMMU compatibles
dt-bindings: arm-smmu: fix clocks/clock-names schema
dt-bindings: arm-smmu: add special case for Google Cheza platform
dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings
iommu/arm-smmu-qcom: Move implementation data into match data
iommu/arm-smmu-qcom: Move the qcom,adreno-smmu check into
qcom_smmu_create
iommu/arm-smmu-qcom: provide separate implementation for
SDM845-smmu-500
iommu/arm-smmu-qcom: Merge table from arm-smmu-qcom-debug into match
data
iommu/arm-smmu-qcom: Stop using mmu500 reset for v2 MMUs
iommu/arm-smmu-qcom: Add generic qcom,smmu-500 match entry
.../devicetree/bindings/iommu/arm,smmu.yaml | 172 +++++++++++++++++-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 31 ++--
.../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 91 ---------
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 156 +++++++++++-----
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 21 ++-
5 files changed, 307 insertions(+), 164 deletions(-)
--
2.35.1
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^ permalink raw reply [flat|nested] 44+ messages in thread* [RFC PATCH v2 01/11] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 18:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
Change order of SMMU clocks to match the schema.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 31 +++++++++++++--------------
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c0a2baffa49d..9331327678d8 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -2205,9 +2205,9 @@ adreno_smmu: iommu@b40000 {
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- clocks = <&mmcc GPU_AHB_CLK>,
- <&gcc GCC_MMSS_BIMC_GFX_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
+ <&mmcc GPU_AHB_CLK>;
+ clock-names = "bus", "iface";
power-domains = <&mmcc GPU_GDSC>;
};
@@ -2272,9 +2272,9 @@ mdp_smmu: iommu@d00000 {
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- clocks = <&mmcc SMMU_MDP_AHB_CLK>,
- <&mmcc SMMU_MDP_AXI_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&mmcc SMMU_MDP_AXI_CLK>,
+ <&mmcc SMMU_MDP_AHB_CLK>;
+ clock-names = "bus", "iface";
power-domains = <&mmcc MDSS_GDSC>;
};
@@ -2292,9 +2292,9 @@ venus_smmu: iommu@d40000 {
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
- clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
- <&mmcc SMMU_VIDEO_AXI_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
+ <&mmcc SMMU_VIDEO_AHB_CLK>;
+ clock-names = "bus", "iface";
#iommu-cells = <1>;
status = "okay";
};
@@ -2308,10 +2308,9 @@ vfe_smmu: iommu@da0000 {
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
- clocks = <&mmcc SMMU_VFE_AHB_CLK>,
- <&mmcc SMMU_VFE_AXI_CLK>;
- clock-names = "iface",
- "bus";
+ clocks = <&mmcc SMMU_VFE_AXI_CLK>,
+ <&mmcc SMMU_VFE_AHB_CLK>;
+ clock-names = "bus", "iface";
#iommu-cells = <1>;
};
@@ -2336,9 +2335,9 @@ lpass_q6_smmu: iommu@1600000 {
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
- <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
+ <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
+ clock-names = "bus", "iface";
};
slpi_pil: remoteproc@1c00000 {
--
2.35.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC PATCH v2 01/11] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
Change order of SMMU clocks to match the schema.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 31 +++++++++++++--------------
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c0a2baffa49d..9331327678d8 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -2205,9 +2205,9 @@ adreno_smmu: iommu@b40000 {
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- clocks = <&mmcc GPU_AHB_CLK>,
- <&gcc GCC_MMSS_BIMC_GFX_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
+ <&mmcc GPU_AHB_CLK>;
+ clock-names = "bus", "iface";
power-domains = <&mmcc GPU_GDSC>;
};
@@ -2272,9 +2272,9 @@ mdp_smmu: iommu@d00000 {
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- clocks = <&mmcc SMMU_MDP_AHB_CLK>,
- <&mmcc SMMU_MDP_AXI_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&mmcc SMMU_MDP_AXI_CLK>,
+ <&mmcc SMMU_MDP_AHB_CLK>;
+ clock-names = "bus", "iface";
power-domains = <&mmcc MDSS_GDSC>;
};
@@ -2292,9 +2292,9 @@ venus_smmu: iommu@d40000 {
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
- clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
- <&mmcc SMMU_VIDEO_AXI_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
+ <&mmcc SMMU_VIDEO_AHB_CLK>;
+ clock-names = "bus", "iface";
#iommu-cells = <1>;
status = "okay";
};
@@ -2308,10 +2308,9 @@ vfe_smmu: iommu@da0000 {
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
- clocks = <&mmcc SMMU_VFE_AHB_CLK>,
- <&mmcc SMMU_VFE_AXI_CLK>;
- clock-names = "iface",
- "bus";
+ clocks = <&mmcc SMMU_VFE_AXI_CLK>,
+ <&mmcc SMMU_VFE_AHB_CLK>;
+ clock-names = "bus", "iface";
#iommu-cells = <1>;
};
@@ -2336,9 +2335,9 @@ lpass_q6_smmu: iommu@1600000 {
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
- <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
+ <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
+ clock-names = "bus", "iface";
};
slpi_pil: remoteproc@1c00000 {
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [RFC PATCH v2 01/11] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 20:55 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 20:55 UTC (permalink / raw)
To: Dmitry Baryshkov, Will Deacon, Robin Murphy, Joerg Roedel,
Rob Herring, Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On 02/11/2022 14:44, Dmitry Baryshkov wrote:
> Change order of SMMU clocks to match the schema.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC PATCH v2 01/11] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform
@ 2022-11-02 20:55 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 20:55 UTC (permalink / raw)
To: Dmitry Baryshkov, Will Deacon, Robin Murphy, Joerg Roedel,
Rob Herring, Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On 02/11/2022 14:44, Dmitry Baryshkov wrote:
> Change order of SMMU clocks to match the schema.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: (subset) [RFC PATCH v2 01/11] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-08 4:36 ` Bjorn Andersson
-1 siblings, 0 replies; 44+ messages in thread
From: Bjorn Andersson @ 2022-11-08 4:36 UTC (permalink / raw)
To: krzysztof.kozlowski+dt, robdclark, will, robh+dt, joro,
konrad.dybcio, dmitry.baryshkov, robin.murphy
Cc: iommu, quic_saipraka, devicetree, freedreno, linux-arm-kernel,
vkoul, linux-arm-msm
On Wed, 2 Nov 2022 21:44:10 +0300, Dmitry Baryshkov wrote:
> Change order of SMMU clocks to match the schema.
>
>
Applied, thanks!
[01/11] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform
commit: d6e636787d462c047a424dd442b68a249edde2a7
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: (subset) [RFC PATCH v2 01/11] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform
@ 2022-11-08 4:36 ` Bjorn Andersson
0 siblings, 0 replies; 44+ messages in thread
From: Bjorn Andersson @ 2022-11-08 4:36 UTC (permalink / raw)
To: krzysztof.kozlowski+dt, robdclark, will, robh+dt, joro,
konrad.dybcio, dmitry.baryshkov, robin.murphy
Cc: iommu, quic_saipraka, devicetree, freedreno, linux-arm-kernel,
vkoul, linux-arm-msm
On Wed, 2 Nov 2022 21:44:10 +0300, Dmitry Baryshkov wrote:
> Change order of SMMU clocks to match the schema.
>
>
Applied, thanks!
[01/11] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform
commit: d6e636787d462c047a424dd442b68a249edde2a7
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* [RFC PATCH v2 02/11] dt-bindings: arm-smmu: Add missing Qualcomm SMMU compatibles
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 18:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno, Krzysztof Kozlowski
Add missing compatibles used for Adreno SMMU on sc7280 and sm8450
platforms and for the Qualcomm v2 SMMU used on SDM630 platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 9066e6df1ba1..34ee33a62ba5 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -28,6 +28,7 @@ properties:
- enum:
- qcom,msm8996-smmu-v2
- qcom,msm8998-smmu-v2
+ - qcom,sdm630-smmu-v2
- const: qcom,smmu-v2
- description: Qcom SoCs implementing "arm,mmu-500"
@@ -48,10 +49,20 @@ properties:
- qcom,sm8350-smmu-500
- qcom,sm8450-smmu-500
- const: arm,mmu-500
+
+ - description: Qcom Adreno GPUs implementing "arm,smmu-500"
+ items:
+ - enum:
+ - qcom,sc7280-smmu-500
+ - qcom,sm8250-smmu-500
+ - const: qcom,adreno-smmu
+ - const: arm,mmu-500
- description: Qcom Adreno GPUs implementing "arm,smmu-v2"
items:
- enum:
+ - qcom,msm8996-smmu-v2
- qcom,sc7180-smmu-v2
+ - qcom,sdm630-smmu-v2
- qcom,sdm845-smmu-v2
- const: qcom,adreno-smmu
- const: qcom,smmu-v2
--
2.35.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC PATCH v2 02/11] dt-bindings: arm-smmu: Add missing Qualcomm SMMU compatibles
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno, Krzysztof Kozlowski
Add missing compatibles used for Adreno SMMU on sc7280 and sm8450
platforms and for the Qualcomm v2 SMMU used on SDM630 platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 9066e6df1ba1..34ee33a62ba5 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -28,6 +28,7 @@ properties:
- enum:
- qcom,msm8996-smmu-v2
- qcom,msm8998-smmu-v2
+ - qcom,sdm630-smmu-v2
- const: qcom,smmu-v2
- description: Qcom SoCs implementing "arm,mmu-500"
@@ -48,10 +49,20 @@ properties:
- qcom,sm8350-smmu-500
- qcom,sm8450-smmu-500
- const: arm,mmu-500
+
+ - description: Qcom Adreno GPUs implementing "arm,smmu-500"
+ items:
+ - enum:
+ - qcom,sc7280-smmu-500
+ - qcom,sm8250-smmu-500
+ - const: qcom,adreno-smmu
+ - const: arm,mmu-500
- description: Qcom Adreno GPUs implementing "arm,smmu-v2"
items:
- enum:
+ - qcom,msm8996-smmu-v2
- qcom,sc7180-smmu-v2
+ - qcom,sdm630-smmu-v2
- qcom,sdm845-smmu-v2
- const: qcom,adreno-smmu
- const: qcom,smmu-v2
--
2.35.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [RFC PATCH v2 03/11] dt-bindings: arm-smmu: fix clocks/clock-names schema
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 18:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
Rework clocks/clock-names properties schema to property describe
possible usage cases.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/iommu/arm,smmu.yaml | 129 ++++++++++++++++--
1 file changed, 121 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 34ee33a62ba5..abcb1ee4b58f 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -158,16 +158,12 @@ properties:
present in such cases.
clock-names:
- items:
- - const: bus
- - const: iface
+ minItems: 1
+ maxItems: 7
clocks:
- items:
- - description: bus clock required for downstream bus access and for the
- smmu ptw
- - description: interface clock required to access smmu's registers
- through the TCU's programming interface.
+ minItems: 1
+ maxItems: 7
power-domains:
maxItems: 1
@@ -217,6 +213,123 @@ allOf:
reg:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-smmu-v2
+ - qcom,sdm630-smmu-v2
+ then:
+ anyOf:
+ - properties:
+ clock-names:
+ items:
+ - const: bus
+ clocks:
+ items:
+ - description: bus clock required for downstream bus access and for
+ the smmu ptw
+ - properties:
+ clock-names:
+ items:
+ - const: iface
+ - const: mem
+ - const: mem_iface
+ clocks:
+ items:
+ - description: interface clock required to access smmu's registers
+ through the TCU's programming interface.
+ - description: bus clock required for memory access
+ - description: bus clock required for GPU memory access
+ - properties:
+ clock-names:
+ items:
+ - const: iface-mm
+ - const: iface-smmu
+ - const: bus-mm
+ - const: bus-smmu
+ clocks:
+ items:
+ - description: interface clock required to access mnoc's registers
+ through the TCU's programming interface.
+ - description: interface clock required to access smmu's registers
+ through the TCU's programming interface.
+ - description: bus clock required for downstream bus access
+ - description: bus clock required for the smmu ptw
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-smmu-v2
+ - qcom,sc7180-smmu-v2
+ - qcom,sdm845-smmu-v2
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+
+ clocks:
+ items:
+ - description: bus clock required for downstream bus access and for
+ the smmu ptw
+ - description: interface clock required to access smmu's registers
+ through the TCU's programming interface.
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sc7280-smmu-500
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: gcc_gpu_memnoc_gfx_clk
+ - const: gcc_gpu_snoc_dvm_gfx_clk
+ - const: gpu_cc_ahb_clk
+ - const: gpu_cc_hlos1_vote_gpu_smmu_clk
+ - const: gpu_cc_cx_gmu_clk
+ - const: gpu_cc_hub_cx_int_clk
+ - const: gpu_cc_hub_aon_clk
+
+ clocks:
+ items:
+ - description: GPU memnoc_gfx clock
+ - description: GPU snoc_dvm_gfx clock
+ - description: GPU ahb clock
+ - description: GPU hlos1_vote_GPU smmu clock
+ - description: GPU cx_gmu clock
+ - description: GPU hub_cx_int clock
+ - description: GPU hub_aon clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8150-smmu-500
+ - qcom,sm8250-smmu-500
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: ahb
+ - const: bus
+ - const: iface
+
+ clocks:
+ items:
+ - description: bus clock required for AHB bus access
+ - description: bus clock required for downstream bus access and for
+ the smmu ptw
+ - description: interface clock required to access smmu's registers
+ through the TCU's programming interface.
+
examples:
- |+
/* SMMU with stream matching or stream indexing */
--
2.35.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC PATCH v2 03/11] dt-bindings: arm-smmu: fix clocks/clock-names schema
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
Rework clocks/clock-names properties schema to property describe
possible usage cases.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/iommu/arm,smmu.yaml | 129 ++++++++++++++++--
1 file changed, 121 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 34ee33a62ba5..abcb1ee4b58f 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -158,16 +158,12 @@ properties:
present in such cases.
clock-names:
- items:
- - const: bus
- - const: iface
+ minItems: 1
+ maxItems: 7
clocks:
- items:
- - description: bus clock required for downstream bus access and for the
- smmu ptw
- - description: interface clock required to access smmu's registers
- through the TCU's programming interface.
+ minItems: 1
+ maxItems: 7
power-domains:
maxItems: 1
@@ -217,6 +213,123 @@ allOf:
reg:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-smmu-v2
+ - qcom,sdm630-smmu-v2
+ then:
+ anyOf:
+ - properties:
+ clock-names:
+ items:
+ - const: bus
+ clocks:
+ items:
+ - description: bus clock required for downstream bus access and for
+ the smmu ptw
+ - properties:
+ clock-names:
+ items:
+ - const: iface
+ - const: mem
+ - const: mem_iface
+ clocks:
+ items:
+ - description: interface clock required to access smmu's registers
+ through the TCU's programming interface.
+ - description: bus clock required for memory access
+ - description: bus clock required for GPU memory access
+ - properties:
+ clock-names:
+ items:
+ - const: iface-mm
+ - const: iface-smmu
+ - const: bus-mm
+ - const: bus-smmu
+ clocks:
+ items:
+ - description: interface clock required to access mnoc's registers
+ through the TCU's programming interface.
+ - description: interface clock required to access smmu's registers
+ through the TCU's programming interface.
+ - description: bus clock required for downstream bus access
+ - description: bus clock required for the smmu ptw
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-smmu-v2
+ - qcom,sc7180-smmu-v2
+ - qcom,sdm845-smmu-v2
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+
+ clocks:
+ items:
+ - description: bus clock required for downstream bus access and for
+ the smmu ptw
+ - description: interface clock required to access smmu's registers
+ through the TCU's programming interface.
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sc7280-smmu-500
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: gcc_gpu_memnoc_gfx_clk
+ - const: gcc_gpu_snoc_dvm_gfx_clk
+ - const: gpu_cc_ahb_clk
+ - const: gpu_cc_hlos1_vote_gpu_smmu_clk
+ - const: gpu_cc_cx_gmu_clk
+ - const: gpu_cc_hub_cx_int_clk
+ - const: gpu_cc_hub_aon_clk
+
+ clocks:
+ items:
+ - description: GPU memnoc_gfx clock
+ - description: GPU snoc_dvm_gfx clock
+ - description: GPU ahb clock
+ - description: GPU hlos1_vote_GPU smmu clock
+ - description: GPU cx_gmu clock
+ - description: GPU hub_cx_int clock
+ - description: GPU hub_aon clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8150-smmu-500
+ - qcom,sm8250-smmu-500
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: ahb
+ - const: bus
+ - const: iface
+
+ clocks:
+ items:
+ - description: bus clock required for AHB bus access
+ - description: bus clock required for downstream bus access and for
+ the smmu ptw
+ - description: interface clock required to access smmu's registers
+ through the TCU's programming interface.
+
examples:
- |+
/* SMMU with stream matching or stream indexing */
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [RFC PATCH v2 03/11] dt-bindings: arm-smmu: fix clocks/clock-names schema
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 20:56 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 20:56 UTC (permalink / raw)
To: Dmitry Baryshkov, Will Deacon, Robin Murphy, Joerg Roedel,
Rob Herring, Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On 02/11/2022 14:44, Dmitry Baryshkov wrote:
> Rework clocks/clock-names properties schema to property describe
> possible usage cases.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC PATCH v2 03/11] dt-bindings: arm-smmu: fix clocks/clock-names schema
@ 2022-11-02 20:56 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 20:56 UTC (permalink / raw)
To: Dmitry Baryshkov, Will Deacon, Robin Murphy, Joerg Roedel,
Rob Herring, Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On 02/11/2022 14:44, Dmitry Baryshkov wrote:
> Rework clocks/clock-names properties schema to property describe
> possible usage cases.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC PATCH v2 03/11] dt-bindings: arm-smmu: fix clocks/clock-names schema
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 20:56 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 20:56 UTC (permalink / raw)
To: Dmitry Baryshkov, Will Deacon, Robin Murphy, Joerg Roedel,
Rob Herring, Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On 02/11/2022 14:44, Dmitry Baryshkov wrote:
> Rework clocks/clock-names properties schema to property describe
s/property/properly/
with that:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC PATCH v2 03/11] dt-bindings: arm-smmu: fix clocks/clock-names schema
@ 2022-11-02 20:56 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 20:56 UTC (permalink / raw)
To: Dmitry Baryshkov, Will Deacon, Robin Murphy, Joerg Roedel,
Rob Herring, Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On 02/11/2022 14:44, Dmitry Baryshkov wrote:
> Rework clocks/clock-names properties schema to property describe
s/property/properly/
with that:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* [RFC PATCH v2 04/11] dt-bindings: arm-smmu: add special case for Google Cheza platform
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 18:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
Cheza fw does not properly program the GPU aperture to allow the
GPU to update the SMMU pagetables for context switches. The board file
works around this by dropping the "qcom,adreno-smmu" compat string.
Add this usecase to arm,smmu.yaml schema.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index abcb1ee4b58f..f44572cbb071 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -66,6 +66,10 @@ properties:
- qcom,sdm845-smmu-v2
- const: qcom,adreno-smmu
- const: qcom,smmu-v2
+ - description: Qcom Adreno GPUs on Google Cheza platform
+ items:
+ - const: qcom,sdm845-smmu-v2
+ - const: qcom,smmu-v2
- description: Marvell SoCs implementing "arm,mmu-500"
items:
- const: marvell,ap806-smmu-500
--
2.35.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC PATCH v2 04/11] dt-bindings: arm-smmu: add special case for Google Cheza platform
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
Cheza fw does not properly program the GPU aperture to allow the
GPU to update the SMMU pagetables for context switches. The board file
works around this by dropping the "qcom,adreno-smmu" compat string.
Add this usecase to arm,smmu.yaml schema.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index abcb1ee4b58f..f44572cbb071 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -66,6 +66,10 @@ properties:
- qcom,sdm845-smmu-v2
- const: qcom,adreno-smmu
- const: qcom,smmu-v2
+ - description: Qcom Adreno GPUs on Google Cheza platform
+ items:
+ - const: qcom,sdm845-smmu-v2
+ - const: qcom,smmu-v2
- description: Marvell SoCs implementing "arm,mmu-500"
items:
- const: marvell,ap806-smmu-500
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [RFC PATCH v2 04/11] dt-bindings: arm-smmu: add special case for Google Cheza platform
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 20:59 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 20:59 UTC (permalink / raw)
To: Dmitry Baryshkov, Will Deacon, Robin Murphy, Joerg Roedel,
Rob Herring, Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On 02/11/2022 14:44, Dmitry Baryshkov wrote:
> Cheza fw does not properly program the GPU aperture to allow the
> GPU to update the SMMU pagetables for context switches. The board file
> works around this by dropping the "qcom,adreno-smmu" compat string.
> Add this usecase to arm,smmu.yaml schema.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC PATCH v2 04/11] dt-bindings: arm-smmu: add special case for Google Cheza platform
@ 2022-11-02 20:59 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 20:59 UTC (permalink / raw)
To: Dmitry Baryshkov, Will Deacon, Robin Murphy, Joerg Roedel,
Rob Herring, Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On 02/11/2022 14:44, Dmitry Baryshkov wrote:
> Cheza fw does not properly program the GPU aperture to allow the
> GPU to update the SMMU pagetables for context switches. The board file
> works around this by dropping the "qcom,adreno-smmu" compat string.
> Add this usecase to arm,smmu.yaml schema.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* [RFC PATCH v2 05/11] dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 18:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno, Krzysztof Kozlowski
Add generic bindings for the Qualcomm variant of the ARM MMU-500. It is
expected that all future platforms will use the generic qcom,smmu-500
compat string in addition to SoC-specific and the generic arm,mmu-500
ones. Older bindings are now described as deprecated.
Note: I have split the sdx55 and sdx65 from the legacy bindings. They
are not supported by the qcom SMMU implementation. I can suppose that
they are using the generic implementation rather than the
Qualcomm-speicific one.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/iommu/arm,smmu.yaml | 28 ++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index f44572cbb071..3d4cc8996195 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -31,7 +31,7 @@ properties:
- qcom,sdm630-smmu-v2
- const: qcom,smmu-v2
- - description: Qcom SoCs implementing "arm,mmu-500"
+ - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
items:
- enum:
- qcom,qcm2290-smmu-500
@@ -40,8 +40,34 @@ properties:
- qcom,sc8180x-smmu-500
- qcom,sc8280xp-smmu-500
- qcom,sdm845-smmu-500
+ - qcom,sm6350-smmu-500
+ - qcom,sm6375-smmu-500
+ - qcom,sm8150-smmu-500
+ - qcom,sm8250-smmu-500
+ - qcom,sm8350-smmu-500
+ - qcom,sm8450-smmu-500
+ - const: qcom,smmu-500
+ - const: arm,mmu-500
+
+ - description: Qcom SoCs implementing "arm,mmu-500" (non-qcom implementation)
+ deprecated: true
+ items:
+ - enum:
- qcom,sdx55-smmu-500
- qcom,sdx65-smmu-500
+ - const: arm,mmu-500
+
+ - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
+ deprecated: true
+ items:
+ # Do not add additional SoC to this list. Instead use two previous lists.
+ - enum:
+ - qcom,qcm2290-smmu-500
+ - qcom,sc7180-smmu-500
+ - qcom,sc7280-smmu-500
+ - qcom,sc8180x-smmu-500
+ - qcom,sc8280xp-smmu-500
+ - qcom,sdm845-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm6375-smmu-500
- qcom,sm8150-smmu-500
--
2.35.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC PATCH v2 05/11] dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno, Krzysztof Kozlowski
Add generic bindings for the Qualcomm variant of the ARM MMU-500. It is
expected that all future platforms will use the generic qcom,smmu-500
compat string in addition to SoC-specific and the generic arm,mmu-500
ones. Older bindings are now described as deprecated.
Note: I have split the sdx55 and sdx65 from the legacy bindings. They
are not supported by the qcom SMMU implementation. I can suppose that
they are using the generic implementation rather than the
Qualcomm-speicific one.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/iommu/arm,smmu.yaml | 28 ++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index f44572cbb071..3d4cc8996195 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -31,7 +31,7 @@ properties:
- qcom,sdm630-smmu-v2
- const: qcom,smmu-v2
- - description: Qcom SoCs implementing "arm,mmu-500"
+ - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
items:
- enum:
- qcom,qcm2290-smmu-500
@@ -40,8 +40,34 @@ properties:
- qcom,sc8180x-smmu-500
- qcom,sc8280xp-smmu-500
- qcom,sdm845-smmu-500
+ - qcom,sm6350-smmu-500
+ - qcom,sm6375-smmu-500
+ - qcom,sm8150-smmu-500
+ - qcom,sm8250-smmu-500
+ - qcom,sm8350-smmu-500
+ - qcom,sm8450-smmu-500
+ - const: qcom,smmu-500
+ - const: arm,mmu-500
+
+ - description: Qcom SoCs implementing "arm,mmu-500" (non-qcom implementation)
+ deprecated: true
+ items:
+ - enum:
- qcom,sdx55-smmu-500
- qcom,sdx65-smmu-500
+ - const: arm,mmu-500
+
+ - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
+ deprecated: true
+ items:
+ # Do not add additional SoC to this list. Instead use two previous lists.
+ - enum:
+ - qcom,qcm2290-smmu-500
+ - qcom,sc7180-smmu-500
+ - qcom,sc7280-smmu-500
+ - qcom,sc8180x-smmu-500
+ - qcom,sc8280xp-smmu-500
+ - qcom,sdm845-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm6375-smmu-500
- qcom,sm8150-smmu-500
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [RFC PATCH v2 06/11] iommu/arm-smmu-qcom: Move implementation data into match data
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 18:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
In preparation to rework of the implementation and configuration
details, make qcom_smmu_create() accept new qcom_smmu_match_data
structure pointer. Make implementation a field in this struct.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 58 ++++++++++++++--------
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 4 ++
2 files changed, 42 insertions(+), 20 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index b2708de25ea3..bd228b7d6817 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -405,10 +405,18 @@ static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
};
static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
- const struct arm_smmu_impl *impl)
+ const struct qcom_smmu_match_data *data)
{
+ const struct arm_smmu_impl *impl;
struct qcom_smmu *qsmmu;
+ if (!data)
+ return ERR_PTR(-EINVAL);
+
+ impl = data->impl;
+ if (!impl)
+ return smmu;
+
/* Check to make sure qcom_scm has finished probing */
if (!qcom_scm_is_available())
return ERR_PTR(-EPROBE_DEFER);
@@ -423,22 +431,30 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
return &qsmmu->smmu;
}
+static const struct qcom_smmu_match_data qcom_smmu_data = {
+ .impl = &qcom_smmu_impl,
+};
+
+static const struct qcom_smmu_match_data qcom_adreno_smmu_data = {
+ .impl = &qcom_adreno_smmu_impl,
+};
+
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
- { .compatible = "qcom,msm8998-smmu-v2" },
- { .compatible = "qcom,qcm2290-smmu-500" },
- { .compatible = "qcom,sc7180-smmu-500" },
- { .compatible = "qcom,sc7280-smmu-500" },
- { .compatible = "qcom,sc8180x-smmu-500" },
- { .compatible = "qcom,sc8280xp-smmu-500" },
- { .compatible = "qcom,sdm630-smmu-v2" },
- { .compatible = "qcom,sdm845-smmu-500" },
- { .compatible = "qcom,sm6125-smmu-500" },
- { .compatible = "qcom,sm6350-smmu-500" },
- { .compatible = "qcom,sm6375-smmu-500" },
- { .compatible = "qcom,sm8150-smmu-500" },
- { .compatible = "qcom,sm8250-smmu-500" },
- { .compatible = "qcom,sm8350-smmu-500" },
- { .compatible = "qcom,sm8450-smmu-500" },
+ { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
+ { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_data },
{ }
};
@@ -453,12 +469,13 @@ static struct acpi_platform_list qcom_acpi_platlist[] = {
struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
{
const struct device_node *np = smmu->dev->of_node;
+ const struct of_device_id *match;
#ifdef CONFIG_ACPI
if (np == NULL) {
/* Match platform for ACPI boot */
if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
- return qcom_smmu_create(smmu, &qcom_smmu_impl);
+ return qcom_smmu_create(smmu, &qcom_smmu_data);
}
#endif
@@ -469,10 +486,11 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
* features if the order is changed.
*/
if (of_device_is_compatible(np, "qcom,adreno-smmu"))
- return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
+ return qcom_smmu_create(smmu, &qcom_adreno_smmu_data);
- if (of_match_node(qcom_smmu_impl_of_match, np))
- return qcom_smmu_create(smmu, &qcom_smmu_impl);
+ match = of_match_node(qcom_smmu_impl_of_match, np);
+ if (match)
+ return qcom_smmu_create(smmu, match->data);
return smmu;
}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index 99ec8f8629a0..2424f10b7110 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -14,6 +14,10 @@ struct qcom_smmu {
u32 stall_enabled;
};
+struct qcom_smmu_match_data {
+ const struct arm_smmu_impl *impl;
+};
+
#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu);
const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu);
--
2.35.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC PATCH v2 06/11] iommu/arm-smmu-qcom: Move implementation data into match data
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
In preparation to rework of the implementation and configuration
details, make qcom_smmu_create() accept new qcom_smmu_match_data
structure pointer. Make implementation a field in this struct.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 58 ++++++++++++++--------
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 4 ++
2 files changed, 42 insertions(+), 20 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index b2708de25ea3..bd228b7d6817 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -405,10 +405,18 @@ static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
};
static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
- const struct arm_smmu_impl *impl)
+ const struct qcom_smmu_match_data *data)
{
+ const struct arm_smmu_impl *impl;
struct qcom_smmu *qsmmu;
+ if (!data)
+ return ERR_PTR(-EINVAL);
+
+ impl = data->impl;
+ if (!impl)
+ return smmu;
+
/* Check to make sure qcom_scm has finished probing */
if (!qcom_scm_is_available())
return ERR_PTR(-EPROBE_DEFER);
@@ -423,22 +431,30 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
return &qsmmu->smmu;
}
+static const struct qcom_smmu_match_data qcom_smmu_data = {
+ .impl = &qcom_smmu_impl,
+};
+
+static const struct qcom_smmu_match_data qcom_adreno_smmu_data = {
+ .impl = &qcom_adreno_smmu_impl,
+};
+
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
- { .compatible = "qcom,msm8998-smmu-v2" },
- { .compatible = "qcom,qcm2290-smmu-500" },
- { .compatible = "qcom,sc7180-smmu-500" },
- { .compatible = "qcom,sc7280-smmu-500" },
- { .compatible = "qcom,sc8180x-smmu-500" },
- { .compatible = "qcom,sc8280xp-smmu-500" },
- { .compatible = "qcom,sdm630-smmu-v2" },
- { .compatible = "qcom,sdm845-smmu-500" },
- { .compatible = "qcom,sm6125-smmu-500" },
- { .compatible = "qcom,sm6350-smmu-500" },
- { .compatible = "qcom,sm6375-smmu-500" },
- { .compatible = "qcom,sm8150-smmu-500" },
- { .compatible = "qcom,sm8250-smmu-500" },
- { .compatible = "qcom,sm8350-smmu-500" },
- { .compatible = "qcom,sm8450-smmu-500" },
+ { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
+ { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_data },
{ }
};
@@ -453,12 +469,13 @@ static struct acpi_platform_list qcom_acpi_platlist[] = {
struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
{
const struct device_node *np = smmu->dev->of_node;
+ const struct of_device_id *match;
#ifdef CONFIG_ACPI
if (np == NULL) {
/* Match platform for ACPI boot */
if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
- return qcom_smmu_create(smmu, &qcom_smmu_impl);
+ return qcom_smmu_create(smmu, &qcom_smmu_data);
}
#endif
@@ -469,10 +486,11 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
* features if the order is changed.
*/
if (of_device_is_compatible(np, "qcom,adreno-smmu"))
- return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
+ return qcom_smmu_create(smmu, &qcom_adreno_smmu_data);
- if (of_match_node(qcom_smmu_impl_of_match, np))
- return qcom_smmu_create(smmu, &qcom_smmu_impl);
+ match = of_match_node(qcom_smmu_impl_of_match, np);
+ if (match)
+ return qcom_smmu_create(smmu, match->data);
return smmu;
}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index 99ec8f8629a0..2424f10b7110 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -14,6 +14,10 @@ struct qcom_smmu {
u32 stall_enabled;
};
+struct qcom_smmu_match_data {
+ const struct arm_smmu_impl *impl;
+};
+
#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu);
const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu);
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [RFC PATCH v2 07/11] iommu/arm-smmu-qcom: Move the qcom,adreno-smmu check into qcom_smmu_create
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 18:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
Move special handling of qcom,adreno-smmu into qcom_smmu_create()
function. This allows us to further customize the Adreno SMMU
implementation.
Note, this also adds two entries to the qcom_smmu_impl_of_match table.
They were used with the qcom,adreno-smmu compat and were handled by the
removed clause.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 32 ++++++++++++----------
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 1 +
2 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index bd228b7d6817..c3bcd6eb2f42 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -407,13 +407,18 @@ static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
const struct qcom_smmu_match_data *data)
{
+ const struct device_node *np = smmu->dev->of_node;
const struct arm_smmu_impl *impl;
struct qcom_smmu *qsmmu;
if (!data)
return ERR_PTR(-EINVAL);
- impl = data->impl;
+ if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))
+ impl = data->adreno_impl;
+ else
+ impl = data->impl;
+
if (!impl)
return smmu;
@@ -431,15 +436,22 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
return &qsmmu->smmu;
}
-static const struct qcom_smmu_match_data qcom_smmu_data = {
- .impl = &qcom_smmu_impl,
+/*
+ * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
+ * there are not enough context banks.
+ */
+static const struct qcom_smmu_match_data msm8996_smmu_data = {
+ .impl = NULL,
+ .adreno_impl = &qcom_adreno_smmu_impl,
};
-static const struct qcom_smmu_match_data qcom_adreno_smmu_data = {
- .impl = &qcom_adreno_smmu_impl,
+static const struct qcom_smmu_match_data qcom_smmu_data = {
+ .impl = &qcom_smmu_impl,
+ .adreno_impl = &qcom_adreno_smmu_impl,
};
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
+ { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_data },
@@ -447,6 +459,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
@@ -479,15 +492,6 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
}
#endif
- /*
- * Do not change this order of implementation, i.e., first adreno
- * smmu impl and then apss smmu since we can have both implementing
- * arm,mmu-500 in which case we will miss setting adreno smmu specific
- * features if the order is changed.
- */
- if (of_device_is_compatible(np, "qcom,adreno-smmu"))
- return qcom_smmu_create(smmu, &qcom_adreno_smmu_data);
-
match = of_match_node(qcom_smmu_impl_of_match, np);
if (match)
return qcom_smmu_create(smmu, match->data);
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index 2424f10b7110..424d8d342ce0 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -16,6 +16,7 @@ struct qcom_smmu {
struct qcom_smmu_match_data {
const struct arm_smmu_impl *impl;
+ const struct arm_smmu_impl *adreno_impl;
};
#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
--
2.35.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC PATCH v2 07/11] iommu/arm-smmu-qcom: Move the qcom,adreno-smmu check into qcom_smmu_create
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
Move special handling of qcom,adreno-smmu into qcom_smmu_create()
function. This allows us to further customize the Adreno SMMU
implementation.
Note, this also adds two entries to the qcom_smmu_impl_of_match table.
They were used with the qcom,adreno-smmu compat and were handled by the
removed clause.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 32 ++++++++++++----------
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 1 +
2 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index bd228b7d6817..c3bcd6eb2f42 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -407,13 +407,18 @@ static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
const struct qcom_smmu_match_data *data)
{
+ const struct device_node *np = smmu->dev->of_node;
const struct arm_smmu_impl *impl;
struct qcom_smmu *qsmmu;
if (!data)
return ERR_PTR(-EINVAL);
- impl = data->impl;
+ if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))
+ impl = data->adreno_impl;
+ else
+ impl = data->impl;
+
if (!impl)
return smmu;
@@ -431,15 +436,22 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
return &qsmmu->smmu;
}
-static const struct qcom_smmu_match_data qcom_smmu_data = {
- .impl = &qcom_smmu_impl,
+/*
+ * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
+ * there are not enough context banks.
+ */
+static const struct qcom_smmu_match_data msm8996_smmu_data = {
+ .impl = NULL,
+ .adreno_impl = &qcom_adreno_smmu_impl,
};
-static const struct qcom_smmu_match_data qcom_adreno_smmu_data = {
- .impl = &qcom_adreno_smmu_impl,
+static const struct qcom_smmu_match_data qcom_smmu_data = {
+ .impl = &qcom_smmu_impl,
+ .adreno_impl = &qcom_adreno_smmu_impl,
};
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
+ { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_data },
@@ -447,6 +459,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
@@ -479,15 +492,6 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
}
#endif
- /*
- * Do not change this order of implementation, i.e., first adreno
- * smmu impl and then apss smmu since we can have both implementing
- * arm,mmu-500 in which case we will miss setting adreno smmu specific
- * features if the order is changed.
- */
- if (of_device_is_compatible(np, "qcom,adreno-smmu"))
- return qcom_smmu_create(smmu, &qcom_adreno_smmu_data);
-
match = of_match_node(qcom_smmu_impl_of_match, np);
if (match)
return qcom_smmu_create(smmu, match->data);
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index 2424f10b7110..424d8d342ce0 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -16,6 +16,7 @@ struct qcom_smmu {
struct qcom_smmu_match_data {
const struct arm_smmu_impl *impl;
+ const struct arm_smmu_impl *adreno_impl;
};
#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [RFC PATCH v2 08/11] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 18:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
There is only one platform, which needs special care in the reset
function, the SDM845. Add special handler for sdm845 and drop the
qcom_smmu500_reset() function.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 34 ++++++++++++----------
1 file changed, 19 insertions(+), 15 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index c3bcd6eb2f42..75bc770ccf8c 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
{
int ret;
+ arm_mmu500_reset(smmu);
+
/*
* To address performance degradation in non-real time clients,
* such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
@@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
return ret;
}
-static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
-{
- const struct device_node *np = smmu->dev->of_node;
-
- arm_mmu500_reset(smmu);
-
- if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
- return qcom_sdm845_smmu500_reset(smmu);
-
- return 0;
-}
-
static const struct arm_smmu_impl qcom_smmu_impl = {
.init_context = qcom_smmu_init_context,
.cfg_probe = qcom_smmu_cfg_probe,
.def_domain_type = qcom_smmu_def_domain_type,
- .reset = qcom_smmu500_reset,
+ .reset = arm_mmu500_reset,
+ .write_s2cr = qcom_smmu_write_s2cr,
+ .tlb_sync = qcom_smmu_tlb_sync,
+};
+
+static const struct arm_smmu_impl sdm845_smmu_500_impl = {
+ .init_context = qcom_smmu_init_context,
+ .cfg_probe = qcom_smmu_cfg_probe,
+ .def_domain_type = qcom_smmu_def_domain_type,
+ .reset = qcom_sdm845_smmu500_reset,
.write_s2cr = qcom_smmu_write_s2cr,
.tlb_sync = qcom_smmu_tlb_sync,
};
@@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = {
static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
.init_context = qcom_adreno_smmu_init_context,
.def_domain_type = qcom_smmu_def_domain_type,
- .reset = qcom_smmu500_reset,
+ .reset = arm_mmu500_reset,
.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
.write_sctlr = qcom_adreno_smmu_write_sctlr,
.tlb_sync = qcom_smmu_tlb_sync,
@@ -450,6 +449,11 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
.adreno_impl = &qcom_adreno_smmu_impl,
};
+static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
+ .impl = &sdm845_smmu_500_impl,
+ /* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
+};
+
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
@@ -460,7 +464,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
- { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
--
2.35.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC PATCH v2 08/11] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
There is only one platform, which needs special care in the reset
function, the SDM845. Add special handler for sdm845 and drop the
qcom_smmu500_reset() function.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 34 ++++++++++++----------
1 file changed, 19 insertions(+), 15 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index c3bcd6eb2f42..75bc770ccf8c 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
{
int ret;
+ arm_mmu500_reset(smmu);
+
/*
* To address performance degradation in non-real time clients,
* such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
@@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
return ret;
}
-static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
-{
- const struct device_node *np = smmu->dev->of_node;
-
- arm_mmu500_reset(smmu);
-
- if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
- return qcom_sdm845_smmu500_reset(smmu);
-
- return 0;
-}
-
static const struct arm_smmu_impl qcom_smmu_impl = {
.init_context = qcom_smmu_init_context,
.cfg_probe = qcom_smmu_cfg_probe,
.def_domain_type = qcom_smmu_def_domain_type,
- .reset = qcom_smmu500_reset,
+ .reset = arm_mmu500_reset,
+ .write_s2cr = qcom_smmu_write_s2cr,
+ .tlb_sync = qcom_smmu_tlb_sync,
+};
+
+static const struct arm_smmu_impl sdm845_smmu_500_impl = {
+ .init_context = qcom_smmu_init_context,
+ .cfg_probe = qcom_smmu_cfg_probe,
+ .def_domain_type = qcom_smmu_def_domain_type,
+ .reset = qcom_sdm845_smmu500_reset,
.write_s2cr = qcom_smmu_write_s2cr,
.tlb_sync = qcom_smmu_tlb_sync,
};
@@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = {
static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
.init_context = qcom_adreno_smmu_init_context,
.def_domain_type = qcom_smmu_def_domain_type,
- .reset = qcom_smmu500_reset,
+ .reset = arm_mmu500_reset,
.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
.write_sctlr = qcom_adreno_smmu_write_sctlr,
.tlb_sync = qcom_smmu_tlb_sync,
@@ -450,6 +449,11 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
.adreno_impl = &qcom_adreno_smmu_impl,
};
+static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
+ .impl = &sdm845_smmu_500_impl,
+ /* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
+};
+
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
@@ -460,7 +464,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
- { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [RFC PATCH v2 08/11] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-04 22:16 ` Richard Acayan
-1 siblings, 0 replies; 44+ messages in thread
From: Richard Acayan @ 2022-11-04 22:16 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark,
Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On Wed, Nov 02, 2022 at 09:44:17PM +0300, Dmitry Baryshkov wrote:
> There is only one platform, which needs special care in the reset
> function, the SDM845. Add special handler for sdm845 and drop the
> qcom_smmu500_reset() function.
>
> Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 34 ++++++++++++----------
> 1 file changed, 19 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index c3bcd6eb2f42..75bc770ccf8c 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> {
> int ret;
>
> + arm_mmu500_reset(smmu);
> +
> /*
> * To address performance degradation in non-real time clients,
> * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
> @@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> return ret;
> }
>
> -static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
> -{
> - const struct device_node *np = smmu->dev->of_node;
> -
> - arm_mmu500_reset(smmu);
> -
> - if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
> - return qcom_sdm845_smmu500_reset(smmu);
> -
> - return 0;
> -}
> -
> static const struct arm_smmu_impl qcom_smmu_impl = {
> .init_context = qcom_smmu_init_context,
> .cfg_probe = qcom_smmu_cfg_probe,
> .def_domain_type = qcom_smmu_def_domain_type,
> - .reset = qcom_smmu500_reset,
> + .reset = arm_mmu500_reset,
> + .write_s2cr = qcom_smmu_write_s2cr,
> + .tlb_sync = qcom_smmu_tlb_sync,
> +};
> +
> +static const struct arm_smmu_impl sdm845_smmu_500_impl = {
> + .init_context = qcom_smmu_init_context,
> + .cfg_probe = qcom_smmu_cfg_probe,
> + .def_domain_type = qcom_smmu_def_domain_type,
> + .reset = qcom_sdm845_smmu500_reset,
> .write_s2cr = qcom_smmu_write_s2cr,
> .tlb_sync = qcom_smmu_tlb_sync,
> };
> @@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = {
> static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
> .init_context = qcom_adreno_smmu_init_context,
> .def_domain_type = qcom_smmu_def_domain_type,
> - .reset = qcom_smmu500_reset,
> + .reset = arm_mmu500_reset,
> .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
> .write_sctlr = qcom_adreno_smmu_write_sctlr,
> .tlb_sync = qcom_smmu_tlb_sync,
> @@ -450,6 +449,11 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
> .adreno_impl = &qcom_adreno_smmu_impl,
> };
>
> +static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
> + .impl = &sdm845_smmu_500_impl,
> + /* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
separete -> separate
Also, while I'm here, does "No adreno impl" constitute adding a
compatible in the driver?
> +};
> +
> static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
> { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
> @@ -460,7 +464,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
> { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
> + { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
> { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [RFC PATCH v2 08/11] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500
@ 2022-11-04 22:16 ` Richard Acayan
0 siblings, 0 replies; 44+ messages in thread
From: Richard Acayan @ 2022-11-04 22:16 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark,
Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On Wed, Nov 02, 2022 at 09:44:17PM +0300, Dmitry Baryshkov wrote:
> There is only one platform, which needs special care in the reset
> function, the SDM845. Add special handler for sdm845 and drop the
> qcom_smmu500_reset() function.
>
> Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 34 ++++++++++++----------
> 1 file changed, 19 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index c3bcd6eb2f42..75bc770ccf8c 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> {
> int ret;
>
> + arm_mmu500_reset(smmu);
> +
> /*
> * To address performance degradation in non-real time clients,
> * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
> @@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> return ret;
> }
>
> -static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
> -{
> - const struct device_node *np = smmu->dev->of_node;
> -
> - arm_mmu500_reset(smmu);
> -
> - if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
> - return qcom_sdm845_smmu500_reset(smmu);
> -
> - return 0;
> -}
> -
> static const struct arm_smmu_impl qcom_smmu_impl = {
> .init_context = qcom_smmu_init_context,
> .cfg_probe = qcom_smmu_cfg_probe,
> .def_domain_type = qcom_smmu_def_domain_type,
> - .reset = qcom_smmu500_reset,
> + .reset = arm_mmu500_reset,
> + .write_s2cr = qcom_smmu_write_s2cr,
> + .tlb_sync = qcom_smmu_tlb_sync,
> +};
> +
> +static const struct arm_smmu_impl sdm845_smmu_500_impl = {
> + .init_context = qcom_smmu_init_context,
> + .cfg_probe = qcom_smmu_cfg_probe,
> + .def_domain_type = qcom_smmu_def_domain_type,
> + .reset = qcom_sdm845_smmu500_reset,
> .write_s2cr = qcom_smmu_write_s2cr,
> .tlb_sync = qcom_smmu_tlb_sync,
> };
> @@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = {
> static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
> .init_context = qcom_adreno_smmu_init_context,
> .def_domain_type = qcom_smmu_def_domain_type,
> - .reset = qcom_smmu500_reset,
> + .reset = arm_mmu500_reset,
> .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
> .write_sctlr = qcom_adreno_smmu_write_sctlr,
> .tlb_sync = qcom_smmu_tlb_sync,
> @@ -450,6 +449,11 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
> .adreno_impl = &qcom_adreno_smmu_impl,
> };
>
> +static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
> + .impl = &sdm845_smmu_500_impl,
> + /* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
separete -> separate
Also, while I'm here, does "No adreno impl" constitute adding a
compatible in the driver?
> +};
> +
> static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
> { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
> @@ -460,7 +464,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
> { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
> + { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
> { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
> { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
> --
> 2.35.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [RFC PATCH v2 08/11] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500
2022-11-04 22:16 ` Richard Acayan
@ 2022-11-05 0:02 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-05 0:02 UTC (permalink / raw)
To: Richard Acayan
Cc: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark,
Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On Sat, 5 Nov 2022 at 01:16, Richard Acayan <mailingradian@gmail.com> wrote:
>
> On Wed, Nov 02, 2022 at 09:44:17PM +0300, Dmitry Baryshkov wrote:
> > There is only one platform, which needs special care in the reset
> > function, the SDM845. Add special handler for sdm845 and drop the
> > qcom_smmu500_reset() function.
> >
> > Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> > Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 34 ++++++++++++----------
> > 1 file changed, 19 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> > index c3bcd6eb2f42..75bc770ccf8c 100644
> > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> > @@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> > {
> > int ret;
> >
> > + arm_mmu500_reset(smmu);
> > +
> > /*
> > * To address performance degradation in non-real time clients,
> > * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
> > @@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> > return ret;
> > }
> >
> > -static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
> > -{
> > - const struct device_node *np = smmu->dev->of_node;
> > -
> > - arm_mmu500_reset(smmu);
> > -
> > - if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
> > - return qcom_sdm845_smmu500_reset(smmu);
> > -
> > - return 0;
> > -}
> > -
> > static const struct arm_smmu_impl qcom_smmu_impl = {
> > .init_context = qcom_smmu_init_context,
> > .cfg_probe = qcom_smmu_cfg_probe,
> > .def_domain_type = qcom_smmu_def_domain_type,
> > - .reset = qcom_smmu500_reset,
> > + .reset = arm_mmu500_reset,
> > + .write_s2cr = qcom_smmu_write_s2cr,
> > + .tlb_sync = qcom_smmu_tlb_sync,
> > +};
> > +
> > +static const struct arm_smmu_impl sdm845_smmu_500_impl = {
> > + .init_context = qcom_smmu_init_context,
> > + .cfg_probe = qcom_smmu_cfg_probe,
> > + .def_domain_type = qcom_smmu_def_domain_type,
> > + .reset = qcom_sdm845_smmu500_reset,
> > .write_s2cr = qcom_smmu_write_s2cr,
> > .tlb_sync = qcom_smmu_tlb_sync,
> > };
> > @@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = {
> > static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
> > .init_context = qcom_adreno_smmu_init_context,
> > .def_domain_type = qcom_smmu_def_domain_type,
> > - .reset = qcom_smmu500_reset,
> > + .reset = arm_mmu500_reset,
> > .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
> > .write_sctlr = qcom_adreno_smmu_write_sctlr,
> > .tlb_sync = qcom_smmu_tlb_sync,
> > @@ -450,6 +449,11 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
> > .adreno_impl = &qcom_adreno_smmu_impl,
> > };
> >
> > +static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
> > + .impl = &sdm845_smmu_500_impl,
> > + /* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
> separete -> separate
Ack.
> Also, while I'm here, does "No adreno impl" constitute adding a
> compatible in the driver?
Not sure that I got your question, please excuse me. Could you please
describe what you meant?
We already have qcom,sdm845-smmu-v2 in the match table, if that's your
question. And there is no need for Adreno impl here, on sdm845 the
SMMU connected to Adreno is v2 rather than mmu-500.
Probably I should change this to "No need for adreno impl....". Would
that be better?
> > +};
> > +
> > static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> > { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
> > { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
> > @@ -460,7 +464,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> > { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
> > { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
> > { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
> > - { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
> > + { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
> > { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
> > { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
> > { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
> > --
> > 2.35.1
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [RFC PATCH v2 08/11] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500
@ 2022-11-05 0:02 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-05 0:02 UTC (permalink / raw)
To: Richard Acayan
Cc: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark,
Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On Sat, 5 Nov 2022 at 01:16, Richard Acayan <mailingradian@gmail.com> wrote:
>
> On Wed, Nov 02, 2022 at 09:44:17PM +0300, Dmitry Baryshkov wrote:
> > There is only one platform, which needs special care in the reset
> > function, the SDM845. Add special handler for sdm845 and drop the
> > qcom_smmu500_reset() function.
> >
> > Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> > Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 34 ++++++++++++----------
> > 1 file changed, 19 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> > index c3bcd6eb2f42..75bc770ccf8c 100644
> > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> > @@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> > {
> > int ret;
> >
> > + arm_mmu500_reset(smmu);
> > +
> > /*
> > * To address performance degradation in non-real time clients,
> > * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
> > @@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
> > return ret;
> > }
> >
> > -static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
> > -{
> > - const struct device_node *np = smmu->dev->of_node;
> > -
> > - arm_mmu500_reset(smmu);
> > -
> > - if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
> > - return qcom_sdm845_smmu500_reset(smmu);
> > -
> > - return 0;
> > -}
> > -
> > static const struct arm_smmu_impl qcom_smmu_impl = {
> > .init_context = qcom_smmu_init_context,
> > .cfg_probe = qcom_smmu_cfg_probe,
> > .def_domain_type = qcom_smmu_def_domain_type,
> > - .reset = qcom_smmu500_reset,
> > + .reset = arm_mmu500_reset,
> > + .write_s2cr = qcom_smmu_write_s2cr,
> > + .tlb_sync = qcom_smmu_tlb_sync,
> > +};
> > +
> > +static const struct arm_smmu_impl sdm845_smmu_500_impl = {
> > + .init_context = qcom_smmu_init_context,
> > + .cfg_probe = qcom_smmu_cfg_probe,
> > + .def_domain_type = qcom_smmu_def_domain_type,
> > + .reset = qcom_sdm845_smmu500_reset,
> > .write_s2cr = qcom_smmu_write_s2cr,
> > .tlb_sync = qcom_smmu_tlb_sync,
> > };
> > @@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = {
> > static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
> > .init_context = qcom_adreno_smmu_init_context,
> > .def_domain_type = qcom_smmu_def_domain_type,
> > - .reset = qcom_smmu500_reset,
> > + .reset = arm_mmu500_reset,
> > .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
> > .write_sctlr = qcom_adreno_smmu_write_sctlr,
> > .tlb_sync = qcom_smmu_tlb_sync,
> > @@ -450,6 +449,11 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
> > .adreno_impl = &qcom_adreno_smmu_impl,
> > };
> >
> > +static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
> > + .impl = &sdm845_smmu_500_impl,
> > + /* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
> separete -> separate
Ack.
> Also, while I'm here, does "No adreno impl" constitute adding a
> compatible in the driver?
Not sure that I got your question, please excuse me. Could you please
describe what you meant?
We already have qcom,sdm845-smmu-v2 in the match table, if that's your
question. And there is no need for Adreno impl here, on sdm845 the
SMMU connected to Adreno is v2 rather than mmu-500.
Probably I should change this to "No need for adreno impl....". Would
that be better?
> > +};
> > +
> > static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> > { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
> > { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
> > @@ -460,7 +464,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> > { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
> > { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
> > { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
> > - { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
> > + { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
> > { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
> > { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
> > { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
> > --
> > 2.35.1
> >
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [RFC PATCH v2 08/11] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500
2022-11-05 0:02 ` Dmitry Baryshkov
@ 2022-11-05 1:42 ` Richard Acayan
-1 siblings, 0 replies; 44+ messages in thread
From: Richard Acayan @ 2022-11-05 1:42 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark,
Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On Sat, Nov 05, 2022 at 03:02:15AM +0300, Dmitry Baryshkov wrote:
> On Sat, 5 Nov 2022 at 01:16, Richard Acayan <mailingradian@gmail.com> wrote:
>>
>> On Wed, Nov 02, 2022 at 09:44:17PM +0300, Dmitry Baryshkov wrote:
>> > There is only one platform, which needs special care in the reset
>> > function, the SDM845. Add special handler for sdm845 and drop the
>> > qcom_smmu500_reset() function.
>> >
>> > Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
>> > Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
>> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> > ---
>> > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 34 ++++++++++++----------
>> > 1 file changed, 19 insertions(+), 15 deletions(-)
>> >
>> > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> > index c3bcd6eb2f42..75bc770ccf8c 100644
>> > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> > @@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
>> > {
>> > int ret;
>> >
>> > + arm_mmu500_reset(smmu);
>> > +
>> > /*
>> > * To address performance degradation in non-real time clients,
>> > * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
>> > @@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
>> > return ret;
>> > }
>> >
>> > -static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
>> > -{
>> > - const struct device_node *np = smmu->dev->of_node;
>> > -
>> > - arm_mmu500_reset(smmu);
>> > -
>> > - if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
>> > - return qcom_sdm845_smmu500_reset(smmu);
>> > -
>> > - return 0;
>> > -}
>> > -
>> > static const struct arm_smmu_impl qcom_smmu_impl = {
>> > .init_context = qcom_smmu_init_context,
>> > .cfg_probe = qcom_smmu_cfg_probe,
>> > .def_domain_type = qcom_smmu_def_domain_type,
>> > - .reset = qcom_smmu500_reset,
>> > + .reset = arm_mmu500_reset,
>> > + .write_s2cr = qcom_smmu_write_s2cr,
>> > + .tlb_sync = qcom_smmu_tlb_sync,
>> > +};
>> > +
>> > +static const struct arm_smmu_impl sdm845_smmu_500_impl = {
>> > + .init_context = qcom_smmu_init_context,
>> > + .cfg_probe = qcom_smmu_cfg_probe,
>> > + .def_domain_type = qcom_smmu_def_domain_type,
>> > + .reset = qcom_sdm845_smmu500_reset,
>> > .write_s2cr = qcom_smmu_write_s2cr,
>> > .tlb_sync = qcom_smmu_tlb_sync,
>> > };
>> > @@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = {
>> > static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
>> > .init_context = qcom_adreno_smmu_init_context,
>> > .def_domain_type = qcom_smmu_def_domain_type,
>> > - .reset = qcom_smmu500_reset,
>> > + .reset = arm_mmu500_reset,
>> > .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
>> > .write_sctlr = qcom_adreno_smmu_write_sctlr,
>> > .tlb_sync = qcom_smmu_tlb_sync,
>> > @@ -450,6 +449,11 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
>> > .adreno_impl = &qcom_adreno_smmu_impl,
>> > };
>> >
>> > +static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
>> > + .impl = &sdm845_smmu_500_impl,
>> > + /* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
>> separete -> separate
>
> Ack.
>
>> Also, while I'm here, does "No adreno impl" constitute adding a
>> compatible in the driver?
>
> Not sure that I got your question, please excuse me. Could you please
> describe what you meant?
> We already have qcom,sdm845-smmu-v2 in the match table, if that's your
> question. And there is no need for Adreno impl here, on sdm845 the
> SMMU connected to Adreno is v2 rather than mmu-500.
I'm asking because I wrote this patch:
https://lore.kernel.org/linux-iommu/20221103232632.217324-3-mailingradian@gmail.com/
on the basis that the SDM670 SMMU shouldn't have an adreno_impl. I
looked at the other code in this series, and it shouldn't be a problem
to use the fallback entry for SDM670. The adreno_impl is simply unused,
and would cause no problems if it were in the match data for any
platform. Going through the code, I'm considering dropping that patch I
wrote. My question should have been, "if I want to add support for an
SMMU, with no differences from a regular Qualcomm MMU-500, except
without an Adreno variant, does that deserve another entry and match
data?"
I would guess that this is not the case. The sdm845-smmu-v2 uses the
qcom_smmu_data, which includes the regular impl, even though there is no
regular sdm845-smmu-v2 that is not for Adreno.
> Probably I should change this to "No need for adreno impl....". Would
> that be better?
Yes, I think it would be better to clarify that this omission wasn't
made because it's necessary for the driver to work. That will possibly
save people from jumping to the match table, seeing this omission, and
writing a similar match data, only to have it dropped after reading
through the full driver.
>
>> > +};
>> > +
>> > static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
>> > { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
>> > { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
>> > @@ -460,7 +464,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
>> > { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
>> > { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
>> > { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
>> > - { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
>> > + { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
>> > { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
>> > { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
>> > { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
>> > --
>> > 2.35.1
>> >
>
>
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [RFC PATCH v2 08/11] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500
@ 2022-11-05 1:42 ` Richard Acayan
0 siblings, 0 replies; 44+ messages in thread
From: Richard Acayan @ 2022-11-05 1:42 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark,
Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
On Sat, Nov 05, 2022 at 03:02:15AM +0300, Dmitry Baryshkov wrote:
> On Sat, 5 Nov 2022 at 01:16, Richard Acayan <mailingradian@gmail.com> wrote:
>>
>> On Wed, Nov 02, 2022 at 09:44:17PM +0300, Dmitry Baryshkov wrote:
>> > There is only one platform, which needs special care in the reset
>> > function, the SDM845. Add special handler for sdm845 and drop the
>> > qcom_smmu500_reset() function.
>> >
>> > Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
>> > Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
>> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> > ---
>> > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 34 ++++++++++++----------
>> > 1 file changed, 19 insertions(+), 15 deletions(-)
>> >
>> > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> > index c3bcd6eb2f42..75bc770ccf8c 100644
>> > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> > @@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
>> > {
>> > int ret;
>> >
>> > + arm_mmu500_reset(smmu);
>> > +
>> > /*
>> > * To address performance degradation in non-real time clients,
>> > * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
>> > @@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
>> > return ret;
>> > }
>> >
>> > -static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
>> > -{
>> > - const struct device_node *np = smmu->dev->of_node;
>> > -
>> > - arm_mmu500_reset(smmu);
>> > -
>> > - if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
>> > - return qcom_sdm845_smmu500_reset(smmu);
>> > -
>> > - return 0;
>> > -}
>> > -
>> > static const struct arm_smmu_impl qcom_smmu_impl = {
>> > .init_context = qcom_smmu_init_context,
>> > .cfg_probe = qcom_smmu_cfg_probe,
>> > .def_domain_type = qcom_smmu_def_domain_type,
>> > - .reset = qcom_smmu500_reset,
>> > + .reset = arm_mmu500_reset,
>> > + .write_s2cr = qcom_smmu_write_s2cr,
>> > + .tlb_sync = qcom_smmu_tlb_sync,
>> > +};
>> > +
>> > +static const struct arm_smmu_impl sdm845_smmu_500_impl = {
>> > + .init_context = qcom_smmu_init_context,
>> > + .cfg_probe = qcom_smmu_cfg_probe,
>> > + .def_domain_type = qcom_smmu_def_domain_type,
>> > + .reset = qcom_sdm845_smmu500_reset,
>> > .write_s2cr = qcom_smmu_write_s2cr,
>> > .tlb_sync = qcom_smmu_tlb_sync,
>> > };
>> > @@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = {
>> > static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
>> > .init_context = qcom_adreno_smmu_init_context,
>> > .def_domain_type = qcom_smmu_def_domain_type,
>> > - .reset = qcom_smmu500_reset,
>> > + .reset = arm_mmu500_reset,
>> > .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
>> > .write_sctlr = qcom_adreno_smmu_write_sctlr,
>> > .tlb_sync = qcom_smmu_tlb_sync,
>> > @@ -450,6 +449,11 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
>> > .adreno_impl = &qcom_adreno_smmu_impl,
>> > };
>> >
>> > +static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
>> > + .impl = &sdm845_smmu_500_impl,
>> > + /* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
>> separete -> separate
>
> Ack.
>
>> Also, while I'm here, does "No adreno impl" constitute adding a
>> compatible in the driver?
>
> Not sure that I got your question, please excuse me. Could you please
> describe what you meant?
> We already have qcom,sdm845-smmu-v2 in the match table, if that's your
> question. And there is no need for Adreno impl here, on sdm845 the
> SMMU connected to Adreno is v2 rather than mmu-500.
I'm asking because I wrote this patch:
https://lore.kernel.org/linux-iommu/20221103232632.217324-3-mailingradian@gmail.com/
on the basis that the SDM670 SMMU shouldn't have an adreno_impl. I
looked at the other code in this series, and it shouldn't be a problem
to use the fallback entry for SDM670. The adreno_impl is simply unused,
and would cause no problems if it were in the match data for any
platform. Going through the code, I'm considering dropping that patch I
wrote. My question should have been, "if I want to add support for an
SMMU, with no differences from a regular Qualcomm MMU-500, except
without an Adreno variant, does that deserve another entry and match
data?"
I would guess that this is not the case. The sdm845-smmu-v2 uses the
qcom_smmu_data, which includes the regular impl, even though there is no
regular sdm845-smmu-v2 that is not for Adreno.
> Probably I should change this to "No need for adreno impl....". Would
> that be better?
Yes, I think it would be better to clarify that this omission wasn't
made because it's necessary for the driver to work. That will possibly
save people from jumping to the match table, seeing this omission, and
writing a similar match data, only to have it dropped after reading
through the full driver.
>
>> > +};
>> > +
>> > static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
>> > { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
>> > { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
>> > @@ -460,7 +464,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
>> > { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
>> > { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
>> > { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
>> > - { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data },
>> > + { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
>> > { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
>> > { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
>> > { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
>> > --
>> > 2.35.1
>> >
>
>
>
> --
> With best wishes
> Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* [RFC PATCH v2 09/11] iommu/arm-smmu-qcom: Merge table from arm-smmu-qcom-debug into match data
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 18:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
There is little point in having a separate match table in
arm-smmu-qcom-debug.c. Merge it into the main match data table in
arm-smmu-qcom.c
Note, this also enables debug support for sm6375 and ACPI-based sc8180x
systems, since these SoCs are expected to support tlb_sync debug.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 91 -------------------
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 46 +++++++---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 16 +++-
3 files changed, 43 insertions(+), 110 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
index 6eed8e67a0ca..74e9ef2fd580 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
@@ -10,16 +10,6 @@
#include "arm-smmu.h"
#include "arm-smmu-qcom.h"
-enum qcom_smmu_impl_reg_offset {
- QCOM_SMMU_TBU_PWR_STATUS,
- QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
- QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
-};
-
-struct qcom_smmu_config {
- const u32 *reg_offset;
-};
-
void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
{
int ret;
@@ -59,84 +49,3 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
tbu_pwr_status, sync_inv_ack, sync_inv_progress);
}
}
-
-/* Implementation Defined Register Space 0 register offsets */
-static const u32 qcom_smmu_impl0_reg_offset[] = {
- [QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
- [QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
- [QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
-};
-
-static const struct qcom_smmu_config qcm2290_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sc7180_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sc7280_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sc8180x_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sc8280xp_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm6125_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm6350_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm8150_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm8250_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm8350_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm8450_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct of_device_id __maybe_unused qcom_smmu_impl_debug_match[] = {
- { .compatible = "qcom,msm8998-smmu-v2" },
- { .compatible = "qcom,qcm2290-smmu-500", .data = &qcm2290_smmu_cfg },
- { .compatible = "qcom,sc7180-smmu-500", .data = &sc7180_smmu_cfg },
- { .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_cfg},
- { .compatible = "qcom,sc8180x-smmu-500", .data = &sc8180x_smmu_cfg },
- { .compatible = "qcom,sc8280xp-smmu-500", .data = &sc8280xp_smmu_cfg },
- { .compatible = "qcom,sdm630-smmu-v2" },
- { .compatible = "qcom,sdm845-smmu-500" },
- { .compatible = "qcom,sm6125-smmu-500", .data = &sm6125_smmu_cfg},
- { .compatible = "qcom,sm6350-smmu-500", .data = &sm6350_smmu_cfg},
- { .compatible = "qcom,sm8150-smmu-500", .data = &sm8150_smmu_cfg },
- { .compatible = "qcom,sm8250-smmu-500", .data = &sm8250_smmu_cfg },
- { .compatible = "qcom,sm8350-smmu-500", .data = &sm8350_smmu_cfg },
- { .compatible = "qcom,sm8450-smmu-500", .data = &sm8450_smmu_cfg },
- { }
-};
-
-const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)
-{
- const struct of_device_id *match;
- const struct device_node *np = smmu->dev->of_node;
-
- match = of_match_node(qcom_smmu_impl_debug_match, np);
- if (!match)
- return NULL;
-
- return match->data;
-}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 75bc770ccf8c..20cbb39cb670 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -430,11 +430,22 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
return ERR_PTR(-ENOMEM);
qsmmu->smmu.impl = impl;
- qsmmu->cfg = qcom_smmu_impl_data(smmu);
+ qsmmu->cfg = data->cfg;
return &qsmmu->smmu;
}
+/* Implementation Defined Register Space 0 register offsets */
+static const u32 qcom_smmu_impl0_reg_offset[] = {
+ [QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
+ [QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
+ [QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
+};
+
+static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
+ .reg_offset = qcom_smmu_impl0_reg_offset,
+};
+
/*
* It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
* there are not enough context banks.
@@ -452,26 +463,33 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
.impl = &sdm845_smmu_500_impl,
/* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
+ /* No debug configuration */
+};
+
+static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
+ .impl = &qcom_smmu_impl,
+ .adreno_impl = &qcom_adreno_smmu_impl,
+ .cfg = &qcom_smmu_impl0_cfg,
};
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
- { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
- { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ }
};
@@ -492,7 +510,7 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
if (np == NULL) {
/* Match platform for ACPI boot */
if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
- return qcom_smmu_create(smmu, &qcom_smmu_data);
+ return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);
}
#endif
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index 424d8d342ce0..593910567b88 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -14,20 +14,26 @@ struct qcom_smmu {
u32 stall_enabled;
};
+enum qcom_smmu_impl_reg_offset {
+ QCOM_SMMU_TBU_PWR_STATUS,
+ QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
+ QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
+};
+
+struct qcom_smmu_config {
+ const u32 *reg_offset;
+};
+
struct qcom_smmu_match_data {
+ const struct qcom_smmu_config *cfg;
const struct arm_smmu_impl *impl;
const struct arm_smmu_impl *adreno_impl;
};
#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu);
-const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu);
#else
static inline void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) { }
-static inline const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)
-{
- return NULL;
-}
#endif
#endif /* _ARM_SMMU_QCOM_H */
--
2.35.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC PATCH v2 09/11] iommu/arm-smmu-qcom: Merge table from arm-smmu-qcom-debug into match data
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
There is little point in having a separate match table in
arm-smmu-qcom-debug.c. Merge it into the main match data table in
arm-smmu-qcom.c
Note, this also enables debug support for sm6375 and ACPI-based sc8180x
systems, since these SoCs are expected to support tlb_sync debug.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 91 -------------------
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 46 +++++++---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 16 +++-
3 files changed, 43 insertions(+), 110 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
index 6eed8e67a0ca..74e9ef2fd580 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
@@ -10,16 +10,6 @@
#include "arm-smmu.h"
#include "arm-smmu-qcom.h"
-enum qcom_smmu_impl_reg_offset {
- QCOM_SMMU_TBU_PWR_STATUS,
- QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
- QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
-};
-
-struct qcom_smmu_config {
- const u32 *reg_offset;
-};
-
void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
{
int ret;
@@ -59,84 +49,3 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
tbu_pwr_status, sync_inv_ack, sync_inv_progress);
}
}
-
-/* Implementation Defined Register Space 0 register offsets */
-static const u32 qcom_smmu_impl0_reg_offset[] = {
- [QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
- [QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
- [QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
-};
-
-static const struct qcom_smmu_config qcm2290_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sc7180_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sc7280_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sc8180x_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sc8280xp_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm6125_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm6350_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm8150_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm8250_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm8350_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct qcom_smmu_config sm8450_smmu_cfg = {
- .reg_offset = qcom_smmu_impl0_reg_offset,
-};
-
-static const struct of_device_id __maybe_unused qcom_smmu_impl_debug_match[] = {
- { .compatible = "qcom,msm8998-smmu-v2" },
- { .compatible = "qcom,qcm2290-smmu-500", .data = &qcm2290_smmu_cfg },
- { .compatible = "qcom,sc7180-smmu-500", .data = &sc7180_smmu_cfg },
- { .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_cfg},
- { .compatible = "qcom,sc8180x-smmu-500", .data = &sc8180x_smmu_cfg },
- { .compatible = "qcom,sc8280xp-smmu-500", .data = &sc8280xp_smmu_cfg },
- { .compatible = "qcom,sdm630-smmu-v2" },
- { .compatible = "qcom,sdm845-smmu-500" },
- { .compatible = "qcom,sm6125-smmu-500", .data = &sm6125_smmu_cfg},
- { .compatible = "qcom,sm6350-smmu-500", .data = &sm6350_smmu_cfg},
- { .compatible = "qcom,sm8150-smmu-500", .data = &sm8150_smmu_cfg },
- { .compatible = "qcom,sm8250-smmu-500", .data = &sm8250_smmu_cfg },
- { .compatible = "qcom,sm8350-smmu-500", .data = &sm8350_smmu_cfg },
- { .compatible = "qcom,sm8450-smmu-500", .data = &sm8450_smmu_cfg },
- { }
-};
-
-const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)
-{
- const struct of_device_id *match;
- const struct device_node *np = smmu->dev->of_node;
-
- match = of_match_node(qcom_smmu_impl_debug_match, np);
- if (!match)
- return NULL;
-
- return match->data;
-}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 75bc770ccf8c..20cbb39cb670 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -430,11 +430,22 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
return ERR_PTR(-ENOMEM);
qsmmu->smmu.impl = impl;
- qsmmu->cfg = qcom_smmu_impl_data(smmu);
+ qsmmu->cfg = data->cfg;
return &qsmmu->smmu;
}
+/* Implementation Defined Register Space 0 register offsets */
+static const u32 qcom_smmu_impl0_reg_offset[] = {
+ [QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
+ [QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
+ [QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
+};
+
+static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
+ .reg_offset = qcom_smmu_impl0_reg_offset,
+};
+
/*
* It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
* there are not enough context banks.
@@ -452,26 +463,33 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
.impl = &sdm845_smmu_500_impl,
/* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
+ /* No debug configuration */
+};
+
+static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
+ .impl = &qcom_smmu_impl,
+ .adreno_impl = &qcom_adreno_smmu_impl,
+ .cfg = &qcom_smmu_impl0_cfg,
};
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
- { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
- { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_data },
- { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ }
};
@@ -492,7 +510,7 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
if (np == NULL) {
/* Match platform for ACPI boot */
if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
- return qcom_smmu_create(smmu, &qcom_smmu_data);
+ return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);
}
#endif
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index 424d8d342ce0..593910567b88 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -14,20 +14,26 @@ struct qcom_smmu {
u32 stall_enabled;
};
+enum qcom_smmu_impl_reg_offset {
+ QCOM_SMMU_TBU_PWR_STATUS,
+ QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
+ QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
+};
+
+struct qcom_smmu_config {
+ const u32 *reg_offset;
+};
+
struct qcom_smmu_match_data {
+ const struct qcom_smmu_config *cfg;
const struct arm_smmu_impl *impl;
const struct arm_smmu_impl *adreno_impl;
};
#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu);
-const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu);
#else
static inline void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) { }
-static inline const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)
-{
- return NULL;
-}
#endif
#endif /* _ARM_SMMU_QCOM_H */
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [RFC PATCH v2 10/11] iommu/arm-smmu-qcom: Stop using mmu500 reset for v2 MMUs
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 18:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
The arm_mmu500_reset() writes into registers specific for MMU500. For
the generic ARM SMMU v2 these registers (sACR) are defined as
'implementation defined'. Downstream Qualcomm driver for SMMUv2 doesn't
touch them.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 41 ++++++++++++++++------
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 20cbb39cb670..9abc40c00f3e 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -376,7 +376,15 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
return ret;
}
-static const struct arm_smmu_impl qcom_smmu_impl = {
+static const struct arm_smmu_impl qcom_smmu_v2_impl = {
+ .init_context = qcom_smmu_init_context,
+ .cfg_probe = qcom_smmu_cfg_probe,
+ .def_domain_type = qcom_smmu_def_domain_type,
+ .write_s2cr = qcom_smmu_write_s2cr,
+ .tlb_sync = qcom_smmu_tlb_sync,
+};
+
+static const struct arm_smmu_impl qcom_smmu_500_impl = {
.init_context = qcom_smmu_init_context,
.cfg_probe = qcom_smmu_cfg_probe,
.def_domain_type = qcom_smmu_def_domain_type,
@@ -394,7 +402,15 @@ static const struct arm_smmu_impl sdm845_smmu_500_impl = {
.tlb_sync = qcom_smmu_tlb_sync,
};
-static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
+static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
+ .init_context = qcom_adreno_smmu_init_context,
+ .def_domain_type = qcom_smmu_def_domain_type,
+ .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
+ .write_sctlr = qcom_adreno_smmu_write_sctlr,
+ .tlb_sync = qcom_smmu_tlb_sync,
+};
+
+static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = {
.init_context = qcom_adreno_smmu_init_context,
.def_domain_type = qcom_smmu_def_domain_type,
.reset = arm_mmu500_reset,
@@ -452,12 +468,17 @@ static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
*/
static const struct qcom_smmu_match_data msm8996_smmu_data = {
.impl = NULL,
- .adreno_impl = &qcom_adreno_smmu_impl,
+ .adreno_impl = &qcom_adreno_smmu_v2_impl,
+};
+
+static const struct qcom_smmu_match_data qcom_smmu_v2_data = {
+ .impl = &qcom_smmu_v2_impl,
+ .adreno_impl = &qcom_adreno_smmu_v2_impl,
};
static const struct qcom_smmu_match_data qcom_smmu_data = {
- .impl = &qcom_smmu_impl,
- .adreno_impl = &qcom_adreno_smmu_impl,
+ .impl = &qcom_smmu_500_impl,
+ .adreno_impl = &qcom_adreno_smmu_500_impl,
};
static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
@@ -467,21 +488,21 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
};
static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
- .impl = &qcom_smmu_impl,
- .adreno_impl = &qcom_adreno_smmu_impl,
+ .impl = &qcom_smmu_500_impl,
+ .adreno_impl = &qcom_adreno_smmu_500_impl,
.cfg = &qcom_smmu_impl0_cfg,
};
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
- { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
+ { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
- { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
- { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
+ { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
--
2.35.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC PATCH v2 10/11] iommu/arm-smmu-qcom: Stop using mmu500 reset for v2 MMUs
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
The arm_mmu500_reset() writes into registers specific for MMU500. For
the generic ARM SMMU v2 these registers (sACR) are defined as
'implementation defined'. Downstream Qualcomm driver for SMMUv2 doesn't
touch them.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 41 ++++++++++++++++------
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 20cbb39cb670..9abc40c00f3e 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -376,7 +376,15 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
return ret;
}
-static const struct arm_smmu_impl qcom_smmu_impl = {
+static const struct arm_smmu_impl qcom_smmu_v2_impl = {
+ .init_context = qcom_smmu_init_context,
+ .cfg_probe = qcom_smmu_cfg_probe,
+ .def_domain_type = qcom_smmu_def_domain_type,
+ .write_s2cr = qcom_smmu_write_s2cr,
+ .tlb_sync = qcom_smmu_tlb_sync,
+};
+
+static const struct arm_smmu_impl qcom_smmu_500_impl = {
.init_context = qcom_smmu_init_context,
.cfg_probe = qcom_smmu_cfg_probe,
.def_domain_type = qcom_smmu_def_domain_type,
@@ -394,7 +402,15 @@ static const struct arm_smmu_impl sdm845_smmu_500_impl = {
.tlb_sync = qcom_smmu_tlb_sync,
};
-static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
+static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
+ .init_context = qcom_adreno_smmu_init_context,
+ .def_domain_type = qcom_smmu_def_domain_type,
+ .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
+ .write_sctlr = qcom_adreno_smmu_write_sctlr,
+ .tlb_sync = qcom_smmu_tlb_sync,
+};
+
+static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = {
.init_context = qcom_adreno_smmu_init_context,
.def_domain_type = qcom_smmu_def_domain_type,
.reset = arm_mmu500_reset,
@@ -452,12 +468,17 @@ static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
*/
static const struct qcom_smmu_match_data msm8996_smmu_data = {
.impl = NULL,
- .adreno_impl = &qcom_adreno_smmu_impl,
+ .adreno_impl = &qcom_adreno_smmu_v2_impl,
+};
+
+static const struct qcom_smmu_match_data qcom_smmu_v2_data = {
+ .impl = &qcom_smmu_v2_impl,
+ .adreno_impl = &qcom_adreno_smmu_v2_impl,
};
static const struct qcom_smmu_match_data qcom_smmu_data = {
- .impl = &qcom_smmu_impl,
- .adreno_impl = &qcom_adreno_smmu_impl,
+ .impl = &qcom_smmu_500_impl,
+ .adreno_impl = &qcom_adreno_smmu_500_impl,
};
static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
@@ -467,21 +488,21 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
};
static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
- .impl = &qcom_smmu_impl,
- .adreno_impl = &qcom_adreno_smmu_impl,
+ .impl = &qcom_smmu_500_impl,
+ .adreno_impl = &qcom_adreno_smmu_500_impl,
.cfg = &qcom_smmu_impl0_cfg,
};
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
- { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
+ { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
- { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
- { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
+ { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
+ { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
--
2.35.1
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^ permalink raw reply related [flat|nested] 44+ messages in thread
* [RFC PATCH v2 11/11] iommu/arm-smmu-qcom: Add generic qcom,smmu-500 match entry
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-02 18:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
Add generic qcom,smmu-500 compatibility string. Newer platforms should
use this generic entry rather than declaring per-SoC entries.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 9abc40c00f3e..3be81338a25b 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -493,6 +493,10 @@ static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
.cfg = &qcom_smmu_impl0_cfg,
};
+/*
+ * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
+ * special handling and can not be covered by the qcom,smmu-500 entry.
+ */
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
@@ -511,6 +515,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
{ }
};
--
2.35.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC PATCH v2 11/11] iommu/arm-smmu-qcom: Add generic qcom,smmu-500 match entry
@ 2022-11-02 18:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-02 18:44 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Clark
Cc: Vinod Koul, Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm,
iommu, devicetree, freedreno
Add generic qcom,smmu-500 compatibility string. Newer platforms should
use this generic entry rather than declaring per-SoC entries.
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 9abc40c00f3e..3be81338a25b 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -493,6 +493,10 @@ static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
.cfg = &qcom_smmu_impl0_cfg,
};
+/*
+ * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
+ * special handling and can not be covered by the qcom,smmu-500 entry.
+ */
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
@@ -511,6 +515,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
{ }
};
--
2.35.1
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^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [RFC PATCH v2 00/11] iommu/arm-smmu-qcom: Rework Qualcomm SMMU bindings and implementation
2022-11-02 18:44 ` Dmitry Baryshkov
@ 2022-11-14 14:23 ` Will Deacon
-1 siblings, 0 replies; 44+ messages in thread
From: Will Deacon @ 2022-11-14 14:23 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Robin Murphy, Joerg Roedel, Rob Herring, Krzysztof Kozlowski,
Bjorn Andersson, Konrad Dybcio, Rob Clark, Vinod Koul,
Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm, iommu,
devicetree, freedreno
On Wed, Nov 02, 2022 at 09:44:09PM +0300, Dmitry Baryshkov wrote:
> The main goal of this patchset is to define a generic qcom,smmu-500
> binding to be used by newer Qualcomm platforms instead of defining each
> and every SoC line with no actual differences between the compats.
Thanks for doing this, I really like the cleanup and the possibility
that we can stop adding all these pointless strings every release!
It looks like Bjorn picked up patch 1, so could you please rebase the
rest of the series onto my SMMU bindings queue:
https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/bindings
and address the minor review comments you had so that I can pick this up?
Cheers,
Will
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC PATCH v2 00/11] iommu/arm-smmu-qcom: Rework Qualcomm SMMU bindings and implementation
@ 2022-11-14 14:23 ` Will Deacon
0 siblings, 0 replies; 44+ messages in thread
From: Will Deacon @ 2022-11-14 14:23 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Robin Murphy, Joerg Roedel, Rob Herring, Krzysztof Kozlowski,
Bjorn Andersson, Konrad Dybcio, Rob Clark, Vinod Koul,
Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm, iommu,
devicetree, freedreno
On Wed, Nov 02, 2022 at 09:44:09PM +0300, Dmitry Baryshkov wrote:
> The main goal of this patchset is to define a generic qcom,smmu-500
> binding to be used by newer Qualcomm platforms instead of defining each
> and every SoC line with no actual differences between the compats.
Thanks for doing this, I really like the cleanup and the possibility
that we can stop adding all these pointless strings every release!
It looks like Bjorn picked up patch 1, so could you please rebase the
rest of the series onto my SMMU bindings queue:
https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/bindings
and address the minor review comments you had so that I can pick this up?
Cheers,
Will
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC PATCH v2 00/11] iommu/arm-smmu-qcom: Rework Qualcomm SMMU bindings and implementation
2022-11-14 14:23 ` Will Deacon
@ 2022-11-14 17:07 ` Dmitry Baryshkov
-1 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-14 17:07 UTC (permalink / raw)
To: Will Deacon
Cc: Robin Murphy, Joerg Roedel, Rob Herring, Krzysztof Kozlowski,
Bjorn Andersson, Konrad Dybcio, Rob Clark, Vinod Koul,
Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm, iommu,
devicetree, freedreno
On 14/11/2022 17:23, Will Deacon wrote:
> On Wed, Nov 02, 2022 at 09:44:09PM +0300, Dmitry Baryshkov wrote:
>> The main goal of this patchset is to define a generic qcom,smmu-500
>> binding to be used by newer Qualcomm platforms instead of defining each
>> and every SoC line with no actual differences between the compats.
>
> Thanks for doing this, I really like the cleanup and the possibility
> that we can stop adding all these pointless strings every release!
>
> It looks like Bjorn picked up patch 1, so could you please rebase the
> rest of the series onto my SMMU bindings queue:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/bindings
>
> and address the minor review comments you had so that I can pick this up?
Done, thank you!
https://lore.kernel.org/linux-arm-msm/20221114170635.1406534-1-dmitry.baryshkov@linaro.org
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC PATCH v2 00/11] iommu/arm-smmu-qcom: Rework Qualcomm SMMU bindings and implementation
@ 2022-11-14 17:07 ` Dmitry Baryshkov
0 siblings, 0 replies; 44+ messages in thread
From: Dmitry Baryshkov @ 2022-11-14 17:07 UTC (permalink / raw)
To: Will Deacon
Cc: Robin Murphy, Joerg Roedel, Rob Herring, Krzysztof Kozlowski,
Bjorn Andersson, Konrad Dybcio, Rob Clark, Vinod Koul,
Sai Prakash Ranjan, linux-arm-kernel, linux-arm-msm, iommu,
devicetree, freedreno
On 14/11/2022 17:23, Will Deacon wrote:
> On Wed, Nov 02, 2022 at 09:44:09PM +0300, Dmitry Baryshkov wrote:
>> The main goal of this patchset is to define a generic qcom,smmu-500
>> binding to be used by newer Qualcomm platforms instead of defining each
>> and every SoC line with no actual differences between the compats.
>
> Thanks for doing this, I really like the cleanup and the possibility
> that we can stop adding all these pointless strings every release!
>
> It looks like Bjorn picked up patch 1, so could you please rebase the
> rest of the series onto my SMMU bindings queue:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/bindings
>
> and address the minor review comments you had so that I can pick this up?
Done, thank you!
https://lore.kernel.org/linux-arm-msm/20221114170635.1406534-1-dmitry.baryshkov@linaro.org
--
With best wishes
Dmitry
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^ permalink raw reply [flat|nested] 44+ messages in thread