From: Chen Guokai <chenguokai17@mails.ucas.ac.cn> To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, rostedt@goodmis.org, mingo@redhat.com, sfr@canb.auug.org.au Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, liaochang1@huawei.com, Liao Chang <liaoclark@163.com> Subject: [PATCH v4 0/8] Add OPTPROBES feature on RISCV Date: Sun, 6 Nov 2022 18:03:08 +0800 [thread overview] Message-ID: <20221106100316.2803176-1-chenguokai17@mails.ucas.ac.cn> (raw) From: Liao Chang <liaoclark@163.com> From: Liao Chang <liaochang1@huawei.com> Add jump optimization support for RISC-V. Replaces ebreak instructions used by normal kprobes with an auipc+jalr instruction pair, at the aim of suppressing the probe-hit overhead. All known optprobe-capable RISC architectures have been using a single jump or branch instructions while this patch chooses not. RISC-V has a quite limited jump range (4KB or 2MB) for both its branch and jump instructions, which prevent optimizations from supporting probes that spread all over the kernel. Auipc-jalr instruction pair is introduced with a much wider jump range (4GB), where auipc loads the upper 12 bits to a free register and jalr Deaconappends the lower 20 bits to form a 32 bit immediate. Note that returns from probe handler requires another free register. As kprobes can appear almost anywhere inside the kernel, the free register should be found in a generic way, not depending on calling convention or any other regulations. The algorithm for finding the free register is inspired by the register renaming in modern processors. From the perspective of register renaming, a register could be represented as two different registers if two neighbour instructions both write to it but no one ever reads. Extending this fact, a register is considered to be free if there is no read before its next write in the execution flow. We are free to change its value without interfering normal execution. Static analysis shows that 51% instructions of the kernel (default config) is capable of being replaced i.e. one free register can be found at both the start and end of replaced instruction pairs while the replaced instructions can be directly executed. Contribution: Chen Guokai invents the algorithm of searching free register, evaluate the ratio of optimizaion, the basic function support RVI kernel binary. Liao Chang adds the support for hybrid RVI and RVC kernel binary, fix some bugs with different kernel configure, refactor out entire feature into some individual patches. v4: Correct the sequence of Signed-off-by and Co-developed-by. v3: 1. Support of hybrid RVI and RVC kernel binary. 2. Refactor out entire feature into some individual patches. v2: 1. Adjust comments 2. Remove improper copyright 3. Clean up format issues that is no common practice 4. Extract common definition of instruction decoder 5. Fix race issue in SMP platform. v1: Chen Guokai contribute the basic functionality code. Liao Chang (8): riscv/kprobe: Prepare the skeleton to implement RISCV OPTPROBES feature riscv/kprobe: Allocate detour buffer from module area riscv/kprobe: Prepare the skeleton to prepare optimized kprobe riscv/kprobe: Add common RVI and RVC instruction decoder code riscv/kprobe: Search free register(s) to clobber for 'AUIPC/JALR' riscv/kprobe: Add code to check if kprobe can be optimized riscv/kprobe: Prepare detour buffer for optimized kprobe riscv/kprobe: Patch AUIPC/JALR pair to optimize kprobe arch/riscv/Kconfig | 1 + arch/riscv/include/asm/bug.h | 5 +- arch/riscv/include/asm/kprobes.h | 48 ++ arch/riscv/include/asm/patch.h | 1 + arch/riscv/kernel/patch.c | 22 +- arch/riscv/kernel/probes/Makefile | 1 + arch/riscv/kernel/probes/decode-insn.h | 145 ++++++ arch/riscv/kernel/probes/kprobes.c | 25 + arch/riscv/kernel/probes/opt.c | 602 ++++++++++++++++++++++ arch/riscv/kernel/probes/opt_trampoline.S | 137 +++++ arch/riscv/kernel/probes/simulate-insn.h | 41 ++ 11 files changed, 1023 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/kernel/probes/opt.c create mode 100644 arch/riscv/kernel/probes/opt_trampoline.S -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
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From: Chen Guokai <chenguokai17@mails.ucas.ac.cn> To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, rostedt@goodmis.org, mingo@redhat.com, sfr@canb.auug.org.au Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, liaochang1@huawei.com, Liao Chang <liaoclark@163.com> Subject: [PATCH v4 0/8] Add OPTPROBES feature on RISCV Date: Sun, 6 Nov 2022 18:03:08 +0800 [thread overview] Message-ID: <20221106100316.2803176-1-chenguokai17@mails.ucas.ac.cn> (raw) From: Liao Chang <liaoclark@163.com> From: Liao Chang <liaochang1@huawei.com> Add jump optimization support for RISC-V. Replaces ebreak instructions used by normal kprobes with an auipc+jalr instruction pair, at the aim of suppressing the probe-hit overhead. All known optprobe-capable RISC architectures have been using a single jump or branch instructions while this patch chooses not. RISC-V has a quite limited jump range (4KB or 2MB) for both its branch and jump instructions, which prevent optimizations from supporting probes that spread all over the kernel. Auipc-jalr instruction pair is introduced with a much wider jump range (4GB), where auipc loads the upper 12 bits to a free register and jalr Deaconappends the lower 20 bits to form a 32 bit immediate. Note that returns from probe handler requires another free register. As kprobes can appear almost anywhere inside the kernel, the free register should be found in a generic way, not depending on calling convention or any other regulations. The algorithm for finding the free register is inspired by the register renaming in modern processors. From the perspective of register renaming, a register could be represented as two different registers if two neighbour instructions both write to it but no one ever reads. Extending this fact, a register is considered to be free if there is no read before its next write in the execution flow. We are free to change its value without interfering normal execution. Static analysis shows that 51% instructions of the kernel (default config) is capable of being replaced i.e. one free register can be found at both the start and end of replaced instruction pairs while the replaced instructions can be directly executed. Contribution: Chen Guokai invents the algorithm of searching free register, evaluate the ratio of optimizaion, the basic function support RVI kernel binary. Liao Chang adds the support for hybrid RVI and RVC kernel binary, fix some bugs with different kernel configure, refactor out entire feature into some individual patches. v4: Correct the sequence of Signed-off-by and Co-developed-by. v3: 1. Support of hybrid RVI and RVC kernel binary. 2. Refactor out entire feature into some individual patches. v2: 1. Adjust comments 2. Remove improper copyright 3. Clean up format issues that is no common practice 4. Extract common definition of instruction decoder 5. Fix race issue in SMP platform. v1: Chen Guokai contribute the basic functionality code. Liao Chang (8): riscv/kprobe: Prepare the skeleton to implement RISCV OPTPROBES feature riscv/kprobe: Allocate detour buffer from module area riscv/kprobe: Prepare the skeleton to prepare optimized kprobe riscv/kprobe: Add common RVI and RVC instruction decoder code riscv/kprobe: Search free register(s) to clobber for 'AUIPC/JALR' riscv/kprobe: Add code to check if kprobe can be optimized riscv/kprobe: Prepare detour buffer for optimized kprobe riscv/kprobe: Patch AUIPC/JALR pair to optimize kprobe arch/riscv/Kconfig | 1 + arch/riscv/include/asm/bug.h | 5 +- arch/riscv/include/asm/kprobes.h | 48 ++ arch/riscv/include/asm/patch.h | 1 + arch/riscv/kernel/patch.c | 22 +- arch/riscv/kernel/probes/Makefile | 1 + arch/riscv/kernel/probes/decode-insn.h | 145 ++++++ arch/riscv/kernel/probes/kprobes.c | 25 + arch/riscv/kernel/probes/opt.c | 602 ++++++++++++++++++++++ arch/riscv/kernel/probes/opt_trampoline.S | 137 +++++ arch/riscv/kernel/probes/simulate-insn.h | 41 ++ 11 files changed, 1023 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/kernel/probes/opt.c create mode 100644 arch/riscv/kernel/probes/opt_trampoline.S -- 2.25.1
next reply other threads:[~2022-11-06 10:04 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-06 10:03 Chen Guokai [this message] 2022-11-06 10:03 ` [PATCH v4 0/8] Add OPTPROBES feature on RISCV Chen Guokai 2022-11-06 10:03 ` [PATCH v4 1/8] riscv/kprobe: Prepare the skeleton to implement RISCV OPTPROBES feature Chen Guokai 2022-11-06 10:03 ` Chen Guokai 2022-11-06 10:03 ` [PATCH v4 2/8] riscv/kprobe: Allocate detour buffer from module area Chen Guokai 2022-11-06 10:03 ` Chen Guokai 2022-11-17 1:25 ` Steven Rostedt 2022-11-17 1:25 ` Steven Rostedt 2022-11-18 1:41 ` liaochang (A) 2022-11-18 1:41 ` liaochang (A) 2022-11-06 10:03 ` [PATCH v4 3/8] riscv/kprobe: Prepare the skeleton to prepare optimized kprobe Chen Guokai 2022-11-06 10:03 ` Chen Guokai 2022-11-06 10:03 ` [PATCH v4 4/8] riscv/kprobe: Add common RVI and RVC instruction decoder code Chen Guokai 2022-11-06 10:03 ` Chen Guokai 2022-11-13 4:15 ` kernel test robot 2022-11-13 4:15 ` kernel test robot 2022-11-06 10:03 ` [PATCH v4 5/8] riscv/kprobe: Search free register(s) to clobber for 'AUIPC/JALR' Chen Guokai 2022-11-06 10:03 ` Chen Guokai 2022-11-07 16:55 ` Björn Töpel 2022-11-07 16:55 ` Björn Töpel 2022-11-06 10:03 ` [PATCH v4 6/8] riscv/kprobe: Add code to check if kprobe can be optimized Chen Guokai 2022-11-06 10:03 ` Chen Guokai 2022-11-07 16:56 ` Björn Töpel 2022-11-07 16:56 ` Björn Töpel 2022-11-06 10:03 ` [PATCH v4 7/8] riscv/kprobe: Prepare detour buffer for optimized kprobe Chen Guokai 2022-11-06 10:03 ` Chen Guokai 2022-11-06 10:03 ` [PATCH v4 8/8] riscv/kprobe: Patch AUIPC/JALR pair to optimize kprobe Chen Guokai 2022-11-06 10:03 ` Chen Guokai 2022-11-07 16:54 ` [PATCH v4 0/8] Add OPTPROBES feature on RISCV Björn Töpel 2022-11-07 16:54 ` Björn Töpel 2022-11-08 11:04 ` Xim 2022-11-08 11:04 ` Xim 2022-11-08 11:33 ` liaochang (A) 2022-11-08 11:33 ` liaochang (A) 2022-11-08 13:12 ` Björn Töpel 2022-11-08 13:12 ` Björn Töpel
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