* [PATCH v4 1/3] dt-bindings: imx6q-pcie: Handle various clock configurations
@ 2022-11-06 22:25 ` Marek Vasut
0 siblings, 0 replies; 12+ messages in thread
From: Marek Vasut @ 2022-11-06 22:25 UTC (permalink / raw)
To: devicetree
Cc: Marek Vasut, Alexander Stein, Fabio Estevam, Krzysztof Kozlowski,
Lucas Stach, Richard Zhu, Rob Herring, Shawn Guo,
linux-arm-kernel, NXP Linux Team
The i.MX SoCs have various clock configurations routed into the PCIe IP,
the list of clock is below. Document all those configurations in the DT
binding document.
All SoCs: pcie, pcie_bus
6QDL, 7D: + pcie_phy
6SX: + pcie_phy pcie_inbound_axi
8MQ: + pcie_phy pcie_aux
8MM, 8MP: + pcie_aux
Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: NXP Linux Team <linux-imx@nxp.com>
To: devicetree@vger.kernel.org
---
V2: - Add AB from Alex
V3: - Duplicate clock-names maxItems to mx6sx and mx8mq compatibles
- Flatten the if-else structure
- The validation no longer works and introduces errors like these:
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: clock-names:2: 'pcie_phy' was expected
V4: - Reinstate minItems: for clock-names in main section, turn the
last two clock-names items into enums to cover all IP variants.
- Add another allOf entry for mx6q/mx6qp/mx7d clock-names list.
- Adjust clock maxItems in the allOf section.
---
.../bindings/pci/fsl,imx6q-pcie.yaml | 73 +++++++++++++++++--
1 file changed, 68 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 376e739bcad40..2df73be0ffbea 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -14,9 +14,6 @@ description: |+
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
-allOf:
- - $ref: /schemas/pci/snps,dw-pcie.yaml#
-
properties:
compatible:
enum:
@@ -60,8 +57,8 @@ properties:
items:
- const: pcie
- const: pcie_bus
- - const: pcie_phy
- - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
+ - enum: [ pcie_phy, pcie_aux ]
+ - enum: [ pcie_aux, pcie_inbound_axi ]
num-lanes:
const: 1
@@ -177,6 +174,72 @@ required:
unevaluatedProperties: false
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-pcie
+ - fsl,imx6qp-pcie
+ - fsl,imx7d-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - const: pcie_phy
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx6sx-pcie
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - const: pcie_phy
+ - const: pcie_inbound_axi
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mq-pcie
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - const: pcie_phy
+ - const: pcie_aux
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8mm-pcie
+ - fsl,imx8mp-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - const: pcie_aux
+
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 1/3] dt-bindings: imx6q-pcie: Handle various clock configurations
@ 2022-11-06 22:25 ` Marek Vasut
0 siblings, 0 replies; 12+ messages in thread
From: Marek Vasut @ 2022-11-06 22:25 UTC (permalink / raw)
To: devicetree
Cc: Marek Vasut, Alexander Stein, Fabio Estevam, Krzysztof Kozlowski,
Lucas Stach, Richard Zhu, Rob Herring, Shawn Guo,
linux-arm-kernel, NXP Linux Team
The i.MX SoCs have various clock configurations routed into the PCIe IP,
the list of clock is below. Document all those configurations in the DT
binding document.
All SoCs: pcie, pcie_bus
6QDL, 7D: + pcie_phy
6SX: + pcie_phy pcie_inbound_axi
8MQ: + pcie_phy pcie_aux
8MM, 8MP: + pcie_aux
Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: NXP Linux Team <linux-imx@nxp.com>
To: devicetree@vger.kernel.org
---
V2: - Add AB from Alex
V3: - Duplicate clock-names maxItems to mx6sx and mx8mq compatibles
- Flatten the if-else structure
- The validation no longer works and introduces errors like these:
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: clock-names:2: 'pcie_phy' was expected
V4: - Reinstate minItems: for clock-names in main section, turn the
last two clock-names items into enums to cover all IP variants.
- Add another allOf entry for mx6q/mx6qp/mx7d clock-names list.
- Adjust clock maxItems in the allOf section.
---
.../bindings/pci/fsl,imx6q-pcie.yaml | 73 +++++++++++++++++--
1 file changed, 68 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 376e739bcad40..2df73be0ffbea 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -14,9 +14,6 @@ description: |+
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
-allOf:
- - $ref: /schemas/pci/snps,dw-pcie.yaml#
-
properties:
compatible:
enum:
@@ -60,8 +57,8 @@ properties:
items:
- const: pcie
- const: pcie_bus
- - const: pcie_phy
- - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
+ - enum: [ pcie_phy, pcie_aux ]
+ - enum: [ pcie_aux, pcie_inbound_axi ]
num-lanes:
const: 1
@@ -177,6 +174,72 @@ required:
unevaluatedProperties: false
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-pcie
+ - fsl,imx6qp-pcie
+ - fsl,imx7d-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - const: pcie_phy
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx6sx-pcie
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - const: pcie_phy
+ - const: pcie_inbound_axi
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mq-pcie
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - const: pcie_phy
+ - const: pcie_aux
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8mm-pcie
+ - fsl,imx8mp-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - const: pcie_aux
+
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 2/3] dt-bindings: imx6q-pcie: Handle various PD configurations
2022-11-06 22:25 ` Marek Vasut
@ 2022-11-06 22:25 ` Marek Vasut
-1 siblings, 0 replies; 12+ messages in thread
From: Marek Vasut @ 2022-11-06 22:25 UTC (permalink / raw)
To: devicetree
Cc: Marek Vasut, Fabio Estevam, Krzysztof Kozlowski, Lucas Stach,
Richard Zhu, Rob Herring, Shawn Guo, linux-arm-kernel,
NXP Linux Team
The i.MX SoCs have various power domain configurations routed into
the PCIe IP. MX6SX is the only one which contains 2 domains and also
uses power-domain-names. MX6QDL do not use any domains. All the rest
uses one domain and does not use power-domain-names anymore.
Document all those configurations in the DT binding document.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: NXP Linux Team <linux-imx@nxp.com>
To: devicetree@vger.kernel.org
---
V2: - Keep the power-domains description in the main section
V3: - Move power-domains back where they were originally (fixes V2)
- Do not use else: in allOf section
V4: - Special-case MX6Q and MX6QP in allOf section since they dont use PDs
- Drop minItems: from power-domains main section
- Handle anything which is not MX6SX,MX6Q,MX6QP as having one PD
---
.../bindings/pci/fsl,imx6q-pcie.yaml | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 2df73be0ffbea..b14c12a47cc1c 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -69,6 +69,7 @@ properties:
required properties for imx7d-pcie and imx8mq-pcie.
power-domains:
+ minItems: 1
items:
- description: The phandle pointing to the DISPLAY domain for
imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
@@ -77,6 +78,7 @@ properties:
for imx6sx-pcie.
power-domain-names:
+ minItems: 1
items:
- const: pcie
- const: pcie_phy
@@ -240,6 +242,47 @@ allOf:
- const: pcie_bus
- const: pcie_aux
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx6sx-pcie
+ then:
+ properties:
+ power-domains:
+ minItems: 2
+ maxItems: 2
+ power-domain-names:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-pcie
+ - fsl,imx6qp-pcie
+ then:
+ properties:
+ power-domains: false
+ power-domain-names: false
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6sx-pcie
+ - fsl,imx6q-pcie
+ - fsl,imx6qp-pcie
+ then:
+ properties:
+ power-domains:
+ maxItems: 1
+ power-domain-names: false
+
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 2/3] dt-bindings: imx6q-pcie: Handle various PD configurations
@ 2022-11-06 22:25 ` Marek Vasut
0 siblings, 0 replies; 12+ messages in thread
From: Marek Vasut @ 2022-11-06 22:25 UTC (permalink / raw)
To: devicetree
Cc: Marek Vasut, Fabio Estevam, Krzysztof Kozlowski, Lucas Stach,
Richard Zhu, Rob Herring, Shawn Guo, linux-arm-kernel,
NXP Linux Team
The i.MX SoCs have various power domain configurations routed into
the PCIe IP. MX6SX is the only one which contains 2 domains and also
uses power-domain-names. MX6QDL do not use any domains. All the rest
uses one domain and does not use power-domain-names anymore.
Document all those configurations in the DT binding document.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: NXP Linux Team <linux-imx@nxp.com>
To: devicetree@vger.kernel.org
---
V2: - Keep the power-domains description in the main section
V3: - Move power-domains back where they were originally (fixes V2)
- Do not use else: in allOf section
V4: - Special-case MX6Q and MX6QP in allOf section since they dont use PDs
- Drop minItems: from power-domains main section
- Handle anything which is not MX6SX,MX6Q,MX6QP as having one PD
---
.../bindings/pci/fsl,imx6q-pcie.yaml | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 2df73be0ffbea..b14c12a47cc1c 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -69,6 +69,7 @@ properties:
required properties for imx7d-pcie and imx8mq-pcie.
power-domains:
+ minItems: 1
items:
- description: The phandle pointing to the DISPLAY domain for
imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
@@ -77,6 +78,7 @@ properties:
for imx6sx-pcie.
power-domain-names:
+ minItems: 1
items:
- const: pcie
- const: pcie_phy
@@ -240,6 +242,47 @@ allOf:
- const: pcie_bus
- const: pcie_aux
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx6sx-pcie
+ then:
+ properties:
+ power-domains:
+ minItems: 2
+ maxItems: 2
+ power-domain-names:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-pcie
+ - fsl,imx6qp-pcie
+ then:
+ properties:
+ power-domains: false
+ power-domain-names: false
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6sx-pcie
+ - fsl,imx6q-pcie
+ - fsl,imx6qp-pcie
+ then:
+ properties:
+ power-domains:
+ maxItems: 1
+ power-domain-names: false
+
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 3/3] dt-bindings: imx6q-pcie: Handle more resets on legacy platforms
2022-11-06 22:25 ` Marek Vasut
@ 2022-11-06 22:25 ` Marek Vasut
-1 siblings, 0 replies; 12+ messages in thread
From: Marek Vasut @ 2022-11-06 22:25 UTC (permalink / raw)
To: devicetree
Cc: Marek Vasut, Fabio Estevam, Krzysztof Kozlowski, Lucas Stach,
Richard Zhu, Rob Herring, Shawn Guo, linux-arm-kernel,
NXP Linux Team
The i.MX6 and i.MX7D does not use block controller to toggle PCIe
reset, hence the PCIe DT description contains three reset entries
on these older SoCs. Add this exception into the binding document.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: NXP Linux Team <linux-imx@nxp.com>
To: devicetree@vger.kernel.org
---
V2: - Add mx8mq to 3-reset PCIe core variant
- Handle the resets in allOf section
V3: - Reinstate reset: maxItems:3 and add minItems:2
- Move reset-names back to main section
- The validation no longer works and introduces errors like these:
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: reset-names:0: 'pciephy' was expected
V4: - Reinstate reset minItems and maxItems
- Turn the first two reset-names items into enums to cover all
the various name combinations, sort the rest in allOf section
---
.../bindings/pci/fsl,imx6q-pcie.yaml | 34 +++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index b14c12a47cc1c..46fc29384ed34 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -84,14 +84,16 @@ properties:
- const: pcie_phy
resets:
+ minItems: 2
maxItems: 3
description: Phandles to PCIe-related reset lines exposed by SRC
IP block. Additional required by imx7d-pcie and imx8mq-pcie.
reset-names:
+ minItems: 2
items:
- - const: pciephy
- - const: apps
+ - enum: [ pciephy, apps ]
+ - enum: [ apps, turnoff ]
- const: turnoff
fsl,tx-deemph-gen1:
@@ -283,6 +285,34 @@ allOf:
maxItems: 1
power-domain-names: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-pcie
+ - fsl,imx6sx-pcie
+ - fsl,imx6qp-pcie
+ - fsl,imx7d-pcie
+ - fsl,imx8mq-pcie
+ then:
+ properties:
+ resets:
+ minItems: 3
+ reset-names:
+ items:
+ - const: pciephy
+ - const: apps
+ - const: turnoff
+ else:
+ properties:
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: apps
+ - const: turnoff
+
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 3/3] dt-bindings: imx6q-pcie: Handle more resets on legacy platforms
@ 2022-11-06 22:25 ` Marek Vasut
0 siblings, 0 replies; 12+ messages in thread
From: Marek Vasut @ 2022-11-06 22:25 UTC (permalink / raw)
To: devicetree
Cc: Marek Vasut, Fabio Estevam, Krzysztof Kozlowski, Lucas Stach,
Richard Zhu, Rob Herring, Shawn Guo, linux-arm-kernel,
NXP Linux Team
The i.MX6 and i.MX7D does not use block controller to toggle PCIe
reset, hence the PCIe DT description contains three reset entries
on these older SoCs. Add this exception into the binding document.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: NXP Linux Team <linux-imx@nxp.com>
To: devicetree@vger.kernel.org
---
V2: - Add mx8mq to 3-reset PCIe core variant
- Handle the resets in allOf section
V3: - Reinstate reset: maxItems:3 and add minItems:2
- Move reset-names back to main section
- The validation no longer works and introduces errors like these:
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: reset-names:0: 'pciephy' was expected
V4: - Reinstate reset minItems and maxItems
- Turn the first two reset-names items into enums to cover all
the various name combinations, sort the rest in allOf section
---
.../bindings/pci/fsl,imx6q-pcie.yaml | 34 +++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index b14c12a47cc1c..46fc29384ed34 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -84,14 +84,16 @@ properties:
- const: pcie_phy
resets:
+ minItems: 2
maxItems: 3
description: Phandles to PCIe-related reset lines exposed by SRC
IP block. Additional required by imx7d-pcie and imx8mq-pcie.
reset-names:
+ minItems: 2
items:
- - const: pciephy
- - const: apps
+ - enum: [ pciephy, apps ]
+ - enum: [ apps, turnoff ]
- const: turnoff
fsl,tx-deemph-gen1:
@@ -283,6 +285,34 @@ allOf:
maxItems: 1
power-domain-names: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-pcie
+ - fsl,imx6sx-pcie
+ - fsl,imx6qp-pcie
+ - fsl,imx7d-pcie
+ - fsl,imx8mq-pcie
+ then:
+ properties:
+ resets:
+ minItems: 3
+ reset-names:
+ items:
+ - const: pciephy
+ - const: apps
+ - const: turnoff
+ else:
+ properties:
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: apps
+ - const: turnoff
+
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v4 2/3] dt-bindings: imx6q-pcie: Handle various PD configurations
2022-11-06 22:25 ` Marek Vasut
@ 2022-11-08 18:15 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-08 18:15 UTC (permalink / raw)
To: Marek Vasut, devicetree
Cc: Fabio Estevam, Krzysztof Kozlowski, Lucas Stach, Richard Zhu,
Rob Herring, Shawn Guo, linux-arm-kernel, NXP Linux Team
On 06/11/2022 23:25, Marek Vasut wrote:
> The i.MX SoCs have various power domain configurations routed into
> the PCIe IP. MX6SX is the only one which contains 2 domains and also
> uses power-domain-names. MX6QDL do not use any domains. All the rest
> uses one domain and does not use power-domain-names anymore.
>
> Document all those configurations in the DT binding document.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 2/3] dt-bindings: imx6q-pcie: Handle various PD configurations
@ 2022-11-08 18:15 ` Krzysztof Kozlowski
0 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-08 18:15 UTC (permalink / raw)
To: Marek Vasut, devicetree
Cc: Fabio Estevam, Krzysztof Kozlowski, Lucas Stach, Richard Zhu,
Rob Herring, Shawn Guo, linux-arm-kernel, NXP Linux Team
On 06/11/2022 23:25, Marek Vasut wrote:
> The i.MX SoCs have various power domain configurations routed into
> the PCIe IP. MX6SX is the only one which contains 2 domains and also
> uses power-domain-names. MX6QDL do not use any domains. All the rest
> uses one domain and does not use power-domain-names anymore.
>
> Document all those configurations in the DT binding document.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 3/3] dt-bindings: imx6q-pcie: Handle more resets on legacy platforms
2022-11-06 22:25 ` Marek Vasut
@ 2022-11-08 18:17 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-08 18:17 UTC (permalink / raw)
To: Marek Vasut, devicetree
Cc: Fabio Estevam, Krzysztof Kozlowski, Lucas Stach, Richard Zhu,
Rob Herring, Shawn Guo, linux-arm-kernel, NXP Linux Team
On 06/11/2022 23:25, Marek Vasut wrote:
> The i.MX6 and i.MX7D does not use block controller to toggle PCIe
> reset, hence the PCIe DT description contains three reset entries
> on these older SoCs. Add this exception into the binding document.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: devicetree@vger.kernel.org
> ---
> V2: - Add mx8mq to 3-reset PCIe core variant
> - Handle the resets in allOf section
> V3: - Reinstate reset: maxItems:3 and add minItems:2
> - Move reset-names back to main section
> - The validation no longer works and introduces errors like these:
> arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: reset-names:0: 'pciephy' was expected
> V4: - Reinstate reset minItems and maxItems
> - Turn the first two reset-names items into enums to cover all
> the various name combinations, sort the rest in allOf section
> ---
> .../bindings/pci/fsl,imx6q-pcie.yaml | 34 +++++++++++++++++--
> 1 file changed, 32 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index b14c12a47cc1c..46fc29384ed34 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -84,14 +84,16 @@ properties:
> - const: pcie_phy
>
> resets:
> + minItems: 2
> maxItems: 3
> description: Phandles to PCIe-related reset lines exposed by SRC
> IP block. Additional required by imx7d-pcie and imx8mq-pcie.
>
> reset-names:
> + minItems: 2
> items:
> - - const: pciephy
> - - const: apps
> + - enum: [ pciephy, apps ]
> + - enum: [ apps, turnoff ]
> - const: turnoff
I would expect to remove all these entries. I asked to keep reset-names
with minIetms and maxItems. It works fine with your approach, but why
having the items in multiple places?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 3/3] dt-bindings: imx6q-pcie: Handle more resets on legacy platforms
@ 2022-11-08 18:17 ` Krzysztof Kozlowski
0 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-08 18:17 UTC (permalink / raw)
To: Marek Vasut, devicetree
Cc: Fabio Estevam, Krzysztof Kozlowski, Lucas Stach, Richard Zhu,
Rob Herring, Shawn Guo, linux-arm-kernel, NXP Linux Team
On 06/11/2022 23:25, Marek Vasut wrote:
> The i.MX6 and i.MX7D does not use block controller to toggle PCIe
> reset, hence the PCIe DT description contains three reset entries
> on these older SoCs. Add this exception into the binding document.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: devicetree@vger.kernel.org
> ---
> V2: - Add mx8mq to 3-reset PCIe core variant
> - Handle the resets in allOf section
> V3: - Reinstate reset: maxItems:3 and add minItems:2
> - Move reset-names back to main section
> - The validation no longer works and introduces errors like these:
> arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: reset-names:0: 'pciephy' was expected
> V4: - Reinstate reset minItems and maxItems
> - Turn the first two reset-names items into enums to cover all
> the various name combinations, sort the rest in allOf section
> ---
> .../bindings/pci/fsl,imx6q-pcie.yaml | 34 +++++++++++++++++--
> 1 file changed, 32 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index b14c12a47cc1c..46fc29384ed34 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -84,14 +84,16 @@ properties:
> - const: pcie_phy
>
> resets:
> + minItems: 2
> maxItems: 3
> description: Phandles to PCIe-related reset lines exposed by SRC
> IP block. Additional required by imx7d-pcie and imx8mq-pcie.
>
> reset-names:
> + minItems: 2
> items:
> - - const: pciephy
> - - const: apps
> + - enum: [ pciephy, apps ]
> + - enum: [ apps, turnoff ]
> - const: turnoff
I would expect to remove all these entries. I asked to keep reset-names
with minIetms and maxItems. It works fine with your approach, but why
having the items in multiple places?
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 3/3] dt-bindings: imx6q-pcie: Handle more resets on legacy platforms
2022-11-08 18:17 ` Krzysztof Kozlowski
@ 2022-11-09 0:23 ` Marek Vasut
-1 siblings, 0 replies; 12+ messages in thread
From: Marek Vasut @ 2022-11-09 0:23 UTC (permalink / raw)
To: Krzysztof Kozlowski, devicetree
Cc: Fabio Estevam, Krzysztof Kozlowski, Lucas Stach, Richard Zhu,
Rob Herring, Shawn Guo, linux-arm-kernel, NXP Linux Team
On 11/8/22 19:17, Krzysztof Kozlowski wrote:
> On 06/11/2022 23:25, Marek Vasut wrote:
>> The i.MX6 and i.MX7D does not use block controller to toggle PCIe
>> reset, hence the PCIe DT description contains three reset entries
>> on these older SoCs. Add this exception into the binding document.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> ---
>> Cc: Fabio Estevam <festevam@gmail.com>
>> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
>> Cc: Lucas Stach <l.stach@pengutronix.de>
>> Cc: Richard Zhu <hongxing.zhu@nxp.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Shawn Guo <shawnguo@kernel.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: NXP Linux Team <linux-imx@nxp.com>
>> To: devicetree@vger.kernel.org
>> ---
>> V2: - Add mx8mq to 3-reset PCIe core variant
>> - Handle the resets in allOf section
>> V3: - Reinstate reset: maxItems:3 and add minItems:2
>> - Move reset-names back to main section
>> - The validation no longer works and introduces errors like these:
>> arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: reset-names:0: 'pciephy' was expected
>> V4: - Reinstate reset minItems and maxItems
>> - Turn the first two reset-names items into enums to cover all
>> the various name combinations, sort the rest in allOf section
>> ---
>> .../bindings/pci/fsl,imx6q-pcie.yaml | 34 +++++++++++++++++--
>> 1 file changed, 32 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>> index b14c12a47cc1c..46fc29384ed34 100644
>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>> @@ -84,14 +84,16 @@ properties:
>> - const: pcie_phy
>>
>> resets:
>> + minItems: 2
>> maxItems: 3
>> description: Phandles to PCIe-related reset lines exposed by SRC
>> IP block. Additional required by imx7d-pcie and imx8mq-pcie.
>>
>> reset-names:
>> + minItems: 2
>> items:
>> - - const: pciephy
>> - - const: apps
>> + - enum: [ pciephy, apps ]
>> + - enum: [ apps, turnoff ]
>> - const: turnoff
>
> I would expect to remove all these entries. I asked to keep reset-names
> with minIetms and maxItems. It works fine with your approach, but why
> having the items in multiple places?
I feel like maybe I'm getting a bit lost in the complexity. I did that ^
and it does seem to work, so V5 is coming.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 3/3] dt-bindings: imx6q-pcie: Handle more resets on legacy platforms
@ 2022-11-09 0:23 ` Marek Vasut
0 siblings, 0 replies; 12+ messages in thread
From: Marek Vasut @ 2022-11-09 0:23 UTC (permalink / raw)
To: Krzysztof Kozlowski, devicetree
Cc: Fabio Estevam, Krzysztof Kozlowski, Lucas Stach, Richard Zhu,
Rob Herring, Shawn Guo, linux-arm-kernel, NXP Linux Team
On 11/8/22 19:17, Krzysztof Kozlowski wrote:
> On 06/11/2022 23:25, Marek Vasut wrote:
>> The i.MX6 and i.MX7D does not use block controller to toggle PCIe
>> reset, hence the PCIe DT description contains three reset entries
>> on these older SoCs. Add this exception into the binding document.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> ---
>> Cc: Fabio Estevam <festevam@gmail.com>
>> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
>> Cc: Lucas Stach <l.stach@pengutronix.de>
>> Cc: Richard Zhu <hongxing.zhu@nxp.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Shawn Guo <shawnguo@kernel.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: NXP Linux Team <linux-imx@nxp.com>
>> To: devicetree@vger.kernel.org
>> ---
>> V2: - Add mx8mq to 3-reset PCIe core variant
>> - Handle the resets in allOf section
>> V3: - Reinstate reset: maxItems:3 and add minItems:2
>> - Move reset-names back to main section
>> - The validation no longer works and introduces errors like these:
>> arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: reset-names:0: 'pciephy' was expected
>> V4: - Reinstate reset minItems and maxItems
>> - Turn the first two reset-names items into enums to cover all
>> the various name combinations, sort the rest in allOf section
>> ---
>> .../bindings/pci/fsl,imx6q-pcie.yaml | 34 +++++++++++++++++--
>> 1 file changed, 32 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>> index b14c12a47cc1c..46fc29384ed34 100644
>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>> @@ -84,14 +84,16 @@ properties:
>> - const: pcie_phy
>>
>> resets:
>> + minItems: 2
>> maxItems: 3
>> description: Phandles to PCIe-related reset lines exposed by SRC
>> IP block. Additional required by imx7d-pcie and imx8mq-pcie.
>>
>> reset-names:
>> + minItems: 2
>> items:
>> - - const: pciephy
>> - - const: apps
>> + - enum: [ pciephy, apps ]
>> + - enum: [ apps, turnoff ]
>> - const: turnoff
>
> I would expect to remove all these entries. I asked to keep reset-names
> with minIetms and maxItems. It works fine with your approach, but why
> having the items in multiple places?
I feel like maybe I'm getting a bit lost in the complexity. I did that ^
and it does seem to work, so V5 is coming.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-11-09 0:25 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-06 22:25 [PATCH v4 1/3] dt-bindings: imx6q-pcie: Handle various clock configurations Marek Vasut
2022-11-06 22:25 ` Marek Vasut
2022-11-06 22:25 ` [PATCH v4 2/3] dt-bindings: imx6q-pcie: Handle various PD configurations Marek Vasut
2022-11-06 22:25 ` Marek Vasut
2022-11-08 18:15 ` Krzysztof Kozlowski
2022-11-08 18:15 ` Krzysztof Kozlowski
2022-11-06 22:25 ` [PATCH v4 3/3] dt-bindings: imx6q-pcie: Handle more resets on legacy platforms Marek Vasut
2022-11-06 22:25 ` Marek Vasut
2022-11-08 18:17 ` Krzysztof Kozlowski
2022-11-08 18:17 ` Krzysztof Kozlowski
2022-11-09 0:23 ` Marek Vasut
2022-11-09 0:23 ` Marek Vasut
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