* [PATCH v2 1/3] arm: move KVM breakpoints helpers
2022-11-16 17:47 [PATCH v2 0/3] Add gdbstub support to HVF francesco.cagnin
@ 2022-11-16 17:47 ` francesco.cagnin
2022-11-22 10:06 ` Alex Bennée
2022-11-16 17:47 ` [PATCH v2 2/3] hvf: implement guest debugging on Apple Silicon hosts francesco.cagnin
2022-11-16 17:47 ` [PATCH v2 3/3] hvf: handle writes of MDSCR_EL1 and DBG*_EL1 francesco.cagnin
2 siblings, 1 reply; 10+ messages in thread
From: francesco.cagnin @ 2022-11-16 17:47 UTC (permalink / raw)
To: qemu-devel
Cc: mads, dirty, peter.maydell, qemu-arm, agraf, pbonzini,
alex.bennee, Francesco Cagnin
From: Francesco Cagnin <fcagnin@quarkslab.com>
These helpers will be also used for HVF. Aside from reformatting a
couple of comments for 'checkpatch.pl' and updating meson to compile
'hyp_gdbstub.c', this is just code motion.
Signed-off-by: Francesco Cagnin <fcagnin@quarkslab.com>
---
target/arm/hyp_gdbstub.c | 242 ++++++++++++++++++++++++++++++++++
target/arm/internals.h | 50 +++++++
target/arm/kvm64.c | 276 ---------------------------------------
target/arm/meson.build | 3 +-
4 files changed, 294 insertions(+), 277 deletions(-)
create mode 100644 target/arm/hyp_gdbstub.c
diff --git a/target/arm/hyp_gdbstub.c b/target/arm/hyp_gdbstub.c
new file mode 100644
index 0000000000..22b2b7de7b
--- /dev/null
+++ b/target/arm/hyp_gdbstub.c
@@ -0,0 +1,242 @@
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+#include "exec/gdbstub.h"
+
+/* Maximum and current break/watch point counts */
+int max_hw_bps, max_hw_wps;
+GArray *hw_breakpoints, *hw_watchpoints;
+
+/**
+ * insert_hw_breakpoint()
+ * @addr: address of breakpoint
+ *
+ * See ARM ARM D2.9.1 for details but here we are only going to create
+ * simple un-linked breakpoints (i.e. we don't chain breakpoints
+ * together to match address and context or vmid). The hardware is
+ * capable of fancier matching but that will require exposing that
+ * fanciness to GDB's interface
+ *
+ * DBGBCR<n>_EL1, Debug Breakpoint Control Registers
+ *
+ * 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0
+ * +------+------+-------+-----+----+------+-----+------+-----+---+
+ * | RES0 | BT | LBN | SSC | HMC| RES0 | BAS | RES0 | PMC | E |
+ * +------+------+-------+-----+----+------+-----+------+-----+---+
+ *
+ * BT: Breakpoint type (0 = unlinked address match)
+ * LBN: Linked BP number (0 = unused)
+ * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12)
+ * BAS: Byte Address Select (RES1 for AArch64)
+ * E: Enable bit
+ *
+ * DBGBVR<n>_EL1, Debug Breakpoint Value Registers
+ *
+ * 63 53 52 49 48 2 1 0
+ * +------+-----------+----------+-----+
+ * | RESS | VA[52:49] | VA[48:2] | 0 0 |
+ * +------+-----------+----------+-----+
+ *
+ * Depending on the addressing mode bits the top bits of the register
+ * are a sign extension of the highest applicable VA bit. Some
+ * versions of GDB don't do it correctly so we ensure they are correct
+ * here so future PC comparisons will work properly.
+ */
+
+int insert_hw_breakpoint(target_ulong addr)
+{
+ HWBreakpoint brk = {
+ .bcr = 0x1, /* BCR E=1, enable */
+ .bvr = sextract64(addr, 0, 53)
+ };
+
+ if (cur_hw_bps >= max_hw_bps) {
+ return -ENOBUFS;
+ }
+
+ brk.bcr = deposit32(brk.bcr, 1, 2, 0x3); /* PMC = 11 */
+ brk.bcr = deposit32(brk.bcr, 5, 4, 0xf); /* BAS = RES1 */
+
+ g_array_append_val(hw_breakpoints, brk);
+
+ return 0;
+}
+
+/**
+ * delete_hw_breakpoint()
+ * @pc: address of breakpoint
+ *
+ * Delete a breakpoint and shuffle any above down
+ */
+
+int delete_hw_breakpoint(target_ulong pc)
+{
+ int i;
+ for (i = 0; i < hw_breakpoints->len; i++) {
+ HWBreakpoint *brk = get_hw_bp(i);
+ if (brk->bvr == pc) {
+ g_array_remove_index(hw_breakpoints, i);
+ return 0;
+ }
+ }
+ return -ENOENT;
+}
+
+/**
+ * insert_hw_watchpoint()
+ * @addr: address of watch point
+ * @len: size of area
+ * @type: type of watch point
+ *
+ * See ARM ARM D2.10. As with the breakpoints we can do some advanced
+ * stuff if we want to. The watch points can be linked with the break
+ * points above to make them context aware. However for simplicity
+ * currently we only deal with simple read/write watch points.
+ *
+ * D7.3.11 DBGWCR<n>_EL1, Debug Watchpoint Control Registers
+ *
+ * 31 29 28 24 23 21 20 19 16 15 14 13 12 5 4 3 2 1 0
+ * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
+ * | RES0 | MASK | RES0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E |
+ * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
+ *
+ * MASK: num bits addr mask (0=none,01/10=res,11=3 bits (8 bytes))
+ * WT: 0 - unlinked, 1 - linked (not currently used)
+ * LBN: Linked BP number (not currently used)
+ * SSC/HMC/PAC: Security, Higher and Priv access control (Table D2-11)
+ * BAS: Byte Address Select
+ * LSC: Load/Store control (01: load, 10: store, 11: both)
+ * E: Enable
+ *
+ * The bottom 2 bits of the value register are masked. Therefore to
+ * break on any sizes smaller than an unaligned word you need to set
+ * MASK=0, BAS=bit per byte in question. For larger regions (^2) you
+ * need to ensure you mask the address as required and set BAS=0xff
+ */
+
+int insert_hw_watchpoint(target_ulong addr, target_ulong len, int type)
+{
+ HWWatchpoint wp = {
+ .wcr = R_DBGWCR_E_MASK, /* E=1, enable */
+ .wvr = addr & (~0x7ULL),
+ .details = { .vaddr = addr, .len = len }
+ };
+
+ if (cur_hw_wps >= max_hw_wps) {
+ return -ENOBUFS;
+ }
+
+ /*
+ * HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state,
+ * valid whether EL3 is implemented or not
+ */
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, PAC, 3);
+
+ switch (type) {
+ case GDB_WATCHPOINT_READ:
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 1);
+ wp.details.flags = BP_MEM_READ;
+ break;
+ case GDB_WATCHPOINT_WRITE:
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 2);
+ wp.details.flags = BP_MEM_WRITE;
+ break;
+ case GDB_WATCHPOINT_ACCESS:
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 3);
+ wp.details.flags = BP_MEM_ACCESS;
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+ if (len <= 8) {
+ /* we align the address and set the bits in BAS */
+ int off = addr & 0x7;
+ int bas = (1 << len) - 1;
+
+ wp.wcr = deposit32(wp.wcr, 5 + off, 8 - off, bas);
+ } else {
+ /* For ranges above 8 bytes we need to be a power of 2 */
+ if (is_power_of_2(len)) {
+ int bits = ctz64(len);
+
+ wp.wvr &= ~((1 << bits) - 1);
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, MASK, bits);
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff);
+ } else {
+ return -ENOBUFS;
+ }
+ }
+
+ g_array_append_val(hw_watchpoints, wp);
+ return 0;
+}
+
+bool check_watchpoint_in_range(int i, target_ulong addr)
+{
+ HWWatchpoint *wp = get_hw_wp(i);
+ uint64_t addr_top, addr_bottom = wp->wvr;
+ int bas = extract32(wp->wcr, 5, 8);
+ int mask = extract32(wp->wcr, 24, 4);
+
+ if (mask) {
+ addr_top = addr_bottom + (1 << mask);
+ } else {
+ /*
+ * BAS must be contiguous but can offset against the base
+ * address in DBGWVR
+ */
+ addr_bottom = addr_bottom + ctz32(bas);
+ addr_top = addr_bottom + clo32(bas);
+ }
+
+ if (addr >= addr_bottom && addr <= addr_top) {
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * delete_hw_watchpoint()
+ * @addr: address of breakpoint
+ *
+ * Delete a breakpoint and shuffle any above down
+ */
+
+int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type)
+{
+ int i;
+ for (i = 0; i < cur_hw_wps; i++) {
+ if (check_watchpoint_in_range(i, addr)) {
+ g_array_remove_index(hw_watchpoints, i);
+ return 0;
+ }
+ }
+ return -ENOENT;
+}
+
+bool find_hw_breakpoint(CPUState *cpu, target_ulong pc)
+{
+ int i;
+
+ for (i = 0; i < cur_hw_bps; i++) {
+ HWBreakpoint *bp = get_hw_bp(i);
+ if (bp->bvr == pc) {
+ return true;
+ }
+ }
+ return false;
+}
+
+CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr)
+{
+ int i;
+
+ for (i = 0; i < cur_hw_wps; i++) {
+ if (check_watchpoint_in_range(i, addr)) {
+ return &get_hw_wp(i)->details;
+ }
+ }
+ return NULL;
+}
diff --git a/target/arm/internals.h b/target/arm/internals.h
index d9121d9ff8..54382e7d76 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1369,4 +1369,54 @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
((1 << (1 - 1)) | (1 << (2 - 1)) | \
(1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1)))
+/*
+ * Although the ARM implementation of hardware assisted debugging
+ * allows for different breakpoints per-core, the current GDB
+ * interface treats them as a global pool of registers (which seems to
+ * be the case for x86, ppc and s390). As a result we store one copy
+ * of registers which is used for all active cores.
+ *
+ * Write access is serialised by virtue of the GDB protocol which
+ * updates things. Read access (i.e. when the values are copied to the
+ * vCPU) is also gated by GDB's run control.
+ *
+ * This is not unreasonable as most of the time debugging kernels you
+ * never know which core will eventually execute your function.
+ */
+
+typedef struct {
+ uint64_t bcr;
+ uint64_t bvr;
+} HWBreakpoint;
+
+/*
+ * The watchpoint registers can cover more area than the requested
+ * watchpoint so we need to store the additional information
+ * somewhere. We also need to supply a CPUWatchpoint to the GDB stub
+ * when the watchpoint is hit.
+ */
+typedef struct {
+ uint64_t wcr;
+ uint64_t wvr;
+ CPUWatchpoint details;
+} HWWatchpoint;
+
+/* Maximum and current break/watch point counts */
+extern int max_hw_bps, max_hw_wps;
+extern GArray *hw_breakpoints, *hw_watchpoints;
+
+#define cur_hw_wps (hw_watchpoints->len)
+#define cur_hw_bps (hw_breakpoints->len)
+#define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i))
+#define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i))
+
+bool find_hw_breakpoint(CPUState *cpu, target_ulong pc);
+int insert_hw_breakpoint(target_ulong pc);
+int delete_hw_breakpoint(target_ulong pc);
+
+bool check_watchpoint_in_range(int i, target_ulong addr);
+CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr);
+int insert_hw_watchpoint(target_ulong addr, target_ulong len, int type);
+int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type);
+
#endif
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 1197253d12..fb7bb65947 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -34,46 +34,6 @@
static bool have_guest_debug;
-/*
- * Although the ARM implementation of hardware assisted debugging
- * allows for different breakpoints per-core, the current GDB
- * interface treats them as a global pool of registers (which seems to
- * be the case for x86, ppc and s390). As a result we store one copy
- * of registers which is used for all active cores.
- *
- * Write access is serialised by virtue of the GDB protocol which
- * updates things. Read access (i.e. when the values are copied to the
- * vCPU) is also gated by GDB's run control.
- *
- * This is not unreasonable as most of the time debugging kernels you
- * never know which core will eventually execute your function.
- */
-
-typedef struct {
- uint64_t bcr;
- uint64_t bvr;
-} HWBreakpoint;
-
-/* The watchpoint registers can cover more area than the requested
- * watchpoint so we need to store the additional information
- * somewhere. We also need to supply a CPUWatchpoint to the GDB stub
- * when the watchpoint is hit.
- */
-typedef struct {
- uint64_t wcr;
- uint64_t wvr;
- CPUWatchpoint details;
-} HWWatchpoint;
-
-/* Maximum and current break/watch point counts */
-int max_hw_bps, max_hw_wps;
-GArray *hw_breakpoints, *hw_watchpoints;
-
-#define cur_hw_wps (hw_watchpoints->len)
-#define cur_hw_bps (hw_breakpoints->len)
-#define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i))
-#define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i))
-
/**
* kvm_arm_init_debug() - check for guest debug capabilities
* @cs: CPUState
@@ -97,217 +57,6 @@ static void kvm_arm_init_debug(CPUState *cs)
return;
}
-/**
- * insert_hw_breakpoint()
- * @addr: address of breakpoint
- *
- * See ARM ARM D2.9.1 for details but here we are only going to create
- * simple un-linked breakpoints (i.e. we don't chain breakpoints
- * together to match address and context or vmid). The hardware is
- * capable of fancier matching but that will require exposing that
- * fanciness to GDB's interface
- *
- * DBGBCR<n>_EL1, Debug Breakpoint Control Registers
- *
- * 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0
- * +------+------+-------+-----+----+------+-----+------+-----+---+
- * | RES0 | BT | LBN | SSC | HMC| RES0 | BAS | RES0 | PMC | E |
- * +------+------+-------+-----+----+------+-----+------+-----+---+
- *
- * BT: Breakpoint type (0 = unlinked address match)
- * LBN: Linked BP number (0 = unused)
- * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12)
- * BAS: Byte Address Select (RES1 for AArch64)
- * E: Enable bit
- *
- * DBGBVR<n>_EL1, Debug Breakpoint Value Registers
- *
- * 63 53 52 49 48 2 1 0
- * +------+-----------+----------+-----+
- * | RESS | VA[52:49] | VA[48:2] | 0 0 |
- * +------+-----------+----------+-----+
- *
- * Depending on the addressing mode bits the top bits of the register
- * are a sign extension of the highest applicable VA bit. Some
- * versions of GDB don't do it correctly so we ensure they are correct
- * here so future PC comparisons will work properly.
- */
-
-static int insert_hw_breakpoint(target_ulong addr)
-{
- HWBreakpoint brk = {
- .bcr = 0x1, /* BCR E=1, enable */
- .bvr = sextract64(addr, 0, 53)
- };
-
- if (cur_hw_bps >= max_hw_bps) {
- return -ENOBUFS;
- }
-
- brk.bcr = deposit32(brk.bcr, 1, 2, 0x3); /* PMC = 11 */
- brk.bcr = deposit32(brk.bcr, 5, 4, 0xf); /* BAS = RES1 */
-
- g_array_append_val(hw_breakpoints, brk);
-
- return 0;
-}
-
-/**
- * delete_hw_breakpoint()
- * @pc: address of breakpoint
- *
- * Delete a breakpoint and shuffle any above down
- */
-
-static int delete_hw_breakpoint(target_ulong pc)
-{
- int i;
- for (i = 0; i < hw_breakpoints->len; i++) {
- HWBreakpoint *brk = get_hw_bp(i);
- if (brk->bvr == pc) {
- g_array_remove_index(hw_breakpoints, i);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-/**
- * insert_hw_watchpoint()
- * @addr: address of watch point
- * @len: size of area
- * @type: type of watch point
- *
- * See ARM ARM D2.10. As with the breakpoints we can do some advanced
- * stuff if we want to. The watch points can be linked with the break
- * points above to make them context aware. However for simplicity
- * currently we only deal with simple read/write watch points.
- *
- * D7.3.11 DBGWCR<n>_EL1, Debug Watchpoint Control Registers
- *
- * 31 29 28 24 23 21 20 19 16 15 14 13 12 5 4 3 2 1 0
- * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
- * | RES0 | MASK | RES0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E |
- * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
- *
- * MASK: num bits addr mask (0=none,01/10=res,11=3 bits (8 bytes))
- * WT: 0 - unlinked, 1 - linked (not currently used)
- * LBN: Linked BP number (not currently used)
- * SSC/HMC/PAC: Security, Higher and Priv access control (Table D2-11)
- * BAS: Byte Address Select
- * LSC: Load/Store control (01: load, 10: store, 11: both)
- * E: Enable
- *
- * The bottom 2 bits of the value register are masked. Therefore to
- * break on any sizes smaller than an unaligned word you need to set
- * MASK=0, BAS=bit per byte in question. For larger regions (^2) you
- * need to ensure you mask the address as required and set BAS=0xff
- */
-
-static int insert_hw_watchpoint(target_ulong addr,
- target_ulong len, int type)
-{
- HWWatchpoint wp = {
- .wcr = R_DBGWCR_E_MASK, /* E=1, enable */
- .wvr = addr & (~0x7ULL),
- .details = { .vaddr = addr, .len = len }
- };
-
- if (cur_hw_wps >= max_hw_wps) {
- return -ENOBUFS;
- }
-
- /*
- * HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state,
- * valid whether EL3 is implemented or not
- */
- wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, PAC, 3);
-
- switch (type) {
- case GDB_WATCHPOINT_READ:
- wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 1);
- wp.details.flags = BP_MEM_READ;
- break;
- case GDB_WATCHPOINT_WRITE:
- wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 2);
- wp.details.flags = BP_MEM_WRITE;
- break;
- case GDB_WATCHPOINT_ACCESS:
- wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 3);
- wp.details.flags = BP_MEM_ACCESS;
- break;
- default:
- g_assert_not_reached();
- break;
- }
- if (len <= 8) {
- /* we align the address and set the bits in BAS */
- int off = addr & 0x7;
- int bas = (1 << len) - 1;
-
- wp.wcr = deposit32(wp.wcr, 5 + off, 8 - off, bas);
- } else {
- /* For ranges above 8 bytes we need to be a power of 2 */
- if (is_power_of_2(len)) {
- int bits = ctz64(len);
-
- wp.wvr &= ~((1 << bits) - 1);
- wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, MASK, bits);
- wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff);
- } else {
- return -ENOBUFS;
- }
- }
-
- g_array_append_val(hw_watchpoints, wp);
- return 0;
-}
-
-
-static bool check_watchpoint_in_range(int i, target_ulong addr)
-{
- HWWatchpoint *wp = get_hw_wp(i);
- uint64_t addr_top, addr_bottom = wp->wvr;
- int bas = extract32(wp->wcr, 5, 8);
- int mask = extract32(wp->wcr, 24, 4);
-
- if (mask) {
- addr_top = addr_bottom + (1 << mask);
- } else {
- /* BAS must be contiguous but can offset against the base
- * address in DBGWVR */
- addr_bottom = addr_bottom + ctz32(bas);
- addr_top = addr_bottom + clo32(bas);
- }
-
- if (addr >= addr_bottom && addr <= addr_top) {
- return true;
- }
-
- return false;
-}
-
-/**
- * delete_hw_watchpoint()
- * @addr: address of breakpoint
- *
- * Delete a breakpoint and shuffle any above down
- */
-
-static int delete_hw_watchpoint(target_ulong addr,
- target_ulong len, int type)
-{
- int i;
- for (i = 0; i < cur_hw_wps; i++) {
- if (check_watchpoint_in_range(i, addr)) {
- g_array_remove_index(hw_watchpoints, i);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
target_ulong len, int type)
{
@@ -372,31 +121,6 @@ bool kvm_arm_hw_debug_active(CPUState *cs)
return ((cur_hw_wps > 0) || (cur_hw_bps > 0));
}
-static bool find_hw_breakpoint(CPUState *cpu, target_ulong pc)
-{
- int i;
-
- for (i = 0; i < cur_hw_bps; i++) {
- HWBreakpoint *bp = get_hw_bp(i);
- if (bp->bvr == pc) {
- return true;
- }
- }
- return false;
-}
-
-static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr)
-{
- int i;
-
- for (i = 0; i < cur_hw_wps; i++) {
- if (check_watchpoint_in_range(i, addr)) {
- return &get_hw_wp(i)->details;
- }
- }
- return NULL;
-}
-
static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr,
const char *name)
{
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 87e911b27f..63f5d30dd8 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -40,7 +40,8 @@ arm_ss.add(files(
))
arm_ss.add(zlib)
-arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
+arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
+arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c'))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
'cpu64.c',
--
2.38.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 1/3] arm: move KVM breakpoints helpers
2022-11-16 17:47 ` [PATCH v2 1/3] arm: move KVM breakpoints helpers francesco.cagnin
@ 2022-11-22 10:06 ` Alex Bennée
0 siblings, 0 replies; 10+ messages in thread
From: Alex Bennée @ 2022-11-22 10:06 UTC (permalink / raw)
To: francesco.cagnin
Cc: qemu-devel, mads, dirty, peter.maydell, qemu-arm, agraf,
pbonzini, Francesco Cagnin
francesco.cagnin@gmail.com writes:
> From: Francesco Cagnin <fcagnin@quarkslab.com>
>
> These helpers will be also used for HVF. Aside from reformatting a
> couple of comments for 'checkpatch.pl' and updating meson to compile
> 'hyp_gdbstub.c', this is just code motion.
>
> Signed-off-by: Francesco Cagnin <fcagnin@quarkslab.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Peter,
I assume as this is all in target/arm you'll take it via your tree?
--
Alex Bennée
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/3] hvf: implement guest debugging on Apple Silicon hosts
2022-11-16 17:47 [PATCH v2 0/3] Add gdbstub support to HVF francesco.cagnin
2022-11-16 17:47 ` [PATCH v2 1/3] arm: move KVM breakpoints helpers francesco.cagnin
@ 2022-11-16 17:47 ` francesco.cagnin
2022-11-17 14:01 ` Mads Ynddal
2022-12-12 16:16 ` Peter Maydell
2022-11-16 17:47 ` [PATCH v2 3/3] hvf: handle writes of MDSCR_EL1 and DBG*_EL1 francesco.cagnin
2 siblings, 2 replies; 10+ messages in thread
From: francesco.cagnin @ 2022-11-16 17:47 UTC (permalink / raw)
To: qemu-devel
Cc: mads, dirty, peter.maydell, qemu-arm, agraf, pbonzini,
alex.bennee, Francesco Cagnin
From: Francesco Cagnin <fcagnin@quarkslab.com>
Support is added for single-stepping, software breakpoints, hardware
breakpoints and watchpoints. The code has been structured like the KVM
counterpart (and many parts are basically identical).
Guests can be debugged through the gdbstub.
Signed-off-by: Francesco Cagnin <fcagnin@quarkslab.com>
---
accel/hvf/hvf-accel-ops.c | 123 ++++++++++++++++++++++++
accel/hvf/hvf-all.c | 24 +++++
cpu.c | 3 +
include/sysemu/hvf.h | 29 ++++++
include/sysemu/hvf_int.h | 1 +
target/arm/hvf/hvf.c | 194 +++++++++++++++++++++++++++++++++++++-
6 files changed, 372 insertions(+), 2 deletions(-)
diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c
index 24913ca9c4..1ce0f94a64 100644
--- a/accel/hvf/hvf-accel-ops.c
+++ b/accel/hvf/hvf-accel-ops.c
@@ -52,6 +52,7 @@
#include "qemu/main-loop.h"
#include "exec/address-spaces.h"
#include "exec/exec-all.h"
+#include "exec/gdbstub.h"
#include "sysemu/cpus.h"
#include "sysemu/hvf.h"
#include "sysemu/hvf_int.h"
@@ -340,12 +341,18 @@ static int hvf_accel_init(MachineState *ms)
return hvf_arch_init();
}
+static int hvf_gdbstub_sstep_flags(void)
+{
+ return SSTEP_ENABLE | SSTEP_NOIRQ;
+}
+
static void hvf_accel_class_init(ObjectClass *oc, void *data)
{
AccelClass *ac = ACCEL_CLASS(oc);
ac->name = "HVF";
ac->init_machine = hvf_accel_init;
ac->allowed = &hvf_allowed;
+ ac->gdbstub_supported_sstep_flags = hvf_gdbstub_sstep_flags;
}
static const TypeInfo hvf_accel_type = {
@@ -462,6 +469,117 @@ static void hvf_start_vcpu_thread(CPUState *cpu)
cpu, QEMU_THREAD_JOINABLE);
}
+static bool hvf_supports_guest_debug(void)
+{
+#ifdef TARGET_AARCH64
+ return true;
+#else
+ return false;
+#endif
+}
+
+static int hvf_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len)
+{
+ struct hvf_sw_breakpoint *bp;
+ int err;
+
+ if (type == GDB_BREAKPOINT_SW) {
+ bp = hvf_find_sw_breakpoint(cpu, addr);
+ if (bp) {
+ bp->use_count++;
+ return 0;
+ }
+
+ bp = g_new(struct hvf_sw_breakpoint, 1);
+ bp->pc = addr;
+ bp->use_count = 1;
+ err = hvf_arch_insert_sw_breakpoint(cpu, bp);
+ if (err) {
+ g_free(bp);
+ return err;
+ }
+
+ QTAILQ_INSERT_HEAD(&cpu->hvf->hvf_sw_breakpoints, bp, entry);
+ } else {
+ err = hvf_arch_insert_hw_breakpoint(addr, len, type);
+ if (err) {
+ return err;
+ }
+ }
+
+ CPU_FOREACH(cpu) {
+ err = hvf_update_guest_debug(cpu);
+ if (err) {
+ return err;
+ }
+ }
+ return 0;
+}
+
+static int hvf_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len)
+{
+ struct hvf_sw_breakpoint *bp;
+ int err;
+
+ if (type == GDB_BREAKPOINT_SW) {
+ bp = hvf_find_sw_breakpoint(cpu, addr);
+ if (!bp) {
+ return -ENOENT;
+ }
+
+ if (bp->use_count > 1) {
+ bp->use_count--;
+ return 0;
+ }
+
+ err = hvf_arch_remove_sw_breakpoint(cpu, bp);
+ if (err) {
+ return err;
+ }
+
+ QTAILQ_REMOVE(&cpu->hvf->hvf_sw_breakpoints, bp, entry);
+ g_free(bp);
+ } else {
+ err = hvf_arch_remove_hw_breakpoint(addr, len, type);
+ if (err) {
+ return err;
+ }
+ }
+
+ CPU_FOREACH(cpu) {
+ err = hvf_update_guest_debug(cpu);
+ if (err) {
+ return err;
+ }
+ }
+ return 0;
+}
+
+static void hvf_remove_all_breakpoints(CPUState *cpu)
+{
+ struct hvf_sw_breakpoint *bp, *next;
+ CPUState *tmpcpu;
+
+ QTAILQ_FOREACH_SAFE(bp, &cpu->hvf->hvf_sw_breakpoints, entry, next) {
+ if (hvf_arch_remove_sw_breakpoint(cpu, bp) != 0) {
+ /* Try harder to find a CPU that currently sees the breakpoint. */
+ CPU_FOREACH(tmpcpu)
+ {
+ if (hvf_arch_remove_sw_breakpoint(tmpcpu, bp) == 0) {
+ break;
+ }
+ }
+ }
+ QTAILQ_REMOVE(&cpu->hvf->hvf_sw_breakpoints, bp, entry);
+ g_free(bp);
+ }
+ hvf_arch_remove_all_hw_breakpoints();
+
+ CPU_FOREACH(cpu) {
+ hvf_update_guest_debug(cpu);
+ }
+}
+
static void hvf_accel_ops_class_init(ObjectClass *oc, void *data)
{
AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
@@ -473,6 +591,11 @@ static void hvf_accel_ops_class_init(ObjectClass *oc, void *data)
ops->synchronize_post_init = hvf_cpu_synchronize_post_init;
ops->synchronize_state = hvf_cpu_synchronize_state;
ops->synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm;
+
+ ops->supports_guest_debug = hvf_supports_guest_debug;
+ ops->insert_breakpoint = hvf_insert_breakpoint;
+ ops->remove_breakpoint = hvf_remove_breakpoint;
+ ops->remove_all_breakpoints = hvf_remove_all_breakpoints;
};
static const TypeInfo hvf_accel_ops_type = {
.name = ACCEL_OPS_NAME("hvf"),
diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c
index 0043f4d308..3f02c090b1 100644
--- a/accel/hvf/hvf-all.c
+++ b/accel/hvf/hvf-all.c
@@ -10,6 +10,7 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
+#include "exec/gdbstub.h"
#include "sysemu/hvf.h"
#include "sysemu/hvf_int.h"
@@ -44,3 +45,26 @@ void assert_hvf_ok(hv_return_t ret)
abort();
}
+
+struct hvf_sw_breakpoint *hvf_find_sw_breakpoint(CPUState *cpu, target_ulong pc)
+{
+ struct hvf_sw_breakpoint *bp;
+
+ QTAILQ_FOREACH(bp, &cpu->hvf->hvf_sw_breakpoints, entry) {
+ if (bp->pc == pc) {
+ return bp;
+ }
+ }
+ return NULL;
+}
+
+int hvf_sw_breakpoints_active(CPUState *cpu)
+{
+ return !QTAILQ_EMPTY(&cpu->hvf->hvf_sw_breakpoints);
+}
+
+int hvf_update_guest_debug(CPUState *cpu)
+{
+ hvf_arch_update_guest_debug(cpu);
+ return 0;
+}
diff --git a/cpu.c b/cpu.c
index 4a7d865427..1fd531aabd 100644
--- a/cpu.c
+++ b/cpu.c
@@ -33,6 +33,7 @@
#endif
#include "sysemu/tcg.h"
#include "sysemu/kvm.h"
+#include "sysemu/hvf.h"
#include "sysemu/replay.h"
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
@@ -389,6 +390,8 @@ void cpu_single_step(CPUState *cpu, int enabled)
cpu->singlestep_enabled = enabled;
if (kvm_enabled()) {
kvm_update_guest_debug(cpu, 0);
+ } else if (hvf_enabled()) {
+ hvf_update_guest_debug(cpu);
}
trace_breakpoint_singlestep(cpu->cpu_index, enabled);
}
diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
index bb70082e45..3e99c80416 100644
--- a/include/sysemu/hvf.h
+++ b/include/sysemu/hvf.h
@@ -36,4 +36,33 @@ typedef struct HVFState HVFState;
DECLARE_INSTANCE_CHECKER(HVFState, HVF_STATE,
TYPE_HVF_ACCEL)
+#ifdef NEED_CPU_H
+#include "cpu.h"
+
+int hvf_update_guest_debug(CPUState *cpu);
+
+struct hvf_sw_breakpoint {
+ target_ulong pc;
+ target_ulong saved_insn;
+ int use_count;
+ QTAILQ_ENTRY(hvf_sw_breakpoint) entry;
+};
+
+struct hvf_sw_breakpoint *hvf_find_sw_breakpoint(CPUState *cpu,
+ target_ulong pc);
+
+int hvf_sw_breakpoints_active(CPUState *cpu);
+
+int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp);
+int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp);
+int hvf_arch_insert_hw_breakpoint(target_ulong addr, target_ulong len,
+ int type);
+int hvf_arch_remove_hw_breakpoint(target_ulong addr, target_ulong len,
+ int type);
+void hvf_arch_remove_all_hw_breakpoints(void);
+
+void hvf_arch_update_guest_debug(CPUState *cpu);
+
+#endif /* NEED_CPU_H */
+
#endif
diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h
index 6545f7cd61..a7957d046b 100644
--- a/include/sysemu/hvf_int.h
+++ b/include/sysemu/hvf_int.h
@@ -53,6 +53,7 @@ struct hvf_vcpu_state {
void *exit;
bool vtimer_masked;
sigset_t unblock_ipi_mask;
+ QTAILQ_HEAD(, hvf_sw_breakpoint) hvf_sw_breakpoints;
};
void assert_hvf_ok(hv_return_t ret);
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 060aa0ccf4..66fc82e9b9 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -31,6 +31,22 @@
#include "trace/trace-target_arm_hvf.h"
#include "migration/vmstate.h"
+#include "exec/gdbstub.h"
+
+static void hvf_arm_init_debug(CPUState *cpu)
+{
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
+
+ max_hw_bps = arm_num_brps(arm_cpu);
+ hw_breakpoints =
+ g_array_sized_new(true, true, sizeof(HWBreakpoint), max_hw_bps);
+
+ max_hw_wps = arm_num_wrps(arm_cpu);
+ hw_watchpoints =
+ g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps);
+ return;
+}
+
#define HVF_SYSREG(crn, crm, op0, op1, op2) \
ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
#define PL1_WRITE_MASK 0x4
@@ -621,6 +637,8 @@ int hvf_arch_init_vcpu(CPUState *cpu)
&arm_cpu->isar.id_aa64mmfr0);
assert_hvf_ok(ret);
+ hvf_arm_init_debug(cpu);
+
return 0;
}
@@ -1166,11 +1184,12 @@ int hvf_vcpu_exec(CPUState *cpu)
{
ARMCPU *arm_cpu = ARM_CPU(cpu);
CPUARMState *env = &arm_cpu->env;
+ int ret;
hv_vcpu_exit_t *hvf_exit = cpu->hvf->exit;
hv_return_t r;
bool advance_pc = false;
- if (hvf_inject_interrupts(cpu)) {
+ if (!(cpu->singlestep_enabled & SSTEP_NOIRQ) && hvf_inject_interrupts(cpu)) {
return EXCP_INTERRUPT;
}
@@ -1188,6 +1207,7 @@ int hvf_vcpu_exec(CPUState *cpu)
uint64_t syndrome = hvf_exit->exception.syndrome;
uint32_t ec = syn_get_ec(syndrome);
+ ret = 0;
qemu_mutex_lock_iothread();
switch (exit_reason) {
case HV_EXIT_REASON_EXCEPTION:
@@ -1207,6 +1227,47 @@ int hvf_vcpu_exec(CPUState *cpu)
hvf_sync_vtimer(cpu);
switch (ec) {
+ case EC_SOFTWARESTEP: {
+ ret = EXCP_DEBUG;
+
+ if (!cpu->singlestep_enabled) {
+ error_report("EC_SOFTWARESTEP but single-stepping not enabled");
+ }
+ break;
+ }
+ case EC_AA64_BKPT: {
+ ret = EXCP_DEBUG;
+
+ cpu_synchronize_state(cpu);
+
+ if (!hvf_find_sw_breakpoint(cpu, env->pc)) {
+ error_report("EC_AA64_BKPT but unknown sw breakpoint");
+ }
+ break;
+ }
+ case EC_BREAKPOINT: {
+ ret = EXCP_DEBUG;
+
+ cpu_synchronize_state(cpu);
+
+ if (!find_hw_breakpoint(cpu, env->pc)) {
+ error_report("EC_BREAKPOINT but unknown hw breakpoint");
+ }
+ break;
+ }
+ case EC_WATCHPOINT: {
+ ret = EXCP_DEBUG;
+
+ cpu_synchronize_state(cpu);
+
+ CPUWatchpoint *wp =
+ find_hw_watchpoint(cpu, hvf_exit->exception.virtual_address);
+ if (!wp) {
+ error_report("EXCP_DEBUG but unknown hw watchpoint");
+ }
+ cpu->watchpoint_hit = wp;
+ break;
+ }
case EC_DATAABORT: {
bool isv = syndrome & ARM_EL_ISV;
bool iswrite = (syndrome >> 6) & 1;
@@ -1313,7 +1374,7 @@ int hvf_vcpu_exec(CPUState *cpu)
assert_hvf_ok(r);
}
- return 0;
+ return ret;
}
static const VMStateDescription vmstate_hvf_vtimer = {
@@ -1347,3 +1408,132 @@ int hvf_arch_init(void)
qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer);
return 0;
}
+
+static inline bool hvf_arm_hw_debug_active(CPUState *cpu)
+{
+ return ((cur_hw_wps > 0) || (cur_hw_bps > 0));
+}
+
+static const uint32_t brk_insn = 0xd4200000;
+
+int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp)
+{
+ if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) ||
+ cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk_insn, 4, 1)) {
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp)
+{
+ static uint32_t brk;
+
+ if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk, 4, 0) ||
+ brk != brk_insn ||
+ cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) {
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int hvf_arch_insert_hw_breakpoint(target_ulong addr, target_ulong len, int type)
+{
+ switch (type) {
+ case GDB_BREAKPOINT_HW:
+ return insert_hw_breakpoint(addr);
+ case GDB_WATCHPOINT_READ:
+ case GDB_WATCHPOINT_WRITE:
+ case GDB_WATCHPOINT_ACCESS:
+ return insert_hw_watchpoint(addr, len, type);
+ default:
+ return -ENOSYS;
+ }
+}
+
+int hvf_arch_remove_hw_breakpoint(target_ulong addr, target_ulong len, int type)
+{
+ switch (type) {
+ case GDB_BREAKPOINT_HW:
+ return delete_hw_breakpoint(addr);
+ case GDB_WATCHPOINT_READ:
+ case GDB_WATCHPOINT_WRITE:
+ case GDB_WATCHPOINT_ACCESS:
+ return delete_hw_watchpoint(addr, len, type);
+ default:
+ return -ENOSYS;
+ }
+}
+
+void hvf_arch_remove_all_hw_breakpoints(void)
+{
+ if (cur_hw_wps > 0) {
+ g_array_remove_range(hw_watchpoints, 0, cur_hw_wps);
+ }
+ if (cur_hw_bps > 0) {
+ g_array_remove_range(hw_breakpoints, 0, cur_hw_bps);
+ }
+}
+
+#define MDSCR_EL1_SS_SHIFT 0
+#define MDSCR_EL1_MDE_SHIFT 15
+
+void hvf_arch_update_guest_debug(CPUState *cpu)
+{
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
+ CPUARMState *env = &arm_cpu->env;
+ hv_return_t r = HV_SUCCESS;
+ bool trap_debug_exceptions = false;
+
+ cpu_synchronize_state(cpu);
+
+ if (cpu->singlestep_enabled) {
+ trap_debug_exceptions = true;
+
+ env->cp15.mdscr_el1 =
+ deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 1);
+ pstate_write(env, pstate_read(env) | PSTATE_SS);
+ } else {
+ env->cp15.mdscr_el1 =
+ deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 0);
+ }
+
+ if (hvf_sw_breakpoints_active(cpu)) {
+ trap_debug_exceptions = true;
+ }
+
+ if (hvf_arm_hw_debug_active(cpu)) {
+ trap_debug_exceptions = true;
+
+ env->cp15.mdscr_el1 =
+ deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 1);
+
+ int i;
+ for (i = 0; i < cur_hw_bps; i++) {
+ HWBreakpoint *bp = get_hw_bp(i);
+ env->cp15.dbgbcr[i] = bp->bcr;
+ env->cp15.dbgbvr[i] = bp->bvr;
+ }
+ for (i = 0; i < cur_hw_wps; i++) {
+ HWWatchpoint *bp = get_hw_wp(i);
+ env->cp15.dbgwcr[i] = bp->wcr;
+ env->cp15.dbgwvr[i] = bp->wvr;
+ }
+ } else {
+ env->cp15.mdscr_el1 =
+ deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0);
+
+ int i;
+ for (i = 0; i < max_hw_bps; i++) {
+ env->cp15.dbgbcr[i] = 0;
+ env->cp15.dbgbvr[i] = 0;
+ }
+ for (i = 0; i < max_hw_wps; i++) {
+ env->cp15.dbgwcr[i] = 0;
+ env->cp15.dbgwvr[i] = 0;
+ }
+ }
+
+ r = hv_vcpu_set_trap_debug_exceptions(cpu->hvf->fd, trap_debug_exceptions);
+ assert_hvf_ok(r);
+}
--
2.38.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 2/3] hvf: implement guest debugging on Apple Silicon hosts
2022-11-16 17:47 ` [PATCH v2 2/3] hvf: implement guest debugging on Apple Silicon hosts francesco.cagnin
@ 2022-11-17 14:01 ` Mads Ynddal
2022-12-12 16:16 ` Peter Maydell
1 sibling, 0 replies; 10+ messages in thread
From: Mads Ynddal @ 2022-11-17 14:01 UTC (permalink / raw)
To: francesco.cagnin
Cc: qemu-devel, dirty, Peter Maydell, open list:ARM cores,
Alexander Graf, Paolo Bonzini, Alex Bennée,
Francesco Cagnin
> On 16 Nov 2022, at 18.47, francesco.cagnin@gmail.com wrote:
>
> From: Francesco Cagnin <fcagnin@quarkslab.com>
>
> Support is added for single-stepping, software breakpoints, hardware
> breakpoints and watchpoints. The code has been structured like the KVM
> counterpart (and many parts are basically identical).
>
> Guests can be debugged through the gdbstub.
>
> Signed-off-by: Francesco Cagnin <fcagnin@quarkslab.com>
> ---
> accel/hvf/hvf-accel-ops.c | 123 ++++++++++++++++++++++++
> accel/hvf/hvf-all.c | 24 +++++
> cpu.c | 3 +
> include/sysemu/hvf.h | 29 ++++++
> include/sysemu/hvf_int.h | 1 +
> target/arm/hvf/hvf.c | 194 +++++++++++++++++++++++++++++++++++++-
> 6 files changed, 372 insertions(+), 2 deletions(-)
Looks good. I've tested hw/sw breakpoints, hw watchpoints and single-stepping.
Reviewed-by: Mads Ynddal <mads@ynddal.dk>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] hvf: implement guest debugging on Apple Silicon hosts
2022-11-16 17:47 ` [PATCH v2 2/3] hvf: implement guest debugging on Apple Silicon hosts francesco.cagnin
2022-11-17 14:01 ` Mads Ynddal
@ 2022-12-12 16:16 ` Peter Maydell
2022-12-20 7:22 ` Francesco Cagnin
1 sibling, 1 reply; 10+ messages in thread
From: Peter Maydell @ 2022-12-12 16:16 UTC (permalink / raw)
To: francesco.cagnin
Cc: qemu-devel, mads, dirty, qemu-arm, agraf, pbonzini, alex.bennee,
Francesco Cagnin
On Wed, 16 Nov 2022 at 17:48, <francesco.cagnin@gmail.com> wrote:
>
> From: Francesco Cagnin <fcagnin@quarkslab.com>
>
> Support is added for single-stepping, software breakpoints, hardware
> breakpoints and watchpoints. The code has been structured like the KVM
> counterpart (and many parts are basically identical).
>
> Guests can be debugged through the gdbstub.
>
> Signed-off-by: Francesco Cagnin <fcagnin@quarkslab.com>
Hi; sorry it's taken me a while to get to this patchset.
> +void hvf_arch_update_guest_debug(CPUState *cpu)
> +{
> + ARMCPU *arm_cpu = ARM_CPU(cpu);
> + CPUARMState *env = &arm_cpu->env;
> + hv_return_t r = HV_SUCCESS;
> + bool trap_debug_exceptions = false;
> +
> + cpu_synchronize_state(cpu);
> +
> + if (cpu->singlestep_enabled) {
> + trap_debug_exceptions = true;
> +
> + env->cp15.mdscr_el1 =
> + deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 1);
> + pstate_write(env, pstate_read(env) | PSTATE_SS);
> + } else {
> + env->cp15.mdscr_el1 =
> + deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 0);
> + }
> +
> + if (hvf_sw_breakpoints_active(cpu)) {
> + trap_debug_exceptions = true;
> + }
> +
> + if (hvf_arm_hw_debug_active(cpu)) {
> + trap_debug_exceptions = true;
> +
> + env->cp15.mdscr_el1 =
> + deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 1);
> +
> + int i;
> + for (i = 0; i < cur_hw_bps; i++) {
> + HWBreakpoint *bp = get_hw_bp(i);
> + env->cp15.dbgbcr[i] = bp->bcr;
> + env->cp15.dbgbvr[i] = bp->bvr;
> + }
> + for (i = 0; i < cur_hw_wps; i++) {
> + HWWatchpoint *bp = get_hw_wp(i);
> + env->cp15.dbgwcr[i] = bp->wcr;
> + env->cp15.dbgwvr[i] = bp->wvr;
> + }
Can you explain how the patches keep the guest's idea of the debug
registers distinct from the QEMU debugstub's values from them?
Looking at this patch it seems like we just directly set the
cp15.* values with what the debug stub wants them to be here;
but in patch 3 any trapped guest writes to the debug registers
also simply write to the same env fields.
With KVM, this is handled by the host kernel: QEMU tells KVM
that it wants to do guest debug, and then uses the KVM_SET_GUEST_DEBUG
ioctl to say what the bp/wp etc register values should be. The
KVM kernel then uses those values when it runs the VM, as well
as ensuring that debug exceptions go to EL2 rather than EL1,
and that EL1 accesses to the debug regs are also trapped to EL2.
Guest attempts to access the debug registers are then handled by
having reads and writes access fields which correspond to the
guest's view of the debug registers, which is separate from the
values that the QEMU debug stub is using. The effect is that while
QEMU is doing debug of the VM, the guest can still read and write
the debug registers, they just don't have any effect. The guest
can't do anything that messes with the state of the debug registers
that QEMU's debug stub is relying on. If/when QEMU says it's
done with doing guest debug, then the host kernel goes back to using
the guest's values of the debug registers. (In the kernel sources
this is done in arch/arm64/kvm/debug.c, with the trapping of debug
registers done in arch/arm64/kvm/sys_regs.c.)
I suspect that with HVF we need to do the equivalent of this ourselves
in QEMU.
thanks
-- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v2 2/3] hvf: implement guest debugging on Apple Silicon hosts
2022-12-12 16:16 ` Peter Maydell
@ 2022-12-20 7:22 ` Francesco Cagnin
2022-12-20 8:31 ` Alex Bennée
0 siblings, 1 reply; 10+ messages in thread
From: Francesco Cagnin @ 2022-12-20 7:22 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, mads, dirty, qemu-arm, agraf, pbonzini, alex.bennee,
Francesco Cagnin
Hi,
indeed, the patch doesn't keep separate copies of debug registers and
just directly sets cp15.* values, as I was not aware of the issue—thanks
for the detailed explanation.
I remain available to implement the required fixes, but I'd need
some guidance on how to proceed. Thanks,
--
Francesco
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] hvf: implement guest debugging on Apple Silicon hosts
2022-12-20 7:22 ` Francesco Cagnin
@ 2022-12-20 8:31 ` Alex Bennée
0 siblings, 0 replies; 10+ messages in thread
From: Alex Bennée @ 2022-12-20 8:31 UTC (permalink / raw)
To: Francesco Cagnin
Cc: Peter Maydell, qemu-devel, mads, dirty, qemu-arm, agraf,
pbonzini, Francesco Cagnin
Francesco Cagnin <francesco.cagnin@gmail.com> writes:
> Hi,
> indeed, the patch doesn't keep separate copies of debug registers and
> just directly sets cp15.* values, as I was not aware of the issue—thanks
> for the detailed explanation.
>
> I remain available to implement the required fixes, but I'd need
> some guidance on how to proceed. Thanks,
In the KVM world we put of the final setting of the registers until
right before the context switch. I guess the equivalent in HVF would be
to modify hvf_put_registers() and make the decision about if to use the
QEMU supplied debug registers or the env values there.
Something like:
for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
if (hvf_sreg_match[i].cp_idx == -1) {
continue;
}
if (hvf_sref_match[i].can_override && should_override) {
val = get_from_debug(...)
} else {
val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx];
}
ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val);
assert_hvf_ok(ret);
}
You will of course have to ensure the get_registers doesn't
inadvertently splat the env values with what we have just written here.
I'm not super familiar with the HVF architecture but maybe its possible
to do directly call hv_vcpu_set_sys_reg steps in your current
update_guest_debug function instead of copying to env and then and just
skip setting/getting them again in the final put registers just before
you exec.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 3/3] hvf: handle writes of MDSCR_EL1 and DBG*_EL1
2022-11-16 17:47 [PATCH v2 0/3] Add gdbstub support to HVF francesco.cagnin
2022-11-16 17:47 ` [PATCH v2 1/3] arm: move KVM breakpoints helpers francesco.cagnin
2022-11-16 17:47 ` [PATCH v2 2/3] hvf: implement guest debugging on Apple Silicon hosts francesco.cagnin
@ 2022-11-16 17:47 ` francesco.cagnin
2022-11-17 14:01 ` Mads Ynddal
2 siblings, 1 reply; 10+ messages in thread
From: francesco.cagnin @ 2022-11-16 17:47 UTC (permalink / raw)
To: qemu-devel
Cc: mads, dirty, peter.maydell, qemu-arm, agraf, pbonzini,
alex.bennee, Francesco Cagnin
From: Francesco Cagnin <fcagnin@quarkslab.com>
This proved to be required when debugging the Linux kernel's initial
code, as the Hypervisor framework was triggering 'EC_SYSTEMREGISTERTRAP'
VM exits after enabling trap exceptions with
'hv_vcpu_set_trap_debug_exceptions()'.
Signed-off-by: Francesco Cagnin <fcagnin@quarkslab.com>
---
target/arm/hvf/hvf.c | 140 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 140 insertions(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 66fc82e9b9..c28c3dbdaa 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -95,6 +95,71 @@ static void hvf_arm_init_debug(CPUState *cpu)
#define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7)
#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0)
#define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7)
+#define SYSREG_MDSCR_EL1 SYSREG(2, 0, 0, 2, 2)
+#define SYSREG_DBGBVR0_EL1 SYSREG(2, 0, 0, 0, 4)
+#define SYSREG_DBGBCR0_EL1 SYSREG(2, 0, 0, 0, 5)
+#define SYSREG_DBGWVR0_EL1 SYSREG(2, 0, 0, 0, 6)
+#define SYSREG_DBGWCR0_EL1 SYSREG(2, 0, 0, 0, 7)
+#define SYSREG_DBGBVR1_EL1 SYSREG(2, 0, 0, 1, 4)
+#define SYSREG_DBGBCR1_EL1 SYSREG(2, 0, 0, 1, 5)
+#define SYSREG_DBGWVR1_EL1 SYSREG(2, 0, 0, 1, 6)
+#define SYSREG_DBGWCR1_EL1 SYSREG(2, 0, 0, 1, 7)
+#define SYSREG_DBGBVR2_EL1 SYSREG(2, 0, 0, 2, 4)
+#define SYSREG_DBGBCR2_EL1 SYSREG(2, 0, 0, 2, 5)
+#define SYSREG_DBGWVR2_EL1 SYSREG(2, 0, 0, 2, 6)
+#define SYSREG_DBGWCR2_EL1 SYSREG(2, 0, 0, 2, 7)
+#define SYSREG_DBGBVR3_EL1 SYSREG(2, 0, 0, 3, 4)
+#define SYSREG_DBGBCR3_EL1 SYSREG(2, 0, 0, 3, 5)
+#define SYSREG_DBGWVR3_EL1 SYSREG(2, 0, 0, 3, 6)
+#define SYSREG_DBGWCR3_EL1 SYSREG(2, 0, 0, 3, 7)
+#define SYSREG_DBGBVR4_EL1 SYSREG(2, 0, 0, 4, 4)
+#define SYSREG_DBGBCR4_EL1 SYSREG(2, 0, 0, 4, 5)
+#define SYSREG_DBGWVR4_EL1 SYSREG(2, 0, 0, 4, 6)
+#define SYSREG_DBGWCR4_EL1 SYSREG(2, 0, 0, 4, 7)
+#define SYSREG_DBGBVR5_EL1 SYSREG(2, 0, 0, 5, 4)
+#define SYSREG_DBGBCR5_EL1 SYSREG(2, 0, 0, 5, 5)
+#define SYSREG_DBGWVR5_EL1 SYSREG(2, 0, 0, 5, 6)
+#define SYSREG_DBGWCR5_EL1 SYSREG(2, 0, 0, 5, 7)
+#define SYSREG_DBGBVR6_EL1 SYSREG(2, 0, 0, 6, 4)
+#define SYSREG_DBGBCR6_EL1 SYSREG(2, 0, 0, 6, 5)
+#define SYSREG_DBGWVR6_EL1 SYSREG(2, 0, 0, 6, 6)
+#define SYSREG_DBGWCR6_EL1 SYSREG(2, 0, 0, 6, 7)
+#define SYSREG_DBGBVR7_EL1 SYSREG(2, 0, 0, 7, 4)
+#define SYSREG_DBGBCR7_EL1 SYSREG(2, 0, 0, 7, 5)
+#define SYSREG_DBGWVR7_EL1 SYSREG(2, 0, 0, 7, 6)
+#define SYSREG_DBGWCR7_EL1 SYSREG(2, 0, 0, 7, 7)
+#define SYSREG_DBGBVR8_EL1 SYSREG(2, 0, 0, 8, 4)
+#define SYSREG_DBGBCR8_EL1 SYSREG(2, 0, 0, 8, 5)
+#define SYSREG_DBGWVR8_EL1 SYSREG(2, 0, 0, 8, 6)
+#define SYSREG_DBGWCR8_EL1 SYSREG(2, 0, 0, 8, 7)
+#define SYSREG_DBGBVR9_EL1 SYSREG(2, 0, 0, 9, 4)
+#define SYSREG_DBGBCR9_EL1 SYSREG(2, 0, 0, 9, 5)
+#define SYSREG_DBGWVR9_EL1 SYSREG(2, 0, 0, 9, 6)
+#define SYSREG_DBGWCR9_EL1 SYSREG(2, 0, 0, 9, 7)
+#define SYSREG_DBGBVR10_EL1 SYSREG(2, 0, 0, 10, 4)
+#define SYSREG_DBGBCR10_EL1 SYSREG(2, 0, 0, 10, 5)
+#define SYSREG_DBGWVR10_EL1 SYSREG(2, 0, 0, 10, 6)
+#define SYSREG_DBGWCR10_EL1 SYSREG(2, 0, 0, 10, 7)
+#define SYSREG_DBGBVR11_EL1 SYSREG(2, 0, 0, 11, 4)
+#define SYSREG_DBGBCR11_EL1 SYSREG(2, 0, 0, 11, 5)
+#define SYSREG_DBGWVR11_EL1 SYSREG(2, 0, 0, 11, 6)
+#define SYSREG_DBGWCR11_EL1 SYSREG(2, 0, 0, 11, 7)
+#define SYSREG_DBGBVR12_EL1 SYSREG(2, 0, 0, 12, 4)
+#define SYSREG_DBGBCR12_EL1 SYSREG(2, 0, 0, 12, 5)
+#define SYSREG_DBGWVR12_EL1 SYSREG(2, 0, 0, 12, 6)
+#define SYSREG_DBGWCR12_EL1 SYSREG(2, 0, 0, 12, 7)
+#define SYSREG_DBGBVR13_EL1 SYSREG(2, 0, 0, 13, 4)
+#define SYSREG_DBGBCR13_EL1 SYSREG(2, 0, 0, 13, 5)
+#define SYSREG_DBGWVR13_EL1 SYSREG(2, 0, 0, 13, 6)
+#define SYSREG_DBGWCR13_EL1 SYSREG(2, 0, 0, 13, 7)
+#define SYSREG_DBGBVR14_EL1 SYSREG(2, 0, 0, 14, 4)
+#define SYSREG_DBGBCR14_EL1 SYSREG(2, 0, 0, 14, 5)
+#define SYSREG_DBGWVR14_EL1 SYSREG(2, 0, 0, 14, 6)
+#define SYSREG_DBGWCR14_EL1 SYSREG(2, 0, 0, 14, 7)
+#define SYSREG_DBGBVR15_EL1 SYSREG(2, 0, 0, 15, 4)
+#define SYSREG_DBGBCR15_EL1 SYSREG(2, 0, 0, 15, 5)
+#define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6)
+#define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7)
#define WFX_IS_WFE (1 << 0)
@@ -1039,6 +1104,81 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
case SYSREG_OSDLR_EL1:
/* Dummy register */
break;
+ case SYSREG_MDSCR_EL1:
+ env->cp15.mdscr_el1 = val;
+ break;
+ case SYSREG_DBGBVR0_EL1:
+ case SYSREG_DBGBVR1_EL1:
+ case SYSREG_DBGBVR2_EL1:
+ case SYSREG_DBGBVR3_EL1:
+ case SYSREG_DBGBVR4_EL1:
+ case SYSREG_DBGBVR5_EL1:
+ case SYSREG_DBGBVR6_EL1:
+ case SYSREG_DBGBVR7_EL1:
+ case SYSREG_DBGBVR8_EL1:
+ case SYSREG_DBGBVR9_EL1:
+ case SYSREG_DBGBVR10_EL1:
+ case SYSREG_DBGBVR11_EL1:
+ case SYSREG_DBGBVR12_EL1:
+ case SYSREG_DBGBVR13_EL1:
+ case SYSREG_DBGBVR14_EL1:
+ case SYSREG_DBGBVR15_EL1:
+ env->cp15.dbgbvr[SYSREG_CRM(reg)] = val;
+ break;
+ case SYSREG_DBGBCR0_EL1:
+ case SYSREG_DBGBCR1_EL1:
+ case SYSREG_DBGBCR2_EL1:
+ case SYSREG_DBGBCR3_EL1:
+ case SYSREG_DBGBCR4_EL1:
+ case SYSREG_DBGBCR5_EL1:
+ case SYSREG_DBGBCR6_EL1:
+ case SYSREG_DBGBCR7_EL1:
+ case SYSREG_DBGBCR8_EL1:
+ case SYSREG_DBGBCR9_EL1:
+ case SYSREG_DBGBCR10_EL1:
+ case SYSREG_DBGBCR11_EL1:
+ case SYSREG_DBGBCR12_EL1:
+ case SYSREG_DBGBCR13_EL1:
+ case SYSREG_DBGBCR14_EL1:
+ case SYSREG_DBGBCR15_EL1:
+ env->cp15.dbgbcr[SYSREG_CRM(reg)] = val;
+ break;
+ case SYSREG_DBGWVR0_EL1:
+ case SYSREG_DBGWVR1_EL1:
+ case SYSREG_DBGWVR2_EL1:
+ case SYSREG_DBGWVR3_EL1:
+ case SYSREG_DBGWVR4_EL1:
+ case SYSREG_DBGWVR5_EL1:
+ case SYSREG_DBGWVR6_EL1:
+ case SYSREG_DBGWVR7_EL1:
+ case SYSREG_DBGWVR8_EL1:
+ case SYSREG_DBGWVR9_EL1:
+ case SYSREG_DBGWVR10_EL1:
+ case SYSREG_DBGWVR11_EL1:
+ case SYSREG_DBGWVR12_EL1:
+ case SYSREG_DBGWVR13_EL1:
+ case SYSREG_DBGWVR14_EL1:
+ case SYSREG_DBGWVR15_EL1:
+ env->cp15.dbgwvr[SYSREG_CRM(reg)] = val;
+ break;
+ case SYSREG_DBGWCR0_EL1:
+ case SYSREG_DBGWCR1_EL1:
+ case SYSREG_DBGWCR2_EL1:
+ case SYSREG_DBGWCR3_EL1:
+ case SYSREG_DBGWCR4_EL1:
+ case SYSREG_DBGWCR5_EL1:
+ case SYSREG_DBGWCR6_EL1:
+ case SYSREG_DBGWCR7_EL1:
+ case SYSREG_DBGWCR8_EL1:
+ case SYSREG_DBGWCR9_EL1:
+ case SYSREG_DBGWCR10_EL1:
+ case SYSREG_DBGWCR11_EL1:
+ case SYSREG_DBGWCR12_EL1:
+ case SYSREG_DBGWCR13_EL1:
+ case SYSREG_DBGWCR14_EL1:
+ case SYSREG_DBGWCR15_EL1:
+ env->cp15.dbgwcr[SYSREG_CRM(reg)] = val;
+ break;
default:
cpu_synchronize_state(cpu);
trace_hvf_unhandled_sysreg_write(env->pc, reg,
--
2.38.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 3/3] hvf: handle writes of MDSCR_EL1 and DBG*_EL1
2022-11-16 17:47 ` [PATCH v2 3/3] hvf: handle writes of MDSCR_EL1 and DBG*_EL1 francesco.cagnin
@ 2022-11-17 14:01 ` Mads Ynddal
0 siblings, 0 replies; 10+ messages in thread
From: Mads Ynddal @ 2022-11-17 14:01 UTC (permalink / raw)
To: francesco.cagnin
Cc: qemu-devel, dirty, Peter Maydell, open list:ARM cores,
Alexander Graf, Paolo Bonzini, Alex Bennée,
Francesco Cagnin
> On 16 Nov 2022, at 18.47, francesco.cagnin@gmail.com wrote:
>
> From: Francesco Cagnin <fcagnin@quarkslab.com>
>
> This proved to be required when debugging the Linux kernel's initial
> code, as the Hypervisor framework was triggering 'EC_SYSTEMREGISTERTRAP'
> VM exits after enabling trap exceptions with
> 'hv_vcpu_set_trap_debug_exceptions()'.
>
> Signed-off-by: Francesco Cagnin <fcagnin@quarkslab.com>
> ---
> target/arm/hvf/hvf.c | 140 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 140 insertions(+)
Looks good to me.
Reviewed-by: Mads Ynddal <mads@ynddal.dk>
^ permalink raw reply [flat|nested] 10+ messages in thread