From: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrzej Hajda <andrzej.hajda@intel.com>, Neil Armstrong <neil.armstrong@linaro.org>, Robert Foss <robert.foss@linaro.org>, Jonas Karlman <jonas@kwiboo.se>, Jernej Skrabec <jernej.skrabec@gmail.com>, Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Subject: [PATCH v1 4/8] arm64: dts: renesas: r8a779g0: Add display related data Date: Thu, 17 Nov 2022 14:25:43 +0200 [thread overview] Message-ID: <20221117122547.809644-5-tomi.valkeinen@ideasonboard.com> (raw) In-Reply-To: <20221117122547.809644-1-tomi.valkeinen@ideasonboard.com> From: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Add DT nodes for components needed to get the DSI output working: - FCPv - VSPd - DU - DSI Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 129 ++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 45d8d927ad26..31d4930c5adc 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -1207,6 +1207,135 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; }; + + fcpvd0: fcp@fea10000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea10000 0 0x200>; + clocks = <&cpg CPG_MOD 508>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 508>; + }; + + fcpvd1: fcp@fea11000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea11000 0 0x200>; + clocks = <&cpg CPG_MOD 509>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 509>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 830>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 830>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 831>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 831>; + + renesas,fcp = <&fcpvd1>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a779g0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 411>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + du_out_dsi1: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 415>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi-encoder@fed90000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed90000 0 0x10000>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 416>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + }; timer { -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Neil Armstrong <neil.armstrong@linaro.org>, Jonas Karlman <jonas@kwiboo.se>, Jernej Skrabec <jernej.skrabec@gmail.com>, Robert Foss <robert.foss@linaro.org>, Andrzej Hajda <andrzej.hajda@intel.com>, Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Subject: [PATCH v1 4/8] arm64: dts: renesas: r8a779g0: Add display related data Date: Thu, 17 Nov 2022 14:25:43 +0200 [thread overview] Message-ID: <20221117122547.809644-5-tomi.valkeinen@ideasonboard.com> (raw) In-Reply-To: <20221117122547.809644-1-tomi.valkeinen@ideasonboard.com> From: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Add DT nodes for components needed to get the DSI output working: - FCPv - VSPd - DU - DSI Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 129 ++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 45d8d927ad26..31d4930c5adc 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -1207,6 +1207,135 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; }; + + fcpvd0: fcp@fea10000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea10000 0 0x200>; + clocks = <&cpg CPG_MOD 508>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 508>; + }; + + fcpvd1: fcp@fea11000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea11000 0 0x200>; + clocks = <&cpg CPG_MOD 509>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 509>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 830>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 830>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 831>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 831>; + + renesas,fcp = <&fcpvd1>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a779g0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 411>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + du_out_dsi1: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 415>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi-encoder@fed90000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed90000 0 0x10000>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 416>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + }; timer { -- 2.34.1
next prev parent reply other threads:[~2022-11-17 12:26 UTC|newest] Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-17 12:25 [PATCH v1 0/8] Renesas V4H DSI & DP output support Tomi Valkeinen 2022-11-17 12:25 ` Tomi Valkeinen 2022-11-17 12:25 ` [PATCH v1 1/8] dt-bindings: display: renesas,du: Provide bindings for r8a779g0 Tomi Valkeinen 2022-11-17 12:25 ` [PATCH v1 1/8] dt-bindings: display: renesas, du: " Tomi Valkeinen 2022-11-17 13:56 ` [PATCH v1 1/8] dt-bindings: display: renesas,du: " Kieran Bingham 2022-11-17 13:56 ` [PATCH v1 1/8] dt-bindings: display: renesas, du: " Kieran Bingham 2022-11-17 18:07 ` [PATCH v1 1/8] dt-bindings: display: renesas,du: " Krzysztof Kozlowski 2022-11-17 18:07 ` [PATCH v1 1/8] dt-bindings: display: renesas, du: " Krzysztof Kozlowski 2022-11-22 2:44 ` [PATCH v1 1/8] dt-bindings: display: renesas,du: " Laurent Pinchart 2022-11-22 2:44 ` Laurent Pinchart 2022-11-17 12:25 ` [PATCH v1 2/8] dt-bindings: display: bridge: renesas,dsi-csi2-tx: Add r8a779g0 Tomi Valkeinen 2022-11-17 12:25 ` [PATCH v1 2/8] dt-bindings: display: bridge: renesas, dsi-csi2-tx: " Tomi Valkeinen 2022-11-17 13:58 ` [PATCH v1 2/8] dt-bindings: display: bridge: renesas,dsi-csi2-tx: " Kieran Bingham 2022-11-17 13:58 ` [PATCH v1 2/8] dt-bindings: display: bridge: renesas, dsi-csi2-tx: " Kieran Bingham 2022-11-17 15:14 ` Geert Uytterhoeven 2022-11-17 15:14 ` [PATCH v1 2/8] dt-bindings: display: bridge: renesas,dsi-csi2-tx: " Geert Uytterhoeven 2022-11-22 2:45 ` Laurent Pinchart 2022-11-22 2:45 ` Laurent Pinchart 2022-11-22 8:20 ` Tomi Valkeinen 2022-11-22 8:20 ` [PATCH v1 2/8] dt-bindings: display: bridge: renesas, dsi-csi2-tx: " Tomi Valkeinen 2022-11-22 8:55 ` [PATCH v1 2/8] dt-bindings: display: bridge: renesas,dsi-csi2-tx: " Geert Uytterhoeven 2022-11-22 8:55 ` [PATCH v1 2/8] dt-bindings: display: bridge: renesas, dsi-csi2-tx: " Geert Uytterhoeven 2022-11-17 18:07 ` [PATCH v1 2/8] dt-bindings: display: bridge: renesas,dsi-csi2-tx: " Krzysztof Kozlowski 2022-11-17 18:07 ` [PATCH v1 2/8] dt-bindings: display: bridge: renesas, dsi-csi2-tx: " Krzysztof Kozlowski 2022-11-17 12:25 ` [PATCH v1 3/8] clk: renesas: r8a779g0: Add display related clocks Tomi Valkeinen 2022-11-17 12:25 ` Tomi Valkeinen 2022-11-17 14:08 ` Kieran Bingham 2022-11-17 14:08 ` Kieran Bingham 2022-11-22 2:52 ` Laurent Pinchart 2022-11-22 2:52 ` Laurent Pinchart 2022-11-17 12:25 ` Tomi Valkeinen [this message] 2022-11-17 12:25 ` [PATCH v1 4/8] arm64: dts: renesas: r8a779g0: Add display related data Tomi Valkeinen 2022-11-17 15:03 ` Kieran Bingham 2022-11-17 15:03 ` Kieran Bingham 2022-11-22 3:00 ` Laurent Pinchart 2022-11-22 3:00 ` Laurent Pinchart 2022-11-22 8:35 ` Tomi Valkeinen 2022-11-22 8:35 ` Tomi Valkeinen 2022-11-17 12:25 ` [PATCH v1 5/8] arm64: dts: renesas: white-hawk-cpu: Add DP output support Tomi Valkeinen 2022-11-17 12:25 ` Tomi Valkeinen 2022-11-17 15:05 ` Kieran Bingham 2022-11-17 15:05 ` Kieran Bingham 2022-11-22 3:01 ` Laurent Pinchart 2022-11-22 3:01 ` Laurent Pinchart 2022-11-17 12:25 ` [PATCH v1 6/8] drm: rcar-du: Add r8a779g0 support Tomi Valkeinen 2022-11-17 12:25 ` Tomi Valkeinen 2022-11-17 15:08 ` Kieran Bingham 2022-11-17 15:08 ` Kieran Bingham 2022-11-22 3:05 ` Laurent Pinchart 2022-11-22 3:05 ` Laurent Pinchart 2022-11-22 8:42 ` Tomi Valkeinen 2022-11-22 8:42 ` Tomi Valkeinen 2022-11-17 12:25 ` [PATCH v1 7/8] drm: rcar-du: dsi: Add r8A779g0 support Tomi Valkeinen 2022-11-17 12:25 ` Tomi Valkeinen 2022-11-17 15:46 ` Kieran Bingham 2022-11-17 15:46 ` Kieran Bingham 2022-11-17 15:49 ` Tomi Valkeinen 2022-11-17 15:49 ` Tomi Valkeinen 2022-11-17 15:56 ` Kieran Bingham 2022-11-17 15:56 ` Kieran Bingham 2022-11-22 8:50 ` Tomi Valkeinen 2022-11-22 8:50 ` Tomi Valkeinen 2022-11-29 0:43 ` Laurent Pinchart 2022-11-29 0:43 ` Laurent Pinchart 2022-11-29 6:57 ` Tomi Valkeinen 2022-11-29 6:57 ` Tomi Valkeinen 2022-11-17 12:25 ` [PATCH v1 8/8] HACK: drm: rcar-du: dsi: use-extal-clk hack Tomi Valkeinen 2022-11-17 12:25 ` Tomi Valkeinen 2022-11-17 12:28 ` [PATCH v1 0/8] Renesas V4H DSI & DP output support Tomi Valkeinen 2022-11-17 12:28 ` Tomi Valkeinen
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