[PATCH v2 0/3] RISC-V interrupt controller select cleanup

[PATCH v2 0/3] RISC-V interrupt controller select cleanup

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Hey Marc, Anup, Palmer,

Submitted a patch yesterday defaulting the SiFive PLIC driver to
enabled [0], and in the ensuing conversation Marc suggested just doing a
select at the arch level and dropping the user selectability completely.

Since we're already selecting SIFIVE_PLIC in Kconfig.socs for all of the
supported SoCs & selecting RISCV_INTC in the arch Kconfig itself,
patches 1 & 2 can go via the irqchip tree without any impact.

@Anup, by the same logic - I think we can also enable the AIA stuff via
selects at the arch level? Dumping as much from Kconfig.socs as possible
is the plan, so adding them there for SOC_VIRT kinda goes contrary to
that.

I spoke with Palmer today about putting my various bits of Kconfig.socs
cleanup on a branch, so I'll take patch 3. It's only in this series as
it is related work, rather due to any sort of dependency between the
patches.

Thanks,
Conor.

[0] https://lore.kernel.org/linux-riscv/86wn7tnx9a.wl-maz@kernel.org/

Conor Dooley (3):
  irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
  irqchip/riscv-intc: remove user selectability of RISCV_INTC
  RISC-V: stop selecting SIFIVE_PLIC at the SoC level

 arch/riscv/Kconfig      |  1 +
 arch/riscv/Kconfig.socs |  5 -----
 drivers/irqchip/Kconfig | 21 ++-------------------
 3 files changed, 3 insertions(+), 24 deletions(-)

-- 
2.37.2

[PATCH v2 0/3] RISC-V interrupt controller select cleanup

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Hey Marc, Anup, Palmer,

Submitted a patch yesterday defaulting the SiFive PLIC driver to
enabled [0], and in the ensuing conversation Marc suggested just doing a
select at the arch level and dropping the user selectability completely.

Since we're already selecting SIFIVE_PLIC in Kconfig.socs for all of the
supported SoCs & selecting RISCV_INTC in the arch Kconfig itself,
patches 1 & 2 can go via the irqchip tree without any impact.

@Anup, by the same logic - I think we can also enable the AIA stuff via
selects at the arch level? Dumping as much from Kconfig.socs as possible
is the plan, so adding them there for SOC_VIRT kinda goes contrary to
that.

I spoke with Palmer today about putting my various bits of Kconfig.socs
cleanup on a branch, so I'll take patch 3. It's only in this series as
it is related work, rather due to any sort of dependency between the
patches.

Thanks,
Conor.

[0] https://lore.kernel.org/linux-riscv/86wn7tnx9a.wl-maz@kernel.org/

Conor Dooley (3):
  irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
  irqchip/riscv-intc: remove user selectability of RISCV_INTC
  RISC-V: stop selecting SIFIVE_PLIC at the SoC level

 arch/riscv/Kconfig      |  1 +
 arch/riscv/Kconfig.socs |  5 -----
 drivers/irqchip/Kconfig | 21 ++-------------------
 3 files changed, 3 insertions(+), 24 deletions(-)

-- 
2.37.2


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[PATCH v2 1/3] irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

The SiFive PLIC driver is used by all current implementations, including
those that do not have a SiFive PLIC. The current driver supports more
than just SiFive PLICs at present and, where possible, future PLIC
implementations will also use this driver. As every supported RISC-V SoC
selects the driver directly in Kconfig.socs there's no point in exposing
this kconfig option to users.

The Kconfig help text, in its current form, is misleading. There's no
point doing anything about that though, as it will no longer be user
selectable. Remove it.

Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 drivers/irqchip/Kconfig | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7ef9f5e696d3..ecb3e3119d2e 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -551,18 +551,10 @@ config RISCV_INTC
 	   If you don't know what to do here, say Y.
 
 config SIFIVE_PLIC
-	bool "SiFive Platform-Level Interrupt Controller"
+	bool
 	depends on RISCV
 	select IRQ_DOMAIN_HIERARCHY
 	select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
-	help
-	   This enables support for the PLIC chip found in SiFive (and
-	   potentially other) RISC-V systems.  The PLIC controls devices
-	   interrupts and connects them to each core's local interrupt
-	   controller.  Aside from timer and software interrupts, all other
-	   interrupt sources are subordinate to the PLIC.
-
-	   If you don't know what to do here, say Y.
 
 config EXYNOS_IRQ_COMBINER
 	bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
-- 
2.37.2

[PATCH v2 1/3] irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

The SiFive PLIC driver is used by all current implementations, including
those that do not have a SiFive PLIC. The current driver supports more
than just SiFive PLICs at present and, where possible, future PLIC
implementations will also use this driver. As every supported RISC-V SoC
selects the driver directly in Kconfig.socs there's no point in exposing
this kconfig option to users.

The Kconfig help text, in its current form, is misleading. There's no
point doing anything about that though, as it will no longer be user
selectable. Remove it.

Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 drivers/irqchip/Kconfig | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7ef9f5e696d3..ecb3e3119d2e 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -551,18 +551,10 @@ config RISCV_INTC
 	   If you don't know what to do here, say Y.
 
 config SIFIVE_PLIC
-	bool "SiFive Platform-Level Interrupt Controller"
+	bool
 	depends on RISCV
 	select IRQ_DOMAIN_HIERARCHY
 	select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
-	help
-	   This enables support for the PLIC chip found in SiFive (and
-	   potentially other) RISC-V systems.  The PLIC controls devices
-	   interrupts and connects them to each core's local interrupt
-	   controller.  Aside from timer and software interrupts, all other
-	   interrupt sources are subordinate to the PLIC.
-
-	   If you don't know what to do here, say Y.
 
 config EXYNOS_IRQ_COMBINER
 	bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
-- 
2.37.2


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[PATCH v2 2/3] irqchip/riscv-intc: remove user selectability of RISCV_INTC

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Since commit e71ee06e3ca3 ("RISC-V: Force select RISCV_INTC for
CONFIG_RISCV") the driver has been enabled at the arch level - and is
mandatory anyway. There's no point exposing this as a choice to users,
so stop bothering.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
I'd swear I had an interaction with someone a few months ago about the
RISCV_INTC Kconfig options but I cannot for the file of me remember who.
I hope this patch is not be going back on what I said then...
---
 drivers/irqchip/Kconfig | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index ecb3e3119d2e..4633a549ebbf 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -538,17 +538,8 @@ config TI_PRUSS_INTC
 	  different processors within the SoC.
 
 config RISCV_INTC
-	bool "RISC-V Local Interrupt Controller"
+	bool
 	depends on RISCV
-	default y
-	help
-	   This enables support for the per-HART local interrupt controller
-	   found in standard RISC-V systems.  The per-HART local interrupt
-	   controller handles timer interrupts, software interrupts, and
-	   hardware interrupts. Without a per-HART local interrupt controller,
-	   a RISC-V system will be unable to handle any interrupts.
-
-	   If you don't know what to do here, say Y.
 
 config SIFIVE_PLIC
 	bool
-- 
2.37.2

[PATCH v2 2/3] irqchip/riscv-intc: remove user selectability of RISCV_INTC

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Since commit e71ee06e3ca3 ("RISC-V: Force select RISCV_INTC for
CONFIG_RISCV") the driver has been enabled at the arch level - and is
mandatory anyway. There's no point exposing this as a choice to users,
so stop bothering.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
I'd swear I had an interaction with someone a few months ago about the
RISCV_INTC Kconfig options but I cannot for the file of me remember who.
I hope this patch is not be going back on what I said then...
---
 drivers/irqchip/Kconfig | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index ecb3e3119d2e..4633a549ebbf 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -538,17 +538,8 @@ config TI_PRUSS_INTC
 	  different processors within the SoC.
 
 config RISCV_INTC
-	bool "RISC-V Local Interrupt Controller"
+	bool
 	depends on RISCV
-	default y
-	help
-	   This enables support for the per-HART local interrupt controller
-	   found in standard RISC-V systems.  The per-HART local interrupt
-	   controller handles timer interrupts, software interrupts, and
-	   hardware interrupts. Without a per-HART local interrupt controller,
-	   a RISC-V system will be unable to handle any interrupts.
-
-	   If you don't know what to do here, say Y.
 
 config SIFIVE_PLIC
 	bool
-- 
2.37.2


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[PATCH v2 3/3] RISC-V: stop selecting SIFIVE_PLIC at the SoC level

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

The SIFIVE_PLIC driver is used by all current RISC-V SoCs & will be,
where possible, used for future implementations. Rather than having each
driver select the option on a case-by-case basis, do so at the arch
level.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/Kconfig      | 1 +
 arch/riscv/Kconfig.socs | 5 -----
 2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa78595a6089..846f61254dfc 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -123,6 +123,7 @@ config RISCV
 	select PCI_MSI if PCI
 	select RISCV_INTC
 	select RISCV_TIMER if RISCV_SBI
+	select SIFIVE_PLIC
 	select SPARSE_IRQ
 	select SYSCTL_EXCEPTION_TRACE
 	select THREAD_INFO_IN_TASK
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..15e391f38f75 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -3,7 +3,6 @@ menu "SoC selection"
 config SOC_MICROCHIP_POLARFIRE
 	bool "Microchip PolarFire SoCs"
 	select MCHP_CLK_MPFS
-	select SIFIVE_PLIC
 	help
 	  This enables support for Microchip PolarFire SoC platforms.
 
@@ -13,7 +12,6 @@ config SOC_SIFIVE
 	select SERIAL_SIFIVE_CONSOLE if TTY
 	select CLK_SIFIVE
 	select CLK_SIFIVE_PRCI
-	select SIFIVE_PLIC
 	select ERRATA_SIFIVE if !XIP_KERNEL
 	help
 	  This enables support for SiFive SoC platform hardware.
@@ -22,7 +20,6 @@ config SOC_STARFIVE
 	bool "StarFive SoCs"
 	select PINCTRL
 	select RESET_CONTROLLER
-	select SIFIVE_PLIC
 	help
 	  This enables support for StarFive SoC platform hardware.
 
@@ -34,7 +31,6 @@ config SOC_VIRT
 	select POWER_RESET_SYSCON_POWEROFF
 	select GOLDFISH
 	select RTC_DRV_GOLDFISH if RTC_CLASS
-	select SIFIVE_PLIC
 	select PM_GENERIC_DOMAINS if PM
 	select PM_GENERIC_DOMAINS_OF if PM && OF
 	select RISCV_SBI_CPUIDLE if CPU_IDLE && RISCV_SBI
@@ -47,7 +43,6 @@ config SOC_CANAAN
 	select CLINT_TIMER if RISCV_M_MODE
 	select SERIAL_SIFIVE if TTY
 	select SERIAL_SIFIVE_CONSOLE if TTY
-	select SIFIVE_PLIC
 	select ARCH_HAS_RESET_CONTROLLER
 	select PINCTRL
 	select COMMON_CLK
-- 
2.37.2

[PATCH v2 3/3] RISC-V: stop selecting SIFIVE_PLIC at the SoC level

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

The SIFIVE_PLIC driver is used by all current RISC-V SoCs & will be,
where possible, used for future implementations. Rather than having each
driver select the option on a case-by-case basis, do so at the arch
level.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/Kconfig      | 1 +
 arch/riscv/Kconfig.socs | 5 -----
 2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa78595a6089..846f61254dfc 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -123,6 +123,7 @@ config RISCV
 	select PCI_MSI if PCI
 	select RISCV_INTC
 	select RISCV_TIMER if RISCV_SBI
+	select SIFIVE_PLIC
 	select SPARSE_IRQ
 	select SYSCTL_EXCEPTION_TRACE
 	select THREAD_INFO_IN_TASK
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..15e391f38f75 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -3,7 +3,6 @@ menu "SoC selection"
 config SOC_MICROCHIP_POLARFIRE
 	bool "Microchip PolarFire SoCs"
 	select MCHP_CLK_MPFS
-	select SIFIVE_PLIC
 	help
 	  This enables support for Microchip PolarFire SoC platforms.
 
@@ -13,7 +12,6 @@ config SOC_SIFIVE
 	select SERIAL_SIFIVE_CONSOLE if TTY
 	select CLK_SIFIVE
 	select CLK_SIFIVE_PRCI
-	select SIFIVE_PLIC
 	select ERRATA_SIFIVE if !XIP_KERNEL
 	help
 	  This enables support for SiFive SoC platform hardware.
@@ -22,7 +20,6 @@ config SOC_STARFIVE
 	bool "StarFive SoCs"
 	select PINCTRL
 	select RESET_CONTROLLER
-	select SIFIVE_PLIC
 	help
 	  This enables support for StarFive SoC platform hardware.
 
@@ -34,7 +31,6 @@ config SOC_VIRT
 	select POWER_RESET_SYSCON_POWEROFF
 	select GOLDFISH
 	select RTC_DRV_GOLDFISH if RTC_CLASS
-	select SIFIVE_PLIC
 	select PM_GENERIC_DOMAINS if PM
 	select PM_GENERIC_DOMAINS_OF if PM && OF
 	select RISCV_SBI_CPUIDLE if CPU_IDLE && RISCV_SBI
@@ -47,7 +43,6 @@ config SOC_CANAAN
 	select CLINT_TIMER if RISCV_M_MODE
 	select SERIAL_SIFIVE if TTY
 	select SERIAL_SIFIVE_CONSOLE if TTY
-	select SIFIVE_PLIC
 	select ARCH_HAS_RESET_CONTROLLER
 	select PINCTRL
 	select COMMON_CLK
-- 
2.37.2


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Re: [PATCH v2 0/3] RISC-V interrupt controller select cleanup

[Marc Zyngier]

On Fri, 18 Nov 2022 10:42:58 +0000,
Conor Dooley <conor@kernel.org> wrote:
> 
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Hey Marc, Anup, Palmer,
> 
> Submitted a patch yesterday defaulting the SiFive PLIC driver to
> enabled [0], and in the ensuing conversation Marc suggested just doing a
> select at the arch level and dropping the user selectability completely.
> 
> Since we're already selecting SIFIVE_PLIC in Kconfig.socs for all of the
> supported SoCs & selecting RISCV_INTC in the arch Kconfig itself,
> patches 1 & 2 can go via the irqchip tree without any impact.
> 
> @Anup, by the same logic - I think we can also enable the AIA stuff via
> selects at the arch level? Dumping as much from Kconfig.socs as possible
> is the plan, so adding them there for SOC_VIRT kinda goes contrary to
> that.
> 
> I spoke with Palmer today about putting my various bits of Kconfig.socs
> cleanup on a branch, so I'll take patch 3. It's only in this series as
> it is related work, rather due to any sort of dependency between the
> patches.
> 
> Thanks,
> Conor.
> 
> [0] https://lore.kernel.org/linux-riscv/86wn7tnx9a.wl-maz@kernel.org/
> 
> Conor Dooley (3):
>   irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
>   irqchip/riscv-intc: remove user selectability of RISCV_INTC
>   RISC-V: stop selecting SIFIVE_PLIC at the SoC level
> 
>  arch/riscv/Kconfig      |  1 +
>  arch/riscv/Kconfig.socs |  5 -----
>  drivers/irqchip/Kconfig | 21 ++-------------------
>  3 files changed, 3 insertions(+), 24 deletions(-)

For the series:

Acked-by: Marc Zyngier <maz@kernel.org>

Please take the whole thing via the RISC-V tree.

Thanks,

	M.

-- 
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Re: [PATCH v2 0/3] RISC-V interrupt controller select cleanup

[Marc Zyngier]

On Fri, 18 Nov 2022 10:42:58 +0000,
Conor Dooley <conor@kernel.org> wrote:
> 
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Hey Marc, Anup, Palmer,
> 
> Submitted a patch yesterday defaulting the SiFive PLIC driver to
> enabled [0], and in the ensuing conversation Marc suggested just doing a
> select at the arch level and dropping the user selectability completely.
> 
> Since we're already selecting SIFIVE_PLIC in Kconfig.socs for all of the
> supported SoCs & selecting RISCV_INTC in the arch Kconfig itself,
> patches 1 & 2 can go via the irqchip tree without any impact.
> 
> @Anup, by the same logic - I think we can also enable the AIA stuff via
> selects at the arch level? Dumping as much from Kconfig.socs as possible
> is the plan, so adding them there for SOC_VIRT kinda goes contrary to
> that.
> 
> I spoke with Palmer today about putting my various bits of Kconfig.socs
> cleanup on a branch, so I'll take patch 3. It's only in this series as
> it is related work, rather due to any sort of dependency between the
> patches.
> 
> Thanks,
> Conor.
> 
> [0] https://lore.kernel.org/linux-riscv/86wn7tnx9a.wl-maz@kernel.org/
> 
> Conor Dooley (3):
>   irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
>   irqchip/riscv-intc: remove user selectability of RISCV_INTC
>   RISC-V: stop selecting SIFIVE_PLIC at the SoC level
> 
>  arch/riscv/Kconfig      |  1 +
>  arch/riscv/Kconfig.socs |  5 -----
>  drivers/irqchip/Kconfig | 21 ++-------------------
>  3 files changed, 3 insertions(+), 24 deletions(-)

For the series:

Acked-by: Marc Zyngier <maz@kernel.org>

Please take the whole thing via the RISC-V tree.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 0/3] RISC-V interrupt controller select cleanup

[Palmer Dabbelt]

On Fri, 18 Nov 2022 10:42:58 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Hey Marc, Anup, Palmer,
> 
> Submitted a patch yesterday defaulting the SiFive PLIC driver to
> enabled [0], and in the ensuing conversation Marc suggested just doing a
> select at the arch level and dropping the user selectability completely.
> 
> [...]

Applied, thanks!

[1/3] irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
      https://git.kernel.org/palmer/c/fdb1742aff43
[2/3] irqchip/riscv-intc: remove user selectability of RISCV_INTC
      https://git.kernel.org/palmer/c/d8fb13070c3c
[3/3] RISC-V: stop selecting SIFIVE_PLIC at the SoC level
      https://git.kernel.org/palmer/c/bf3d7b1d8499

Best regards,
-- 
Palmer Dabbelt <palmer@rivosinc.com>

Re: [PATCH v2 0/3] RISC-V interrupt controller select cleanup

[Palmer Dabbelt]

On Fri, 18 Nov 2022 10:42:58 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Hey Marc, Anup, Palmer,
> 
> Submitted a patch yesterday defaulting the SiFive PLIC driver to
> enabled [0], and in the ensuing conversation Marc suggested just doing a
> select at the arch level and dropping the user selectability completely.
> 
> [...]

Applied, thanks!

[1/3] irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
      https://git.kernel.org/palmer/c/fdb1742aff43
[2/3] irqchip/riscv-intc: remove user selectability of RISCV_INTC
      https://git.kernel.org/palmer/c/d8fb13070c3c
[3/3] RISC-V: stop selecting SIFIVE_PLIC at the SoC level
      https://git.kernel.org/palmer/c/bf3d7b1d8499

Best regards,
-- 
Palmer Dabbelt <palmer@rivosinc.com>

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Re: [PATCH v2 0/3] RISC-V interrupt controller select cleanup

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Fri, 18 Nov 2022 10:42:58 +0000 you wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Hey Marc, Anup, Palmer,
> 
> Submitted a patch yesterday defaulting the SiFive PLIC driver to
> enabled [0], and in the ensuing conversation Marc suggested just doing a
> select at the arch level and dropping the user selectability completely.
> 
> [...]

Here is the summary with links:
  - [v2,1/3] irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
    https://git.kernel.org/riscv/c/fdb1742aff43
  - [v2,2/3] irqchip/riscv-intc: remove user selectability of RISCV_INTC
    https://git.kernel.org/riscv/c/d8fb13070c3c
  - [v2,3/3] RISC-V: stop selecting SIFIVE_PLIC at the SoC level
    https://git.kernel.org/riscv/c/bf3d7b1d8499

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
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Re: [PATCH v2 0/3] RISC-V interrupt controller select cleanup

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Fri, 18 Nov 2022 10:42:58 +0000 you wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Hey Marc, Anup, Palmer,
> 
> Submitted a patch yesterday defaulting the SiFive PLIC driver to
> enabled [0], and in the ensuing conversation Marc suggested just doing a
> select at the arch level and dropping the user selectability completely.
> 
> [...]

Here is the summary with links:
  - [v2,1/3] irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
    https://git.kernel.org/riscv/c/fdb1742aff43
  - [v2,2/3] irqchip/riscv-intc: remove user selectability of RISCV_INTC
    https://git.kernel.org/riscv/c/d8fb13070c3c
  - [v2,3/3] RISC-V: stop selecting SIFIVE_PLIC at the SoC level
    https://git.kernel.org/riscv/c/bf3d7b1d8499

You are awesome, thank you!
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