* [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4
@ 2022-11-22 5:50 Yifan Zhang
2022-11-22 5:50 ` [PATCH 02/19] drm/amdgpu/discovery: enable gmc v11 " Yifan Zhang
` (17 more replies)
0 siblings, 18 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
Enable soc21 common for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 2509341df92d..b8db6184dcbd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1512,6 +1512,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
+ case IP_VERSION(11, 0, 4):
amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
break;
default:
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 02/19] drm/amdgpu/discovery: enable gmc v11 for GC 11.0.4
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 03/19] drm/amdgpu/discovery: enable gfx " Yifan Zhang
` (16 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
Enable gmc (graphic memory controller) v11 for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index b8db6184dcbd..a047db7f8ed5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1557,6 +1557,7 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
+ case IP_VERSION(11, 0, 4):
amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
break;
default:
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 03/19] drm/amdgpu/discovery: enable gfx v11 for GC 11.0.4
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
2022-11-22 5:50 ` [PATCH 02/19] drm/amdgpu/discovery: enable gmc v11 " Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 04/19] drm/amdgpu/discovery: enable mes support for GC v11.0.4 Yifan Zhang
` (15 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
Enable gfx v11 for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index a047db7f8ed5..de8c2d81e09f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1806,6 +1806,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
+ case IP_VERSION(11, 0, 4):
amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
break;
default:
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 04/19] drm/amdgpu/discovery: enable mes support for GC v11.0.4
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
2022-11-22 5:50 ` [PATCH 02/19] drm/amdgpu/discovery: enable gmc v11 " Yifan Zhang
2022-11-22 5:50 ` [PATCH 03/19] drm/amdgpu/discovery: enable gfx " Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 05/19] drm/amdgpu/discovery: add PSP IP v13.0.11 support Yifan Zhang
` (14 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
this patch is to enable mes for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index de8c2d81e09f..45fe805b5f5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1970,6 +1970,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
+ case IP_VERSION(11, 0, 4):
amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
adev->enable_mes = true;
adev->enable_mes_kiq = true;
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 05/19] drm/amdgpu/discovery: add PSP IP v13.0.11 support
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (2 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 04/19] drm/amdgpu/discovery: enable mes support for GC v11.0.4 Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 06/19] drm/amdgpu: set GC 11.0.4 family Yifan Zhang
` (13 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim Huang, Xiaojian.Du, Yifan Zhang
From: Tim Huang <tim.huang@amd.com>
Add PSP IP v13.0.11 ip discovery support.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 45fe805b5f5c..49ed3c826088 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1643,6 +1643,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 7):
case IP_VERSION(13, 0, 8):
case IP_VERSION(13, 0, 10):
+ case IP_VERSION(13, 0, 11):
amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
break;
case IP_VERSION(13, 0, 4):
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 06/19] drm/amdgpu: set GC 11.0.4 family
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (3 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 05/19] drm/amdgpu/discovery: add PSP IP v13.0.11 support Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 07/19] drm/amdgpu/discovery: set the APU flag for GC 11.0.4 Yifan Zhang
` (12 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
this patch is to set GC 11.0.4 family.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 49ed3c826088..524e2aa849c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2202,6 +2202,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
adev->family = AMDGPU_FAMILY_GC_11_0_0;
break;
case IP_VERSION(11, 0, 1):
+ case IP_VERSION(11, 0, 4):
adev->family = AMDGPU_FAMILY_GC_11_0_1;
break;
default:
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 07/19] drm/amdgpu/discovery: set the APU flag for GC 11.0.4
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (4 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 06/19] drm/amdgpu: set GC 11.0.4 family Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 08/19] drm/amdgpu: add gfx support " Yifan Zhang
` (11 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
Set the APU flag appropriately for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 524e2aa849c0..19dbd75a6176 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2220,6 +2220,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(10, 3, 6):
case IP_VERSION(10, 3, 7):
case IP_VERSION(11, 0, 1):
+ case IP_VERSION(11, 0, 4):
adev->flags |= AMD_IS_APU;
break;
default:
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 08/19] drm/amdgpu: add gfx support for GC 11.0.4
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (5 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 07/19] drm/amdgpu/discovery: set the APU flag for GC 11.0.4 Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 09/19] drm/amdgpu: add soc21 common ip block " Yifan Zhang
` (10 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
this patch to add GC 11.0.4 gfx support to gfx11 implementation.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 9d2c6523f546..bf78440e1e70 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -77,6 +77,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin");
MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin");
MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin");
MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin");
static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
{
@@ -262,6 +266,7 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
{
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(11, 0, 1):
+ case IP_VERSION(11, 0, 4):
soc15_program_register_sequence(adev,
golden_settings_gc_11_0_1,
(const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
@@ -855,6 +860,7 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
break;
case IP_VERSION(11, 0, 1):
+ case IP_VERSION(11, 0, 4):
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -1284,6 +1290,7 @@ static int gfx_v11_0_sw_init(void *handle)
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
+ case IP_VERSION(11, 0, 4):
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1;
@@ -2486,7 +2493,8 @@ static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
for (i = 0; i < adev->usec_timeout; i++) {
cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
- if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1))
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) ||
+ adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 4))
bootload_status = RREG32_SOC15(GC, 0,
regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
else
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 09/19] drm/amdgpu: add soc21 common ip block support for GC 11.0.4
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (6 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 08/19] drm/amdgpu: add gfx support " Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 10/19] drm/amdgpu: add gmc v11 " Yifan Zhang
` (9 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
Add common soc21 ip block support for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index b258e9aa0558..69dac2aa8151 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -644,6 +644,12 @@ static int soc21_common_early_init(void *handle)
AMD_PG_SUPPORT_JPEG;
adev->external_rev_id = adev->rev_id + 0x20;
break;
+ case IP_VERSION(11, 0, 4):
+ adev->cg_flags = 0;
+ adev->pg_flags = 0;
+ adev->external_rev_id = adev->rev_id + 0x1;
+ break;
+
default:
/* FIXME: not supported yet */
return -EINVAL;
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 10/19] drm/amdgpu: add gmc v11 support for GC 11.0.4
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (7 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 09/19] drm/amdgpu: add soc21 common ip block " Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 11/19] drm/amdkfd: add GC 11.0.4 KFD support Yifan Zhang
` (8 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
Add gmc v11 support for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 96e52ec0fb69..4326078689cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -759,6 +759,7 @@ static int gmc_v11_0_sw_init(void *handle)
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
+ case IP_VERSION(11, 0, 4):
adev->num_vmhubs = 2;
/*
* To fulfill 4-level page support,
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 11/19] drm/amdkfd: add GC 11.0.4 KFD support
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (8 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 10/19] drm/amdgpu: add gmc v11 " Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 12/19] drm/amdgpu/pm: enable swsmu for SMU IP v13.0.11 Yifan Zhang
` (7 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
Add initial support for GC 11.0.4 in KFD compute driver.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index af01ba061e1b..3251f4783ba1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1521,6 +1521,7 @@ int kfd_get_gpu_cache_info(struct kfd_dev *kdev, struct kfd_gpu_cache_info **pca
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
+ case IP_VERSION(11, 0, 4):
num_of_cache_types =
kfd_fill_gpu_cache_info_from_gfx_config(kdev, *pcache_info);
break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index b4d24600e1db..091fc2bb8ce5 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -154,6 +154,7 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
+ case IP_VERSION(11, 0, 4):
kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
break;
default:
@@ -395,6 +396,7 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
f2g = &gfx_v11_kfd2kgd;
break;
case IP_VERSION(11, 0, 1):
+ case IP_VERSION(11, 0, 4):
gfx_target_version = 110003;
f2g = &gfx_v11_kfd2kgd;
break;
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 12/19] drm/amdgpu/pm: enable swsmu for SMU IP v13.0.11
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (9 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 11/19] drm/amdkfd: add GC 11.0.4 KFD support Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 13/19] drm/amdgpu: add smu 13 support for smu 13.0.11 Yifan Zhang
` (6 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
Add the entry to set the ppt functions for SMU IP v13.0.11.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 20e5f66f853f..61eafaf09912 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -585,6 +585,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
yellow_carp_set_ppt_funcs(smu);
break;
case IP_VERSION(13, 0, 4):
+ case IP_VERSION(13, 0, 11):
smu_v13_0_4_set_ppt_funcs(smu);
break;
case IP_VERSION(13, 0, 5):
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 13/19] drm/amdgpu: add smu 13 support for smu 13.0.11
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (10 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 12/19] drm/amdgpu/pm: enable swsmu for SMU IP v13.0.11 Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 14/19] drm/amdgpu/pm: add GFXOFF control IP version check for SMU IP v13.0.11 Yifan Zhang
` (5 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
this patch to add smu 13 support for smu 13.0.11.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 19dbd75a6176..ac0f0e09a60c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1694,6 +1694,7 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 7):
case IP_VERSION(13, 0, 8):
case IP_VERSION(13, 0, 10):
+ case IP_VERSION(13, 0, 11):
amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
break;
default:
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 53abd7709242..6a9bdfda4e6f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -250,6 +250,7 @@ int smu_v13_0_check_fw_status(struct smu_context *smu)
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 4):
+ case IP_VERSION(13, 0, 11):
mp1_fw_flags = RREG32_PCIE(MP1_Public |
(smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
break;
@@ -301,6 +302,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
break;
case IP_VERSION(13, 0, 4):
+ case IP_VERSION(13, 0, 11):
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4;
break;
case IP_VERSION(13, 0, 5):
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 14/19] drm/amdgpu/pm: add GFXOFF control IP version check for SMU IP v13.0.11
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (11 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 13/19] drm/amdgpu: add smu 13 support for smu 13.0.11 Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 15/19] drm/amdgpu/soc21: add mode2 asic reset " Yifan Zhang
` (4 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
Enable the SMU IP v13.0.11 GFXOFF control
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 6a9bdfda4e6f..f5e90e0a99df 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -843,6 +843,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
case IP_VERSION(13, 0, 7):
case IP_VERSION(13, 0, 8):
case IP_VERSION(13, 0, 10):
+ case IP_VERSION(13, 0, 11):
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0;
if (enable)
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 15/19] drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.11
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (12 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 14/19] drm/amdgpu/pm: add GFXOFF control IP version check for SMU IP v13.0.11 Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 16/19] drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4 Yifan Zhang
` (3 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim Huang, Xiaojian.Du, Yifan Zhang
From: Tim Huang <tim.huang@amd.com>
Set the default reset method to mode2 for SMU IP v13.0.11
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 69dac2aa8151..ba11e06d6941 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -325,6 +325,7 @@ soc21_asic_reset_method(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 10):
return AMD_RESET_METHOD_MODE1;
case IP_VERSION(13, 0, 4):
+ case IP_VERSION(13, 0, 11):
return AMD_RESET_METHOD_MODE2;
default:
if (amdgpu_dpm_is_baco_supported(adev))
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 16/19] drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (13 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 15/19] drm/amdgpu/soc21: add mode2 asic reset " Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 17/19] drm/amdgpu/discovery: enable nbio support for NBIO v7.7.1 Yifan Zhang
` (2 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim Huang, Xiaojian.Du, Yifan Zhang
From: Tim Huang <tim.huang@amd.com>
The SMU IP v13.0.4 ppt interface is shared by IP v13.0.11, they use
the different mailbox register offset. So use the specific mailbox
registers offset for v13.0.4.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 97e1d55dcaad..8fa9a36c38b6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -1026,6 +1026,15 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = {
.set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu,
};
+static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+}
+
void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
@@ -1035,7 +1044,9 @@ void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
smu->feature_map = smu_v13_0_4_feature_mask_map;
smu->table_map = smu_v13_0_4_table_map;
smu->is_apu = true;
- smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
- smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
- smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
+ smu_v13_0_4_set_smu_mailbox_registers(smu);
+ else
+ smu_v13_0_set_smu_mailbox_registers(smu);
}
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 17/19] drm/amdgpu/discovery: enable nbio support for NBIO v7.7.1
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (14 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 16/19] drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4 Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 18/19] drm/amdgpu: Enable pg/cg flags on GC11_0_4 for VCN Yifan Zhang
2022-11-22 5:50 ` [PATCH 19/19] drm/amdgpu: enable PSP IP v13.0.11 support Yifan Zhang
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim.Huang, Xiaojian.Du, Yifan Zhang
this patch is to enable nbio support for NBIO v7.7.1.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index ac0f0e09a60c..1bbd56029a4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2278,6 +2278,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
break;
case IP_VERSION(7, 7, 0):
+ case IP_VERSION(7, 7, 1):
adev->nbio.funcs = &nbio_v7_7_funcs;
adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
break;
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 18/19] drm/amdgpu: Enable pg/cg flags on GC11_0_4 for VCN
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (15 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 17/19] drm/amdgpu/discovery: enable nbio support for NBIO v7.7.1 Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-22 5:50 ` [PATCH 19/19] drm/amdgpu: enable PSP IP v13.0.11 support Yifan Zhang
17 siblings, 0 replies; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx
Cc: Tim.Huang, Xiaojian.Du, Yifan Zhang, Alexander.Deucher, Leo Liu,
Saleemkhan Jamadar
From: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
This enable VCN PG, CG and JPEG PG, CG
Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index ba11e06d6941..7ec428279d78 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -646,8 +646,11 @@ static int soc21_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x20;
break;
case IP_VERSION(11, 0, 4):
- adev->cg_flags = 0;
- adev->pg_flags = 0;
+ adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
+ AMD_CG_SUPPORT_JPEG_MGCG;
+ adev->pg_flags = AMD_PG_SUPPORT_VCN |
+ AMD_PG_SUPPORT_GFX_PG |
+ AMD_PG_SUPPORT_JPEG;
adev->external_rev_id = adev->rev_id + 0x1;
break;
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 19/19] drm/amdgpu: enable PSP IP v13.0.11 support
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
` (16 preceding siblings ...)
2022-11-22 5:50 ` [PATCH 18/19] drm/amdgpu: Enable pg/cg flags on GC11_0_4 for VCN Yifan Zhang
@ 2022-11-22 5:50 ` Yifan Zhang
2022-11-23 1:44 ` Liu, Aaron
17 siblings, 1 reply; 20+ messages in thread
From: Yifan Zhang @ 2022-11-22 5:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Tim Huang, Xiaojian.Du, Yifan Zhang
From: Tim Huang <tim.huang@amd.com>
Enable PSP FW loading for PSP IP v13.0.11
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 7bb2de1d11ff..4670b86ebf74 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -165,6 +165,7 @@ static int psp_early_init(void *handle)
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 8):
case IP_VERSION(13, 0, 10):
+ case IP_VERSION(13, 0, 11):
psp_v13_0_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 2abf48f187fa..1c7eb46aa4e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -45,6 +45,8 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
+MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
+MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
/* For large FW files the time to complete can be very long */
#define USBC_PD_POLLING_LIMIT_S 240
@@ -101,6 +103,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
case IP_VERSION(13, 0, 3):
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 8):
+ case IP_VERSION(13, 0, 11):
err = psp_init_toc_microcode(psp, chip_name);
if (err)
return err;
--
2.37.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* RE: [PATCH 19/19] drm/amdgpu: enable PSP IP v13.0.11 support
2022-11-22 5:50 ` [PATCH 19/19] drm/amdgpu: enable PSP IP v13.0.11 support Yifan Zhang
@ 2022-11-23 1:44 ` Liu, Aaron
0 siblings, 0 replies; 20+ messages in thread
From: Liu, Aaron @ 2022-11-23 1:44 UTC (permalink / raw)
To: Zhang, Yifan, amd-gfx
Cc: Deucher, Alexander, Huang, Tim, Du, Xiaojian, Zhang, Yifan
[-- Attachment #1: Type: text/plain, Size: 2476 bytes --]
[AMD Official Use Only - General]
Series is
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Yifan
> Zhang
> Sent: Tuesday, November 22, 2022 1:50 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Huang, Tim
> <Tim.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Zhang, Yifan
> <Yifan1.Zhang@amd.com>
> Subject: [PATCH 19/19] drm/amdgpu: enable PSP IP v13.0.11 support
>
> From: Tim Huang <tim.huang@amd.com>
>
> Enable PSP FW loading for PSP IP v13.0.11
>
> Signed-off-by: Tim Huang <tim.huang@amd.com>
> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
> drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 7bb2de1d11ff..4670b86ebf74 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -165,6 +165,7 @@ static int psp_early_init(void *handle)
> case IP_VERSION(13, 0, 5):
> case IP_VERSION(13, 0, 8):
> case IP_VERSION(13, 0, 10):
> + case IP_VERSION(13, 0, 11):
> psp_v13_0_set_psp_funcs(psp);
> psp->autoload_supported = true;
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> index 2abf48f187fa..1c7eb46aa4e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> @@ -45,6 +45,8 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
> MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
> MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
> MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
> +MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
> +MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
>
> /* For large FW files the time to complete can be very long */ #define
> USBC_PD_POLLING_LIMIT_S 240 @@ -101,6 +103,7 @@ static int
> psp_v13_0_init_microcode(struct psp_context *psp)
> case IP_VERSION(13, 0, 3):
> case IP_VERSION(13, 0, 5):
> case IP_VERSION(13, 0, 8):
> + case IP_VERSION(13, 0, 11):
> err = psp_init_toc_microcode(psp, chip_name);
> if (err)
> return err;
> --
> 2.37.3
[-- Attachment #2: winmail.dat --]
[-- Type: application/ms-tnef, Size: 16201 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-11-23 1:44 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-22 5:50 [PATCH 01/19] drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Yifan Zhang
2022-11-22 5:50 ` [PATCH 02/19] drm/amdgpu/discovery: enable gmc v11 " Yifan Zhang
2022-11-22 5:50 ` [PATCH 03/19] drm/amdgpu/discovery: enable gfx " Yifan Zhang
2022-11-22 5:50 ` [PATCH 04/19] drm/amdgpu/discovery: enable mes support for GC v11.0.4 Yifan Zhang
2022-11-22 5:50 ` [PATCH 05/19] drm/amdgpu/discovery: add PSP IP v13.0.11 support Yifan Zhang
2022-11-22 5:50 ` [PATCH 06/19] drm/amdgpu: set GC 11.0.4 family Yifan Zhang
2022-11-22 5:50 ` [PATCH 07/19] drm/amdgpu/discovery: set the APU flag for GC 11.0.4 Yifan Zhang
2022-11-22 5:50 ` [PATCH 08/19] drm/amdgpu: add gfx support " Yifan Zhang
2022-11-22 5:50 ` [PATCH 09/19] drm/amdgpu: add soc21 common ip block " Yifan Zhang
2022-11-22 5:50 ` [PATCH 10/19] drm/amdgpu: add gmc v11 " Yifan Zhang
2022-11-22 5:50 ` [PATCH 11/19] drm/amdkfd: add GC 11.0.4 KFD support Yifan Zhang
2022-11-22 5:50 ` [PATCH 12/19] drm/amdgpu/pm: enable swsmu for SMU IP v13.0.11 Yifan Zhang
2022-11-22 5:50 ` [PATCH 13/19] drm/amdgpu: add smu 13 support for smu 13.0.11 Yifan Zhang
2022-11-22 5:50 ` [PATCH 14/19] drm/amdgpu/pm: add GFXOFF control IP version check for SMU IP v13.0.11 Yifan Zhang
2022-11-22 5:50 ` [PATCH 15/19] drm/amdgpu/soc21: add mode2 asic reset " Yifan Zhang
2022-11-22 5:50 ` [PATCH 16/19] drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4 Yifan Zhang
2022-11-22 5:50 ` [PATCH 17/19] drm/amdgpu/discovery: enable nbio support for NBIO v7.7.1 Yifan Zhang
2022-11-22 5:50 ` [PATCH 18/19] drm/amdgpu: Enable pg/cg flags on GC11_0_4 for VCN Yifan Zhang
2022-11-22 5:50 ` [PATCH 19/19] drm/amdgpu: enable PSP IP v13.0.11 support Yifan Zhang
2022-11-23 1:44 ` Liu, Aaron
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.