[PATCH 0/2] x86: fixes for MTRR/PAT decoupling

[PATCH 0/2] x86: fixes for MTRR/PAT decoupling

[Juergen Gross]

Two small fixes for the decoupling of MTRR and PAT.

Juergen Gross (2):
  x86/pat: fix TDX guest PAT initialization
  x86/mtrr: make message for disabled MTRRs more descriptive

 arch/x86/kernel/cpu/mtrr/mtrr.c | 4 +++-
 arch/x86/mm/pat/memtype.c       | 6 +++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

-- 
2.35.3

[PATCH 1/2] x86/pat: fix TDX guest PAT initialization

[Juergen Gross]

With the decoupling of PAT and MTRR initialization, PAT will be used
even with MTRRs disabled. This seems to break booting up as TDX guest,
as the recommended sequence to set the PAT MSR across CPUs can't work
in TDX guests due to disabling caches via setting CR0.CD isn't allowed
in TDX mode.

This is an inconsistency in the Intel documentation between the SDM
and the TDX specification. For now handle TDX mode the same way as Xen
PV guest mode by just accepting the current PAT MSR setting without
trying to modify it.

Signed-off-by: Juergen Gross <jgross@suse.com>
---
 arch/x86/mm/pat/memtype.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
index 9aab17d660cd..4e50add760ad 100644
--- a/arch/x86/mm/pat/memtype.c
+++ b/arch/x86/mm/pat/memtype.c
@@ -296,8 +296,12 @@ void __init pat_bp_init(void)
 	/*
 	 * Xen PV doesn't allow to set PAT MSR, but all cache modes are
 	 * supported.
+	 * When running as TDX guest setting the PAT MSR won't work either
+	 * due to the requirement to set CR0.CD when doing so. Rely on
+	 * firmware to have set the PAT MSR correctly.
 	 */
-	if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV)) {
+	if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV) ||
+	    cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
 		init_cache_modes(pat_msr_val);
 		return;
 	}
-- 
2.35.3

[PATCH 2/2] x86/mtrr: make message for disabled MTRRs more descriptive

[Juergen Gross]

Instead of just saying "Disabled" when MTRRs are disabled for any
reason, tell what is disabled and why.

Signed-off-by: Juergen Gross <jgross@suse.com>
---
 arch/x86/kernel/cpu/mtrr/mtrr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c
index 6432abccbf56..94d5739758ba 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.c
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.c
@@ -630,6 +630,7 @@ int __initdata changed_by_mtrr_cleanup;
 void __init mtrr_bp_init(void)
 {
 	u32 phys_addr;
+	const char *why = "(not available)";
 
 	phys_addr = 32;
 
@@ -705,12 +706,13 @@ void __init mtrr_bp_init(void)
 				changed_by_mtrr_cleanup = mtrr_cleanup(phys_addr);
 			} else {
 				mtrr_if = NULL;
+				why = "by BIOS";
 			}
 		}
 	}
 
 	if (!mtrr_enabled())
-		pr_info("Disabled\n");
+		pr_info("MTRRs disabled %s\n", why);
 }
 
 /**
-- 
2.35.3

[tip: x86/cpu] x86/mtrr: Make message for disabled MTRRs more descriptive

[tip-bot2 for Juergen Gross]

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     7882b69eb6cdf6288a89d831d95c8547400a8b4d
Gitweb:        https://git.kernel.org/tip/7882b69eb6cdf6288a89d831d95c8547400a8b4d
Author:        Juergen Gross <jgross@suse.com>
AuthorDate:    Mon, 05 Dec 2022 09:04:33 +01:00
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Mon, 05 Dec 2022 11:08:25 +01:00

x86/mtrr: Make message for disabled MTRRs more descriptive

Instead of just saying "Disabled" when MTRRs are disabled for any
reason, tell what is disabled and why.

Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20221205080433.16643-3-jgross@suse.com
---
 arch/x86/kernel/cpu/mtrr/mtrr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c
index 6432abc..783f321 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.c
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.c
@@ -629,6 +629,7 @@ int __initdata changed_by_mtrr_cleanup;
  */
 void __init mtrr_bp_init(void)
 {
+	const char *why = "(not available)";
 	u32 phys_addr;
 
 	phys_addr = 32;
@@ -705,12 +706,13 @@ void __init mtrr_bp_init(void)
 				changed_by_mtrr_cleanup = mtrr_cleanup(phys_addr);
 			} else {
 				mtrr_if = NULL;
+				why = "by BIOS";
 			}
 		}
 	}
 
 	if (!mtrr_enabled())
-		pr_info("Disabled\n");
+		pr_info("MTRRs disabled %s\n", why);
 }
 
 /**

[tip: x86/cpu] x86/pat: Handle TDX guest PAT initialization

[tip-bot2 for Juergen Gross]

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     c11ca45441d56ed6d353548cad660e04f0b6605d
Gitweb:        https://git.kernel.org/tip/c11ca45441d56ed6d353548cad660e04f0b6605d
Author:        Juergen Gross <jgross@suse.com>
AuthorDate:    Mon, 05 Dec 2022 09:04:32 +01:00
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Mon, 05 Dec 2022 11:03:27 +01:00

x86/pat: Handle TDX guest PAT initialization

With the decoupling of PAT and MTRR initialization, PAT will be used
even with MTRRs disabled. This seems to break booting up as TDX guest,
as the recommended sequence to set the PAT MSR across CPUs can't work
in TDX guests due to disabling caches via setting CR0.CD isn't allowed
in TDX mode.

This is an inconsistency in the Intel documentation between the SDM
and the TDX specification. For now handle TDX mode the same way as Xen
PV guest mode by just accepting the current PAT MSR setting without
trying to modify it.

  [ bp: Align conditions for better readability. ]

Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20221205080433.16643-2-jgross@suse.com
---
 arch/x86/mm/pat/memtype.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
index 9aab17d..46de9cf 100644
--- a/arch/x86/mm/pat/memtype.c
+++ b/arch/x86/mm/pat/memtype.c
@@ -296,8 +296,13 @@ void __init pat_bp_init(void)
 	/*
 	 * Xen PV doesn't allow to set PAT MSR, but all cache modes are
 	 * supported.
+	 * When running as TDX guest setting the PAT MSR won't work either
+	 * due to the requirement to set CR0.CD when doing so. Rely on
+	 * firmware to have set the PAT MSR correctly.
 	 */
-	if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV)) {
+	if (pat_disabled ||
+	    cpu_feature_enabled(X86_FEATURE_XENPV) ||
+	    cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
 		init_cache_modes(pat_msr_val);
 		return;
 	}

Re: [PATCH 1/2] x86/pat: fix TDX guest PAT initialization

[kirill]

On Mon, Dec 05, 2022 at 09:04:32AM +0100, Juergen Gross wrote:
> With the decoupling of PAT and MTRR initialization, PAT will be used
> even with MTRRs disabled. This seems to break booting up as TDX guest,
> as the recommended sequence to set the PAT MSR across CPUs can't work
> in TDX guests due to disabling caches via setting CR0.CD isn't allowed
> in TDX mode.
> 
> This is an inconsistency in the Intel documentation between the SDM
> and the TDX specification. For now handle TDX mode the same way as Xen
> PV guest mode by just accepting the current PAT MSR setting without
> trying to modify it.
> 
> Signed-off-by: Juergen Gross <jgross@suse.com>

Good enough for now. I will follow up if something comes up from the
discussion around the topic.

Acked-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>

> ---
>  arch/x86/mm/pat/memtype.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
> index 9aab17d660cd..4e50add760ad 100644
> --- a/arch/x86/mm/pat/memtype.c
> +++ b/arch/x86/mm/pat/memtype.c
> @@ -296,8 +296,12 @@ void __init pat_bp_init(void)
>  	/*
>  	 * Xen PV doesn't allow to set PAT MSR, but all cache modes are
>  	 * supported.
> +	 * When running as TDX guest setting the PAT MSR won't work either
> +	 * due to the requirement to set CR0.CD when doing so. Rely on
> +	 * firmware to have set the PAT MSR correctly.

s/firmware/TDX module/

>  	 */
> -	if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV)) {
> +	if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV) ||
> +	    cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
>  		init_cache_modes(pat_msr_val);
>  		return;
>  	}

-- 
  Kiryl Shutsemau / Kirill A. Shutemov

Re: [PATCH 2/2] x86/mtrr: make message for disabled MTRRs more descriptive

[kirill]

On Mon, Dec 05, 2022 at 09:04:33AM +0100, Juergen Gross wrote:
> Instead of just saying "Disabled" when MTRRs are disabled for any
> reason, tell what is disabled and why.
> 
> Signed-off-by: Juergen Gross <jgross@suse.com>

Acked-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>

-- 
  Kiryl Shutsemau / Kirill A. Shutemov