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From: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
To: <xen-devel@lists.xenproject.org>
Cc: <sstabellini@kernel.org>, <stefanos@xilinx.com>, <julien@xen.org>,
	<Volodymyr_Babchuk@epam.com>, <bertrand.marquis@arm.com>,
	<michal.orzel@amd.com>, <jgrall@amazon.com>,
	<burzalodowa@gmail.com>,
	"Ayan Kumar Halder" <ayan.kumar.halder@amd.com>
Subject: [XEN v5 02/11] xen/Arm: GICv3: Do not calculate affinity level 3 for AArch32
Date: Mon, 5 Dec 2022 13:26:28 +0000	[thread overview]
Message-ID: <20221205132637.26775-3-ayan.kumar.halder@amd.com> (raw)
In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com>

Refer ARM DDI 0487I.a ID081822, G8-9817, G8.2.169
Affinity level 3 is not present in AArch32.
Also, refer ARM DDI 0406C.d ID040418, B4-1644, B4.1.106,
Affinity level 3 is not present in Armv7 (ie arm32).
Thus, any access to affinity level 3 needs to be guarded within
"ifdef CONFIG_ARM_64".

Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
Acked-by: Julien Grall <jgrall@amazon.com>
---
Changes from -

v1 - NA (as it is a new patch)

v2 - NA (as it is a new patch)

v3 - Modified the title. Added Rb.

v4 - Added Ack.

 xen/arch/arm/gic-v3.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 018fa0dfa0..64a76307dd 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -527,7 +527,10 @@ static void gicv3_set_pending_state(struct irq_desc *irqd, bool pending)
 static inline uint64_t gicv3_mpidr_to_affinity(int cpu)
 {
      uint64_t mpidr = cpu_logical_map(cpu);
-     return (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
+     return (
+#ifdef CONFIG_ARM_64
+             MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
+#endif
              MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
              MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8  |
              MPIDR_AFFINITY_LEVEL(mpidr, 0));
@@ -720,7 +723,10 @@ static int __init gicv3_populate_rdist(void)
      * Convert affinity to a 32bit value that can be matched to GICR_TYPER
      * bits [63:32]
      */
-    aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
+    aff = (
+#ifdef CONFIG_ARM_64
+           MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
+#endif
            MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
            MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
            MPIDR_AFFINITY_LEVEL(mpidr, 0));
@@ -972,7 +978,10 @@ static void gicv3_send_sgi_list(enum gic_sgi sgi, const cpumask_t *cpumask)
          * Prepare affinity path of the cluster for which SGI is generated
          * along with SGI number
          */
-        val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48  |
+        val = (
+#ifdef CONFIG_ARM_64
+               MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48  |
+#endif
                MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32  |
                sgi << 24                                  |
                MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16  |
-- 
2.17.1



  parent reply	other threads:[~2022-12-05 13:27 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-05 13:26 [XEN v5 00/11] Arm: Enable GICv3 for AArch32 Ayan Kumar Halder
2022-12-05 13:26 ` [XEN v5 01/11] xen/Arm: vGICv3: Sysreg emulation is applicable for AArch64 only Ayan Kumar Halder
2022-12-05 13:26 ` Ayan Kumar Halder [this message]
2022-12-05 13:26 ` [XEN v5 03/11] xen/Arm: vreg: Support vreg_reg64_* helpers on AArch32 Ayan Kumar Halder
2022-12-05 13:26 ` [XEN v5 04/11] xen/Arm: vGICv3: Adapt emulation of GICR_TYPER for AArch32 Ayan Kumar Halder
2022-12-05 13:26 ` [XEN v5 05/11] xen/Arm: GICv3: Fix GICR_{PENDBASER, PROPBASER} emulation on 32-bit host Ayan Kumar Halder
2022-12-05 13:26 ` [XEN v5 06/11] xen/Arm: vGICv3: Fix emulation of ICC_SGI1R on AArch32 Ayan Kumar Halder
2022-12-05 13:26 ` [XEN v5 07/11] xen/Arm: GICv3: Define ICH_LR<n>_EL2 " Ayan Kumar Halder
2022-12-13 21:21   ` Julien Grall
2022-12-05 13:26 ` [XEN v5 08/11] xen/Arm: GICv3: Define ICH_AP0R<n> and ICH_AP1R<n> for AArch32 Ayan Kumar Halder
2022-12-13 21:21   ` Julien Grall
2022-12-05 13:26 ` [XEN v5 09/11] xen/Arm: GICv3: Define remaining GIC registers " Ayan Kumar Halder
2022-12-13 21:22   ` Julien Grall
2022-12-05 13:26 ` [XEN v5 10/11] xen/Arm: GICv3: Define macros to read/write 64 bit Ayan Kumar Halder
2022-12-13 21:24   ` Julien Grall
2022-12-05 13:26 ` [XEN v5 11/11] xen/Arm: GICv3: Enable GICv3 for AArch32 Ayan Kumar Halder
2022-12-13 21:26   ` Julien Grall
2022-12-15 11:28 ` [XEN v5 00/11] Arm: " Julien Grall

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