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From: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
To: <xen-devel@lists.xenproject.org>
Cc: <sstabellini@kernel.org>, <stefanos@xilinx.com>, <julien@xen.org>,
	<Volodymyr_Babchuk@epam.com>, <bertrand.marquis@arm.com>,
	<michal.orzel@amd.com>, <jgrall@amazon.com>,
	<burzalodowa@gmail.com>,
	"Ayan Kumar Halder" <ayan.kumar.halder@amd.com>
Subject: [XEN v5 04/11] xen/Arm: vGICv3: Adapt emulation of GICR_TYPER for AArch32
Date: Mon, 5 Dec 2022 13:26:30 +0000	[thread overview]
Message-ID: <20221205132637.26775-5-ayan.kumar.halder@amd.com> (raw)
In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com>

Refer ARM DDI 0487I.a ID081822, G8-9650, G8.2.113
Aff3 does not exist on AArch32.
Also, refer ARM DDI 0406C.d ID040418, B4-1644, B4.1.106
Aff3 does not exist on Armv7 (ie arm32).

Thus, access to aff3 has been protected with "#ifdef CONFIG_ARM_64".
Also, v->arch.vmpidr is a 32 bit register on AArch32. So, we have assigned it to
'uint64_t vmpidr' to perform the shifts.

Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
Acked-by: Julien Grall <jgrall@amazon.com>
---

Changes from :-
v1 - Assigned v->arch.vmpidr to "uint64_t vmpdir". Then, we can use 
MPIDR_AFFINITY_LEVEL macros to extract the affinity value.

v2 - 1. "MPIDR_AFFINITY_LEVEL(vmpidr, 3)" is contained within
"#ifdef CONFIG_ARM_64".
2. Updated commit message.

v3 - 1. Added an inline comment to explain type widening for v->arch.vmpidr.
2. Updated the commit message. Added Rb.

v4 - 1. Added Ack.

 xen/arch/arm/vgic-v3.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 3f4509dcd3..e0b636b95f 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -191,12 +191,20 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info,
     case VREG64(GICR_TYPER):
     {
         uint64_t typer, aff;
+        /*
+         * This is to enable shifts greater than 32 bits which would have
+         * otherwise caused overflow (as v->arch.vmpidr is 32 bit on AArch32).
+         */
+        uint64_t vmpidr = v->arch.vmpidr;
 
         if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
-        aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 |
-               MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 |
-               MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 |
-               MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32);
+        aff = (
+#ifdef CONFIG_ARM_64
+               MPIDR_AFFINITY_LEVEL(vmpidr, 3) << 56 |
+#endif
+               MPIDR_AFFINITY_LEVEL(vmpidr, 2) << 48 |
+               MPIDR_AFFINITY_LEVEL(vmpidr, 1) << 40 |
+               MPIDR_AFFINITY_LEVEL(vmpidr, 0) << 32);
         typer = aff;
         /* We use the VCPU ID as the redistributor ID in bits[23:8] */
         typer |= v->vcpu_id << GICR_TYPER_PROC_NUM_SHIFT;
-- 
2.17.1



  parent reply	other threads:[~2022-12-05 14:48 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-05 13:26 [XEN v5 00/11] Arm: Enable GICv3 for AArch32 Ayan Kumar Halder
2022-12-05 13:26 ` [XEN v5 01/11] xen/Arm: vGICv3: Sysreg emulation is applicable for AArch64 only Ayan Kumar Halder
2022-12-05 13:26 ` [XEN v5 02/11] xen/Arm: GICv3: Do not calculate affinity level 3 for AArch32 Ayan Kumar Halder
2022-12-05 13:26 ` [XEN v5 03/11] xen/Arm: vreg: Support vreg_reg64_* helpers on AArch32 Ayan Kumar Halder
2022-12-05 13:26 ` Ayan Kumar Halder [this message]
2022-12-05 13:26 ` [XEN v5 05/11] xen/Arm: GICv3: Fix GICR_{PENDBASER, PROPBASER} emulation on 32-bit host Ayan Kumar Halder
2022-12-05 13:26 ` [XEN v5 06/11] xen/Arm: vGICv3: Fix emulation of ICC_SGI1R on AArch32 Ayan Kumar Halder
2022-12-05 13:26 ` [XEN v5 07/11] xen/Arm: GICv3: Define ICH_LR<n>_EL2 " Ayan Kumar Halder
2022-12-13 21:21   ` Julien Grall
2022-12-05 13:26 ` [XEN v5 08/11] xen/Arm: GICv3: Define ICH_AP0R<n> and ICH_AP1R<n> for AArch32 Ayan Kumar Halder
2022-12-13 21:21   ` Julien Grall
2022-12-05 13:26 ` [XEN v5 09/11] xen/Arm: GICv3: Define remaining GIC registers " Ayan Kumar Halder
2022-12-13 21:22   ` Julien Grall
2022-12-05 13:26 ` [XEN v5 10/11] xen/Arm: GICv3: Define macros to read/write 64 bit Ayan Kumar Halder
2022-12-13 21:24   ` Julien Grall
2022-12-05 13:26 ` [XEN v5 11/11] xen/Arm: GICv3: Enable GICv3 for AArch32 Ayan Kumar Halder
2022-12-13 21:26   ` Julien Grall
2022-12-15 11:28 ` [XEN v5 00/11] Arm: " Julien Grall

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