[PATCH-for-8.0 v2 00/11] hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API

[PATCH-for-8.0 v2 00/11] hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API

[Philippe Mathieu-Daudé]

Bernhard posted his "Consolidate PIIX south bridges" v3 series:
https://lore.kernel.org/qemu-devel/20221204190553.3274-1-shentey@gmail.com/

However in order to simplify it, on the Malta board we need to set
the PIIX IRQC[A:D] routing values via the embedded bootloader (used
when no external BIOS is provided). Jiaxun added a "bootloader
generator API" for 32-bit wide instructions, and we use it in the
write_bootloader() function.
This series provides the nanoMIPS equivalent generated instructions
and update the write_bootloader_nanomips() function.
That allow fixing the TODO left in
https://lore.kernel.org/qemu-devel/20221027204720.33611-3-philmd@linaro.org/
and apply Bernhard's consolidation.

Since v1:
- addressed review comments
- generate JALRc
- split write_bootloader_nanomips() convertion in 5 parts
- use bl_gen_jump_kernel()
- merge common code to bl_setup_gt64120_jump_kernel()

Philippe Mathieu-Daudé (11):
  hw/mips/bootloader: Handle buffers as opaque arrays
  hw/mips/bootloader: Implement nanoMIPS NOP opcode generator
  hw/mips/bootloader: Implement nanoMIPS SW opcode generator
  hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator
  hw/mips/bootloader: Implement nanoMIPS JALRc opcode generator
  hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5)
  hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5)
  hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5)
  hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5)
  hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5)
  hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel()

 hw/mips/bootloader.c         | 141 ++++++++++++++----
 hw/mips/malta.c              | 281 ++++++++---------------------------
 include/hw/mips/bootloader.h |  10 +-
 3 files changed, 177 insertions(+), 255 deletions(-)

-- 
2.38.1

[PATCH-for-8.0 v2 01/11] hw/mips/bootloader: Handle buffers as opaque arrays

[Philippe Mathieu-Daudé]

It is irrelevant to the API what the buffers to fill are made of.
In particular, some MIPS ISA have 16-bit wide instructions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c         | 55 +++++++++++++++++++++---------------
 hw/mips/malta.c              | 19 +++++++------
 include/hw/mips/bootloader.h | 10 +++----
 3 files changed, 48 insertions(+), 36 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index f5f42f2bf2..21ffd4d772 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -55,16 +55,20 @@ static bool bootcpu_supports_isa(uint64_t isa_mask)
 }
 
 /* Base types */
-static void bl_gen_nop(uint32_t **p)
+static void bl_gen_nop(void **ptr)
 {
-    stl_p(*p, 0);
-    *p = *p + 1;
+    uint32_t *p = *ptr;
+
+    stl_p(p, 0);
+    p++;
+    *ptr = p;
 }
 
-static void bl_gen_r_type(uint32_t **p, uint8_t opcode,
+static void bl_gen_r_type(void **ptr, uint8_t opcode,
                           bl_reg rs, bl_reg rt, bl_reg rd,
                           uint8_t shift, uint8_t funct)
 {
+    uint32_t *p = *ptr;
     uint32_t insn = 0;
 
     insn = deposit32(insn, 26, 6, opcode);
@@ -74,13 +78,16 @@ static void bl_gen_r_type(uint32_t **p, uint8_t opcode,
     insn = deposit32(insn, 6, 5, shift);
     insn = deposit32(insn, 0, 6, funct);
 
-    stl_p(*p, insn);
-    *p = *p + 1;
+    stl_p(p, insn);
+    p++;
+
+    *ptr = p;
 }
 
-static void bl_gen_i_type(uint32_t **p, uint8_t opcode,
+static void bl_gen_i_type(void **ptr, uint8_t opcode,
                           bl_reg rs, bl_reg rt, uint16_t imm)
 {
+    uint32_t *p = *ptr;
     uint32_t insn = 0;
 
     insn = deposit32(insn, 26, 6, opcode);
@@ -88,12 +95,14 @@ static void bl_gen_i_type(uint32_t **p, uint8_t opcode,
     insn = deposit32(insn, 16, 5, rt);
     insn = deposit32(insn, 0, 16, imm);
 
-    stl_p(*p, insn);
-    *p = *p + 1;
+    stl_p(p, insn);
+    p++;
+
+    *ptr = p;
 }
 
 /* Single instructions */
-static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
+static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
 {
     if (bootcpu_supports_isa(ISA_MIPS3)) {
         bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
@@ -102,28 +111,28 @@ static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
     }
 }
 
-static void bl_gen_jalr(uint32_t **p, bl_reg rs)
+static void bl_gen_jalr(void **p, bl_reg rs)
 {
     bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
 }
 
-static void bl_gen_lui(uint32_t **p, bl_reg rt, uint16_t imm)
+static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm)
 {
     /* R6: It's a alias of AUI with RS = 0 */
     bl_gen_i_type(p, 0x0f, 0, rt, imm);
 }
 
-static void bl_gen_ori(uint32_t **p, bl_reg rt, bl_reg rs, uint16_t imm)
+static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
 {
     bl_gen_i_type(p, 0x0d, rs, rt, imm);
 }
 
-static void bl_gen_sw(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
+static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
 {
     bl_gen_i_type(p, 0x2b, base, rt, offset);
 }
 
-static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
+static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
 {
     if (bootcpu_supports_isa(ISA_MIPS3)) {
         bl_gen_i_type(p, 0x3f, base, rt, offset);
@@ -133,13 +142,13 @@ static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
 }
 
 /* Pseudo instructions */
-static void bl_gen_li(uint32_t **p, bl_reg rt, uint32_t imm)
+static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
 {
     bl_gen_lui(p, rt, extract32(imm, 16, 16));
     bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
 }
 
-static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
+static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)
 {
     bl_gen_li(p, rt, extract64(imm, 32, 32));
     bl_gen_dsll(p, rt, rt, 16);
@@ -148,7 +157,7 @@ static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
     bl_gen_ori(p, rt, rt, extract64(imm, 0, 16));
 }
 
-static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
+static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm)
 {
     if (bootcpu_supports_isa(ISA_MIPS3)) {
         bl_gen_dli(p, rt, imm); /* 64bit */
@@ -158,14 +167,14 @@ static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
 }
 
 /* Helpers */
-void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr)
+void bl_gen_jump_to(void **p, target_ulong jump_addr)
 {
     bl_gen_load_ulong(p, BL_REG_T9, jump_addr);
     bl_gen_jalr(p, BL_REG_T9);
     bl_gen_nop(p); /* delay slot */
 }
 
-void bl_gen_jump_kernel(uint32_t **p,
+void bl_gen_jump_kernel(void **p,
                         bool set_sp, target_ulong sp,
                         bool set_a0, target_ulong a0,
                         bool set_a1, target_ulong a1,
@@ -192,7 +201,7 @@ void bl_gen_jump_kernel(uint32_t **p,
     bl_gen_jump_to(p, kernel_addr);
 }
 
-void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val)
+void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val)
 {
     bl_gen_load_ulong(p, BL_REG_K0, val);
     bl_gen_load_ulong(p, BL_REG_K1, addr);
@@ -203,14 +212,14 @@ void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val)
     }
 }
 
-void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val)
+void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val)
 {
     bl_gen_li(p, BL_REG_K0, val);
     bl_gen_load_ulong(p, BL_REG_K1, addr);
     bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
 }
 
-void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val)
+void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val)
 {
     bl_gen_dli(p, BL_REG_K0, val);
     bl_gen_load_ulong(p, BL_REG_K1, addr);
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 1f4e0c7acc..8f84846f97 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -838,6 +838,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
                              uint64_t kernel_entry)
 {
     uint32_t *p;
+    void *v;
 
     /* Small bootloader */
     p = (uint32_t *)base;
@@ -880,38 +881,39 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
 #else
 #define cpu_to_gt32 cpu_to_be32
 #endif
+    v = p;
 
     /* move GT64120 registers from 0x14000000 to 0x1be00000 */
-    bl_gen_write_u32(&p, /* GT_ISD */
+    bl_gen_write_u32(&v, /* GT_ISD */
                      cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
                      cpu_to_gt32(0x1be00000 << 3));
 
     /* setup MEM-to-PCI0 mapping */
     /* setup PCI0 io window to 0x18000000-0x181fffff */
-    bl_gen_write_u32(&p, /* GT_PCI0IOLD */
+    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
                      cpu_to_gt32(0x18000000 << 3));
-    bl_gen_write_u32(&p, /* GT_PCI0IOHD */
+    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
                      cpu_to_gt32(0x08000000 << 3));
     /* setup PCI0 mem windows */
-    bl_gen_write_u32(&p, /* GT_PCI0M0LD */
+    bl_gen_write_u32(&v, /* GT_PCI0M0LD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
                      cpu_to_gt32(0x10000000 << 3));
-    bl_gen_write_u32(&p, /* GT_PCI0M0HD */
+    bl_gen_write_u32(&v, /* GT_PCI0M0HD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
                      cpu_to_gt32(0x07e00000 << 3));
 
-    bl_gen_write_u32(&p, /* GT_PCI0M1LD */
+    bl_gen_write_u32(&v, /* GT_PCI0M1LD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
                      cpu_to_gt32(0x18200000 << 3));
-    bl_gen_write_u32(&p, /* GT_PCI0M1HD */
+    bl_gen_write_u32(&v, /* GT_PCI0M1HD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
                      cpu_to_gt32(0x0bc00000 << 3));
 
 #undef cpu_to_gt32
 
-    bl_gen_jump_kernel(&p,
+    bl_gen_jump_kernel(&v,
                        true, ENVP_VADDR - 64,
                        /*
                         * If semihosting is used, arguments have already been
@@ -922,6 +924,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
                        true, ENVP_VADDR + 8,
                        true, loaderparams.ram_low_size,
                        kernel_entry);
+    p = v;
 
     /* YAMON subroutines */
     p = (uint32_t *) (base + 0x800);
diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
index fffb0b7da8..c32f6c2835 100644
--- a/include/hw/mips/bootloader.h
+++ b/include/hw/mips/bootloader.h
@@ -11,16 +11,16 @@
 
 #include "exec/cpu-defs.h"
 
-void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr);
-void bl_gen_jump_kernel(uint32_t **p,
+void bl_gen_jump_to(void **ptr, target_ulong jump_addr);
+void bl_gen_jump_kernel(void **ptr,
                         bool set_sp, target_ulong sp,
                         bool set_a0, target_ulong a0,
                         bool set_a1, target_ulong a1,
                         bool set_a2, target_ulong a2,
                         bool set_a3, target_ulong a3,
                         target_ulong kernel_addr);
-void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val);
-void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val);
-void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val);
+void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val);
+void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val);
+void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val);
 
 #endif
-- 
2.38.1

[PATCH-for-8.0 v2 02/11] hw/mips/bootloader: Implement nanoMIPS NOP opcode generator

[Philippe Mathieu-Daudé]

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 21ffd4d772..0035f37335 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -54,14 +54,30 @@ static bool bootcpu_supports_isa(uint64_t isa_mask)
     return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask);
 }
 
+static void st_nm32_p(void **ptr, uint32_t insn)
+{
+    uint16_t *p = *ptr;
+
+    stw_p(p, insn >> 16);
+    p++;
+    stw_p(p, insn >> 0);
+    p++;
+
+    *ptr = p;
+}
+
 /* Base types */
 static void bl_gen_nop(void **ptr)
 {
-    uint32_t *p = *ptr;
+    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+        st_nm32_p(ptr, 0x8000c000);
+    } else {
+        uint32_t *p = *ptr;
 
-    stl_p(p, 0);
-    p++;
-    *ptr = p;
+        stl_p(p, 0);
+        p++;
+        *ptr = p;
+    }
 }
 
 static void bl_gen_r_type(void **ptr, uint8_t opcode,
-- 
2.38.1

[PATCH-for-8.0 v2 03/11] hw/mips/bootloader: Implement nanoMIPS SW opcode generator

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 0035f37335..3e1e73360f 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -143,9 +143,27 @@ static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
     bl_gen_i_type(p, 0x0d, rs, rt, imm);
 }
 
+static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12)
+{
+    uint32_t insn = 0;
+
+    assert(extract32(ofs12, 0, 12) == ofs12);
+    insn = deposit32(insn, 26, 6, 0b100001);
+    insn = deposit32(insn, 21, 5, rt);
+    insn = deposit32(insn, 16, 5, rs);
+    insn = deposit32(insn, 12, 4, 0b1001);
+    insn = deposit32(insn, 0, 12, ofs12);
+
+    st_nm32_p(ptr, insn);
+}
+
 static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
 {
-    bl_gen_i_type(p, 0x2b, base, rt, offset);
+    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+        bl_gen_sw_nm(p, rt, base, offset);
+    } else {
+        bl_gen_i_type(p, 0x2b, base, rt, offset);
+    }
 }
 
 static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
-- 
2.38.1

[PATCH-for-8.0 v2 04/11] hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 36 ++++++++++++++++++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 3e1e73360f..9fc926d83f 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -132,12 +132,39 @@ static void bl_gen_jalr(void **p, bl_reg rs)
     bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
 }
 
+static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)
+{
+    uint32_t insn = 0;
+
+    assert(extract32(imm20, 0, 20) == imm20);
+    insn = deposit32(insn, 26, 6, 0b111000);
+    insn = deposit32(insn, 21, 5, rt);
+    insn = deposit32(insn, 12, 9, extract32(imm20, 0, 9));
+    insn = deposit32(insn, 2, 10, extract32(imm20, 9, 10));
+    insn = deposit32(insn, 0, 1, sextract32(imm20, 19, 1));
+
+    st_nm32_p(ptr, insn);
+}
+
 static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm)
 {
     /* R6: It's a alias of AUI with RS = 0 */
     bl_gen_i_type(p, 0x0f, 0, rt, imm);
 }
 
+static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm12)
+{
+    uint32_t insn = 0;
+
+    assert(extract32(imm12, 0, 12) == imm12);
+    insn = deposit32(insn, 26, 6, 0b100000);
+    insn = deposit32(insn, 21, 5, rt);
+    insn = deposit32(insn, 16, 5, rs);
+    insn = deposit32(insn, 0, 12, imm12);
+
+    st_nm32_p(ptr, insn);
+}
+
 static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
 {
     bl_gen_i_type(p, 0x0d, rs, rt, imm);
@@ -178,8 +205,13 @@ static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
 /* Pseudo instructions */
 static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
 {
-    bl_gen_lui(p, rt, extract32(imm, 16, 16));
-    bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
+    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+        bl_gen_lui_nm(p, rt, extract32(imm, 12, 20));
+        bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12));
+    } else {
+        bl_gen_lui(p, rt, extract32(imm, 16, 16));
+        bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
+    }
 }
 
 static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)
-- 
2.38.1

[PATCH-for-8.0 v2 05/11] hw/mips/bootloader: Implement nanoMIPS JALRc opcode generator

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 9fc926d83f..1dd6ef2096 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -129,7 +129,17 @@ static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
 
 static void bl_gen_jalr(void **p, bl_reg rs)
 {
-    bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
+    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+        uint32_t insn = 0;
+
+        insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */
+        insn = deposit32(insn, 21, 5, BL_REG_RA);
+        insn = deposit32(insn, 16, 5, rs);
+
+        st_nm32_p(p, insn);
+    } else {
+        bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
+    }
 }
 
 static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)
-- 
2.38.1

[PATCH-for-8.0 v2 06/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5)

[Philippe Mathieu-Daudé]

Similarly to how commit 0c8427baf0 ("hw/mips/malta: Use bootloader
helper to set BAR registers") converted write_bootloader(), convert
the equivalent write_bootloader_nanomips(), allowing us to modify
the bootloader code more easily in the future.

Part 1/5: Convert PCI0 MEM1 BAR setup

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 34 +++++++++++++++-------------------
 1 file changed, 15 insertions(+), 19 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 8f84846f97..30ca4e0000 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -614,6 +614,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
                                       uint64_t kernel_entry)
 {
     uint16_t *p;
+    void *v;
 
     /* Small bootloader */
     p = (uint16_t *)base;
@@ -687,13 +688,13 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
      *
      *  - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
      *  - set up PCI0 MEM0 at 0x10000000, size 0x8000000
-     *  - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
      *
      */
     stw_p(p++, 0xe040); stw_p(p++, 0x0681);
                                 /* lui t1, %hi(0xb4000000)      */
 
 #if TARGET_BIG_ENDIAN
+#define cpu_to_gt32 cpu_to_le32
 
     stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
                                 /* lui t0, %hi(0xdf000000)      */
@@ -736,14 +737,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
     stw_p(p++, 0xe020); stw_p(p++, 0x0821);
                                 /* lui t0, %hi(0xc1000000)      */
 
-    /* 0x80 corresponds to GT_PCI0M1LD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9080);
-                                /* sw t0, 0x80(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
-                                /* lui t0, %hi(0x5e000000)      */
-
 #else
+#define cpu_to_gt32 cpu_to_be32
 
     stw_p(p++, 0x0020); stw_p(p++, 0x00df);
                                 /* addiu[32] t0, $0, 0xdf       */
@@ -786,19 +781,20 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
 
     stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
                                 /* addiu[32] t0, $0, 0xc1       */
-
-    /* 0x80 corresponds to GT_PCI0M1LD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9080);
-                                /* sw t0, 0x80(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x005e);
-                                /* addiu[32] t0, $0, 0x5e       */
-
 #endif
+    v = p;
 
-    /* 0x88 corresponds to GT_PCI0M1HD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9088);
-                                /* sw t0, 0x88(t1)              */
+    /* setup PCI0 mem windows */
+    bl_gen_write_u32(&v, /* GT_PCI0M1LD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
+                     cpu_to_gt32(0x18200000 << 3));
+    bl_gen_write_u32(&v, /* GT_PCI0M1HD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
+                     cpu_to_gt32(0x0bc00000 << 3));
+
+    p = v;
+
+#undef cpu_to_gt32
 
     stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
 
-- 
2.38.1

[PATCH-for-8.0 v2 07/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5)

[Philippe Mathieu-Daudé]

Part 2/5: Convert PCI0 MEM0 BAR setup

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 35 ++++++-----------------------------
 1 file changed, 6 insertions(+), 29 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 30ca4e0000..3e80a12221 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -687,7 +687,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
      * Load BAR registers as done by YAMON:
      *
      *  - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
-     *  - set up PCI0 MEM0 at 0x10000000, size 0x8000000
      *
      */
     stw_p(p++, 0xe040); stw_p(p++, 0x0681);
@@ -723,20 +722,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
     stw_p(p++, 0xe020); stw_p(p++, 0x0001);
                                 /* lui t0, %hi(0x80000000)      */
 
-    /* 0x58 corresponds to GT_PCI0M0LD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9058);
-                                /* sw t0, 0x58(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
-                                /* lui t0, %hi(0x3f000000)      */
-
-    /* 0x60 corresponds to GT_PCI0M0HD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9060);
-                                /* sw t0, 0x60(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0821);
-                                /* lui t0, %hi(0xc1000000)      */
-
 #else
 #define cpu_to_gt32 cpu_to_be32
 
@@ -767,24 +752,16 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
 
     stw_p(p++, 0x0020); stw_p(p++, 0x0080);
                                 /* addiu[32] t0, $0, 0x80       */
-
-    /* 0x58 corresponds to GT_PCI0M0LD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9058);
-                                /* sw t0, 0x58(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x003f);
-                                /* addiu[32] t0, $0, 0x3f       */
-
-    /* 0x60 corresponds to GT_PCI0M0HD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9060);
-                                /* sw t0, 0x60(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
-                                /* addiu[32] t0, $0, 0xc1       */
 #endif
     v = p;
 
     /* setup PCI0 mem windows */
+    bl_gen_write_u32(&v, /* GT_PCI0M0LD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
+                     cpu_to_gt32(0x10000000 << 3));
+    bl_gen_write_u32(&v, /* GT_PCI0M0HD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
+                     cpu_to_gt32(0x07e00000 << 3));
     bl_gen_write_u32(&v, /* GT_PCI0M1LD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
                      cpu_to_gt32(0x18200000 << 3));
-- 
2.38.1

[PATCH-for-8.0 v2 08/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5)

[Philippe Mathieu-Daudé]

Part 3/5: Convert PCI0 I/O BAR setup

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 40 ++++++++--------------------------------
 1 file changed, 8 insertions(+), 32 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 3e80a12221..16161b1b03 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -685,9 +685,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
 
     /*
      * Load BAR registers as done by YAMON:
-     *
-     *  - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
-     *
      */
     stw_p(p++, 0xe040); stw_p(p++, 0x0681);
                                 /* lui t1, %hi(0xb4000000)      */
@@ -707,21 +704,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
 
     stw_p(p++, 0xe020); stw_p(p++, 0x0801);
                                 /* lui t0, %hi(0xc0000000)      */
-
-    /* 0x48 corresponds to GT_PCI0IOLD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
-                                /* sw t0, 0x48(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0800);
-                                /* lui t0, %hi(0x40000000)      */
-
-    /* 0x50 corresponds to GT_PCI0IOHD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
-                                /* sw t0, 0x50(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0001);
-                                /* lui t0, %hi(0x80000000)      */
-
 #else
 #define cpu_to_gt32 cpu_to_be32
 
@@ -738,23 +720,17 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
 
     stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
                                 /* addiu[32] t0, $0, 0xc0       */
-
-    /* 0x48 corresponds to GT_PCI0IOLD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
-                                /* sw t0, 0x48(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x0040);
-                                /* addiu[32] t0, $0, 0x40       */
-
-    /* 0x50 corresponds to GT_PCI0IOHD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
-                                /* sw t0, 0x50(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x0080);
-                                /* addiu[32] t0, $0, 0x80       */
 #endif
     v = p;
 
+    /* setup PCI0 io window to 0x18000000-0x181fffff */
+    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
+                     cpu_to_gt32(0x18000000 << 3));
+    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
+                     cpu_to_gt32(0x08000000 << 3));
+
     /* setup PCI0 mem windows */
     bl_gen_write_u32(&v, /* GT_PCI0M0LD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
-- 
2.38.1

[PATCH-for-8.0 v2 09/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5)

[Philippe Mathieu-Daudé]

Part 4/5: Convert GT64120 ISD base address setup

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 40 +++++++---------------------------------
 1 file changed, 7 insertions(+), 33 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 16161b1b03..451908b217 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -683,46 +683,20 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
     stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
                                 /* ori a3,a3,%lo(loaderparams.ram_low_size) */
 
-    /*
-     * Load BAR registers as done by YAMON:
-     */
-    stw_p(p++, 0xe040); stw_p(p++, 0x0681);
-                                /* lui t1, %hi(0xb4000000)      */
-
 #if TARGET_BIG_ENDIAN
 #define cpu_to_gt32 cpu_to_le32
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
-                                /* lui t0, %hi(0xdf000000)      */
-
-    /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c)  */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9068);
-                                /* sw t0, 0x68(t1)              */
-
-    stw_p(p++, 0xe040); stw_p(p++, 0x077d);
-                                /* lui t1, %hi(0xbbe00000)      */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0801);
-                                /* lui t0, %hi(0xc0000000)      */
 #else
 #define cpu_to_gt32 cpu_to_be32
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x00df);
-                                /* addiu[32] t0, $0, 0xdf       */
-
-    /* 0x68 corresponds to GT_ISD                               */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9068);
-                                /* sw t0, 0x68(t1)              */
-
-    /* Use kseg2 remapped address 0x1be00000                    */
-    stw_p(p++, 0xe040); stw_p(p++, 0x077d);
-                                /* lui t1, %hi(0xbbe00000)      */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
-                                /* addiu[32] t0, $0, 0xc0       */
 #endif
     v = p;
 
+    /* setup MEM-to-PCI0 mapping as done by YAMON */
+
+    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+    bl_gen_write_u32(&v, /* GT_ISD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
+                     cpu_to_gt32(0x1be00000 << 3));
+
     /* setup PCI0 io window to 0x18000000-0x181fffff */
     bl_gen_write_u32(&v, /* GT_PCI0IOLD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
-- 
2.38.1

[PATCH-for-8.0 v2 10/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5)

[Philippe Mathieu-Daudé]

Part 5/5: Convert jumping to kernel

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 68 ++++++++-----------------------------------------
 1 file changed, 11 insertions(+), 57 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 451908b217..876bc26a7f 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -619,11 +619,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
     /* Small bootloader */
     p = (uint16_t *)base;
 
-#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
-#define NM_HI2(VAL) \
-          (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
-#define NM_LO(VAL)  ((VAL) & 0xfff)
-
     stw_p(p++, 0x2800); stw_p(p++, 0x001c);
                                 /* bc to_here */
     stw_p(p++, 0x8000); stw_p(p++, 0xc000);
@@ -642,46 +637,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
                                 /* nop */
 
     /* to_here: */
-    if (semihosting_get_argc()) {
-        /* Preserve a0 content as arguments have been passed    */
-        stw_p(p++, 0x8000); stw_p(p++, 0xc000);
-                                /* nop                          */
-    } else {
-        stw_p(p++, 0x0080); stw_p(p++, 0x0002);
-                                /* li a0,2                      */
-    }
-
-    stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64));
-
-    stw_p(p++, NM_HI2(ENVP_VADDR - 64));
-                                /* lui sp,%hi(ENVP_VADDR - 64)   */
-
-    stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64));
-                                /* ori sp,sp,%lo(ENVP_VADDR - 64) */
-
-    stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR));
-
-    stw_p(p++, NM_HI2(ENVP_VADDR));
-                                /* lui a1,%hi(ENVP_VADDR)        */
-
-    stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR));
-                                /* ori a1,a1,%lo(ENVP_VADDR)     */
-
-    stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8));
-
-    stw_p(p++, NM_HI2(ENVP_VADDR + 8));
-                                /* lui a2,%hi(ENVP_VADDR + 8)    */
-
-    stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8));
-                                /* ori a2,a2,%lo(ENVP_VADDR + 8) */
-
-    stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
-
-    stw_p(p++, NM_HI2(loaderparams.ram_low_size));
-                                /* lui a3,%hi(loaderparams.ram_low_size) */
-
-    stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
-                                /* ori a3,a3,%lo(loaderparams.ram_low_size) */
 
 #if TARGET_BIG_ENDIAN
 #define cpu_to_gt32 cpu_to_le32
@@ -719,20 +674,19 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
                      cpu_to_gt32(0x0bc00000 << 3));
 
-    p = v;
-
 #undef cpu_to_gt32
 
-    stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
-
-    stw_p(p++, NM_HI2(kernel_entry));
-                                /* lui t9,%hi(kernel_entry)     */
-
-    stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
-                                /* ori t9,t9,%lo(kernel_entry)  */
-
-    stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
-                                /* jalrc   t8                   */
+    bl_gen_jump_kernel(&v,
+                       true, ENVP_VADDR - 64,
+                       /*
+                        * If semihosting is used, arguments have already been
+                        * passed, so we preserve $a0.
+                        */
+                       !semihosting_get_argc(), 2,
+                       true, ENVP_VADDR,
+                       true, ENVP_VADDR + 8,
+                       true, loaderparams.ram_low_size,
+                       kernel_entry);
 }
 
 /*
-- 
2.38.1

[PATCH-for-8.0 v2 11/11] hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel()

[Philippe Mathieu-Daudé]

Merge common code shared between write_bootloader() and
write_bootloader_nanomips() into bl_setup_gt64120_jump_kernel().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 155 +++++++++++++++++-------------------------------
 1 file changed, 56 insertions(+), 99 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 876bc26a7f..9cd59c13e4 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -610,11 +610,64 @@ static void network_init(PCIBus *pci_bus)
     }
 }
 
+static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
+                                         uint64_t kernel_entry)
+{
+    /* Bus endianess is always reversed */
+#if TARGET_BIG_ENDIAN
+#define cpu_to_gt32 cpu_to_le32
+#else
+#define cpu_to_gt32 cpu_to_be32
+#endif
+
+    /* setup MEM-to-PCI0 mapping as done by YAMON */
+
+    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+    bl_gen_write_u32(p, /* GT_ISD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
+                     cpu_to_gt32(0x1be00000 << 3));
+
+    /* setup PCI0 io window to 0x18000000-0x181fffff */
+    bl_gen_write_u32(p, /* GT_PCI0IOLD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
+                     cpu_to_gt32(0x18000000 << 3));
+    bl_gen_write_u32(p, /* GT_PCI0IOHD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
+                     cpu_to_gt32(0x08000000 << 3));
+
+    /* setup PCI0 mem windows */
+    bl_gen_write_u32(p, /* GT_PCI0M0LD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
+                     cpu_to_gt32(0x10000000 << 3));
+    bl_gen_write_u32(p, /* GT_PCI0M0HD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
+                     cpu_to_gt32(0x07e00000 << 3));
+    bl_gen_write_u32(p, /* GT_PCI0M1LD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
+                     cpu_to_gt32(0x18200000 << 3));
+    bl_gen_write_u32(p, /* GT_PCI0M1HD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
+                     cpu_to_gt32(0x0bc00000 << 3));
+
+#undef cpu_to_gt32
+
+    bl_gen_jump_kernel(p,
+                       true, ENVP_VADDR - 64,
+                       /*
+                        * If semihosting is used, arguments have already
+                        * been passed, so we preserve $a0.
+                        */
+                       !semihosting_get_argc(), 2,
+                       true, ENVP_VADDR,
+                       true, ENVP_VADDR + 8,
+                       true, loaderparams.ram_low_size,
+                       kernel_entry);
+}
+
 static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
                                       uint64_t kernel_entry)
 {
     uint16_t *p;
-    void *v;
 
     /* Small bootloader */
     p = (uint16_t *)base;
@@ -638,55 +691,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
 
     /* to_here: */
 
-#if TARGET_BIG_ENDIAN
-#define cpu_to_gt32 cpu_to_le32
-#else
-#define cpu_to_gt32 cpu_to_be32
-#endif
-    v = p;
-
-    /* setup MEM-to-PCI0 mapping as done by YAMON */
-
-    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
-    bl_gen_write_u32(&v, /* GT_ISD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
-                     cpu_to_gt32(0x1be00000 << 3));
-
-    /* setup PCI0 io window to 0x18000000-0x181fffff */
-    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
-                     cpu_to_gt32(0x18000000 << 3));
-    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
-                     cpu_to_gt32(0x08000000 << 3));
-
-    /* setup PCI0 mem windows */
-    bl_gen_write_u32(&v, /* GT_PCI0M0LD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
-                     cpu_to_gt32(0x10000000 << 3));
-    bl_gen_write_u32(&v, /* GT_PCI0M0HD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
-                     cpu_to_gt32(0x07e00000 << 3));
-    bl_gen_write_u32(&v, /* GT_PCI0M1LD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
-                     cpu_to_gt32(0x18200000 << 3));
-    bl_gen_write_u32(&v, /* GT_PCI0M1HD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
-                     cpu_to_gt32(0x0bc00000 << 3));
-
-#undef cpu_to_gt32
-
-    bl_gen_jump_kernel(&v,
-                       true, ENVP_VADDR - 64,
-                       /*
-                        * If semihosting is used, arguments have already been
-                        * passed, so we preserve $a0.
-                        */
-                       !semihosting_get_argc(), 2,
-                       true, ENVP_VADDR,
-                       true, ENVP_VADDR + 8,
-                       true, loaderparams.ram_low_size,
-                       kernel_entry);
+    bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
 }
 
 /*
@@ -752,55 +757,8 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
      *
      */
 
-    /* Bus endianess is always reversed */
-#if TARGET_BIG_ENDIAN
-#define cpu_to_gt32 cpu_to_le32
-#else
-#define cpu_to_gt32 cpu_to_be32
-#endif
     v = p;
-
-    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
-    bl_gen_write_u32(&v, /* GT_ISD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
-                     cpu_to_gt32(0x1be00000 << 3));
-
-    /* setup MEM-to-PCI0 mapping */
-    /* setup PCI0 io window to 0x18000000-0x181fffff */
-    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
-                     cpu_to_gt32(0x18000000 << 3));
-    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
-                     cpu_to_gt32(0x08000000 << 3));
-    /* setup PCI0 mem windows */
-    bl_gen_write_u32(&v, /* GT_PCI0M0LD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
-                     cpu_to_gt32(0x10000000 << 3));
-    bl_gen_write_u32(&v, /* GT_PCI0M0HD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
-                     cpu_to_gt32(0x07e00000 << 3));
-
-    bl_gen_write_u32(&v, /* GT_PCI0M1LD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
-                     cpu_to_gt32(0x18200000 << 3));
-    bl_gen_write_u32(&v, /* GT_PCI0M1HD */
-                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
-                     cpu_to_gt32(0x0bc00000 << 3));
-
-#undef cpu_to_gt32
-
-    bl_gen_jump_kernel(&v,
-                       true, ENVP_VADDR - 64,
-                       /*
-                        * If semihosting is used, arguments have already been
-                        * passed, so we preserve $a0.
-                        */
-                       !semihosting_get_argc(), 2,
-                       true, ENVP_VADDR,
-                       true, ENVP_VADDR + 8,
-                       true, loaderparams.ram_low_size,
-                       kernel_entry);
+    bl_setup_gt64120_jump_kernel(&v, run_addr, kernel_entry);
     p = v;
 
     /* YAMON subroutines */
@@ -845,7 +803,6 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
     stl_p(p++, 0x00000000);                  /* nop */
     stl_p(p++, 0x03e00009);                  /* jalr ra */
     stl_p(p++, 0xa1040000);                  /* sb a0,0(t0) */
-
 }
 
 static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,
-- 
2.38.1

Re: [PATCH-for-8.0 v2 01/11] hw/mips/bootloader: Handle buffers as opaque arrays

[Philippe Mathieu-Daudé]

On 11/12/22 21:45, Philippe Mathieu-Daudé wrote:
> It is irrelevant to the API what the buffers to fill are made of.
> In particular, some MIPS ISA have 16-bit wide instructions.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/mips/bootloader.c         | 55 +++++++++++++++++++++---------------
>   hw/mips/malta.c              | 19 +++++++------
>   include/hw/mips/bootloader.h | 10 +++----
>   3 files changed, 48 insertions(+), 36 deletions(-)


> diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
> index fffb0b7da8..c32f6c2835 100644
> --- a/include/hw/mips/bootloader.h
> +++ b/include/hw/mips/bootloader.h
> @@ -11,16 +11,16 @@
>   
>   #include "exec/cpu-defs.h"
>   
> -void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr);
> -void bl_gen_jump_kernel(uint32_t **p,
> +void bl_gen_jump_to(void **ptr, target_ulong jump_addr);
> +void bl_gen_jump_kernel(void **ptr,
>                           bool set_sp, target_ulong sp,
>                           bool set_a0, target_ulong a0,
>                           bool set_a1, target_ulong a1,
>                           bool set_a2, target_ulong a2,
>                           bool set_a3, target_ulong a3,
>                           target_ulong kernel_addr);
> -void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val);
> -void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val);
> -void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val);
> +void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val);
> +void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val);
> +void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val);

And I forgot to squash this...:

-- >8 --
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index edda87e23c..b6dd9fb200 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -323,7 +323,7 @@ static void boston_register_types(void)
  }
  type_init(boston_register_types)

-static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
+static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr)
  {
      uint64_t regaddr;

diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 34befa5dd5..cfc8ca6ae4 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -179,7 +179,7 @@ static void write_bootloader(CPUMIPSState *env, 
uint8_t *base,
      /* Second part of the bootloader */
      p = (uint32_t *)(base + 0x040);

-    bl_gen_jump_kernel(&p,
+    bl_gen_jump_kernel((void **)&p,
                         true, ENVP_VADDR - 64,
                         true, 2, true, ENVP_VADDR,
                         true, ENVP_VADDR + 8,
---

Re: [PATCH-for-8.0 v2 01/11] hw/mips/bootloader: Handle buffers as opaque arrays

[Richard Henderson]

On 12/11/22 14:52, Philippe Mathieu-Daudé wrote:
> On 11/12/22 21:45, Philippe Mathieu-Daudé wrote:
>> It is irrelevant to the API what the buffers to fill are made of.
>> In particular, some MIPS ISA have 16-bit wide instructions.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   hw/mips/bootloader.c         | 55 +++++++++++++++++++++---------------
>>   hw/mips/malta.c              | 19 +++++++------
>>   include/hw/mips/bootloader.h | 10 +++----
>>   3 files changed, 48 insertions(+), 36 deletions(-)
> 
> 
>> diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
>> index fffb0b7da8..c32f6c2835 100644
>> --- a/include/hw/mips/bootloader.h
>> +++ b/include/hw/mips/bootloader.h
>> @@ -11,16 +11,16 @@
>>   #include "exec/cpu-defs.h"
>> -void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr);
>> -void bl_gen_jump_kernel(uint32_t **p,
>> +void bl_gen_jump_to(void **ptr, target_ulong jump_addr);
>> +void bl_gen_jump_kernel(void **ptr,
>>                           bool set_sp, target_ulong sp,
>>                           bool set_a0, target_ulong a0,
>>                           bool set_a1, target_ulong a1,
>>                           bool set_a2, target_ulong a2,
>>                           bool set_a3, target_ulong a3,
>>                           target_ulong kernel_addr);
>> -void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val);
>> -void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val);
>> -void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val);
>> +void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val);
>> +void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val);
>> +void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val);
> 
> And I forgot to squash this...:

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

> 
> -- >8 --
> diff --git a/hw/mips/boston.c b/hw/mips/boston.c
> index edda87e23c..b6dd9fb200 100644
> --- a/hw/mips/boston.c
> +++ b/hw/mips/boston.c
> @@ -323,7 +323,7 @@ static void boston_register_types(void)
>   }
>   type_init(boston_register_types)
> 
> -static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
> +static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr)
>   {
>       uint64_t regaddr;
> 
> diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
> index 34befa5dd5..cfc8ca6ae4 100644
> --- a/hw/mips/fuloong2e.c
> +++ b/hw/mips/fuloong2e.c
> @@ -179,7 +179,7 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base,
>       /* Second part of the bootloader */
>       p = (uint32_t *)(base + 0x040);
> 
> -    bl_gen_jump_kernel(&p,
> +    bl_gen_jump_kernel((void **)&p,
>                          true, ENVP_VADDR - 64,
>                          true, 2, true, ENVP_VADDR,
>                          true, ENVP_VADDR + 8,
> ---
> 

Re: [PATCH-for-8.0 v2 03/11] hw/mips/bootloader: Implement nanoMIPS SW opcode generator

[Richard Henderson]

On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/mips/bootloader.c | 20 +++++++++++++++++++-
>   1 file changed, 19 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
> 
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> index 0035f37335..3e1e73360f 100644
> --- a/hw/mips/bootloader.c
> +++ b/hw/mips/bootloader.c
> @@ -143,9 +143,27 @@ static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
>       bl_gen_i_type(p, 0x0d, rs, rt, imm);
>   }
>   
> +static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12)
> +{
> +    uint32_t insn = 0;
> +
> +    assert(extract32(ofs12, 0, 12) == ofs12);
> +    insn = deposit32(insn, 26, 6, 0b100001);
> +    insn = deposit32(insn, 21, 5, rt);
> +    insn = deposit32(insn, 16, 5, rs);
> +    insn = deposit32(insn, 12, 4, 0b1001);
> +    insn = deposit32(insn, 0, 12, ofs12);
> +
> +    st_nm32_p(ptr, insn);
> +}
> +
>   static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
>   {
> -    bl_gen_i_type(p, 0x2b, base, rt, offset);
> +    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
> +        bl_gen_sw_nm(p, rt, base, offset);
> +    } else {
> +        bl_gen_i_type(p, 0x2b, base, rt, offset);
> +    }
>   }
>   
>   static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)

Re: [PATCH-for-8.0 v2 04/11] hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator

[Richard Henderson]

On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/mips/bootloader.c | 36 ++++++++++++++++++++++++++++++++++--
>   1 file changed, 34 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

> 
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> index 3e1e73360f..9fc926d83f 100644
> --- a/hw/mips/bootloader.c
> +++ b/hw/mips/bootloader.c
> @@ -132,12 +132,39 @@ static void bl_gen_jalr(void **p, bl_reg rs)
>       bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
>   }
>   
> +static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)
> +{
> +    uint32_t insn = 0;
> +
> +    assert(extract32(imm20, 0, 20) == imm20);
> +    insn = deposit32(insn, 26, 6, 0b111000);
> +    insn = deposit32(insn, 21, 5, rt);
> +    insn = deposit32(insn, 12, 9, extract32(imm20, 0, 9));
> +    insn = deposit32(insn, 2, 10, extract32(imm20, 9, 10));
> +    insn = deposit32(insn, 0, 1, sextract32(imm20, 19, 1));
> +
> +    st_nm32_p(ptr, insn);
> +}
> +
>   static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm)
>   {
>       /* R6: It's a alias of AUI with RS = 0 */
>       bl_gen_i_type(p, 0x0f, 0, rt, imm);
>   }
>   
> +static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm12)
> +{
> +    uint32_t insn = 0;
> +
> +    assert(extract32(imm12, 0, 12) == imm12);
> +    insn = deposit32(insn, 26, 6, 0b100000);
> +    insn = deposit32(insn, 21, 5, rt);
> +    insn = deposit32(insn, 16, 5, rs);
> +    insn = deposit32(insn, 0, 12, imm12);
> +
> +    st_nm32_p(ptr, insn);
> +}
> +
>   static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
>   {
>       bl_gen_i_type(p, 0x0d, rs, rt, imm);
> @@ -178,8 +205,13 @@ static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
>   /* Pseudo instructions */
>   static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
>   {
> -    bl_gen_lui(p, rt, extract32(imm, 16, 16));
> -    bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
> +    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
> +        bl_gen_lui_nm(p, rt, extract32(imm, 12, 20));
> +        bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12));
> +    } else {
> +        bl_gen_lui(p, rt, extract32(imm, 16, 16));
> +        bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
> +    }
>   }
>   
>   static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)

Re: [PATCH-for-8.0 v2 05/11] hw/mips/bootloader: Implement nanoMIPS JALRc opcode generator

[Richard Henderson]

On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/mips/bootloader.c | 12 +++++++++++-
>   1 file changed, 11 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

> 
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> index 9fc926d83f..1dd6ef2096 100644
> --- a/hw/mips/bootloader.c
> +++ b/hw/mips/bootloader.c
> @@ -129,7 +129,17 @@ static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
>   
>   static void bl_gen_jalr(void **p, bl_reg rs)
>   {
> -    bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
> +    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
> +        uint32_t insn = 0;
> +
> +        insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */
> +        insn = deposit32(insn, 21, 5, BL_REG_RA);
> +        insn = deposit32(insn, 16, 5, rs);
> +
> +        st_nm32_p(p, insn);
> +    } else {
> +        bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
> +    }
>   }
>   
>   static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)

Re: [PATCH-for-8.0 v2 06/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5)

[Richard Henderson]

On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Similarly to how commit 0c8427baf0 ("hw/mips/malta: Use bootloader
> helper to set BAR registers") converted write_bootloader(), convert
> the equivalent write_bootloader_nanomips(), allowing us to modify
> the bootloader code more easily in the future.
> 
> Part 1/5: Convert PCI0 MEM1 BAR setup
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH-for-8.0 v2 07/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5)

[Richard Henderson]

On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Part 2/5: Convert PCI0 MEM0 BAR setup
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/mips/malta.c | 35 ++++++-----------------------------
>   1 file changed, 6 insertions(+), 29 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

> 
> diff --git a/hw/mips/malta.c b/hw/mips/malta.c
> index 30ca4e0000..3e80a12221 100644
> --- a/hw/mips/malta.c
> +++ b/hw/mips/malta.c
> @@ -687,7 +687,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>        * Load BAR registers as done by YAMON:
>        *
>        *  - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
> -     *  - set up PCI0 MEM0 at 0x10000000, size 0x8000000
>        *
>        */
>       stw_p(p++, 0xe040); stw_p(p++, 0x0681);
> @@ -723,20 +722,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>       stw_p(p++, 0xe020); stw_p(p++, 0x0001);
>                                   /* lui t0, %hi(0x80000000)      */
>   
> -    /* 0x58 corresponds to GT_PCI0M0LD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9058);
> -                                /* sw t0, 0x58(t1)              */
> -
> -    stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
> -                                /* lui t0, %hi(0x3f000000)      */
> -
> -    /* 0x60 corresponds to GT_PCI0M0HD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9060);
> -                                /* sw t0, 0x60(t1)              */
> -
> -    stw_p(p++, 0xe020); stw_p(p++, 0x0821);
> -                                /* lui t0, %hi(0xc1000000)      */
> -
>   #else
>   #define cpu_to_gt32 cpu_to_be32
>   
> @@ -767,24 +752,16 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>   
>       stw_p(p++, 0x0020); stw_p(p++, 0x0080);
>                                   /* addiu[32] t0, $0, 0x80       */
> -
> -    /* 0x58 corresponds to GT_PCI0M0LD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9058);
> -                                /* sw t0, 0x58(t1)              */
> -
> -    stw_p(p++, 0x0020); stw_p(p++, 0x003f);
> -                                /* addiu[32] t0, $0, 0x3f       */
> -
> -    /* 0x60 corresponds to GT_PCI0M0HD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9060);
> -                                /* sw t0, 0x60(t1)              */
> -
> -    stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
> -                                /* addiu[32] t0, $0, 0xc1       */
>   #endif
>       v = p;
>   
>       /* setup PCI0 mem windows */
> +    bl_gen_write_u32(&v, /* GT_PCI0M0LD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
> +                     cpu_to_gt32(0x10000000 << 3));
> +    bl_gen_write_u32(&v, /* GT_PCI0M0HD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
> +                     cpu_to_gt32(0x07e00000 << 3));
>       bl_gen_write_u32(&v, /* GT_PCI0M1LD */
>                        cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
>                        cpu_to_gt32(0x18200000 << 3));

Re: [PATCH-for-8.0 v2 08/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5)

[Richard Henderson]

On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Part 3/5: Convert PCI0 I/O BAR setup
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

> ---
>   hw/mips/malta.c | 40 ++++++++--------------------------------
>   1 file changed, 8 insertions(+), 32 deletions(-)
> 
> diff --git a/hw/mips/malta.c b/hw/mips/malta.c
> index 3e80a12221..16161b1b03 100644
> --- a/hw/mips/malta.c
> +++ b/hw/mips/malta.c
> @@ -685,9 +685,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>   
>       /*
>        * Load BAR registers as done by YAMON:
> -     *
> -     *  - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
> -     *
>        */
>       stw_p(p++, 0xe040); stw_p(p++, 0x0681);
>                                   /* lui t1, %hi(0xb4000000)      */
> @@ -707,21 +704,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>   
>       stw_p(p++, 0xe020); stw_p(p++, 0x0801);
>                                   /* lui t0, %hi(0xc0000000)      */
> -
> -    /* 0x48 corresponds to GT_PCI0IOLD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
> -                                /* sw t0, 0x48(t1)              */
> -
> -    stw_p(p++, 0xe020); stw_p(p++, 0x0800);
> -                                /* lui t0, %hi(0x40000000)      */
> -
> -    /* 0x50 corresponds to GT_PCI0IOHD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
> -                                /* sw t0, 0x50(t1)              */
> -
> -    stw_p(p++, 0xe020); stw_p(p++, 0x0001);
> -                                /* lui t0, %hi(0x80000000)      */
> -
>   #else
>   #define cpu_to_gt32 cpu_to_be32
>   
> @@ -738,23 +720,17 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>   
>       stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
>                                   /* addiu[32] t0, $0, 0xc0       */
> -
> -    /* 0x48 corresponds to GT_PCI0IOLD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
> -                                /* sw t0, 0x48(t1)              */
> -
> -    stw_p(p++, 0x0020); stw_p(p++, 0x0040);
> -                                /* addiu[32] t0, $0, 0x40       */
> -
> -    /* 0x50 corresponds to GT_PCI0IOHD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
> -                                /* sw t0, 0x50(t1)              */
> -
> -    stw_p(p++, 0x0020); stw_p(p++, 0x0080);
> -                                /* addiu[32] t0, $0, 0x80       */
>   #endif
>       v = p;
>   
> +    /* setup PCI0 io window to 0x18000000-0x181fffff */
> +    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
> +                     cpu_to_gt32(0x18000000 << 3));
> +    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
> +                     cpu_to_gt32(0x08000000 << 3));
> +
>       /* setup PCI0 mem windows */
>       bl_gen_write_u32(&v, /* GT_PCI0M0LD */
>                        cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),

Re: [PATCH-for-8.0 v2 09/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5)

[Richard Henderson]

On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Part 4/5: Convert GT64120 ISD base address setup
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

> ---
>   hw/mips/malta.c | 40 +++++++---------------------------------
>   1 file changed, 7 insertions(+), 33 deletions(-)
> 
> diff --git a/hw/mips/malta.c b/hw/mips/malta.c
> index 16161b1b03..451908b217 100644
> --- a/hw/mips/malta.c
> +++ b/hw/mips/malta.c
> @@ -683,46 +683,20 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>       stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
>                                   /* ori a3,a3,%lo(loaderparams.ram_low_size) */
>   
> -    /*
> -     * Load BAR registers as done by YAMON:
> -     */
> -    stw_p(p++, 0xe040); stw_p(p++, 0x0681);
> -                                /* lui t1, %hi(0xb4000000)      */
> -
>   #if TARGET_BIG_ENDIAN
>   #define cpu_to_gt32 cpu_to_le32
> -
> -    stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
> -                                /* lui t0, %hi(0xdf000000)      */
> -
> -    /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c)  */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9068);
> -                                /* sw t0, 0x68(t1)              */
> -
> -    stw_p(p++, 0xe040); stw_p(p++, 0x077d);
> -                                /* lui t1, %hi(0xbbe00000)      */
> -
> -    stw_p(p++, 0xe020); stw_p(p++, 0x0801);
> -                                /* lui t0, %hi(0xc0000000)      */
>   #else
>   #define cpu_to_gt32 cpu_to_be32
> -
> -    stw_p(p++, 0x0020); stw_p(p++, 0x00df);
> -                                /* addiu[32] t0, $0, 0xdf       */
> -
> -    /* 0x68 corresponds to GT_ISD                               */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9068);
> -                                /* sw t0, 0x68(t1)              */
> -
> -    /* Use kseg2 remapped address 0x1be00000                    */
> -    stw_p(p++, 0xe040); stw_p(p++, 0x077d);
> -                                /* lui t1, %hi(0xbbe00000)      */
> -
> -    stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
> -                                /* addiu[32] t0, $0, 0xc0       */
>   #endif
>       v = p;
>   
> +    /* setup MEM-to-PCI0 mapping as done by YAMON */
> +
> +    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
> +    bl_gen_write_u32(&v, /* GT_ISD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
> +                     cpu_to_gt32(0x1be00000 << 3));
> +
>       /* setup PCI0 io window to 0x18000000-0x181fffff */
>       bl_gen_write_u32(&v, /* GT_PCI0IOLD */
>                        cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),

Re: [PATCH-for-8.0 v2 10/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5)

[Richard Henderson]

On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Part 5/5: Convert jumping to kernel
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/mips/malta.c | 68 ++++++++-----------------------------------------
>   1 file changed, 11 insertions(+), 57 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


> 
> diff --git a/hw/mips/malta.c b/hw/mips/malta.c
> index 451908b217..876bc26a7f 100644
> --- a/hw/mips/malta.c
> +++ b/hw/mips/malta.c
> @@ -619,11 +619,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>       /* Small bootloader */
>       p = (uint16_t *)base;
>   
> -#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
> -#define NM_HI2(VAL) \
> -          (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
> -#define NM_LO(VAL)  ((VAL) & 0xfff)
> -
>       stw_p(p++, 0x2800); stw_p(p++, 0x001c);
>                                   /* bc to_here */
>       stw_p(p++, 0x8000); stw_p(p++, 0xc000);
> @@ -642,46 +637,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>                                   /* nop */
>   
>       /* to_here: */
> -    if (semihosting_get_argc()) {
> -        /* Preserve a0 content as arguments have been passed    */
> -        stw_p(p++, 0x8000); stw_p(p++, 0xc000);
> -                                /* nop                          */
> -    } else {
> -        stw_p(p++, 0x0080); stw_p(p++, 0x0002);
> -                                /* li a0,2                      */
> -    }
> -
> -    stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64));
> -
> -    stw_p(p++, NM_HI2(ENVP_VADDR - 64));
> -                                /* lui sp,%hi(ENVP_VADDR - 64)   */
> -
> -    stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64));
> -                                /* ori sp,sp,%lo(ENVP_VADDR - 64) */
> -
> -    stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR));
> -
> -    stw_p(p++, NM_HI2(ENVP_VADDR));
> -                                /* lui a1,%hi(ENVP_VADDR)        */
> -
> -    stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR));
> -                                /* ori a1,a1,%lo(ENVP_VADDR)     */
> -
> -    stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8));
> -
> -    stw_p(p++, NM_HI2(ENVP_VADDR + 8));
> -                                /* lui a2,%hi(ENVP_VADDR + 8)    */
> -
> -    stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8));
> -                                /* ori a2,a2,%lo(ENVP_VADDR + 8) */
> -
> -    stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
> -
> -    stw_p(p++, NM_HI2(loaderparams.ram_low_size));
> -                                /* lui a3,%hi(loaderparams.ram_low_size) */
> -
> -    stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
> -                                /* ori a3,a3,%lo(loaderparams.ram_low_size) */
>   
>   #if TARGET_BIG_ENDIAN
>   #define cpu_to_gt32 cpu_to_le32
> @@ -719,20 +674,19 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>                        cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
>                        cpu_to_gt32(0x0bc00000 << 3));
>   
> -    p = v;
> -
>   #undef cpu_to_gt32
>   
> -    stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
> -
> -    stw_p(p++, NM_HI2(kernel_entry));
> -                                /* lui t9,%hi(kernel_entry)     */
> -
> -    stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
> -                                /* ori t9,t9,%lo(kernel_entry)  */
> -
> -    stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
> -                                /* jalrc   t8                   */
> +    bl_gen_jump_kernel(&v,
> +                       true, ENVP_VADDR - 64,
> +                       /*
> +                        * If semihosting is used, arguments have already been
> +                        * passed, so we preserve $a0.
> +                        */
> +                       !semihosting_get_argc(), 2,
> +                       true, ENVP_VADDR,
> +                       true, ENVP_VADDR + 8,
> +                       true, loaderparams.ram_low_size,
> +                       kernel_entry);
>   }
>   
>   /*

Re: [PATCH-for-8.0 v2 11/11] hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel()

[Richard Henderson]

On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Merge common code shared between write_bootloader() and
> write_bootloader_nanomips() into bl_setup_gt64120_jump_kernel().
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


> ---
>   hw/mips/malta.c | 155 +++++++++++++++++-------------------------------
>   1 file changed, 56 insertions(+), 99 deletions(-)
> 
> diff --git a/hw/mips/malta.c b/hw/mips/malta.c
> index 876bc26a7f..9cd59c13e4 100644
> --- a/hw/mips/malta.c
> +++ b/hw/mips/malta.c
> @@ -610,11 +610,64 @@ static void network_init(PCIBus *pci_bus)
>       }
>   }
>   
> +static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
> +                                         uint64_t kernel_entry)
> +{
> +    /* Bus endianess is always reversed */
> +#if TARGET_BIG_ENDIAN
> +#define cpu_to_gt32 cpu_to_le32
> +#else
> +#define cpu_to_gt32 cpu_to_be32
> +#endif
> +
> +    /* setup MEM-to-PCI0 mapping as done by YAMON */
> +
> +    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
> +    bl_gen_write_u32(p, /* GT_ISD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
> +                     cpu_to_gt32(0x1be00000 << 3));
> +
> +    /* setup PCI0 io window to 0x18000000-0x181fffff */
> +    bl_gen_write_u32(p, /* GT_PCI0IOLD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
> +                     cpu_to_gt32(0x18000000 << 3));
> +    bl_gen_write_u32(p, /* GT_PCI0IOHD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
> +                     cpu_to_gt32(0x08000000 << 3));
> +
> +    /* setup PCI0 mem windows */
> +    bl_gen_write_u32(p, /* GT_PCI0M0LD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
> +                     cpu_to_gt32(0x10000000 << 3));
> +    bl_gen_write_u32(p, /* GT_PCI0M0HD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
> +                     cpu_to_gt32(0x07e00000 << 3));
> +    bl_gen_write_u32(p, /* GT_PCI0M1LD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
> +                     cpu_to_gt32(0x18200000 << 3));
> +    bl_gen_write_u32(p, /* GT_PCI0M1HD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
> +                     cpu_to_gt32(0x0bc00000 << 3));
> +
> +#undef cpu_to_gt32
> +
> +    bl_gen_jump_kernel(p,
> +                       true, ENVP_VADDR - 64,
> +                       /*
> +                        * If semihosting is used, arguments have already
> +                        * been passed, so we preserve $a0.
> +                        */
> +                       !semihosting_get_argc(), 2,
> +                       true, ENVP_VADDR,
> +                       true, ENVP_VADDR + 8,
> +                       true, loaderparams.ram_low_size,
> +                       kernel_entry);
> +}
> +
>   static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>                                         uint64_t kernel_entry)
>   {
>       uint16_t *p;
> -    void *v;
>   
>       /* Small bootloader */
>       p = (uint16_t *)base;
> @@ -638,55 +691,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>   
>       /* to_here: */
>   
> -#if TARGET_BIG_ENDIAN
> -#define cpu_to_gt32 cpu_to_le32
> -#else
> -#define cpu_to_gt32 cpu_to_be32
> -#endif
> -    v = p;
> -
> -    /* setup MEM-to-PCI0 mapping as done by YAMON */
> -
> -    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
> -    bl_gen_write_u32(&v, /* GT_ISD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
> -                     cpu_to_gt32(0x1be00000 << 3));
> -
> -    /* setup PCI0 io window to 0x18000000-0x181fffff */
> -    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
> -                     cpu_to_gt32(0x18000000 << 3));
> -    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
> -                     cpu_to_gt32(0x08000000 << 3));
> -
> -    /* setup PCI0 mem windows */
> -    bl_gen_write_u32(&v, /* GT_PCI0M0LD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
> -                     cpu_to_gt32(0x10000000 << 3));
> -    bl_gen_write_u32(&v, /* GT_PCI0M0HD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
> -                     cpu_to_gt32(0x07e00000 << 3));
> -    bl_gen_write_u32(&v, /* GT_PCI0M1LD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
> -                     cpu_to_gt32(0x18200000 << 3));
> -    bl_gen_write_u32(&v, /* GT_PCI0M1HD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
> -                     cpu_to_gt32(0x0bc00000 << 3));
> -
> -#undef cpu_to_gt32
> -
> -    bl_gen_jump_kernel(&v,
> -                       true, ENVP_VADDR - 64,
> -                       /*
> -                        * If semihosting is used, arguments have already been
> -                        * passed, so we preserve $a0.
> -                        */
> -                       !semihosting_get_argc(), 2,
> -                       true, ENVP_VADDR,
> -                       true, ENVP_VADDR + 8,
> -                       true, loaderparams.ram_low_size,
> -                       kernel_entry);
> +    bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
>   }
>   
>   /*
> @@ -752,55 +757,8 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
>        *
>        */
>   
> -    /* Bus endianess is always reversed */
> -#if TARGET_BIG_ENDIAN
> -#define cpu_to_gt32 cpu_to_le32
> -#else
> -#define cpu_to_gt32 cpu_to_be32
> -#endif
>       v = p;
> -
> -    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
> -    bl_gen_write_u32(&v, /* GT_ISD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
> -                     cpu_to_gt32(0x1be00000 << 3));
> -
> -    /* setup MEM-to-PCI0 mapping */
> -    /* setup PCI0 io window to 0x18000000-0x181fffff */
> -    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
> -                     cpu_to_gt32(0x18000000 << 3));
> -    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
> -                     cpu_to_gt32(0x08000000 << 3));
> -    /* setup PCI0 mem windows */
> -    bl_gen_write_u32(&v, /* GT_PCI0M0LD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
> -                     cpu_to_gt32(0x10000000 << 3));
> -    bl_gen_write_u32(&v, /* GT_PCI0M0HD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
> -                     cpu_to_gt32(0x07e00000 << 3));
> -
> -    bl_gen_write_u32(&v, /* GT_PCI0M1LD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
> -                     cpu_to_gt32(0x18200000 << 3));
> -    bl_gen_write_u32(&v, /* GT_PCI0M1HD */
> -                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
> -                     cpu_to_gt32(0x0bc00000 << 3));
> -
> -#undef cpu_to_gt32
> -
> -    bl_gen_jump_kernel(&v,
> -                       true, ENVP_VADDR - 64,
> -                       /*
> -                        * If semihosting is used, arguments have already been
> -                        * passed, so we preserve $a0.
> -                        */
> -                       !semihosting_get_argc(), 2,
> -                       true, ENVP_VADDR,
> -                       true, ENVP_VADDR + 8,
> -                       true, loaderparams.ram_low_size,
> -                       kernel_entry);
> +    bl_setup_gt64120_jump_kernel(&v, run_addr, kernel_entry);
>       p = v;
>   
>       /* YAMON subroutines */
> @@ -845,7 +803,6 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
>       stl_p(p++, 0x00000000);                  /* nop */
>       stl_p(p++, 0x03e00009);                  /* jalr ra */
>       stl_p(p++, 0xa1040000);                  /* sb a0,0(t0) */
> -
>   }
>   
>   static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,

Re: [PATCH-for-8.0 v2 00/11] hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API

[Philippe Mathieu-Daudé]

On 11/12/22 21:45, Philippe Mathieu-Daudé wrote:

>    hw/mips/bootloader: Handle buffers as opaque arrays
>    hw/mips/bootloader: Implement nanoMIPS NOP opcode generator
>    hw/mips/bootloader: Implement nanoMIPS SW opcode generator
>    hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator
>    hw/mips/bootloader: Implement nanoMIPS JALRc opcode generator
>    hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5)
>    hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5)
>    hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5)
>    hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5)
>    hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5)
>    hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel()

Series queued to mips-next.