[PATCH v3 00/19] Add USB on SAM9X60, SAMA7G5 and SAMA5D2 boards

[PATCH v3 00/19] Add USB on SAM9X60, SAMA7G5 and SAMA5D2 boards

[Sergiu Moga]

This series of patches is meant to add support for USB Mass Storage
on SAM9X60, SAMA7G5 and SAMA5D2 boards and register ohci-at91 driver into
Driver Model. In order for this to be achieved, the respective
DT nodes have been added, the USB clock has been registered into CCF
and the required defconfigs have been added to the boards' defconfig.
What is more, in order for the VBUS to stay enabled, a `child_pre_probe`
method has been added to overcome the DM core disabling it in
`usb_scan_device`: when the generic `device_probe` method is called,
the pinctrl is processed once again, undoing whatever changes have
been made in our driver's probe method.
In order to enable USB on SAMA7G5 the addition of RSTC and USB 2.0 PHY
drivers were required.



v1 -> v2:
- Additional patch included:
[PATCH v2 04/19] clk: at91: pmc: export clock setup to pmc
- Updated
[PATCH v2 05/19] clk: at91: sam9x60: Add initial setup of UPLL and USBCK rates
in concordance with the previously mentioned additional patch
- Move ` #include <asm/arch/clk.h>` below `#if !(CONFIG_IS_ENABLED(DM_USB))` to
avoid implicit declarations warnings/errors in the OHCI driver


v2 ->  v3:
- Also add USB pinctrl nodes and USB Mass Storage for SAM9X60 Curiosity and
remove no longer necessary ifdef in sam9x60 clk driver
- Remove no longer required CONFIG_SYS_USB_* configs from the defconfigs
and add CONFIG_RESET_AT91 to all defconfigs


Claudiu Beznea (1):
  clk: at91: pmc: export clock setup to pmc

Cristian Birsan (2):
  ARM: at91: add sama7 SFR definitions
  usb: ohci-at91: Add `ohci_t` field in `ohci_at91_priv`

Sergiu Moga (16):
  ARM: dts: sam9x60: Add OHCI and EHCI DT nodes
  clk: at91: Add support for sam9x60 USB clock
  clk: at91: sam9x60: Register the required clocks for USB
  clk: at91: sam9x60: Add initial setup of UPLL and USBCK rates
  usb: ohci-at91: Enable OHCI functionality and register into DM
  dt-bindings: reset: add sama7g5 definitions
  dt-bindings: clk: at91: Define additional UTMI related clocks
  ARM: dts: at91: sama7: Add USB related DT nodes
  reset: at91: Add reset driver for basic assert/deassert operations
  phy: at91: Add support for the USB 2.0 PHY's of SAMA7
  usb: ohci-at91: Add USB PHY functionality
  ARM: dts: at91: sama5d2_icp: Add pinctrl nodes for USB related DT
    nodes
  ARM: dts: at91: sama5d27_wlsom1_ek: Add pinctrl nodes for USB DT nodes
  configs: at91: sam9x60ek: Add required configs for the USB command
  configs: at91: sama5d2: Enable OHCI/EHCI related configs
  configs: at91: sama7: Enable USB and RESET functionality

 arch/arm/dts/at91-sam9x60_curiosity.dts       |  21 ++
 arch/arm/dts/at91-sama5d27_wlsom1_ek.dts      |  25 ++
 arch/arm/dts/at91-sama5d2_icp.dts             |  22 ++
 arch/arm/dts/at91-sama7g5ek.dts               |  34 +++
 arch/arm/dts/sam9x60.dtsi                     |  18 ++
 arch/arm/dts/sam9x60ek.dts                    |  21 ++
 arch/arm/dts/sama7g5.dtsi                     |  73 ++++++
 arch/arm/mach-at91/include/mach/sama7-sfr.h   |  59 +++++
 configs/sam9x60_curiosity_mmc_defconfig       |   8 +
 configs/sam9x60ek_mmc_defconfig               |   9 +
 configs/sam9x60ek_nandflash_defconfig         |   9 +
 configs/sam9x60ek_qspiflash_defconfig         |   9 +
 configs/sama5d27_giantboard_defconfig         |   4 +
 configs/sama5d27_som1_ek_mmc1_defconfig       |   4 +
 configs/sama5d27_som1_ek_mmc_defconfig        |   4 +
 configs/sama5d27_som1_ek_qspiflash_defconfig  |   4 +
 configs/sama5d27_wlsom1_ek_mmc_defconfig      |   5 +
 .../sama5d27_wlsom1_ek_qspiflash_defconfig    |   4 +
 configs/sama5d2_icp_mmc_defconfig             |   8 +
 configs/sama5d2_icp_qspiflash_defconfig       |   4 +
 configs/sama5d2_ptc_ek_mmc_defconfig          |   4 +
 configs/sama5d2_ptc_ek_nandflash_defconfig    |   4 +
 configs/sama5d2_xplained_emmc_defconfig       |   4 +
 configs/sama5d2_xplained_mmc_defconfig        |   4 +
 configs/sama5d2_xplained_qspiflash_defconfig  |   4 +
 configs/sama5d2_xplained_spiflash_defconfig   |   4 +
 configs/sama7g5ek_mmc1_defconfig              |  10 +
 configs/sama7g5ek_mmc_defconfig               |  10 +
 drivers/clk/at91/Kconfig                      |   7 +
 drivers/clk/at91/Makefile                     |   1 +
 drivers/clk/at91/clk-sam9x60-usb.c            | 156 +++++++++++++
 drivers/clk/at91/pmc.c                        |  42 ++++
 drivers/clk/at91/pmc.h                        |  27 +++
 drivers/clk/at91/sam9x60.c                    |  63 +++++
 drivers/clk/at91/sama7g5.c                    |  48 +---
 drivers/phy/Kconfig                           |  10 +
 drivers/phy/Makefile                          |   1 +
 drivers/phy/phy-sama7-usb.c                   |  92 ++++++++
 drivers/phy/phy-sama7-utmi-clk.c              | 202 ++++++++++++++++
 drivers/reset/Kconfig                         |   8 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-at91.c                    | 141 ++++++++++++
 drivers/sysreset/sysreset_at91.c              |  10 +-
 drivers/usb/host/ohci-at91.c                  | 215 ++++++++++++++++++
 include/dt-bindings/clk/at91.h                |   5 +
 include/dt-bindings/reset/sama7g5-reset.h     |  10 +
 46 files changed, 1377 insertions(+), 51 deletions(-)
 create mode 100644 arch/arm/mach-at91/include/mach/sama7-sfr.h
 create mode 100644 drivers/clk/at91/clk-sam9x60-usb.c
 create mode 100644 drivers/phy/phy-sama7-usb.c
 create mode 100644 drivers/phy/phy-sama7-utmi-clk.c
 create mode 100644 drivers/reset/reset-at91.c
 create mode 100644 include/dt-bindings/reset/sama7g5-reset.h

-- 
2.34.1

[PATCH v3 01/19] ARM: dts: sam9x60: Add OHCI and EHCI DT nodes

[Sergiu Moga]

Add the OHCI and EHCI DT nodes for the sam9x60 boards.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---


v1 -> v2:
- No change


v2 -> v3:
- Also add pinctrl nodes to sam9x60 curiosity



 arch/arm/dts/at91-sam9x60_curiosity.dts | 21 +++++++++++++++++++++
 arch/arm/dts/sam9x60.dtsi               | 18 ++++++++++++++++++
 arch/arm/dts/sam9x60ek.dts              | 21 +++++++++++++++++++++
 3 files changed, 60 insertions(+)

diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts
index 7c5b6ae2b8..d6ae3d648d 100644
--- a/arch/arm/dts/at91-sam9x60_curiosity.dts
+++ b/arch/arm/dts/at91-sam9x60_curiosity.dts
@@ -49,6 +49,13 @@
 						atmel,pins =
 							<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
 					};
+
+					usb1 {
+						pinctrl_usb_default: usb_default {
+							atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+									AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+						};
+					};
 			};
 		};
 	};
@@ -89,3 +96,17 @@
 	phy-mode = "rmii";
 	status = "okay";
 };
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   &pioD 15 GPIO_ACTIVE_HIGH
+			   &pioD 18 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_default>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index 17224ef771..e36a540f78 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -69,6 +69,24 @@
 		#size-cells = <1>;
 		ranges;
 
+		usb1: ohci@600000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00600000 0x100000>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 21>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		usb2: ehci@700000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00700000 0x100000>;
+			clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+			clock-names = "usb_clk", "ehci_clk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE 8>;
+			assigned-clock-rates = <480000000>;
+			status = "disabled";
+		};
+
 		ebi: ebi@10000000 {
 			compatible = "microchip,sam9x60-ebi";
 			#address-cells = <2>;
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index 1a02e2cb79..45e2f4cc40 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -139,6 +139,13 @@
 						<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
 				};
 
+				usb1 {
+					pinctrl_usb_default: usb_default {
+						atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+								AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
+				};
+
 			};
 		};
 	};
@@ -213,3 +220,17 @@
 	phy-mode = "rmii";
 	status = "okay";
 };
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   &pioD 15 GPIO_ACTIVE_HIGH
+			   &pioD 16 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_default>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
-- 
2.34.1

[PATCH v3 02/19] clk: at91: Add support for sam9x60 USB clock

[Sergiu Moga]

Implement sam9x60 USB clock driver. This clock has
three parents: PLLA, UPLL and MAINXTAL. The driver is
aware of the three possible parents with the help of the
two mux tables provied to the driver during the registration
of the clock.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---


v1 -> v3:
- No change



 drivers/clk/at91/Kconfig           |   7 ++
 drivers/clk/at91/Makefile          |   1 +
 drivers/clk/at91/clk-sam9x60-usb.c | 156 +++++++++++++++++++++++++++++
 drivers/clk/at91/pmc.h             |  11 ++
 4 files changed, 175 insertions(+)
 create mode 100644 drivers/clk/at91/clk-sam9x60-usb.c

diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig
index 4abc8026b4..4563892647 100644
--- a/drivers/clk/at91/Kconfig
+++ b/drivers/clk/at91/Kconfig
@@ -61,3 +61,10 @@ config AT91_SAM9X60_PLL
 	help
 	  This option is used to enable the AT91 SAM9X60's PLL clock
 	  driver.
+
+config AT91_SAM9X60_USB
+	bool "USB Clock support for SAM9X60 SoCs"
+	depends on CLK_AT91
+	help
+	  This option is used to enable the AT91 SAM9X60's USB clock
+	  driver.
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 580b406d7b..e53dcb4ca7 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -9,6 +9,7 @@ obj-y += clk-peripheral.o
 obj-$(CONFIG_AT91_GENERIC_CLK)	+= clk-generic.o
 obj-$(CONFIG_AT91_UTMI)		+= clk-utmi.o
 obj-$(CONFIG_AT91_SAM9X60_PLL)	+= clk-sam9x60-pll.o
+obj-$(CONFIG_AT91_SAM9X60_USB)	+= clk-sam9x60-usb.o
 obj-$(CONFIG_SAMA7G5)		+= sama7g5.o
 obj-$(CONFIG_SAM9X60)		+= sam9x60.o
 else
diff --git a/drivers/clk/at91/clk-sam9x60-usb.c b/drivers/clk/at91/clk-sam9x60-usb.c
new file mode 100644
index 0000000000..0ccdc1494d
--- /dev/null
+++ b/drivers/clk/at91/clk-sam9x60-usb.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SAM9X60's USB Clock support.
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sergiu Moga <sergiu.moga@microchip.com>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/clk-provider.h>
+
+#include "pmc.h"
+
+#define UBOOT_DM_CLK_AT91_SAM9X60_USB		"at91-sam9x60-usb-clk"
+
+struct sam9x60_usb {
+	const struct clk_usbck_layout		*layout;
+	void					__iomem *base;
+	struct clk				clk;
+	const u32				*clk_mux_table;
+	const u32				*mux_table;
+	const char * const			*parent_names;
+	u32					num_parents;
+	u8					id;
+};
+
+#define to_sam9x60_usb(_clk)	container_of(_clk, struct sam9x60_usb, clk)
+#define USB_MAX_DIV		15
+
+static int sam9x60_usb_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct sam9x60_usb *usb = to_sam9x60_usb(clk);
+	u32 val, index;
+
+	index = at91_clk_mux_val_to_index(usb->clk_mux_table, usb->num_parents,
+					  parent->id);
+	if (index < 0)
+		return index;
+
+	index = at91_clk_mux_index_to_val(usb->mux_table, usb->num_parents,
+					  index);
+	if (index < 0)
+		return index;
+
+	pmc_read(usb->base, usb->layout->offset, &val);
+	val &= ~usb->layout->usbs_mask;
+	val |= index << (ffs(usb->layout->usbs_mask - 1));
+	pmc_write(usb->base, usb->layout->offset, val);
+
+	return 0;
+}
+
+static ulong sam9x60_usb_clk_get_rate(struct clk *clk)
+{
+	struct sam9x60_usb *usb = to_sam9x60_usb(clk);
+	ulong parent_rate = clk_get_parent_rate(clk);
+	u32 val, usbdiv;
+
+	if (!parent_rate)
+		return 0;
+
+	pmc_read(usb->base, usb->layout->offset, &val);
+	usbdiv = (val & usb->layout->usbdiv_mask) >>
+		(ffs(usb->layout->usbdiv_mask) - 1);
+	return parent_rate / (usbdiv + 1);
+}
+
+static ulong sam9x60_usb_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct sam9x60_usb *usb = to_sam9x60_usb(clk);
+	ulong parent_rate = clk_get_parent_rate(clk);
+	u32 usbdiv, val;
+
+	if (!parent_rate)
+		return 0;
+
+	usbdiv = DIV_ROUND_CLOSEST(parent_rate, rate);
+	if (usbdiv > USB_MAX_DIV + 1 || !usbdiv)
+		return 0;
+
+	pmc_read(usb->base, usb->layout->offset, &val);
+	val &= usb->layout->usbdiv_mask;
+	val |= (usbdiv - 1) << (ffs(usb->layout->usbdiv_mask) - 1);
+	pmc_write(usb->base, usb->layout->offset, val);
+
+	return parent_rate / usbdiv;
+}
+
+static const struct clk_ops sam9x60_usb_ops = {
+	.set_parent = sam9x60_usb_clk_set_parent,
+	.set_rate = sam9x60_usb_clk_set_rate,
+	.get_rate = sam9x60_usb_clk_get_rate,
+};
+
+struct clk *
+sam9x60_clk_register_usb(void __iomem *base,  const char *name,
+			 const char * const *parent_names, u8 num_parents,
+			 const struct clk_usbck_layout *usbck_layout,
+			 const u32 *clk_mux_table, const u32 *mux_table, u8 id)
+{
+	struct sam9x60_usb *usb;
+	struct clk *clk;
+	int ret;
+	u32 val, index;
+
+	if (!base || !name || !parent_names || !num_parents ||
+	    !clk_mux_table || !mux_table)
+		return ERR_PTR(-EINVAL);
+
+	usb = kzalloc(sizeof(*usb), GFP_KERNEL);
+	if (!usb)
+		return ERR_PTR(-ENOMEM);
+
+	usb->id = id;
+	usb->base = base;
+	usb->layout = usbck_layout;
+	usb->parent_names = parent_names;
+	usb->num_parents = num_parents;
+	usb->clk_mux_table = clk_mux_table;
+	usb->mux_table = mux_table;
+
+	clk = &usb->clk;
+	clk->flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+		     CLK_SET_RATE_PARENT;
+
+	pmc_read(usb->base, usb->layout->offset, &val);
+
+	val = (val & usb->layout->usbs_mask) >>
+		(ffs(usb->layout->usbs_mask) - 1);
+
+	index = at91_clk_mux_val_to_index(usb->mux_table, usb->num_parents,
+					  val);
+
+	if (index < 0) {
+		kfree(usb);
+		return ERR_PTR(index);
+	}
+
+	ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X60_USB, name,
+			   parent_names[index]);
+	if (ret) {
+		kfree(usb);
+		clk = ERR_PTR(ret);
+	}
+
+	return clk;
+}
+
+U_BOOT_DRIVER(at91_sam9x60_usb_clk) = {
+	.name = UBOOT_DM_CLK_AT91_SAM9X60_USB,
+	.id = UCLASS_CLK,
+	.ops = &sam9x60_usb_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 2b4dd9a3d9..17793b8802 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -71,6 +71,12 @@ struct clk_pcr_layout {
 	u32 pid_mask;
 };
 
+struct clk_usbck_layout {
+	u32 offset;
+	u32 usbs_mask;
+	u32 usbdiv_mask;
+};
+
 extern const struct clk_programmable_layout at91rm9200_programmable_layout;
 extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
 extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
@@ -87,6 +93,11 @@ struct clk *at91_clk_sam9x5_main(void __iomem *reg, const char *name,
 			const char * const *parent_names, int num_parents,
 			const u32 *mux_table, int type);
 struct clk *
+sam9x60_clk_register_usb(void __iomem *base,  const char *name,
+			 const char * const *parent_names, u8 num_parents,
+			 const struct clk_usbck_layout *usbck_layout,
+			 const u32 *clk_mux_table, const u32 *mux_table, u8 id);
+struct clk *
 sam9x60_clk_register_div_pll(void __iomem *base, const char *name,
 			const char *parent_name, u8 id,
 			const struct clk_pll_characteristics *characteristics,
-- 
2.34.1

[PATCH v3 03/19] clk: at91: sam9x60: Register the required clocks for USB

[Sergiu Moga]

Register into DM the clocks required to properly enable USB functionality
within the bootloader.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---



v1 -> v2:
- No change


v2 -> v3:
- Remove the no longer required #if CONFIG_IS_ENABLED(AT91_SAM9X60_USB)




 drivers/clk/at91/sam9x60.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index 6b5486c6c9..14c2ffcac1 100644
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -76,6 +76,8 @@ enum pmc_clk_ids {
 	ID_QSPI			= 18,
 
 	ID_MCK_PRES		= 19,
+	ID_USBCK		= 20,
+	ID_UHPCK		= 21,
 
 	ID_MAX,
 };
@@ -99,6 +101,7 @@ static const char *clk_names[] = {
 	[ID_PLL_A_DIV]		= "plla_divpmcck",
 	[ID_MCK_PRES]		= "mck_pres",
 	[ID_MCK_DIV]		= "mck_div",
+	[ID_USBCK]		= "usbck",
 };
 
 /* Fractional PLL output range. */
@@ -171,6 +174,13 @@ static const struct clk_pcr_layout pcr_layout = {
 	.pid_mask = GENMASK(6, 0),
 };
 
+/* USB clock layout */
+static const struct clk_usbck_layout usbck_layout = {
+	.offset = 0x38,
+	.usbs_mask = GENMASK(1, 0),
+	.usbdiv_mask = GENMASK(11, 8),
+};
+
 /**
  * PLL clocks description
  * @n:		clock name
@@ -266,6 +276,7 @@ static const struct {
 	u8 cid;
 } sam9x60_systemck[] = {
 	{ .n = "ddrck",		.p = "mck_div",  .id = 2, .cid = ID_DDR, },
+	{ .n = "uhpck",		.p = "usbck",    .id = 6, .cid = ID_UHPCK },
 	{ .n = "pck0",		.p = "prog0",    .id = 8, .cid = ID_PCK0, },
 	{ .n = "pck1",		.p = "prog1",    .id = 9, .cid = ID_PCK1, },
 	{ .n = "qspick",	.p = "mck_div",  .id = 19, .cid = ID_QSPI, },
@@ -543,6 +554,28 @@ static int sam9x60_clk_probe(struct udevice *dev)
 	}
 	clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV), c);
 
+	/* Register usbck. */
+	p[0] = clk_names[ID_PLL_A_DIV];
+	p[1] = clk_names[ID_PLL_U_DIV];
+	p[2] = clk_names[ID_MAIN_XTAL];
+	m[0] = 0;
+	m[1] = 1;
+	m[2] = 2;
+	cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
+	cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
+	cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_XTAL);
+	prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm,
+			  3, fail);
+	prepare_mux_table(muxallocs, muxallocindex, tmpmux, m, 3, fail);
+	c = sam9x60_clk_register_usb(base, clk_names[ID_USBCK], p, 3,
+				     &usbck_layout, tmpclkmux, tmpmux,
+				     ID_USBCK);
+	if (IS_ERR(c)) {
+		ret = PTR_ERR(c);
+		goto fail;
+	}
+	clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_USBCK), c);
+
 	/* Register programmable clocks. */
 	p[0] = clk_names[ID_MD_SLCK];
 	p[1] = clk_names[ID_TD_SLCK];
-- 
2.34.1

[PATCH v3 04/19] clk: at91: pmc: export clock setup to pmc

[Sergiu Moga]

From: Claudiu Beznea <claudiu.beznea@microchip.com>

Clock setup was intended for setting clocks at boot time on SAMA7G5,
e.g. for root clocks like PLLs, that were used to feed IPs needed alive
in u-boot (e.g. Ethernet clock feed by a PLL). Export this functionality
to all at91 clocks as it may be necessary on other SoCs.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---



v1 -> v2:
- Additional patch, this was not here in v1


v2 -> v3:
- Nothing



 drivers/clk/at91/pmc.c     | 42 +++++++++++++++++++++++++++++++++
 drivers/clk/at91/pmc.h     | 16 +++++++++++++
 drivers/clk/at91/sama7g5.c | 48 +++++---------------------------------
 3 files changed, 64 insertions(+), 42 deletions(-)

diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 270892517a..87d2069d89 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -120,3 +120,45 @@ int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index)
 
 	return table[index];
 }
+
+int at91_clk_setup(const struct pmc_clk_setup *setup, int size)
+{
+	struct clk *c, *parent;
+	int i, ret;
+
+	if (!size)
+		return 0;
+
+	if (!setup)
+		return -EINVAL;
+
+	for (i = 0; i < size; i++) {
+		ret = clk_get_by_id(setup[i].cid, &c);
+		if (ret)
+			return ret;
+
+		if (setup[i].pid) {
+			ret = clk_get_by_id(setup[i].pid, &parent);
+			if (ret)
+				return ret;
+
+			ret = clk_set_parent(c, parent);
+			if (ret)
+				return ret;
+
+			if (setup[i].prate) {
+				ret = clk_set_rate(parent, setup[i].prate);
+				if (ret < 0)
+					return ret;
+			}
+		}
+
+		if (setup[i].rate) {
+			ret = clk_set_rate(c, setup[i].rate);
+			if (ret < 0)
+				return ret;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 17793b8802..ff464522aa 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -77,6 +77,20 @@ struct clk_usbck_layout {
 	u32 usbdiv_mask;
 };
 
+/**
+ * Clock setup description
+ * @cid:	clock id corresponding to clock subsystem
+ * @pid:	parent clock id corresponding to clock subsystem
+ * @rate:	clock rate
+ * @prate:	parent rate
+ */
+struct pmc_clk_setup {
+	unsigned int cid;
+	unsigned int pid;
+	unsigned long rate;
+	unsigned long prate;
+};
+
 extern const struct clk_programmable_layout at91rm9200_programmable_layout;
 extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
 extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
@@ -160,4 +174,6 @@ void pmc_write(void __iomem *base, unsigned int off, unsigned int val);
 void pmc_update_bits(void __iomem *base, unsigned int off, unsigned int mask,
 			unsigned int bits);
 
+int at91_clk_setup(const struct pmc_clk_setup *setup, int size);
+
 #endif
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index d1ec3c82b5..8bd9c14156 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -1070,19 +1070,8 @@ static const struct {
 	},
 };
 
-/**
- * Clock setup description
- * @cid:	clock id corresponding to clock subsystem
- * @pid:	parent clock id corresponding to clock subsystem
- * @rate:	clock rate
- * @prate:	parent rate
- */
-static const struct pmc_clk_setup {
-	unsigned int cid;
-	unsigned int pid;
-	unsigned long rate;
-	unsigned long prate;
-} sama7g5_clk_setup[] = {
+/* Clock setup description */
+static const struct pmc_clk_setup sama7g5_clk_setup[] = {
 	{
 		.cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_FRAC),
 		.rate = 625000000,
@@ -1119,7 +1108,7 @@ static int sama7g5_clk_probe(struct udevice *dev)
 	unsigned int *muxallocs[SAMA7G5_MAX_MUX_ALLOCS];
 	const char *p[10];
 	unsigned int cm[10], m[10], *tmpclkmux, *tmpmux;
-	struct clk clk, *c, *parent;
+	struct clk clk, *c;
 	bool main_osc_bypass;
 	int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j;
 
@@ -1353,34 +1342,9 @@ static int sama7g5_clk_probe(struct udevice *dev)
 	}
 
 	/* Setup clocks. */
-	for (i = 0; i < ARRAY_SIZE(sama7g5_clk_setup); i++) {
-		ret = clk_get_by_id(sama7g5_clk_setup[i].cid, &c);
-		if (ret)
-			goto fail;
-
-		if (sama7g5_clk_setup[i].pid) {
-			ret = clk_get_by_id(sama7g5_clk_setup[i].pid, &parent);
-			if (ret)
-				goto fail;
-
-			ret = clk_set_parent(c, parent);
-			if (ret)
-				goto fail;
-
-			if (sama7g5_clk_setup[i].prate) {
-				ret = clk_set_rate(parent,
-					sama7g5_clk_setup[i].prate);
-				if (ret < 0)
-					goto fail;
-			}
-		}
-
-		if (sama7g5_clk_setup[i].rate) {
-			ret = clk_set_rate(c, sama7g5_clk_setup[i].rate);
-			if (ret < 0)
-				goto fail;
-		}
-	}
+	ret = at91_clk_setup(sama7g5_clk_setup, ARRAY_SIZE(sama7g5_clk_setup));
+	if (ret)
+		goto fail;
 
 	return 0;
 
-- 
2.34.1

[PATCH v3 05/19] clk: at91: sam9x60: Add initial setup of UPLL and USBCK rates

[Sergiu Moga]

In order for some of the functionalities, such as the USB clocks,
to work properly we need some clocks to be properly initialised
at the very beginning of booting.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---

v1 -> v2:
- Adapted according to the additional 04/19 PATCH, now making use of
`at91_clk_setup`



v2 -> v3:
- No change


 drivers/clk/at91/sam9x60.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index 14c2ffcac1..e2f72446d5 100644
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -378,6 +378,31 @@ static const struct {
 	{ .n = "dbgu_gclk",   .id = 47, },
 };
 
+/**
+ * Clock setup description
+ * @cid:	clock id corresponding to clock subsystem
+ * @pid:	parent clock id corresponding to clock subsystem
+ * @rate:	clock rate
+ * @prate:	parent rate
+ */
+static const struct pmc_clk_setup sam9x60_clk_setup[] = {
+	{
+		.cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_FRAC),
+		.rate = 960000000,
+	},
+
+	{
+		.cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV),
+		.rate = 480000000,
+	},
+
+	{
+		.cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_USBCK),
+		.pid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV),
+		.rate = 48000000,
+	},
+};
+
 #define prepare_mux_table(_allocs, _index, _dst, _src, _num, _label)	\
 	do {								\
 		int _i;							\
@@ -668,6 +693,11 @@ static int sam9x60_clk_probe(struct udevice *dev)
 		clk_dm(AT91_TO_CLK_ID(PMC_TYPE_GCK, sam9x60_gck[i].id), c);
 	}
 
+	/* Setup clocks. */
+	ret = at91_clk_setup(sam9x60_clk_setup, ARRAY_SIZE(sam9x60_clk_setup));
+	if (ret)
+		goto fail;
+
 	return 0;
 
 fail:
-- 
2.34.1

[PATCH v3 06/19] usb: ohci-at91: Enable OHCI functionality and register into DM

[Sergiu Moga]

Register the OHCI driver into DM by properly initializing the required
clocks and pins required by the DT node of OHCI. In order for the VBUS
to stay enabled, a `child_pre_probe` method has been added to overcome
the DM core disabling it in `usb_scan_device`: when the generic
`device_probe` method is called, the pinctrl is processed once again,
undoing whatever changes have been made in our driver's probe method.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---



v1 -> v2:
- Move ` #include <asm/arch/clk.h>` below `#if !(CONFIG_IS_ENABLED(DM_USB))` to
avoid implicit declarations warnings/errors


v2 -> v3:
- No change



 drivers/usb/host/ohci-at91.c | 183 +++++++++++++++++++++++++++++++++++
 1 file changed, 183 insertions(+)

diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 9b955c1bd6..8a10a29564 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -5,6 +5,9 @@
  */
 
 #include <common.h>
+
+#if !(CONFIG_IS_ENABLED(DM_USB))
+
 #include <asm/arch/clk.h>
 
 int usb_cpu_init(void)
@@ -62,3 +65,183 @@ int usb_cpu_init_fail(void)
 {
 	return usb_cpu_stop();
 }
+
+#elif CONFIG_IS_ENABLED(DM_GPIO)
+
+#include <clk.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <usb.h>
+#include "ohci.h"
+
+#define AT91_MAX_USBH_PORTS        3
+
+#define at91_for_each_port(index)	\
+		for ((index) = 0; (index) < AT91_MAX_USBH_PORTS; (index)++)
+
+struct at91_usbh_data {
+	enum usb_init_type init_type;
+	struct gpio_desc vbus_pin[AT91_MAX_USBH_PORTS];
+	u8 ports;				/* number of ports on root hub */
+};
+
+struct ohci_at91_priv {
+	struct clk *iclk;
+	struct clk *fclk;
+	struct clk *hclk;
+	bool clocked;
+};
+
+static void at91_start_clock(struct ohci_at91_priv *ohci_at91)
+{
+	if (ohci_at91->clocked)
+		return;
+
+	clk_set_rate(ohci_at91->fclk, 48000000);
+	clk_prepare_enable(ohci_at91->hclk);
+	clk_prepare_enable(ohci_at91->iclk);
+	clk_prepare_enable(ohci_at91->fclk);
+	ohci_at91->clocked = true;
+}
+
+static void at91_stop_clock(struct ohci_at91_priv *ohci_at91)
+{
+	if (!ohci_at91->clocked)
+		return;
+
+	clk_disable_unprepare(ohci_at91->fclk);
+	clk_disable_unprepare(ohci_at91->iclk);
+	clk_disable_unprepare(ohci_at91->hclk);
+	ohci_at91->clocked = false;
+}
+
+static void ohci_at91_set_power(struct at91_usbh_data *pdata, int port,
+				bool enable)
+{
+	if (!dm_gpio_is_valid(&pdata->vbus_pin[port]))
+		return;
+
+	if (enable)
+		dm_gpio_set_dir_flags(&pdata->vbus_pin[port],
+				      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	else
+		dm_gpio_set_dir_flags(&pdata->vbus_pin[port], 0);
+}
+
+static void at91_start_hc(struct udevice *dev)
+{
+	struct ohci_at91_priv *ohci_at91 = dev_get_priv(dev);
+
+	at91_start_clock(ohci_at91);
+}
+
+static void at91_stop_hc(struct udevice *dev)
+{
+	struct ohci_at91_priv *ohci_at91 = dev_get_priv(dev);
+
+	at91_stop_clock(ohci_at91);
+}
+
+static int ohci_atmel_deregister(struct udevice *dev)
+{
+	struct at91_usbh_data *pdata = dev_get_plat(dev);
+	int i;
+
+	at91_stop_hc(dev);
+
+	at91_for_each_port(i) {
+		if (i >= pdata->ports)
+			break;
+
+		ohci_at91_set_power(pdata, i, false);
+	}
+
+	return ohci_deregister(dev);
+}
+
+static int ohci_atmel_child_pre_probe(struct udevice *dev)
+{
+	struct udevice *ohci_controller = dev_get_parent(dev);
+	struct at91_usbh_data *pdata = dev_get_plat(ohci_controller);
+	int i;
+
+	at91_for_each_port(i) {
+		if (i >= pdata->ports)
+			break;
+
+		ohci_at91_set_power(pdata, i, true);
+	}
+
+	return 0;
+}
+
+static int ohci_atmel_probe(struct udevice *dev)
+{
+	struct at91_usbh_data *pdata = dev_get_plat(dev);
+	struct ohci_at91_priv *ohci_at91 = dev_get_priv(dev);
+	int		      i;
+	int		      ret;
+	u32		      ports;
+	struct ohci_regs      *regs = (struct ohci_regs *)dev_read_addr(dev);
+
+	if (!dev_read_u32(dev, "num-ports", &ports))
+		pdata->ports = ports;
+
+	at91_for_each_port(i) {
+		if (i >= pdata->ports)
+			break;
+
+		gpio_request_by_name(dev, "atmel,vbus-gpio", i,
+				     &pdata->vbus_pin[i], GPIOD_IS_OUT |
+				     GPIOD_IS_OUT_ACTIVE);
+	}
+
+	ohci_at91->iclk = devm_clk_get(dev, "ohci_clk");
+	if (IS_ERR(ohci_at91->iclk)) {
+		ret = PTR_ERR(ohci_at91->iclk);
+		goto fail;
+	}
+
+	ohci_at91->fclk = devm_clk_get(dev, "uhpck");
+	if (IS_ERR(ohci_at91->fclk)) {
+		ret = PTR_ERR(ohci_at91->fclk);
+		goto fail;
+	}
+
+	ohci_at91->hclk = devm_clk_get(dev, "hclk");
+	if (IS_ERR(ohci_at91->hclk)) {
+		ret = PTR_ERR(ohci_at91->hclk);
+		goto fail;
+	}
+
+	at91_start_hc(dev);
+
+	return ohci_register(dev, regs);
+
+fail:
+	at91_for_each_port(i)
+		if (&pdata->vbus_pin[i])
+			gpio_free(pdata->vbus_pin[i].offset);
+
+	return ret;
+}
+
+static const struct udevice_id ohci_usb_ids[] = {
+	{ .compatible = "atmel,at91rm9200-ohci", },
+	{ }
+};
+
+U_BOOT_DRIVER(ohci_atmel) = {
+	.name		 = "ohci_atmel",
+	.id		 = UCLASS_USB,
+	.of_match	 = ohci_usb_ids,
+	.probe		 = ohci_atmel_probe,
+	.remove		 = ohci_atmel_deregister,
+	.child_pre_probe = ohci_atmel_child_pre_probe,
+	.ops		 = &ohci_usb_ops,
+	.plat_auto	 = sizeof(struct at91_usbh_data),
+	.priv_auto	 = sizeof(struct ohci_at91_priv),
+	.flags		 = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+#endif /* CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(DM_GPIO) */
-- 
2.34.1

[PATCH v3 07/19] dt-bindings: reset: add sama7g5 definitions

[Sergiu Moga]

Upstream linux commit 5994f58977e0.

Add reset bindings for SAMA7G5. At the moment only USB PHYs are
included.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---


v1 -> v3:
- No change



 include/dt-bindings/reset/sama7g5-reset.h | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 include/dt-bindings/reset/sama7g5-reset.h

diff --git a/include/dt-bindings/reset/sama7g5-reset.h b/include/dt-bindings/reset/sama7g5-reset.h
new file mode 100644
index 0000000000..2116f41d04
--- /dev/null
+++ b/include/dt-bindings/reset/sama7g5-reset.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef __DT_BINDINGS_RESET_SAMA7G5_H
+#define __DT_BINDINGS_RESET_SAMA7G5_H
+
+#define SAMA7G5_RESET_USB_PHY1		4
+#define SAMA7G5_RESET_USB_PHY2		5
+#define SAMA7G5_RESET_USB_PHY3		6
+
+#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */
-- 
2.34.1

[PATCH v3 08/19] dt-bindings: clk: at91: Define additional UTMI related clocks

[Sergiu Moga]

Add definitions for an additional main UTMI clock as well as its
respective subclocks.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---

v1 -> v3:
- No change


 include/dt-bindings/clk/at91.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clk/at91.h
index e30756b280..386f01cf31 100644
--- a/include/dt-bindings/clk/at91.h
+++ b/include/dt-bindings/clk/at91.h
@@ -18,5 +18,10 @@
 #define PMC_TYPE_PERIPHERAL	3
 #define PMC_TYPE_GCK		4
 #define PMC_TYPE_SLOW		5
+#define UTMI			6
+
+#define UTMI1			0
+#define UTMI2			1
+#define UTMI3			2
 
 #endif
-- 
2.34.1

[PATCH v3 09/19] ARM: dts: at91: sama7: Add USB related DT nodes

[Sergiu Moga]

Add the USB related DT nodes for the sama7g5ek board.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---


v1 -> v3:
- No change



 arch/arm/dts/at91-sama7g5ek.dts | 34 +++++++++++++++
 arch/arm/dts/sama7g5.dtsi       | 73 +++++++++++++++++++++++++++++++++
 2 files changed, 107 insertions(+)

diff --git a/arch/arm/dts/at91-sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts
index 9b247fcaf6..31adc4d3e7 100644
--- a/arch/arm/dts/at91-sama7g5ek.dts
+++ b/arch/arm/dts/at91-sama7g5ek.dts
@@ -761,6 +761,11 @@
 		pinmux = <PIN_PB1__SPDIF_TX>;
 		bias-disable;
 	};
+
+	pinctrl_usb_default: usb_default {
+		pinmux = <PIN_PC6__GPIO>;
+		bias-disable;
+	};
 };
 
 &pwm {
@@ -837,6 +842,35 @@
 	status = "okay";
 };
 
+&usb2 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   0
+			   &pioA PIN_PC6 GPIO_ACTIVE_HIGH
+			  >;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_default>;
+	phys = <&usb_phy2>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&usb_phy0 {
+	status = "okay";
+};
+
+&usb_phy1 {
+	status = "okay";
+};
+
+&usb_phy2 {
+	status = "okay";
+};
+
 &vddout25 {
 	vin-supply = <&vdd_3v3>;
 	status = "okay";
diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi
index 6388a60e53..a6521aaa82 100644
--- a/arch/arm/dts/sama7g5.dtsi
+++ b/arch/arm/dts/sama7g5.dtsi
@@ -16,6 +16,8 @@
 #include <dt-bindings/dma/at91.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/mfd/at91-usart.h>
+#include <dt-bindings/reset/sama7g5-reset.h>
+#include <dt-bindings/clock/at91.h>
 
 / {
 	model = "Microchip SAMA7G5 family SoC";
@@ -103,6 +105,54 @@
 		};
 	};
 
+	utmi_clk: utmi-clk {
+		compatible = "microchip,sama7g5-utmi-clk";
+		sfr-phandle = <&sfr>;
+		#clock-cells = <1>;
+		clocks = <&pmc PMC_TYPE_CORE 27>;
+		clock-names = "utmi_clk";
+		resets = <&reset_controller SAMA7G5_RESET_USB_PHY1>,
+			 <&reset_controller SAMA7G5_RESET_USB_PHY2>,
+			 <&reset_controller SAMA7G5_RESET_USB_PHY3>;
+		reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
+	};
+
+	utmi {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb_phy0: phy@0 {
+			compatible = "microchip,sama7g5-usb-phy";
+			sfr-phandle = <&sfr>;
+			reg = <0>;
+			clocks = <&utmi_clk UTMI1>;
+			clock-names = "utmi_clk";
+			status = "disabled";
+			#phy-cells = <0>;
+		};
+
+		usb_phy1: phy@1 {
+			compatible = "microchip,sama7g5-usb-phy";
+			sfr-phandle = <&sfr>;
+			reg = <1>;
+			clocks = <&utmi_clk UTMI2>;
+			clock-names = "utmi_clk";
+			status = "disabled";
+			#phy-cells = <0>;
+		};
+
+		usb_phy2: phy@2 {
+			compatible = "microchip,sama7g5-usb-phy";
+			sfr-phandle = <&sfr>;
+			reg = <2>;
+			clocks = <&utmi_clk UTMI3>;
+			clock-names = "utmi_clk";
+			status = "disabled";
+			#phy-cells = <0>;
+		};
+	};
+
 	vddout25: fixed-regulator-vddout25 {
 		compatible = "regulator-fixed";
 
@@ -127,6 +177,24 @@
 		#size-cells = <1>;
 		ranges;
 
+		usb2: ohci@400000 {
+			compatible = "microchip,sama7g5-ohci", "usb-ohci";
+			reg = <0x00400000 0x100000>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 106>, <&utmi_clk UTMI1>, <&usb_clk>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		usb3: ehci@500000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00500000 0x100000>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>;
+			clock-names = "usb_clk", "ehci_clk";
+			status = "disabled";
+		};
+
 		nfc_sram: sram@600000 {
 			compatible = "mmio-sram";
 			no-memory-wc;
@@ -559,6 +627,11 @@
 			status = "disabled";
 		};
 
+		sfr: sfr@e1624000 {
+			compatible = "microchip,sama7g5-sfr", "syscon";
+			reg = <0xe1624000 0x4000>;
+		};
+
 		eic: interrupt-controller@e1628000 {
 			compatible = "microchip,sama7g5-eic";
 			reg = <0xe1628000 0xec>;
-- 
2.34.1

[PATCH v3 10/19] ARM: at91: add sama7 SFR definitions

[Sergiu Moga]

From: Cristian Birsan <cristian.birsan@microchip.com>

Special Function Registers(SFR) definitions for SAMA7 product family.

Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---



v1 -> v3:
- No change



 arch/arm/mach-at91/include/mach/sama7-sfr.h | 59 +++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 arch/arm/mach-at91/include/mach/sama7-sfr.h

diff --git a/arch/arm/mach-at91/include/mach/sama7-sfr.h b/arch/arm/mach-at91/include/mach/sama7-sfr.h
new file mode 100644
index 0000000000..a987ff5465
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama7-sfr.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Microchip SFR (Special Function Registers) registers for SAMA7 family.
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Cristian Birsan <cristian.birsan@microchip.com>
+ */
+
+#ifndef _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H
+#define _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H
+
+#define SAMA7_SFR_OHCIICR	0x00	/* OHCI INT Configuration Register */
+#define SAMA7_SFR_OHCIISR	0x04	/* OHCI INT Status Register */
+/* 0x08 ~ 0xe3: Reserved */
+#define SAMA7_SFR_WPMR		0xe4	/* Write Protection Mode Register */
+#define SAMA7_SFR_WPSR		0xe4	/* Write Protection Status Register */
+/* 0xec ~ 0x200b: Reserved */
+#define SAMA7_SFR_DEBUG		0x200c	/* Debug Register */
+
+/* 0x2010 ~ 0x2027: Reserved */
+#define SAMA7_SFR_EHCIOHCI	0x2020  /* EHCI OHCI Clock Configuration Reg */
+
+#define SAMA7_SFR_HSS_AXI_QOS	0x2028	/* HSS AXI QOS Register */
+#define SAMA7_SFR_UDDRC		0x202c  /* UDDRC Register */
+#define SAMA7_SFR_CAN_SRAM_SEL	0x2030	/* CAN SRAM Select. Register */
+/* 0x2034 ~ 0x203f: Reserved */
+
+#define SAMA7_SFR_UTMI0		0x2040
+#define SAMA7_SFR_UTMI0R(x)	(SAMA7_SFR_UTMI0 + 4 * (x))
+
+#define SAMA7_SFR_UTMI0R0	0x2040	/* UTMI0 Configuration Register */
+#define SAMA7_SFR_UTMI0R1	0x2044	/* UTMI1 Configuration Register */
+#define SAMA7_SFR_UTMI0R2	0x2048	/* UTMI2 Configuration Register */
+
+/* Field definitions */
+#define SAMA7_SFR_OHCIICR_ARIE			BIT(0)
+#define SAMA7_SFR_OHCIICR_APPSTART		BIT(1)
+#define SAMA7_SFR_OHCIICR_USB_SUSP(x)		BIT(8 + (x))
+#define SAMA7_SFR_OHCIICR_USB_SUSPEND		GENMASK(10, 8)
+
+#define SAMA7_SFR_OHCIISR_RIS(x)		BIT(x)
+
+#define SAMA7_SFR_WPMR_WPEN			BIT(0)
+#define SAMA7_SFR_WPMR_KEY			0x53465200 /* SFR in ASCII*/
+#define SAMA7_SFR_WPMR_WPKEY_MASK		GENMASK(31, 8)
+
+#define SAMA7_SFR_WPSR_WPSRC_MASK		GENMASK(23, 8)
+#define SAMA7_SFR_WPSR_WPVS_MASK		BIT(0)
+
+#define SAMA7_SFR_CAN_SRAM_UPPER(x)		BIT(x)
+
+#define SAMA7_SFR_UTMI_RX_VBUS			BIT(25) /* VBUS Valid bit */
+#define SAMA7_SFR_UTMI_RX_TX_PREEM_AMP_TUNE_1X	BIT(23) /* TXPREEMPAMPTUNE 1x */
+#define SAMA7_SFR_UTMI_COMMONON			BIT(3)  /* PLL Common ON bit */
+
+#define SAMA7_SFR_EHCIOHCI_PHYCLK		BIT(1)  /* Alternate PHY Clk */
+
+#endif /* _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H */
-- 
2.34.1

[PATCH v3 11/19] reset: at91: Add reset driver for basic assert/deassert operations

[Sergiu Moga]

Add support for at91 reset controller's basic assert/deassert
operations. Since this driver conflicts with the
SYSRESET driver because they both bind to the same RSTC node,
implement a custom bind hook that would manually bind the
sysreset driver, if enabled, to the same RSTC DT node.
Furthermore, delete the no longer needed compatibles from the
SYSRESET driver and rename it to make sure than any possible
conflicts are avoided.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Tested-by: Mihai Sain <mihai.sain@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---


v1 -> v3:
- No change


 drivers/reset/Kconfig            |   8 ++
 drivers/reset/Makefile           |   1 +
 drivers/reset/reset-at91.c       | 141 +++++++++++++++++++++++++++++++
 drivers/sysreset/sysreset_at91.c |  10 +--
 4 files changed, 151 insertions(+), 9 deletions(-)
 create mode 100644 drivers/reset/reset-at91.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 4cb0ba0850..e4039d7474 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -211,4 +211,12 @@ config RESET_DRA7
 	help
 	  Support for TI DRA7-RESET subsystem. Basic Assert/Deassert
 	  is supported.
+
+config RESET_AT91
+	bool "Enable support for Microchip/Atmel Reset Controller driver"
+	depends on DM_RESET && ARCH_AT91
+	help
+	  This enables the Reset Controller driver support for Microchip/Atmel
+	  SoCs. Mainly used to expose assert/deassert methods to other drivers
+	  that require it.
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 0620b62809..6c8b45ecba 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
 obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
+obj-$(CONFIG_RESET_AT91) += reset-at91.o
diff --git a/drivers/reset/reset-at91.c b/drivers/reset/reset-at91.c
new file mode 100644
index 0000000000..165c87acdc
--- /dev/null
+++ b/drivers/reset/reset-at91.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support for Atmel/Microchip Reset Controller.
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sergiu Moga <sergiu.moga@microchip.com>
+ */
+
+#include <clk.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <reset-uclass.h>
+#include <asm/arch/at91_rstc.h>
+#include <dt-bindings/reset/sama7g5-reset.h>
+
+struct at91_reset {
+	void __iomem *dev_base;
+	struct at91_reset_data *data;
+};
+
+struct at91_reset_data {
+	u32 n_device_reset;
+	u8 device_reset_min_id;
+	u8 device_reset_max_id;
+};
+
+static const struct at91_reset_data sama7g5_data = {
+	.n_device_reset = 3,
+	.device_reset_min_id = SAMA7G5_RESET_USB_PHY1,
+	.device_reset_max_id = SAMA7G5_RESET_USB_PHY3,
+};
+
+static int at91_rst_update(struct at91_reset *reset, unsigned long id,
+			   bool assert)
+{
+	u32 val;
+
+	if (!reset->dev_base)
+		return 0;
+
+	val = readl(reset->dev_base);
+	if (assert)
+		val |= BIT(id);
+	else
+		val &= ~BIT(id);
+	writel(val, reset->dev_base);
+
+	return 0;
+}
+
+static int at91_reset_of_xlate(struct reset_ctl *reset_ctl,
+			       struct ofnode_phandle_args *args)
+{
+	struct at91_reset *reset = dev_get_priv(reset_ctl->dev);
+
+	if (!reset->data->n_device_reset ||
+	    args->args[0] < reset->data->device_reset_min_id ||
+	    args->args[0] > reset->data->device_reset_max_id)
+		return -EINVAL;
+
+	reset_ctl->id = args->args[0];
+
+	return 0;
+}
+
+static int at91_rst_assert(struct reset_ctl *reset_ctl)
+{
+	struct at91_reset *reset = dev_get_priv(reset_ctl->dev);
+
+	return at91_rst_update(reset, reset_ctl->id, true);
+}
+
+static int at91_rst_deassert(struct reset_ctl *reset_ctl)
+{
+	struct at91_reset *reset = dev_get_priv(reset_ctl->dev);
+
+	return at91_rst_update(reset, reset_ctl->id, false);
+}
+
+struct reset_ops at91_reset_ops = {
+	.of_xlate = at91_reset_of_xlate,
+	.rst_assert = at91_rst_assert,
+	.rst_deassert = at91_rst_deassert,
+};
+
+static int at91_reset_probe(struct udevice *dev)
+{
+	struct at91_reset *reset = dev_get_priv(dev);
+	struct clk sclk;
+	int ret;
+
+	reset->data = (struct at91_reset_data *)dev_get_driver_data(dev);
+	reset->dev_base = dev_remap_addr_index(dev, 1);
+	if (reset->data && reset->data->n_device_reset && !reset->dev_base)
+		return -EINVAL;
+
+	ret = clk_get_by_index(dev, 0, &sclk);
+	if (ret)
+		return ret;
+
+	return clk_prepare_enable(&sclk);
+}
+
+static int at91_reset_bind(struct udevice *dev)
+{
+	struct udevice *at91_sysreset;
+
+	if (CONFIG_IS_ENABLED(SYSRESET_AT91))
+		return device_bind_driver_to_node(dev, "at91_sysreset",
+						  "at91_sysreset",
+						  dev_ofnode(dev),
+						  &at91_sysreset);
+
+	return 0;
+}
+
+static const struct udevice_id at91_reset_ids[] = {
+	{
+		.compatible = "microchip,sama7g5-rstc",
+		.data = (ulong)&sama7g5_data,
+	},
+	{
+		.compatible = "atmel,sama5d3-rstc",
+	},
+	{
+		.compatible = "microchip,sam9x60-rstc",
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(at91_reset) = {
+	.name = "at91_reset",
+	.id = UCLASS_RESET,
+	.of_match = at91_reset_ids,
+	.bind = at91_reset_bind,
+	.probe = at91_reset_probe,
+	.priv_auto = sizeof(struct at91_reset),
+	.ops = &at91_reset_ops,
+};
diff --git a/drivers/sysreset/sysreset_at91.c b/drivers/sysreset/sysreset_at91.c
index 6119a29927..fc85f31ebf 100644
--- a/drivers/sysreset/sysreset_at91.c
+++ b/drivers/sysreset/sysreset_at91.c
@@ -56,17 +56,9 @@ static struct sysreset_ops at91_sysreset = {
 	.request = at91_sysreset_request,
 };
 
-static const struct udevice_id a91_sysreset_ids[] = {
-	{ .compatible = "atmel,sama5d3-rstc" },
-	{ .compatible = "microchip,sam9x60-rstc" },
-	{ .compatible = "microchip,sama7g5-rstc" },
-	{ }
-};
-
 U_BOOT_DRIVER(sysreset_at91) = {
 	.id	= UCLASS_SYSRESET,
-	.name	= "at91_reset",
+	.name	= "at91_sysreset",
 	.ops	= &at91_sysreset,
 	.probe  = at91_sysreset_probe,
-	.of_match = a91_sysreset_ids,
 };
-- 
2.34.1

[PATCH v3 12/19] phy: at91: Add support for the USB 2.0 PHY's of SAMA7

[Sergiu Moga]

In order to have USB functionality, drivers for SAMA7's
USB 2.0 PHY's have been added. There is one driver
for UTMI clock's SFR and RESET required functionalities and
one for its three possible subclocks of the phy's themselves.
In order for this layout to properly work in conjunction with
CCF and DT, the former driver will also act as a clock provider
for the three phy's with the help of a custom hook into the
driver's of_xlate method.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Tested-by: Mihai Sain <mihai.sain@microchip.com>
---

v1 -> v3:
- No change


 drivers/phy/Kconfig              |  10 ++
 drivers/phy/Makefile             |   1 +
 drivers/phy/phy-sama7-usb.c      |  92 ++++++++++++++
 drivers/phy/phy-sama7-utmi-clk.c | 202 +++++++++++++++++++++++++++++++
 4 files changed, 305 insertions(+)
 create mode 100644 drivers/phy/phy-sama7-usb.c
 create mode 100644 drivers/phy/phy-sama7-utmi-clk.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index cf4d5908d7..9fbb956783 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -281,6 +281,16 @@ config PHY_XILINX_ZYNQMP
 	  Enable this to support ZynqMP High Speed Gigabit Transceiver
 	  that is part of ZynqMP SoC.
 
+config PHY_MICROCHIP_SAMA7_USB
+       tristate "Microchip SAMA7 USB 2.0 PHY"
+       depends on PHY && ARCH_AT91
+       help
+	 Enable this to support SAMA7 USB 2.0 PHY.
+
+	 The USB 2.0 PHY integrates high-speed, full-speed and low-speed
+	 termination and signal switching. With a single resistor, it
+	 requires minimal external components.
+
 source "drivers/phy/rockchip/Kconfig"
 source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/ti/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a3b9f3c5b1..9d50affd47 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
 obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
 obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
 obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
+obj-$(CONFIG_PHY_MICROCHIP_SAMA7_USB)  += phy-sama7-utmi-clk.o phy-sama7-usb.o
 obj-y += cadence/
 obj-y += ti/
 obj-y += qcom/
diff --git a/drivers/phy/phy-sama7-usb.c b/drivers/phy/phy-sama7-usb.c
new file mode 100644
index 0000000000..b6fe40ecc1
--- /dev/null
+++ b/drivers/phy/phy-sama7-usb.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support for Atmel/Microchip USB PHY's.
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sergiu Moga <sergiu.moga@microchip.com>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <syscon.h>
+#include <regmap.h>
+#include <mach/sama7-sfr.h>
+
+struct sama7_usb_phy {
+	struct clk *uclk;
+	struct regmap *sfr;
+	int port;
+};
+
+int sama7_usb_phy_init(struct phy *phy)
+{
+	struct sama7_usb_phy *sama7_phy = dev_get_priv(phy->dev);
+	int port = sama7_phy->port;
+
+	regmap_update_bits(sama7_phy->sfr, SAMA7_SFR_UTMI0R(port),
+			   SAMA7_SFR_UTMI_RX_TX_PREEM_AMP_TUNE_1X,
+			   SAMA7_SFR_UTMI_RX_TX_PREEM_AMP_TUNE_1X);
+
+	regmap_update_bits(sama7_phy->sfr, SAMA7_SFR_UTMI0R(port),
+			   SAMA7_SFR_UTMI_RX_VBUS,
+			   SAMA7_SFR_UTMI_RX_VBUS);
+
+	return 0;
+}
+
+int sama7_phy_power_on(struct phy *phy)
+{
+	struct sama7_usb_phy *sama7_phy = dev_get_priv(phy->dev);
+
+	clk_prepare_enable(sama7_phy->uclk);
+
+	return 0;
+}
+
+int sama7_phy_power_off(struct phy *phy)
+{
+	struct sama7_usb_phy *sama7_phy = dev_get_priv(phy->dev);
+
+	clk_disable_unprepare(sama7_phy->uclk);
+
+	return 0;
+}
+
+int sama7_usb_phy_probe(struct udevice *dev)
+{
+	struct sama7_usb_phy *sama7_phy = dev_get_priv(dev);
+
+	sama7_phy->uclk = devm_clk_get(dev, "utmi_clk");
+	if (IS_ERR(sama7_phy->uclk))
+		return PTR_ERR(sama7_phy->uclk);
+
+	sama7_phy->sfr = syscon_regmap_lookup_by_phandle(dev, "sfr-phandle");
+	if (IS_ERR(sama7_phy->sfr)) {
+		sama7_phy->sfr = NULL;
+		return PTR_ERR(sama7_phy->sfr);
+	}
+
+	return dev_read_u32(dev, "reg", &sama7_phy->port);
+}
+
+static const struct phy_ops sama7_usb_phy_ops = {
+	.init = sama7_usb_phy_init,
+	.power_on = sama7_phy_power_on,
+	.power_off = sama7_phy_power_off,
+};
+
+static const struct udevice_id sama7_usb_phy_of_match[] = {
+	{ .compatible = "microchip,sama7g5-usb-phy", },
+	{ },
+};
+
+U_BOOT_DRIVER(sama7_usb_phy_driver) = {
+	.name = "sama7-usb-phy",
+	.id = UCLASS_PHY,
+	.of_match = sama7_usb_phy_of_match,
+	.ops = &sama7_usb_phy_ops,
+	.probe = sama7_usb_phy_probe,
+	.priv_auto = sizeof(struct sama7_usb_phy),
+};
diff --git a/drivers/phy/phy-sama7-utmi-clk.c b/drivers/phy/phy-sama7-utmi-clk.c
new file mode 100644
index 0000000000..ab9fddccf6
--- /dev/null
+++ b/drivers/phy/phy-sama7-utmi-clk.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support for Atmel/Microchip USB PHY's.
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sergiu Moga <sergiu.moga@microchip.com>
+ */
+
+#include <dm.h>
+#include <linux/clk-provider.h>
+#include <syscon.h>
+#include <regmap.h>
+#include <mach/sama7-sfr.h>
+#include <reset.h>
+#include <dt-bindings/clk/at91.h>
+
+struct sama7_utmi_clk {
+	struct clk		uclk;
+	struct regmap		*regmap_sfr;
+	struct reset_ctl	*reset;
+	u8 id;
+};
+
+#define to_sama7_utmi_clk(_c) container_of(_c, struct sama7_utmi_clk, uclk)
+
+#define UBOOT_DM_CLK_MICROCHIP_SAMA7G5_UTMI "sama7-utmi-clk"
+#define UBOOT_DM_MICROCHIP_SAMA7G5_UTMI "sama7-utmi"
+
+#define AT91_TO_CLK_ID(_t, _i)		(((_t) << 8) | ((_i) & 0xff))
+
+/*
+ * UTMI clock description
+ * @n:	clock name
+ * @p:	clock parent name
+ * @id: clock id in RSTC_GRSTR
+ */
+static struct {
+	const char *n;
+	const char *p;
+	u8 id;
+} sama7_utmick[] = {
+	{ .n = "utmi1",	.p = "utmick", .id = 0, },
+	{ .n = "utmi2",	.p = "utmi1",  .id = 1, },
+	{ .n = "utmi3",	.p = "utmi1",  .id = 2, },
+};
+
+static int sama7_utmi_clk_enable(struct clk *clk)
+{
+	int ret;
+
+	struct sama7_utmi_clk *utmi = to_sama7_utmi_clk(clk);
+	u8 id = utmi->id;
+
+	ret = reset_assert(utmi->reset);
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(utmi->regmap_sfr, SAMA7_SFR_UTMI0R(id),
+				 SAMA7_SFR_UTMI_COMMONON, 0);
+	if (ret < 0)
+		return ret;
+
+	ret = reset_deassert(utmi->reset);
+	if (ret)
+		return ret;
+
+	/* Datasheet states a minimum of 45 us before any USB operation */
+	udelay(50);
+
+	return 0;
+}
+
+static int sama7_utmi_clk_disable(struct clk *clk)
+{
+	int ret;
+	struct sama7_utmi_clk *utmi = to_sama7_utmi_clk(clk);
+	u8 id = utmi->id;
+
+	ret = reset_assert(utmi->reset);
+	if (ret)
+		return ret;
+
+	regmap_update_bits(utmi->regmap_sfr, SAMA7_SFR_UTMI0R(id),
+			   SAMA7_SFR_UTMI_COMMONON, SAMA7_SFR_UTMI_COMMONON);
+
+	return 0;
+}
+
+static ulong sama7_utmi_clk_get_rate(struct clk *clk)
+{
+	/* Return utmick's rate: 480MHz */
+	return clk_get_parent_rate(clk);
+}
+
+static const struct clk_ops sama7_utmi_clk_ops = {
+	.enable = sama7_utmi_clk_enable,
+	.disable = sama7_utmi_clk_disable,
+	.get_rate = sama7_utmi_clk_get_rate,
+};
+
+static struct clk*
+sama7_utmi_clk_register(struct regmap *regmap_sfr, struct reset_ctl *reset,
+			const char *name, const char *parent_name, u8 id)
+{
+	struct clk *clk;
+	struct sama7_utmi_clk *utmi_clk;
+	int ret;
+
+	if (!regmap_sfr || !reset || !name || !parent_name)
+		return ERR_PTR(-EINVAL);
+
+	utmi_clk = kzalloc(sizeof(*utmi_clk), GFP_KERNEL);
+	if (!utmi_clk)
+		return ERR_PTR(-ENOMEM);
+
+	utmi_clk->reset = reset;
+	utmi_clk->regmap_sfr = regmap_sfr;
+	utmi_clk->id = id;
+
+	clk = &utmi_clk->uclk;
+	ret = clk_register(clk, UBOOT_DM_CLK_MICROCHIP_SAMA7G5_UTMI,
+			   name, parent_name);
+	if (ret) {
+		kfree(utmi_clk);
+		clk = ERR_PTR(ret);
+	}
+
+	clk_dm(AT91_TO_CLK_ID(UTMI, utmi_clk->id), clk);
+
+	return clk;
+}
+
+static int sama7_utmi_probe(struct udevice *dev)
+{
+	struct clk *utmi_parent_clk, *utmi_clk;
+	struct regmap *regmap_sfr;
+	struct reset_ctl *phy_reset;
+	int i;
+	char name[16];
+
+	utmi_parent_clk = devm_clk_get(dev, "utmi_clk");
+	if (IS_ERR(utmi_parent_clk))
+		return PTR_ERR(utmi_parent_clk);
+
+	regmap_sfr = syscon_regmap_lookup_by_phandle(dev, "sfr-phandle");
+	if (IS_ERR(regmap_sfr))
+		return PTR_ERR(regmap_sfr);
+
+	for (i = 0; i < ARRAY_SIZE(sama7_utmick); i++) {
+		snprintf(name, sizeof(name), "usb%d_reset", i);
+		phy_reset = devm_reset_control_get(dev, name);
+		if (IS_ERR(phy_reset))
+			return PTR_ERR(phy_reset);
+
+		utmi_clk = sama7_utmi_clk_register(regmap_sfr, phy_reset,
+						   sama7_utmick[i].n,
+						   sama7_utmick[i].p,
+						   sama7_utmick[i].id);
+		if (IS_ERR(utmi_clk))
+			return PTR_ERR(utmi_clk);
+	}
+
+	return 0;
+};
+
+static const struct udevice_id sama7_utmi_clk_dt_ids[] = {
+	{ .compatible = "microchip,sama7g5-utmi-clk", },
+	{ /* sentinel */},
+};
+
+static int utmi_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	if (args->args_count != 1) {
+		debug("UTMI: clk: Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	clk->id = AT91_TO_CLK_ID(UTMI, args->args[0]);
+
+	return 0;
+}
+
+static const struct clk_ops sama7_utmi_ops = {
+	.of_xlate	= utmi_clk_of_xlate,
+	.enable		= ccf_clk_enable,
+	.disable	= ccf_clk_disable,
+};
+
+U_BOOT_DRIVER(microhip_sama7g5_utmi_clk) = {
+	.name = UBOOT_DM_CLK_MICROCHIP_SAMA7G5_UTMI,
+	.id = UCLASS_CLK,
+	.ops = &sama7_utmi_clk_ops,
+};
+
+U_BOOT_DRIVER(microhip_sama7g5_utmi) = {
+	.name = UBOOT_DM_MICROCHIP_SAMA7G5_UTMI,
+	.of_match = sama7_utmi_clk_dt_ids,
+	.id = UCLASS_CLK,
+	.ops = &sama7_utmi_ops,
+	.probe = sama7_utmi_probe,
+};
-- 
2.34.1

[PATCH v3 13/19] usb: ohci-at91: Add USB PHY functionality

[Sergiu Moga]

Add the ability to enable/disable whatever USB PHY's are
passed to the AT91 OHCI driver through DT.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Tested-by: Mihai Sain <mihai.sain@microchip.com>
---



v1 -> v3:
- No change



 drivers/usb/host/ohci-at91.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 8a10a29564..4b1aff4127 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -74,6 +74,10 @@ int usb_cpu_init_fail(void)
 #include <usb.h>
 #include "ohci.h"
 
+#if CONFIG_IS_ENABLED(PHY_MICROCHIP_SAMA7_USB)
+#include <generic-phy.h>
+#endif
+
 #define AT91_MAX_USBH_PORTS        3
 
 #define at91_for_each_port(index)	\
@@ -90,6 +94,10 @@ struct ohci_at91_priv {
 	struct clk *fclk;
 	struct clk *hclk;
 	bool clocked;
+
+#if CONFIG_IS_ENABLED(PHY_MICROCHIP_SAMA7_USB)
+	struct phy phy[AT91_MAX_USBH_PORTS];
+#endif
 };
 
 static void at91_start_clock(struct ohci_at91_priv *ohci_at91)
@@ -97,6 +105,13 @@ static void at91_start_clock(struct ohci_at91_priv *ohci_at91)
 	if (ohci_at91->clocked)
 		return;
 
+#if CONFIG_IS_ENABLED(PHY_MICROCHIP_SAMA7_USB)
+	int i;
+
+	at91_for_each_port(i)
+		generic_phy_power_on(&ohci_at91->phy[i]);
+#endif
+
 	clk_set_rate(ohci_at91->fclk, 48000000);
 	clk_prepare_enable(ohci_at91->hclk);
 	clk_prepare_enable(ohci_at91->iclk);
@@ -109,6 +124,13 @@ static void at91_stop_clock(struct ohci_at91_priv *ohci_at91)
 	if (!ohci_at91->clocked)
 		return;
 
+#if CONFIG_IS_ENABLED(PHY_MICROCHIP_SAMA7_USB)
+	int i;
+
+	at91_for_each_port(i)
+		generic_phy_power_off(&ohci_at91->phy[i]);
+#endif
+
 	clk_disable_unprepare(ohci_at91->fclk);
 	clk_disable_unprepare(ohci_at91->iclk);
 	clk_disable_unprepare(ohci_at91->hclk);
@@ -214,6 +236,14 @@ static int ohci_atmel_probe(struct udevice *dev)
 		goto fail;
 	}
 
+#if CONFIG_IS_ENABLED(PHY_MICROCHIP_SAMA7_USB)
+	at91_for_each_port(i) {
+		generic_phy_get_by_index(dev, i, &ohci_at91->phy[i]);
+		generic_phy_init(&ohci_at91->phy[i]);
+		generic_phy_configure(&ohci_at91->phy[i], NULL);
+	}
+#endif
+
 	at91_start_hc(dev);
 
 	return ohci_register(dev, regs);
@@ -228,6 +258,7 @@ fail:
 
 static const struct udevice_id ohci_usb_ids[] = {
 	{ .compatible = "atmel,at91rm9200-ohci", },
+	{ .compatible = "microchip,sama7g5-ohci", },
 	{ }
 };
 
-- 
2.34.1

[PATCH v3 14/19] ARM: dts: at91: sama5d2_icp: Add pinctrl nodes for USB related DT nodes

[Sergiu Moga]

Add the pinctrl subnodes required by the USB related DT nodes.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---


v1 -> v3:
- No change



 arch/arm/dts/at91-sama5d2_icp.dts | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts
index 2dffae9c5c..4f796c6c94 100644
--- a/arch/arm/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/dts/at91-sama5d2_icp.dts
@@ -154,7 +154,29 @@
 						 <PIN_PA13__SDMMC0_CD>;
 					bias-disable;
 				};
+
+				pinctrl_usb_default: usb_default {
+					pinmux = <PIN_PC17__GPIO>;
+					bias-disable;
+				};
+
+				pinctrl_usba_vbus: usba_vbus {
+					pinmux = <PIN_PD23__GPIO>;
+					bias-disable;
+				};
 			};
 		};
 	};
 };
+
+&usb1 {
+	num-ports = <3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_default>;
+	status = "okay";
+};
+
+&usb2 {
+	phy_type = "hsic";
+	status = "okay";
+};
-- 
2.34.1

[PATCH v3 15/19] ARM: dts: at91: sama5d27_wlsom1_ek: Add pinctrl nodes for USB DT nodes

[Sergiu Moga]

Add the pinctrl nodes required by the USB related DT nodes.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---




v1 -> v3:
- No change



 arch/arm/dts/at91-sama5d27_wlsom1_ek.dts | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
index eec183d5de..6d4b35ea96 100644
--- a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
+++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
@@ -143,7 +143,32 @@
 					pinmux = <PIN_PC9__GPIO>;
 					bias-pull-up;
 				};
+
+				pinctrl_usb_default: usb_default {
+					pinmux = <PIN_PA10__GPIO>;
+					bias-disable;
+				};
+
+				pinctrl_usba_vbus: usba_vbus {
+					pinmux = <PIN_PA16__GPIO>;
+					bias-disable;
+				};
 			};
 		};
 	};
 };
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   &pioA PIN_PA10 GPIO_ACTIVE_HIGH
+			   0
+			  >;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_default>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
-- 
2.34.1

[PATCH v3 16/19] configs: at91: sam9x60ek: Add required configs for the USB command

[Sergiu Moga]

Add the configs required to use the USB-related functionalities within
the bootloader.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---


v1 -> v2:
- No change


v2 -> v3:
- Also add USB Mass Storage on SAM9X60 Curiosity
- Add CONFIG_RESET_AT91 to enable RSTC



 configs/sam9x60_curiosity_mmc_defconfig | 8 ++++++++
 configs/sam9x60ek_mmc_defconfig         | 9 +++++++++
 configs/sam9x60ek_nandflash_defconfig   | 9 +++++++++
 configs/sam9x60ek_qspiflash_defconfig   | 9 +++++++++
 4 files changed, 35 insertions(+)

diff --git a/configs/sam9x60_curiosity_mmc_defconfig b/configs/sam9x60_curiosity_mmc_defconfig
index 732b5adf26..a09e01c197 100644
--- a/configs/sam9x60_curiosity_mmc_defconfig
+++ b/configs/sam9x60_curiosity_mmc_defconfig
@@ -37,6 +37,7 @@ CONFIG_CMD_DM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
@@ -54,6 +55,7 @@ CONFIG_CLK_CCF=y
 CONFIG_CLK_AT91=y
 CONFIG_AT91_GENERIC_CLK=y
 CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_AT91_SAM9X60_USB=y
 CONFIG_CPU=y
 CONFIG_AT91_GPIO=y
 CONFIG_DM_I2C=y
@@ -66,11 +68,17 @@ CONFIG_PHY_MICREL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_TIMER=y
 CONFIG_MCHP_PIT64B_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ATMEL=y
+CONFIG_USB_STORAGE=y
 CONFIG_W1=y
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig
index 268a485456..f703f5f39b 100644
--- a/configs/sam9x60ek_mmc_defconfig
+++ b/configs/sam9x60ek_mmc_defconfig
@@ -40,6 +40,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
@@ -59,6 +60,7 @@ CONFIG_CLK_CCF=y
 CONFIG_CLK_AT91=y
 CONFIG_AT91_GENERIC_CLK=y
 CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_AT91_SAM9X60_USB=y
 CONFIG_CPU=y
 CONFIG_AT91_GPIO=y
 CONFIG_DM_I2C=y
@@ -85,6 +87,8 @@ CONFIG_PHY_MICREL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -95,6 +99,11 @@ CONFIG_SYSRESET=y
 CONFIG_SYSRESET_AT91=y
 CONFIG_TIMER=y
 CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
+CONFIG_USB_STORAGE=y
 CONFIG_W1=y
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig
index a9cbb6e953..ff653090f7 100644
--- a/configs/sam9x60ek_nandflash_defconfig
+++ b/configs/sam9x60ek_nandflash_defconfig
@@ -41,6 +41,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
@@ -61,6 +62,7 @@ CONFIG_CLK_CCF=y
 CONFIG_CLK_AT91=y
 CONFIG_AT91_GENERIC_CLK=y
 CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_AT91_SAM9X60_USB=y
 CONFIG_CPU=y
 CONFIG_AT91_GPIO=y
 CONFIG_DM_I2C=y
@@ -87,6 +89,8 @@ CONFIG_PHY_MICREL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -97,6 +101,11 @@ CONFIG_SYSRESET=y
 CONFIG_SYSRESET_AT91=y
 CONFIG_TIMER=y
 CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
+CONFIG_USB_STORAGE=y
 CONFIG_W1=y
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig
index 72f08f1375..3e8277e39a 100644
--- a/configs/sam9x60ek_qspiflash_defconfig
+++ b/configs/sam9x60ek_qspiflash_defconfig
@@ -41,6 +41,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
@@ -61,6 +62,7 @@ CONFIG_CLK_CCF=y
 CONFIG_CLK_AT91=y
 CONFIG_AT91_GENERIC_CLK=y
 CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_AT91_SAM9X60_USB=y
 CONFIG_CPU=y
 CONFIG_AT91_GPIO=y
 CONFIG_DM_I2C=y
@@ -86,6 +88,8 @@ CONFIG_PHY_MICREL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -96,6 +100,11 @@ CONFIG_SYSRESET=y
 CONFIG_SYSRESET_AT91=y
 CONFIG_TIMER=y
 CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
+CONFIG_USB_STORAGE=y
 CONFIG_W1=y
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
-- 
2.34.1

[PATCH v3 17/19] configs: at91: sama5d2: Enable OHCI/EHCI related configs

[Sergiu Moga]

Enable the OHCI and EHCI related configs required in order to be
able to use the USB command properly.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---



v1 -> v2:
- No change


v2 -> v3:
- Also add CONFIG_RESET_AT91 to enable RSTC



 configs/sama5d27_giantboard_defconfig          | 4 ++++
 configs/sama5d27_som1_ek_mmc1_defconfig        | 4 ++++
 configs/sama5d27_som1_ek_mmc_defconfig         | 4 ++++
 configs/sama5d27_som1_ek_qspiflash_defconfig   | 4 ++++
 configs/sama5d27_wlsom1_ek_mmc_defconfig       | 5 +++++
 configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 4 ++++
 configs/sama5d2_icp_mmc_defconfig              | 8 ++++++++
 configs/sama5d2_icp_qspiflash_defconfig        | 4 ++++
 configs/sama5d2_ptc_ek_mmc_defconfig           | 4 ++++
 configs/sama5d2_ptc_ek_nandflash_defconfig     | 4 ++++
 configs/sama5d2_xplained_emmc_defconfig        | 4 ++++
 configs/sama5d2_xplained_mmc_defconfig         | 4 ++++
 configs/sama5d2_xplained_qspiflash_defconfig   | 4 ++++
 configs/sama5d2_xplained_spiflash_defconfig    | 4 ++++
 14 files changed, 61 insertions(+)

diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig
index d08a42d911..d33b886116 100644
--- a/configs/sama5d27_giantboard_defconfig
+++ b/configs/sama5d27_giantboard_defconfig
@@ -81,6 +81,8 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -95,6 +97,8 @@ CONFIG_ATMEL_PIT_TIMER=y
 CONFIG_SPL_ATMEL_PIT_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index 93ae714b62..a1f17e0f16 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -93,6 +93,8 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -108,6 +110,8 @@ CONFIG_ATMEL_PIT_TIMER=y
 CONFIG_SPL_ATMEL_PIT_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index 5096366de7..67deb04af2 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -93,6 +93,8 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -108,6 +110,8 @@ CONFIG_ATMEL_PIT_TIMER=y
 CONFIG_SPL_ATMEL_PIT_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
index d7c7f42c93..265c1df32c 100644
--- a/configs/sama5d27_som1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -92,6 +92,8 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -107,6 +109,8 @@ CONFIG_ATMEL_PIT_TIMER=y
 CONFIG_SPL_ATMEL_PIT_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index 7634a6c68f..3aa2dfda8f 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -56,6 +56,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
@@ -98,6 +99,8 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -113,6 +116,8 @@ CONFIG_ATMEL_PIT_TIMER=y
 CONFIG_SPL_ATMEL_PIT_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
index bb018d4c69..9a5b98df92 100644
--- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
@@ -102,6 +102,8 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -117,6 +119,8 @@ CONFIG_ATMEL_PIT_TIMER=y
 CONFIG_SPL_ATMEL_PIT_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index 51f7104b35..f7646cce50 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -58,6 +58,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
@@ -97,6 +98,8 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -110,5 +113,10 @@ CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_ATMEL_TCB_TIMER=y
 CONFIG_SPL_ATMEL_TCB_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
+CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER_HII is not set
diff --git a/configs/sama5d2_icp_qspiflash_defconfig b/configs/sama5d2_icp_qspiflash_defconfig
index ab7308848f..b36dfb3bdb 100644
--- a/configs/sama5d2_icp_qspiflash_defconfig
+++ b/configs/sama5d2_icp_qspiflash_defconfig
@@ -83,6 +83,8 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -95,6 +97,8 @@ CONFIG_TIMER=y
 CONFIG_ATMEL_PIT_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig
index 8ae20d5a76..c0cdd48dc0 100644
--- a/configs/sama5d2_ptc_ek_mmc_defconfig
+++ b/configs/sama5d2_ptc_ek_mmc_defconfig
@@ -68,6 +68,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -77,6 +79,8 @@ CONFIG_TIMER=y
 CONFIG_ATMEL_TCB_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_W1=y
 CONFIG_W1_GPIO=y
diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig
index f987278101..28f8c676c0 100644
--- a/configs/sama5d2_ptc_ek_nandflash_defconfig
+++ b/configs/sama5d2_ptc_ek_nandflash_defconfig
@@ -68,6 +68,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -77,6 +79,8 @@ CONFIG_TIMER=y
 CONFIG_ATMEL_TCB_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_W1=y
 CONFIG_W1_GPIO=y
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index 9509091c4e..fd67f0d09b 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -92,6 +92,8 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -107,6 +109,8 @@ CONFIG_ATMEL_TCB_TIMER=y
 CONFIG_SPL_ATMEL_TCB_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index fe267f33e2..e7a79afc4c 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -94,6 +94,8 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -109,6 +111,8 @@ CONFIG_ATMEL_TCB_TIMER=y
 CONFIG_SPL_ATMEL_TCB_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
index 7fc5dad631..17d05b44b0 100644
--- a/configs/sama5d2_xplained_qspiflash_defconfig
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -94,6 +94,8 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -109,6 +111,8 @@ CONFIG_ATMEL_TCB_TIMER=y
 CONFIG_SPL_ATMEL_TCB_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 95e2b449f9..79b18604d4 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -98,6 +98,8 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -113,6 +115,8 @@ CONFIG_ATMEL_TCB_TIMER=y
 CONFIG_SPL_ATMEL_TCB_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
-- 
2.34.1

[PATCH v3 18/19] configs: at91: sama7: Enable USB and RESET functionality

[Sergiu Moga]

Enable USB and RESET functionality. In order for USB to
work properly on SAMA7, the driver needs to be able
to have access to PHY's, which, in turn, need to have
access to the RSTC driver's assert/deassert functionalities.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Tested-by: Mihai Sain <mihai.sain@microchip.com>
---



v1 -> v3:
- No change




 configs/sama7g5ek_mmc1_defconfig | 10 ++++++++++
 configs/sama7g5ek_mmc_defconfig  | 10 ++++++++++
 2 files changed, 20 insertions(+)

diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig
index f004e44803..6c92781e60 100644
--- a/configs/sama7g5ek_mmc1_defconfig
+++ b/configs/sama7g5ek_mmc1_defconfig
@@ -38,6 +38,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -68,8 +69,12 @@ CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_MACB=y
+CONFIG_PHY=y
+CONFIG_PHY_MICROCHIP_SAMA7_USB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -77,5 +82,10 @@ CONFIG_SYSRESET=y
 CONFIG_SYSRESET_AT91=y
 CONFIG_TIMER=y
 CONFIG_MCHP_PIT64B_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
+CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER_HII is not set
diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig
index 5b42fc63f3..a4e57c7ba5 100644
--- a/configs/sama7g5ek_mmc_defconfig
+++ b/configs/sama7g5ek_mmc_defconfig
@@ -38,6 +38,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -68,8 +69,12 @@ CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_MACB=y
+CONFIG_PHY=y
+CONFIG_PHY_MICROCHIP_SAMA7_USB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
@@ -77,5 +82,10 @@ CONFIG_SYSRESET=y
 CONFIG_SYSRESET_AT91=y
 CONFIG_TIMER=y
 CONFIG_MCHP_PIT64B_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ATMEL=y
+CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER_HII is not set
-- 
2.34.1

[PATCH v3 19/19] usb: ohci-at91: Add `ohci_t` field in `ohci_at91_priv`

[Sergiu Moga]

From: Cristian Birsan <cristian.birsan@microchip.com>

The `ohci_register` function expects that the OHCI driver's
priv is a struct whose first field is of type `ohci_t`.
The original conversion to DM did not have it and this
inconsistency revealed itself whenever U-Boot required
multiple memory allocations resulting in a memory overwrite
of where this field would supposedly be.

Thus, add this missing field and automatically increase
the implicit size of the driver's priv to avoid whatever
future memory allocations may take place from overwriting
it.

Fixes: de1cf0a9c6 ("drivers: usb: ohci-at91: Enable OHCI functionality and register into DM")
Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Tested-by: Mihai Sain <mihai.sain@microchip.com>
---


v1 -> v3:
- No change



 drivers/usb/host/ohci-at91.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 4b1aff4127..0791769026 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -90,6 +90,7 @@ struct at91_usbh_data {
 };
 
 struct ohci_at91_priv {
+	ohci_t ohci;
 	struct clk *iclk;
 	struct clk *fclk;
 	struct clk *hclk;
-- 
2.34.1

Re: [PATCH v3 12/19] phy: at91: Add support for the USB 2.0 PHY's of SAMA7

[Claudiu.Beznea]

On 12.12.2022 15:39, Sergiu Moga wrote:
> In order to have USB functionality, drivers for SAMA7's
> USB 2.0 PHY's have been added. There is one driver
> for UTMI clock's SFR and RESET required functionalities and
> one for its three possible subclocks of the phy's themselves.
> In order for this layout to properly work in conjunction with
> CCF and DT, the former driver will also act as a clock provider
> for the three phy's with the help of a custom hook into the
> driver's of_xlate method.
> 
> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
> Tested-by: Mihai Sain <mihai.sain@microchip.com>
> ---
> 
> v1 -> v3:
> - No change
> 
> 
>  drivers/phy/Kconfig              |  10 ++
>  drivers/phy/Makefile             |   1 +
>  drivers/phy/phy-sama7-usb.c      |  92 ++++++++++++++
>  drivers/phy/phy-sama7-utmi-clk.c | 202 +++++++++++++++++++++++++++++++
>  4 files changed, 305 insertions(+)
>  create mode 100644 drivers/phy/phy-sama7-usb.c
>  create mode 100644 drivers/phy/phy-sama7-utmi-clk.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index cf4d5908d7..9fbb956783 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -281,6 +281,16 @@ config PHY_XILINX_ZYNQMP
>  	  Enable this to support ZynqMP High Speed Gigabit Transceiver
>  	  that is part of ZynqMP SoC.
>  
> +config PHY_MICROCHIP_SAMA7_USB
> +       tristate "Microchip SAMA7 USB 2.0 PHY"
> +       depends on PHY && ARCH_AT91
> +       help
> +	 Enable this to support SAMA7 USB 2.0 PHY.
> +
> +	 The USB 2.0 PHY integrates high-speed, full-speed and low-speed
> +	 termination and signal switching. With a single resistor, it
> +	 requires minimal external components.
> +
>  source "drivers/phy/rockchip/Kconfig"
>  source "drivers/phy/cadence/Kconfig"
>  source "drivers/phy/ti/Kconfig"
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a3b9f3c5b1..9d50affd47 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -38,6 +38,7 @@ obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
>  obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
>  obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
>  obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
> +obj-$(CONFIG_PHY_MICROCHIP_SAMA7_USB)  += phy-sama7-utmi-clk.o phy-sama7-usb.o
>  obj-y += cadence/
>  obj-y += ti/
>  obj-y += qcom/
> diff --git a/drivers/phy/phy-sama7-usb.c b/drivers/phy/phy-sama7-usb.c
> new file mode 100644
> index 0000000000..b6fe40ecc1
> --- /dev/null
> +++ b/drivers/phy/phy-sama7-usb.c
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Support for Atmel/Microchip USB PHY's.
> + *
> + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Sergiu Moga <sergiu.moga@microchip.com>
> + */
> +
> +#include <clk.h>
> +#include <dm.h>
> +#include <generic-phy.h>
> +#include <syscon.h>
> +#include <regmap.h>
> +#include <mach/sama7-sfr.h>
> +
> +struct sama7_usb_phy {
> +	struct clk *uclk;
> +	struct regmap *sfr;
> +	int port;
> +};
> +
> +int sama7_usb_phy_init(struct phy *phy)
> +{
> +	struct sama7_usb_phy *sama7_phy = dev_get_priv(phy->dev);
> +	int port = sama7_phy->port;
> +
> +	regmap_update_bits(sama7_phy->sfr, SAMA7_SFR_UTMI0R(port),
> +			   SAMA7_SFR_UTMI_RX_TX_PREEM_AMP_TUNE_1X,
> +			   SAMA7_SFR_UTMI_RX_TX_PREEM_AMP_TUNE_1X);
> +
> +	regmap_update_bits(sama7_phy->sfr, SAMA7_SFR_UTMI0R(port),
> +			   SAMA7_SFR_UTMI_RX_VBUS,
> +			   SAMA7_SFR_UTMI_RX_VBUS);
> +
> +	return 0;
> +}
> +
> +int sama7_phy_power_on(struct phy *phy)
> +{
> +	struct sama7_usb_phy *sama7_phy = dev_get_priv(phy->dev);
> +
> +	clk_prepare_enable(sama7_phy->uclk);
> +
> +	return 0;
> +}
> +
> +int sama7_phy_power_off(struct phy *phy)
> +{
> +	struct sama7_usb_phy *sama7_phy = dev_get_priv(phy->dev);
> +
> +	clk_disable_unprepare(sama7_phy->uclk);
> +
> +	return 0;
> +}
> +
> +int sama7_usb_phy_probe(struct udevice *dev)
> +{
> +	struct sama7_usb_phy *sama7_phy = dev_get_priv(dev);
> +
> +	sama7_phy->uclk = devm_clk_get(dev, "utmi_clk");
> +	if (IS_ERR(sama7_phy->uclk))
> +		return PTR_ERR(sama7_phy->uclk);
> +
> +	sama7_phy->sfr = syscon_regmap_lookup_by_phandle(dev, "sfr-phandle");
> +	if (IS_ERR(sama7_phy->sfr)) {
> +		sama7_phy->sfr = NULL;

Is this needed?

> +		return PTR_ERR(sama7_phy->sfr);
> +	}
> +
> +	return dev_read_u32(dev, "reg", &sama7_phy->port);
> +}
> +
> +static const struct phy_ops sama7_usb_phy_ops = {
> +	.init = sama7_usb_phy_init,
> +	.power_on = sama7_phy_power_on,
> +	.power_off = sama7_phy_power_off,
> +};
> +
> +static const struct udevice_id sama7_usb_phy_of_match[] = {
> +	{ .compatible = "microchip,sama7g5-usb-phy", },
> +	{ },
> +};
> +
> +U_BOOT_DRIVER(sama7_usb_phy_driver) = {
> +	.name = "sama7-usb-phy",
> +	.id = UCLASS_PHY,
> +	.of_match = sama7_usb_phy_of_match,
> +	.ops = &sama7_usb_phy_ops,
> +	.probe = sama7_usb_phy_probe,
> +	.priv_auto = sizeof(struct sama7_usb_phy),
> +};
> diff --git a/drivers/phy/phy-sama7-utmi-clk.c b/drivers/phy/phy-sama7-utmi-clk.c
> new file mode 100644
> index 0000000000..ab9fddccf6
> --- /dev/null
> +++ b/drivers/phy/phy-sama7-utmi-clk.c
> @@ -0,0 +1,202 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Support for Atmel/Microchip USB PHY's.
> + *
> + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Sergiu Moga <sergiu.moga@microchip.com>
> + */
> +
> +#include <dm.h>
> +#include <linux/clk-provider.h>
> +#include <syscon.h>
> +#include <regmap.h>
> +#include <mach/sama7-sfr.h>
> +#include <reset.h>
> +#include <dt-bindings/clk/at91.h>
> +
> +struct sama7_utmi_clk {
> +	struct clk		uclk;
> +	struct regmap		*regmap_sfr;
> +	struct reset_ctl	*reset;
> +	u8 id;
> +};
> +
> +#define to_sama7_utmi_clk(_c) container_of(_c, struct sama7_utmi_clk, uclk)
> +
> +#define UBOOT_DM_CLK_MICROCHIP_SAMA7G5_UTMI "sama7-utmi-clk"
> +#define UBOOT_DM_MICROCHIP_SAMA7G5_UTMI "sama7-utmi"
> +
> +#define AT91_TO_CLK_ID(_t, _i)		(((_t) << 8) | ((_i) & 0xff))
> +
> +/*
> + * UTMI clock description
> + * @n:	clock name
> + * @p:	clock parent name
> + * @id: clock id in RSTC_GRSTR
> + */
> +static struct {
> +	const char *n;
> +	const char *p;
> +	u8 id;
> +} sama7_utmick[] = {
> +	{ .n = "utmi1",	.p = "utmick", .id = 0, },
> +	{ .n = "utmi2",	.p = "utmi1",  .id = 1, },
> +	{ .n = "utmi3",	.p = "utmi1",  .id = 2, },
> +};
> +
> +static int sama7_utmi_clk_enable(struct clk *clk)
> +{
> +	int ret;
> +
> +	struct sama7_utmi_clk *utmi = to_sama7_utmi_clk(clk);
> +	u8 id = utmi->id;
> +
> +	ret = reset_assert(utmi->reset);
> +	if (ret)
> +		return ret;
> +
> +	ret = regmap_update_bits(utmi->regmap_sfr, SAMA7_SFR_UTMI0R(id),
> +				 SAMA7_SFR_UTMI_COMMONON, 0);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = reset_deassert(utmi->reset);
> +	if (ret)
> +		return ret;
> +
> +	/* Datasheet states a minimum of 45 us before any USB operation */
> +	udelay(50);
> +
> +	return 0;
> +}
> +
> +static int sama7_utmi_clk_disable(struct clk *clk)
> +{
> +	int ret;
> +	struct sama7_utmi_clk *utmi = to_sama7_utmi_clk(clk);
> +	u8 id = utmi->id;
> +
> +	ret = reset_assert(utmi->reset);
> +	if (ret)
> +		return ret;
> +
> +	regmap_update_bits(utmi->regmap_sfr, SAMA7_SFR_UTMI0R(id),
> +			   SAMA7_SFR_UTMI_COMMONON, SAMA7_SFR_UTMI_COMMONON);
> +
> +	return 0;
> +}
> +
> +static ulong sama7_utmi_clk_get_rate(struct clk *clk)
> +{
> +	/* Return utmick's rate: 480MHz */
> +	return clk_get_parent_rate(clk);
> +}
> +
> +static const struct clk_ops sama7_utmi_clk_ops = {
> +	.enable = sama7_utmi_clk_enable,
> +	.disable = sama7_utmi_clk_disable,
> +	.get_rate = sama7_utmi_clk_get_rate,
> +};
> +
> +static struct clk*
> +sama7_utmi_clk_register(struct regmap *regmap_sfr, struct reset_ctl *reset,
> +			const char *name, const char *parent_name, u8 id)
> +{
> +	struct clk *clk;
> +	struct sama7_utmi_clk *utmi_clk;
> +	int ret;
> +
> +	if (!regmap_sfr || !reset || !name || !parent_name)
> +		return ERR_PTR(-EINVAL);
> +
> +	utmi_clk = kzalloc(sizeof(*utmi_clk), GFP_KERNEL);
> +	if (!utmi_clk)
> +		return ERR_PTR(-ENOMEM);
> +
> +	utmi_clk->reset = reset;
> +	utmi_clk->regmap_sfr = regmap_sfr;
> +	utmi_clk->id = id;
> +
> +	clk = &utmi_clk->uclk;
> +	ret = clk_register(clk, UBOOT_DM_CLK_MICROCHIP_SAMA7G5_UTMI,
> +			   name, parent_name);
> +	if (ret) {
> +		kfree(utmi_clk);
> +		clk = ERR_PTR(ret);
> +	}
> +
> +	clk_dm(AT91_TO_CLK_ID(UTMI, utmi_clk->id), clk);
> +
> +	return clk;
> +}
> +
> +static int sama7_utmi_probe(struct udevice *dev)
> +{
> +	struct clk *utmi_parent_clk, *utmi_clk;
> +	struct regmap *regmap_sfr;
> +	struct reset_ctl *phy_reset;
> +	int i;
> +	char name[16];
> +
> +	utmi_parent_clk = devm_clk_get(dev, "utmi_clk");
> +	if (IS_ERR(utmi_parent_clk))
> +		return PTR_ERR(utmi_parent_clk);
> +
> +	regmap_sfr = syscon_regmap_lookup_by_phandle(dev, "sfr-phandle");
> +	if (IS_ERR(regmap_sfr))
> +		return PTR_ERR(regmap_sfr);
> +
> +	for (i = 0; i < ARRAY_SIZE(sama7_utmick); i++) {
> +		snprintf(name, sizeof(name), "usb%d_reset", i);
> +		phy_reset = devm_reset_control_get(dev, name);
> +		if (IS_ERR(phy_reset))
> +			return PTR_ERR(phy_reset);
> +
> +		utmi_clk = sama7_utmi_clk_register(regmap_sfr, phy_reset,
> +						   sama7_utmick[i].n,
> +						   sama7_utmick[i].p,
> +						   sama7_utmick[i].id);
> +		if (IS_ERR(utmi_clk))
> +			return PTR_ERR(utmi_clk);
> +	}
> +
> +	return 0;
> +};
> +
> +static const struct udevice_id sama7_utmi_clk_dt_ids[] = {
> +	{ .compatible = "microchip,sama7g5-utmi-clk", },
> +	{ /* sentinel */},
> +};
> +
> +static int utmi_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
> +{
> +	if (args->args_count != 1) {
> +		debug("UTMI: clk: Invalid args_count: %d\n", args->args_count);
> +		return -EINVAL;
> +	}
> +
> +	clk->id = AT91_TO_CLK_ID(UTMI, args->args[0]);
> +
> +	return 0;
> +}
> +
> +static const struct clk_ops sama7_utmi_ops = {
> +	.of_xlate	= utmi_clk_of_xlate,
> +	.enable		= ccf_clk_enable,
> +	.disable	= ccf_clk_disable,
> +};
> +
> +U_BOOT_DRIVER(microhip_sama7g5_utmi_clk) = {
> +	.name = UBOOT_DM_CLK_MICROCHIP_SAMA7G5_UTMI,
> +	.id = UCLASS_CLK,
> +	.ops = &sama7_utmi_clk_ops,
> +};
> +
> +U_BOOT_DRIVER(microhip_sama7g5_utmi) = {
> +	.name = UBOOT_DM_MICROCHIP_SAMA7G5_UTMI,
> +	.of_match = sama7_utmi_clk_dt_ids,
> +	.id = UCLASS_CLK,
> +	.ops = &sama7_utmi_ops,
> +	.probe = sama7_utmi_probe,
> +};