[PATCH v1 0/2] Add irq number property for loongarch pch interrupt controller

[PATCH v1 0/2] Add irq number property for loongarch pch interrupt controller

[Tianrui Zhao]

This series add irq number property for loongarch pch_msi
and pch_pic interrupt controller.

Changes for v1:
(1) Add irq number property for loongarch_pch_msi.
(2) Add irq number property for loongarch_pch_pic.

Tianrui Zhao (2):
  hw/intc/loongarch_pch_msi: add irq number property
  hw/intc/loongarch_pch_pic: add irq number property

 hw/intc/loongarch_pch_msi.c         | 22 +++++++++++++++++++---
 hw/intc/loongarch_pch_pic.c         | 29 +++++++++++++++++++++++++----
 hw/loongarch/virt.c                 | 19 ++++++++++++-------
 include/hw/intc/loongarch_pch_msi.h |  3 ++-
 include/hw/intc/loongarch_pch_pic.h |  5 ++---
 include/hw/pci-host/ls7a.h          |  1 -
 6 files changed, 60 insertions(+), 19 deletions(-)

-- 
2.31.1

[PATCH v1 1/2] hw/intc/loongarch_pch_msi: add irq number property

[Tianrui Zhao]

This patch adds irq number property for loongarch msi interrupt
controller, and remove hard coding irq number macro.

Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
---
 hw/intc/loongarch_pch_msi.c         | 22 +++++++++++++++++++---
 hw/loongarch/virt.c                 | 11 +++++++----
 include/hw/intc/loongarch_pch_msi.h |  3 ++-
 include/hw/pci-host/ls7a.h          |  1 -
 4 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c
index b36d6d76e4..279be448d2 100644
--- a/hw/intc/loongarch_pch_msi.c
+++ b/hw/intc/loongarch_pch_msi.c
@@ -32,7 +32,7 @@ static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
      */
     irq_num = (val & 0xff) - s->irq_base;
     trace_loongarch_msi_set_irq(irq_num);
-    assert(irq_num < PCH_MSI_IRQ_NUM);
+    assert(irq_num < s->irq_num);
     qemu_set_irq(s->pch_msi_irq[irq_num], 1);
 }
 
@@ -49,6 +49,22 @@ static void pch_msi_irq_handler(void *opaque, int irq, int level)
     qemu_set_irq(s->pch_msi_irq[irq], level);
 }
 
+static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
+{
+    LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
+
+    assert(s->irq_num > 0);
+
+    s->pch_msi_irq = g_malloc(sizeof(qemu_irq) * s->irq_num);
+    if (!s->pch_msi_irq) {
+        error_report("loongarch_pch_msi: fail to alloc memory");
+        exit(1);
+    }
+
+    qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num);
+    qdev_init_gpio_in(dev, pch_msi_irq_handler, s->irq_num);
+}
+
 static void loongarch_pch_msi_init(Object *obj)
 {
     LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
@@ -59,12 +75,11 @@ static void loongarch_pch_msi_init(Object *obj)
     sysbus_init_mmio(sbd, &s->msi_mmio);
     msi_nonbroken = true;
 
-    qdev_init_gpio_out(DEVICE(obj), s->pch_msi_irq, PCH_MSI_IRQ_NUM);
-    qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, PCH_MSI_IRQ_NUM);
 }
 
 static Property loongarch_msi_properties[] = {
     DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0),
+    DEFINE_PROP_UINT32("msi_irq_num",  LoongArchPCHMSI, irq_num, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -72,6 +87,7 @@ static void loongarch_pch_msi_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
+    dc->realize = loongarch_pch_msi_realize;
     device_class_set_props(dc, loongarch_msi_properties);
 }
 
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 958be74fa1..3547d5f711 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -496,7 +496,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
     LoongArchCPU *lacpu;
     CPULoongArchState *env;
     CPUState *cpu_state;
-    int cpu, pin, i;
+    int cpu, pin, i, start, num;
 
     ipi = qdev_new(TYPE_LOONGARCH_IPI);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
@@ -576,14 +576,17 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
     }
 
     pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
-    qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START);
+    start   =  PCH_PIC_IRQ_NUM;
+    num = 256 - start;
+    qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
+    qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
     d = SYS_BUS_DEVICE(pch_msi);
     sysbus_realize_and_unref(d, &error_fatal);
     sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
-    for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
+    for (i = 0; i < num; i++) {
         /* Connect 192 pch_msi irqs to extioi */
         qdev_connect_gpio_out(DEVICE(d), i,
-                              qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
+                              qdev_get_gpio_in(extioi, i + start));
     }
 
     loongarch_devices_init(pch_pic, lams);
diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarch_pch_msi.h
index 6d67560dea..c5a52bc327 100644
--- a/include/hw/intc/loongarch_pch_msi.h
+++ b/include/hw/intc/loongarch_pch_msi.h
@@ -15,8 +15,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)
 
 struct LoongArchPCHMSI {
     SysBusDevice parent_obj;
-    qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM];
+    qemu_irq *pch_msi_irq;
     MemoryRegion msi_mmio;
     /* irq base passed to upper extioi intc */
     unsigned int irq_base;
+    unsigned int irq_num;
 };
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
index df7fa55a30..6443327bd7 100644
--- a/include/hw/pci-host/ls7a.h
+++ b/include/hw/pci-host/ls7a.h
@@ -34,7 +34,6 @@
  */
 #define PCH_PIC_IRQ_OFFSET       64
 #define VIRT_DEVICE_IRQS         16
-#define VIRT_PCI_IRQS            48
 #define VIRT_UART_IRQ            (PCH_PIC_IRQ_OFFSET + 2)
 #define VIRT_UART_BASE           0x1fe001e0
 #define VIRT_UART_SIZE           0X100
-- 
2.31.1

[PATCH v1 2/2] hw/intc/loongarch_pch_pic: add irq number property

[Tianrui Zhao]

With loongarch 7A1000 manual, irq number supported can be set
in PCH_PIC_INT_ID_HI register. This patch adds irq number property
for loongarch_pch_pic, so that virt machine can set different
irq number when pch_pic intc is added.

Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
---
 hw/intc/loongarch_pch_pic.c         | 29 +++++++++++++++++++++++++----
 hw/loongarch/virt.c                 | 10 ++++++----
 include/hw/intc/loongarch_pch_pic.h |  5 ++---
 3 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
index 3380b09807..26f36501b4 100644
--- a/hw/intc/loongarch_pch_pic.c
+++ b/hw/intc/loongarch_pch_pic.c
@@ -10,6 +10,7 @@
 #include "hw/loongarch/virt.h"
 #include "hw/irq.h"
 #include "hw/intc/loongarch_pch_pic.h"
+#include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "trace.h"
 
@@ -40,7 +41,7 @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
     LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
     uint64_t mask = 1ULL << irq;
 
-    assert(irq < PCH_PIC_IRQ_NUM);
+    assert(irq < s->irq_num);
     trace_loongarch_pch_pic_irq_handler(irq, level);
 
     if (s->intedge & mask) {
@@ -78,7 +79,12 @@ static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
         val = PCH_PIC_INT_ID_VAL;
         break;
     case PCH_PIC_INT_ID_HI:
-        val = PCH_PIC_INT_ID_NUM;
+        /*
+         * With 7A1000 manual
+         *   bit  0-15 pch irqchip version
+         *   bit 16-31 irq number supported with pch irqchip
+         */
+        val = PCH_PIC_INT_ID_VER + ((s->irq_num - 1) << 16);
         break;
     case PCH_PIC_INT_MASK_LO:
         val = (uint32_t)s->int_mask;
@@ -365,6 +371,16 @@ static void loongarch_pch_pic_reset(DeviceState *d)
     s->int_polarity = 0x0;
 }
 
+static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
+{
+    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
+
+    assert(s->irq_num > 0 && (s->irq_num <= 64));
+
+    qdev_init_gpio_out(dev, s->parent_irq, s->irq_num);
+    qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
+}
+
 static void loongarch_pch_pic_init(Object *obj)
 {
     LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
@@ -382,10 +398,13 @@ static void loongarch_pch_pic_init(Object *obj)
     sysbus_init_mmio(sbd, &s->iomem8);
     sysbus_init_mmio(sbd, &s->iomem32_high);
 
-    qdev_init_gpio_out(DEVICE(obj), s->parent_irq, PCH_PIC_IRQ_NUM);
-    qdev_init_gpio_in(DEVICE(obj), pch_pic_irq_handler, PCH_PIC_IRQ_NUM);
 }
 
+static Property loongarch_pch_pic_properties[] = {
+    DEFINE_PROP_UINT32("pch_pic_irq_num",  LoongArchPCHPIC, irq_num, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static const VMStateDescription vmstate_loongarch_pch_pic = {
     .name = TYPE_LOONGARCH_PCH_PIC,
     .version_id = 1,
@@ -411,8 +430,10 @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
+    dc->realize = loongarch_pch_pic_realize;
     dc->reset = loongarch_pch_pic_reset;
     dc->vmsd = &vmstate_loongarch_pch_pic;
+    device_class_set_props(dc, loongarch_pch_pic_properties);
 }
 
 static const TypeInfo loongarch_pch_pic_info = {
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 3547d5f711..761eb81c65 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -559,6 +559,8 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
     }
 
     pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
+    num = PCH_PIC_IRQ_NUM;
+    qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
     d = SYS_BUS_DEVICE(pch_pic);
     sysbus_realize_and_unref(d, &error_fatal);
     memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
@@ -570,13 +572,13 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
                             VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
                             sysbus_mmio_get_region(d, 2));
 
-    /* Connect 64 pch_pic irqs to extioi */
-    for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) {
+    /* Connect pch_pic irqs to extioi */
+    for (int i = 0; i < num; i++) {
         qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
     }
 
     pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
-    start   =  PCH_PIC_IRQ_NUM;
+    start   =  num;
     num = 256 - start;
     qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
     qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
@@ -584,7 +586,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
     sysbus_realize_and_unref(d, &error_fatal);
     sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
     for (i = 0; i < num; i++) {
-        /* Connect 192 pch_msi irqs to extioi */
+        /* Connect pch_msi irqs to extioi */
         qdev_connect_gpio_out(DEVICE(d), i,
                               qdev_get_gpio_in(extioi, i + start));
     }
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
index 2d4aa9ed6f..ba3a47fa88 100644
--- a/include/hw/intc/loongarch_pch_pic.h
+++ b/include/hw/intc/loongarch_pch_pic.h
@@ -9,11 +9,9 @@
 #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
 
-#define PCH_PIC_IRQ_START               0
-#define PCH_PIC_IRQ_END                 63
 #define PCH_PIC_IRQ_NUM                 64
 #define PCH_PIC_INT_ID_VAL              0x7000000UL
-#define PCH_PIC_INT_ID_NUM              0x3f0001UL
+#define PCH_PIC_INT_ID_VER              0x1UL
 
 #define PCH_PIC_INT_ID_LO               0x00
 #define PCH_PIC_INT_ID_HI               0x04
@@ -66,4 +64,5 @@ struct LoongArchPCHPIC {
     MemoryRegion iomem32_low;
     MemoryRegion iomem32_high;
     MemoryRegion iomem8;
+    unsigned int  irq_num;
 };
-- 
2.31.1

Re: [PATCH v1 1/2] hw/intc/loongarch_pch_msi: add irq number property

[Philippe Mathieu-Daudé]

On 15/12/22 07:50, Tianrui Zhao wrote:
> This patch adds irq number property for loongarch msi interrupt
> controller, and remove hard coding irq number macro.
> 
> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
> ---
>   hw/intc/loongarch_pch_msi.c         | 22 +++++++++++++++++++---
>   hw/loongarch/virt.c                 | 11 +++++++----
>   include/hw/intc/loongarch_pch_msi.h |  3 ++-
>   include/hw/pci-host/ls7a.h          |  1 -
>   4 files changed, 28 insertions(+), 9 deletions(-)


> @@ -49,6 +49,22 @@ static void pch_msi_irq_handler(void *opaque, int irq, int level)
>       qemu_set_irq(s->pch_msi_irq[irq], level);
>   }
>   
> +static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
> +{
> +    LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
> +
> +    assert(s->irq_num > 0);

        if (!s->irq_num || s->irq_num  > PCH_MSI_IRQ_NUM) {
            error_setg(errp, "Invalid 'msi_irq_num'");
            return;
        }

> +    s->pch_msi_irq = g_malloc(sizeof(qemu_irq) * s->irq_num);

        s->pch_msi_irq = g_new(qemu_irq, s->irq_num);

> +    if (!s->pch_msi_irq) {
> +        error_report("loongarch_pch_msi: fail to alloc memory");
> +        exit(1);
> +    }
> +
> +    qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num);
> +    qdev_init_gpio_in(dev, pch_msi_irq_handler, s->irq_num);
> +}

Missing g_free(s->pch_msi_irq) in loongarch_pch_msi_unrealize().

>   static void loongarch_pch_msi_init(Object *obj)
>   {
>       LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
> @@ -59,12 +75,11 @@ static void loongarch_pch_msi_init(Object *obj)
>       sysbus_init_mmio(sbd, &s->msi_mmio);
>       msi_nonbroken = true;
>   
> -    qdev_init_gpio_out(DEVICE(obj), s->pch_msi_irq, PCH_MSI_IRQ_NUM);
> -    qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, PCH_MSI_IRQ_NUM);
>   }
>   
>   static Property loongarch_msi_properties[] = {
>       DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0),
> +    DEFINE_PROP_UINT32("msi_irq_num",  LoongArchPCHMSI, irq_num, 0),
>       DEFINE_PROP_END_OF_LIST(),
>   };
>   
> @@ -72,6 +87,7 @@ static void loongarch_pch_msi_class_init(ObjectClass *klass, void *data)
>   {
>       DeviceClass *dc = DEVICE_CLASS(klass);
>   
> +    dc->realize = loongarch_pch_msi_realize;

        dc->unrealize = loongarch_pch_msi_unrealize;

>       device_class_set_props(dc, loongarch_msi_properties);
>   }
>   
> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
> index 958be74fa1..3547d5f711 100644
> --- a/hw/loongarch/virt.c
> +++ b/hw/loongarch/virt.c
> @@ -496,7 +496,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
>       LoongArchCPU *lacpu;
>       CPULoongArchState *env;
>       CPUState *cpu_state;
> -    int cpu, pin, i;
> +    int cpu, pin, i, start, num;
>   
>       ipi = qdev_new(TYPE_LOONGARCH_IPI);
>       sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
> @@ -576,14 +576,17 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
>       }
>   
>       pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
> -    qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START);
> +    start   =  PCH_PIC_IRQ_NUM;
> +    num = 256 - start;

This part is confuse. So you don't need PCH_MSI_IRQ_START anymore?
What is this magic '256' value?

> +    qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
> +    qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
>       d = SYS_BUS_DEVICE(pch_msi);
>       sysbus_realize_and_unref(d, &error_fatal);
>       sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
> -    for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
> +    for (i = 0; i < num; i++) {
>           /* Connect 192 pch_msi irqs to extioi */
>           qdev_connect_gpio_out(DEVICE(d), i,
> -                              qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
> +                              qdev_get_gpio_in(extioi, i + start));
>       }

Re: [PATCH v1 1/2] hw/intc/loongarch_pch_msi: add irq number property

[Tianrui Zhao]

在 2022年12月15日 15:40, Philippe Mathieu-Daudé 写道:
> On 15/12/22 07:50, Tianrui Zhao wrote:
>> This patch adds irq number property for loongarch msi interrupt
>> controller, and remove hard coding irq number macro.
>>
>> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
>> ---
>>   hw/intc/loongarch_pch_msi.c         | 22 +++++++++++++++++++---
>>   hw/loongarch/virt.c                 | 11 +++++++----
>>   include/hw/intc/loongarch_pch_msi.h |  3 ++-
>>   include/hw/pci-host/ls7a.h          |  1 -
>>   4 files changed, 28 insertions(+), 9 deletions(-)
>
>
>> @@ -49,6 +49,22 @@ static void pch_msi_irq_handler(void *opaque, int 
>> irq, int level)
>>       qemu_set_irq(s->pch_msi_irq[irq], level);
>>   }
>>   +static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
>> +{
>> +    LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
>> +
>> +    assert(s->irq_num > 0);
>
>        if (!s->irq_num || s->irq_num  > PCH_MSI_IRQ_NUM) {
>            error_setg(errp, "Invalid 'msi_irq_num'");
>            return;
>        }
>
>> +    s->pch_msi_irq = g_malloc(sizeof(qemu_irq) * s->irq_num);
>
>        s->pch_msi_irq = g_new(qemu_irq, s->irq_num);
>
>> +    if (!s->pch_msi_irq) {
>> +        error_report("loongarch_pch_msi: fail to alloc memory");
>> +        exit(1);
>> +    }
>> +
>> +    qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num);
>> +    qdev_init_gpio_in(dev, pch_msi_irq_handler, s->irq_num);
>> +}
>
> Missing g_free(s->pch_msi_irq) in loongarch_pch_msi_unrealize().
>
>>   static void loongarch_pch_msi_init(Object *obj)
>>   {
>>       LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
>> @@ -59,12 +75,11 @@ static void loongarch_pch_msi_init(Object *obj)
>>       sysbus_init_mmio(sbd, &s->msi_mmio);
>>       msi_nonbroken = true;
>>   -    qdev_init_gpio_out(DEVICE(obj), s->pch_msi_irq, PCH_MSI_IRQ_NUM);
>> -    qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, 
>> PCH_MSI_IRQ_NUM);
>>   }
>>     static Property loongarch_msi_properties[] = {
>>       DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0),
>> +    DEFINE_PROP_UINT32("msi_irq_num",  LoongArchPCHMSI, irq_num, 0),
>>       DEFINE_PROP_END_OF_LIST(),
>>   };
>>   @@ -72,6 +87,7 @@ static void 
>> loongarch_pch_msi_class_init(ObjectClass *klass, void *data)
>>   {
>>       DeviceClass *dc = DEVICE_CLASS(klass);
>>   +    dc->realize = loongarch_pch_msi_realize;
>
>        dc->unrealize = loongarch_pch_msi_unrealize;
>
>>       device_class_set_props(dc, loongarch_msi_properties);
>>   }
>>   diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
>> index 958be74fa1..3547d5f711 100644
>> --- a/hw/loongarch/virt.c
>> +++ b/hw/loongarch/virt.c
>> @@ -496,7 +496,7 @@ static void 
>> loongarch_irq_init(LoongArchMachineState *lams)
>>       LoongArchCPU *lacpu;
>>       CPULoongArchState *env;
>>       CPUState *cpu_state;
>> -    int cpu, pin, i;
>> +    int cpu, pin, i, start, num;
>>         ipi = qdev_new(TYPE_LOONGARCH_IPI);
>>       sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
>> @@ -576,14 +576,17 @@ static void 
>> loongarch_irq_init(LoongArchMachineState *lams)
>>       }
>>         pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
>> -    qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START);
>> +    start   =  PCH_PIC_IRQ_NUM;
>> +    num = 256 - start;
>
> This part is confuse. So you don't need PCH_MSI_IRQ_START anymore?
> What is this magic '256' value?
On loongarch platform, both PCH_pic and PCH_MSI intc are connected to upper
extioi controller, PCH_pic is triggered by irq line and PCH_MSI is 
trigger by message method.

No, PCH_MSI_IRQ_START is not necessary any more. 256 is total supported 
irq number with extioi controller,
we will replace it with macro EXTIOI_IRQS. We can adjust irq number 
between PCH_pic and PCH_MSI, only if
the total number is no larger than EXTIOI_IRQS. In general there are 
lots of msi vectors requirements
since there may be many virtio devices; there is no much requirements 
for PCH_pic intc, since gpex pcie
irq number is 4 and there is fewer legacy non-pci devices(such as 
rtc/uart/acpi ged).

I want to adjust number PCH_pic intc with smaller value, and increase 
irq number of PCH_MSI intc in future.
>
>
>> +    qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
>> +    qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
>>       d = SYS_BUS_DEVICE(pch_msi);
>>       sysbus_realize_and_unref(d, &error_fatal);
>>       sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
>> -    for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
>> +    for (i = 0; i < num; i++) {
>>           /* Connect 192 pch_msi irqs to extioi */
>>           qdev_connect_gpio_out(DEVICE(d), i,
>> -                              qdev_get_gpio_in(extioi, i + 
>> PCH_MSI_IRQ_START));
>> +                              qdev_get_gpio_in(extioi, i + start));
>>       }
>